WO2020233203A1 - 对存储信息更新的方法和装置 - Google Patents

对存储信息更新的方法和装置 Download PDF

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Publication number
WO2020233203A1
WO2020233203A1 PCT/CN2020/078768 CN2020078768W WO2020233203A1 WO 2020233203 A1 WO2020233203 A1 WO 2020233203A1 CN 2020078768 W CN2020078768 W CN 2020078768W WO 2020233203 A1 WO2020233203 A1 WO 2020233203A1
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Prior art keywords
information
candidate
data information
data
ecc
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PCT/CN2020/078768
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English (en)
French (fr)
Inventor
梁伟光
耿东玉
黄沁辉
马会肖
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华为技术有限公司
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Publication of WO2020233203A1 publication Critical patent/WO2020233203A1/zh
Priority to US17/230,056 priority Critical patent/US11914895B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • This application relates to the field of communication technology, and in particular to a method and device for updating stored information.
  • RAM random access memory
  • flash memory flash memory
  • ROM read only memory
  • RAM is the most common system memory, which can read and write memory cells randomly. According to the data storage method, RAM can be divided into static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM).
  • Bit flip refers to that the correct data written in the memory may change after a period of time, making the correct data become incorrect data.
  • ECC error correction code verification mechanism
  • ECC error correction code verification mechanism
  • ECC uses an ECC encoding algorithm to calculate the data to generate ECC check information of the data information.
  • the ECC check information of the data information is referred to as ECC check information or check information for short.
  • the ECC decoder can use the ECC decoding algorithm to perform an error correction operation in conjunction with the ECC check information to generate error-corrected data information.
  • the traditional way to update the data stored in the memory includes: read the stored data information, perform ECC decoding, and update according to the error-corrected data information generated by the ECC decoding; then update the updated data and include ECC
  • the error-corrected data information is ECC encoded to generate written data information and written ECC verification information, and the written data information and written ECC verification information generated after encoding are substituted for the stored data
  • the information and ECC check information are written into the memory. Therefore, when the data information in the code-word stored in the memory is updated, the information written in the memory is all data information based on the stored code-word and the updated information that are read once.
  • the embodiments of the present application provide a method and device for updating stored information, which can realize that when updating the data stored in the memory, it is only necessary to write data content that is different from the data information of the code word already stored in the memory. Therefore, it is not necessary to write all the data content in the data message of the codeword that has been stored in the memory into the memory again, thereby reducing the waste of power consumption during writing and the time for executing the writing operation.
  • an embodiment of the present application provides a method for updating stored information.
  • the controller performs ECC decoding on the stored data information according to the stored data information and the stored error check code (ECC) check information to generate error-corrected codewords.
  • ECC error check code
  • the error-corrected codewords include error Data information after the error.
  • the controller generates data information for candidate writing according to the error-corrected data information and the update data instruction.
  • the controller performs a mask operation on the candidate write data information according to the stored data information.
  • the controller writes the unmasked content in the candidate write data information into the memory.
  • the written data information is the data content that is not masked in the candidate write data information, and the data content that is masked in the candidate write data information will not be written To the memory, thereby saving power consumption and delay due to the write operation of updating the data content.
  • the present invention performs error correction on the stored information before writing the information, so that the updated content is based on the corrected content, which ensures the accuracy of the updated content.
  • the indication of the update data is used to indicate the location of the data to be updated in the stored data information
  • the controller further generates updated data information according to the indication of the update data.
  • the generating data information for candidate writing according to the error-corrected data information and an indication of updated data includes: generating the data information for candidate writing according to the error-corrected data information and the updated data information .
  • the generating candidate write data information according to the error-corrected data information and the updated data information includes: executing the error-corrected data information and the updated data information XOR processing generates the data information of the candidate write.
  • the data information of the candidate write is generated through exclusive OR processing, which makes the operation simple.
  • the update data indication is used to indicate the updated data content and the updated data location
  • the candidate write data information is generated according to the error-corrected data information and the update data indication
  • the method includes: replacing the data content in the same position in the error-corrected data information with the updated data content according to the updated data location.
  • the controller further performs exclusive OR processing on the stored data information and the data information written by the candidate, and generates a mask control signal for the data information written by the candidate, And perform a mask operation on the data information written by the candidate according to the mask control signal for the data information written by the candidate. Through the mask operation, less data information is written, saving writing time and consumption.
  • the controller combines the stored data information and the stored ECC check information to generate a stored codeword.
  • the controller combines the stored data information and the stored ECC check information to generate a stored codeword.
  • the controller performs ECC encoding on the candidate write data information, generates candidate write ECC check information, and writes the candidate write ECC check information to The memory.
  • the candidate ECC verification information is also written into the memory, which is beneficial for the updated data information to be verified using the ECC verification information, and the accuracy of the information is ensured.
  • the codeword after error correction further includes ECC check information after error correction
  • the controller is further based on the ECC check information after error correction and updated ECC check information Generate ECC check information for candidate writing; perform a mask operation on the ECC check information written by candidate according to the stored ECC check information, and unmask the ECC check information written by candidate The content of the code is written into the memory.
  • the ECC check information of candidate writing is also masked, which reduces the time and consumption of writing.
  • the controller further performs ECC encoding on the data information of the candidate write, generates ECC check information of the candidate write, and compares the candidate write information according to the stored ECC check information.
  • the written ECC verification information performs a mask operation.
  • the controller writes the unmasked content in the candidate write ECC check information into the memory. Through this method, the ECC check information of candidate writing is also masked, which reduces the time and consumption of writing.
  • the generating candidate write ECC check information according to the error-corrected ECC check information and the updated ECC check information includes: checking the error-corrected ECC check information Perform an exclusive OR process with the updated ECC check information to generate ECC check information for candidate writing.
  • the controller further performs XOR processing on the ECC check information of the candidate write and the stored ECC check information to generate ECC check information for the candidate write
  • the performing a mask operation on the ECC check information of the candidate write according to the stored ECC check information includes: according to the mask of the ECC check information written to the candidate
  • the code control signal performs a mask operation on the ECC check information written by the candidate.
  • an embodiment of the present invention provides a device, which includes a controller and a memory.
  • the memory is used to store data information and error check code (ECC) check information corresponding to the data information.
  • ECC error check code
  • the controller is used to execute any steps performed by the controller in the first aspect described above.
  • an embodiment of the present invention provides a chip including a core processor and a controller.
  • the core processor is used to exchange data with the memory through the controller.
  • the controller is used to execute any steps performed by the controller in the first aspect described above.
  • the chip further includes a memory, and the memory is used to store data information and error check code (ECC) check information corresponding to the data information.
  • ECC error check code
  • an embodiment of the present invention provides a controller.
  • the controller includes a processing circuit and a memory interface circuit.
  • the memory interface circuit is used to provide an interface between the controller and the memory.
  • the processing circuit is used to interact with the memory through the memory interface circuit and execute any steps performed by the controller in the first aspect.
  • an embodiment of the present invention provides a device.
  • the device includes a processor and a memory.
  • the memory is used to store computer-executed instructions; the processor is used to execute the computer-executed instructions stored in the memory when the device is running, so that the device executes any steps executed by the controller in the first aspect.
  • a computer-readable storage medium stores instructions that, when run on a computer, enable the computer to execute the data information described in any one of the first aspects.
  • the generation method is provided.
  • an embodiment of the present invention provides a device that includes an error check code (ECC) decoder, a candidate information generation module, and a mask control module.
  • ECC error check code
  • the ECC decoder is used to perform ECC decoding on the stored data information according to the stored data information and the stored error check code (ECC) check information to generate error-corrected data information.
  • the candidate information generating module is used to generate candidate write data information according to the error-corrected data information and updated data information.
  • the mask control module performs a mask operation on the candidate write data information according to the stored data information, so that the unmasked content in the candidate write data information is written into the memory.
  • an example of the present invention provides a computer program product, which when the computer product is executed, is used to execute the method described in the foregoing aspect.
  • the controller performs error correction on the stored data information and then performs exclusive OR processing with the updated data information, and performs a mask operation to generate the written data
  • the number of information so that the written data information is the data content that is not masked in the candidate write data information, and the data content that is masked in the candidate write data information will not be written to In the memory, the power consumption and delay of a single write operation for updating data content are thus saved.
  • FIG. 1 is a schematic structural diagram of an apparatus provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for updating stored information provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of data information and ECC verification information stored in the same memory provided by an embodiment of the application;
  • FIG. 4 is a schematic diagram of data information and ECC check information separately stored in different memories provided by an embodiment of the application;
  • FIG. 5 is a schematic diagram of the structure of a controller provided by an embodiment of the application.
  • 6A is a schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • FIG 6B present application a schematic view D e data storage according to an embodiment
  • FIG. 6C is a schematic diagram of updated data information D f provided by an embodiment of the application.
  • 6D is a schematic diagram of performing a mask operation and writing data according to a mask control signal according to an embodiment of the application;
  • 6E is another schematic diagram of performing a mask operation and writing data according to a mask control signal according to an embodiment of the application;
  • FIG. 7A is another schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • 7B is a schematic diagram of generating candidate write data information based on error-corrected data information and updated data information according to an embodiment of the application;
  • FIG. 8 is another schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • FIG. 9 is another schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • FIG. 10 is another schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • FIG. 11 is another schematic flowchart of a method for updating stored information provided by an embodiment of the application.
  • FIG. 12 is a schematic diagram of another structure of a controller provided by an embodiment of the application.
  • FIG. 13 is another schematic structural diagram of a device including a controller provided by an embodiment of the application.
  • FIG. 14 is a schematic diagram of another structure of an apparatus for performing controller functions according to an embodiment of the application.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations, or illustrations. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present invention should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as “exemplary” or “for example” are used to present related concepts in a specific manner.
  • the data information in the embodiment of the present invention refers to a k-bit data sequence.
  • the ECC check information is a p-bit data sequence.
  • the codeword is a data sequence of n bits. Among them, n bits are equal to k bits plus p bits.
  • the data content in the embodiment of the present invention refers to the value of a specific bit.
  • the data position in the embodiment of the present invention refers to the position of the bit in the data information, the ECC check information or the codeword, such as the first bit and the third bit.
  • the updated data content refers to the value corresponding to the bit that needs to be updated, such as the value of the 3rd bit and the 5th bit, such as 0 or 1.
  • the controller performs ECC decoding on the data information stored in the memory to generate error-corrected data information.
  • the controller generates data information for candidate writing according to the data information after error correction and the indication of updated data (such as updated data location, or updated data content and location).
  • the controller determines the bits or bytes that actually need to be updated according to the stored data information and the candidate write data information, and writes the determined bits or bytes in the candidate write data information To the memory.
  • the ECC check information containing the code word of 72-bit C e, C e codeword comprising 64 data bits and 8 information bits D e ECC parity information P e.
  • the ECC decoding the ECC parity information is generated according to data stored in P e D e error correction information
  • 64-bit candidate write data information D n is generated.
  • the controller determines the bits or bytes that actually need to be updated according to the stored data information D e and the candidate write data information D n (for example, the value of 1 or 2 bits that only needs to be updated, or the updated 1 The value of one or two bits and the value of the bit error-corrected during ECC decoding). Therefore, only the determined value of 1 or 2 bits (or bytes) needs to be written into the memory, and it is not necessary to write the entire 64-bit content of the data information D n that can be written into the memory. , To reduce the power consumption and delay of write operations.
  • FIG. 1 is a schematic structural diagram of an apparatus for updating stored information provided by an embodiment of the present invention.
  • the apparatus 100 may at least include a controller 106, a processor 110, and at least one memory 108.
  • the controller 106 exchanges data with the processor 110 and the memory 108 through the system bus.
  • the controller 106 may be integrated with the processor 110 on the same chip, and the controller 106 may also be a separate chip.
  • the controller 106, the processor 110, and the memory 108 may also be integrated on the same chip.
  • the controller 106 can control, read and write data information and ECC verification information stored in the memory.
  • the device 100 may also include a communication interface and other devices such as a magnetic disk as an external memory, which is not limited here.
  • the processor 110 provides the controller 106 with computing and processing capabilities, and can implement access to the memory 108, cache, and disk.
  • the controller 106 is used to control the memory 108 and a bus circuit controller for managing and planning data transmission from the memory 108 to the processor 110.
  • the controller 106 can be implemented by hardware or software. In practical applications, the controller 106 may control necessary logic to write data into the memory 108 or obtain data from the memory 108.
  • the memory 108 is the main memory of the device 100.
  • the memory 108 is generally used to store various running software in the operating system, input and output data, and information exchanged with external memory.
  • the processor 110 can access the memory 108 through the controller 106, and perform read and write operations on the memory 108.
  • One or more memories 108 are used to store data information and ECC check information of the data information.
  • the data information and the ECC check information may be stored in the same memory as shown in FIG. 3, and may also be stored in different memories as shown in FIG. 4.
  • the memory 108 may be RAM, Flash, ROM, etc.
  • Fig. 2 is a flowchart of a method for updating stored information according to an embodiment of the present invention.
  • the controller performing this method may be the controller 106 in FIG. 1.
  • the method includes:
  • Step 202 The controller 106 obtains the data information and the ECC verification information stored in the memory 108.
  • the data information and ECC verification information may be stored in one memory 108 or in different memories 108.
  • Step 204 The controller 106 performs ECC decoding on the stored data information and ECC check information to generate error-corrected data information.
  • Step 206 The controller 106 receives an instruction to update the data to update the data information stored in the memory 108.
  • the indication of the update data is used to indicate the data position in the stored data information that needs to be updated (for example, indicating which bit needs to be updated).
  • the updated data indication is used to indicate the updated data content and the updated data position (for example, indicating the bit position and value to be updated).
  • Step 208 The controller 106 generates candidate write data information according to the error-corrected data information and the indication of the updated data.
  • the controller 106 may perform XOR processing on the error-corrected data information and the updated data information to generate the candidate write data information. Or, the controller 106 uses the updated data content to replace the data content at the same position in the error-corrected data information according to the updated data location to generate the candidate write data information.
  • Step 210 The controller 106 determines the bits or bytes that actually need to be updated according to the stored data information and the candidate write data information;
  • the determination of the bits or bytes that actually need to be updated may be: the controller 106 performs a mask operation on the data information of the candidate write according to the stored data information, and the data information of the candidate write is not masked.
  • the content of the code is the actual bits or bytes that need to be updated.
  • the determination of the bits or bytes that actually need to be updated may also be: the controller 106, such as the stored data information and the data information of the candidate write, and the data information of the candidate write is related to the stored data.
  • the bits or bytes with different values of information are the bits or bytes that actually need to be updated.
  • Step 212 The controller 106 writes the determined bits or bytes that actually need to be updated in the candidate write data information into the memory.
  • the controller 106 performs error correction on the stored data information to generate error-corrected data information, and then generates candidate writes according to the error-corrected data information and the instruction of the updated data.
  • the stored data information determine the bits or bytes that actually need to be updated for the candidate write data information, and write the content of the determined bits or bytes into the memory.
  • the embodiment of the present invention performs a minimal write operation for data information that needs to be updated. In a scenario where there are only a few bits or even one bit in the stored data information that needs to be updated, there is no need to update the content of all bits in the stored data information, which saves the power consumption and delay of a single write operation.
  • the present invention performs error correction on the stored information before writing the information, so that the updated content is based on the corrected content, which ensures the accuracy of the updated content.
  • FIG. 3 is a form of a code-word (code-word) stored in the memory 108 provided by an embodiment of the present invention.
  • the code word contains data information and ECC check information of the data information.
  • the data information of the same codeword and the ECC check information corresponding to the data information are stored in the same memory 108.
  • the data information and the ECC verification information corresponding to the data information have the same read and write address, and the controller 106 may obtain the data information and the corresponding ECC verification information at one time through the read and write address.
  • the memory 108 in FIG. 1 may be in the form of FIG. 3, and the data information 102 and the ECC check information 104 of the same codeword are stored in the same memory.
  • Fig. 4 is another alternative way of storing codewords provided by an embodiment of the present invention.
  • the data information of the codeword and the corresponding ECC verification information are stored in different memories 108.
  • the memory 108-1 stores codeword data information
  • the memory 108-2 stores codeword ECC check information. That is, the data information and the ECC check information have different read and write addresses.
  • the device 100 stores a mapping table of storage addresses of data information and ECC verification information in different memories, or storage addresses in different memories (such as data information storage addresses and ECC verification information storage addresses) and code words The mapping relationship table.
  • a mapping table of storage addresses for storing data information and ECC verification information in the hard disk or flash in the device 100 are examples of mapping relationship table.
  • the controller 106 reads the data information and the ECC check information corresponding to the data information respectively according to the mapping table.
  • the storage of codewords may also adopt the form in FIG. 4, that is, the data information of the same codeword and the ECC check information are stored in different memories 108.
  • Fig. 5 is a schematic structural diagram of a controller provided by an embodiment of the present invention.
  • the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, a sequence generation module 506, and a combination module 507.
  • the controller 106 may be the controller in FIG. 1.
  • the ECC decoder 501 is configured to perform ECC decoding on the stored data information according to the stored data information and the stored ECC check information to generate error-corrected codewords, and the error-corrected codewords include error correction After the data information;
  • the candidate information generating module 503 is configured to generate candidate write data information according to the error-corrected data information and the instruction of the updated data;
  • the mask control module 505 performs a mask operation on the candidate write data information according to the stored data information, and the unmasked content of the candidate write data information is written into the memory.
  • each module in the controller 106 can execute the steps performed by the corresponding module of the controller 106 in the method flow of FIG. 6A, FIG. 7A, FIG. 8 to FIG. 11, and the foregoing FIG. 4.
  • FIG. 6A is a schematic flowchart of a method for updating stored information according to an embodiment of the present invention.
  • the controller that executes this method may be the controller 106 in FIG. 4 or FIG. 5. That is, the controller 106 that executes the method in FIG. 6A includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, and a sequence generation module 506.
  • the codeword is stored in the manner shown in FIG. 3, that is, the data information of the codeword and the ECC check information are stored in the same memory 108.
  • the controller 106 generates an updated code word C f according to the instruction of the update content, and generates a candidate write code based on the error-corrected code word C c and the updated code word C f The word C n .
  • the controller 106 then masking the candidate codeword C n written in accordance with the stored codeword C e, C n code words of the candidate mask is not written to write the contents of the memory 108.
  • the method includes the following steps:
  • Step 601 The ECC decoder 501 and the control signal generation module 504 obtain the codeword C e stored in the memory 108.
  • the codeword stored in the memory 108 is referred to as the stored codeword C e .
  • the acquisition in the embodiment of the present invention may be reading, active acquisition, or reception.
  • the length of the codeword C e assume that storage is n bits.
  • Data length information stored in the D e is k bits
  • the stored data information De may refer to that shown in FIG. 6B.
  • the stored data information De includes k bits, and each small cell represents one bit.
  • One byte includes 8 consecutive bits.
  • Step 602 The candidate information generating module 503 obtains the error-corrected codeword C c generated by the ECC decoder 501.
  • the ECC decoder 501 after obtaining the code word stored in the C e, C e of the codeword stored ECC decoding, the generated error correction code word C c.
  • the codeword C c after error correction includes data information D c after error correction and ECC check information P c after error correction.
  • the ECC check information after the error correction is the ECC check information corresponding to the data message after the error correction.
  • Step 603-1 The sequence generation module 506 obtains the update data instruction, and generates data information that needs to be updated according to the update data instruction.
  • the update instruction data for instructing storing of said codeword C e need to be updated location data.
  • the sequence generating module 506 obtains the indication of the updated data, and generates updated data information D f according to the updated data location.
  • the updated data D f is the same as the stored data length information bit sequence D e, i.e., the updated data D f k equal to the length of the bit sequence.
  • D f value indicates the need to update the data one bit position, such as data stored in the information D e first bit, the third bit and so on. , If bits 3-5 of the stored data values D e in FIG.
  • the other bits need not be updated, the updating information data D f, the sequence generating module 506 will be updated The bit of is set to 1, and the bit that is not updated is set to 0. Then the updated data information D f is [0,0,1,1,1,0,...,0].
  • Step 603-2 The ECC encoder 502 obtains the updated data information D f .
  • the updated data information D f is a bit sequence of length equal to k.
  • the bit with a value of 1 in the updated data information D f is the bit that needs to be updated in the stored code word C e .
  • Step 604 The candidate information generating module 503 obtains the updated codeword C f generated by the ECC encoder 502.
  • the ECC encoder 502 After obtaining the updated data information D f , the ECC encoder 502 performs ECC encoding on the updated data information D f to generate an updated codeword C f .
  • the updated codeword C f includes updated data information D f and updated ECC check information P f .
  • ECC check the updated information to the updated P f D f corresponding to the data information of an ECC parity information P f.
  • steps 602 and 604 have no time sequence.
  • Step 605 The mask control module 505 and the control signal generation module 504 obtain the candidate written codeword C n generated by the candidate information generation module 503.
  • the candidate information generation module 503 After the ECC decoder 501 generates the error-corrected codeword C c and the ECC encoder 502 generates the updated codeword C f , the candidate information generation module 503 generates the error-corrected codeword C c and The updated code word C f generates a code word C n for candidate writing. Part of the content of the candidate codeword C n will be written into the memory 108.
  • the candidate-written codeword C n includes candidate-written data information D n and candidate-written ECC check information P n .
  • Step 606 The mask control module 505 obtains the mask control signal S generated by the control signal generation module 504.
  • a control signal generation module 504 after obtaining the candidate codeword C n candidate information generation module 503 generates the writing, in accordance with the code word C n and storing said candidate code word written for generating the C e The mask control signal S of the candidate codeword C n .
  • the mask control signal is referred to as a control signal.
  • the mask control signal S can be used to perform a mask operation on the candidate written codeword C n .
  • the masking operation refers to masking the current input bit through a bitwise operation with the target number (ie, the codeword C n written by the candidate) for a string of binary numbers.
  • the mask control signal S for the codeword C n of the candidate write includes the mask control signal S1 for the data information D n of the candidate write and the ECC check information P n for the candidate write.
  • the mask control signal S for the candidate written codeword C n is a bit sequence with a length equal to n, and is used to instruct to perform a mask operation on the candidate written codeword C n having the same length.
  • C n codeword generation module 504 when the control signal when the code word C e C n performs processing codeword with the stored write the candidate (such as XOR), and comparing the candidate writing the Describe the stored code word C e .
  • the same value as the value of the same position as the same position C e C n, corresponding to the position signal S is 0, the control content.
  • the contents of the numerical value of the same position as the same C e C n different positions, the control signal S 1 corresponding position.
  • the length of the codeword C n to be written by candidate is n bits, including k bits of data information and p bits of ECC check information.
  • the length of the mask control signal S in FIG. 6D is also n bits.
  • the bit whose content is 1 indicates that no mask operation is performed on the corresponding bit of the codeword written by the candidate.
  • the bit whose content is 0 indicates that a mask operation is performed on the corresponding bit of the codeword written by the candidate.
  • the mask control module 505 does not perform a mask operation on the 1st and 5th bits of the codeword C n written by the candidate, but on the candidate write The other bits of the input codeword C n perform a mask operation.
  • Step 607 The mask control module 505 performs a mask operation on the candidate written codeword C n , so that the unmasked content in the candidate written code word C n is written into the memory 108.
  • the unmasked content includes unmasked data content and/or unmasked ECC check content in the candidate written codeword C n .
  • the mask control module 505 After obtaining the mask control signal S generated by the control signal generation module 504, the mask control module 505 performs a mask operation on the candidate written codeword C n according to the mask control signal S.
  • Data mask technology can mask specified bits (such as bits or bytes) to achieve bitwise (such as bits or bytes) operations.
  • the mask operation refers to a string of binary numbers, which masks the current input bit through bit-wise operation with the target number.
  • the mask control module 505 performs a mask operation on the candidate written codeword C n according to the mask control signal S in FIG. 6D. If the content of the corresponding position (such as a bit) of the mask control signal S is 0, the mask operation is performed on the corresponding position of the codeword C n written by the candidate. That is, the content of the corresponding position in the codeword C n to be written in the candidate is shielded and does not need to be written into the storage module. If the content of the control signal S is at the position of 1, the content of the corresponding position in the codeword C n to be written by candidate is not shielded and needs to be written into the memory 108. Still taking FIG.
  • the first and fifth bits of the control signal S have the value 1, and the other bits have the value 0 (not shown in the figure).
  • the content of the bits other than the first and fifth bits in the codeword C n to be written in the candidate are all masked, and does not need to be stored in the corresponding position of the stored codeword C e . Only the contents of the first and fifth bits need to be written into the memory.
  • the data content of the first and fifth bits in the n-bit updated codeword Cu is the written updated data content. Elsewhere the updated codeword C u still position information corresponding to the code word C e stored. Therefore, with this method, when the stored data is partially updated, only a small number of updated bits (such as the first and fifth bits) need to be written, which saves writing time and power consumption.
  • the mask control module 505 may also perform a mask operation in units of bytes. After receiving the control signal S generated by the control signal generating module 504, the mask control module 505 determines that the value of all bits of the corresponding byte in the control signal S is 0, and then performs a mask operation on the byte. As shown in FIG. 6E, the mask control signal S of n bits contains a mask control signal for m bytes. The value of all the bits in the first byte is 0. The 2, 4, 6, 7, and 8 bits in the m-th byte are 1, and the other bits are 0.
  • the mask control module 505 Since the value of at least one bit in the m-th byte is not 0, the mask control module 505 does not perform a mask operation on the m-th byte, and the content of the m-th byte needs to be written into the memory 108. Therefore, in the n-bit updated codeword Cu , the content of the mth byte is the updated data content written.
  • the mask control module 505 may also perform a mask operation in units of multiple bytes. For example, only when the values of all the bits of two or more adjacent bytes are 0, the mask control module 505 performs a mask operation on the content of the corresponding position of the codeword written by the candidate.
  • the mask operation performed on the codeword Cn written by the candidate according to the control signal S may be: the mask control module 505 shields the codeword Cn written by the candidate from the control signal S.
  • an updated codeword is generated for the location of the updated data.
  • the controller 106 generates an error-corrected codeword according to the error correction of the stored codeword and according to the updated codeword.
  • Word generates the candidate written codeword.
  • the controller 106 performs a mask operation on the codeword written by the candidate, and writes the unmasked content of the codeword written by the candidate into the memory.
  • the present invention provides a minimal write operation for the bit sequence to be updated and the corresponding ECC information. In a scenario where only some bits or even one bit of the stored bytes need to be updated, there is no need to update all the bits of the byte, which saves the power consumption and delay of a single write operation.
  • the present invention performs error correction on the stored information before updating, so that the updated content is based on the corrected content, which ensures the accuracy of the updated content.
  • FIG. 7A is a schematic flowchart of a method for updating stored information provided by an embodiment of the present invention.
  • the controller that executes this method may be the controller 106 in FIG. 5. That is, the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, and a mask control module 505.
  • the codeword is stored in the manner shown in FIG. 3, that is, the data information of the codeword and the ECC check information are stored in the same memory 108.
  • the controller 106 in FIG. 6A receives the updated data position, generates updated data information according to the updated data position, encodes the updated data information ECC to generate the code word to be updated, and then corrects the code word after error correction and the required
  • the updated codeword generates a codeword C n for candidate writing.
  • the controller 106 receives the updated data location and the updated data content, and generates candidate candidates based on the corrected data information D c and the updated data content and the data location.
  • the written data information D n .
  • the ECC encoder 502 performs ECC encoding on the candidate-written data information D n to generate a candidate-written codeword C n .
  • the method provided in FIG. 7A includes the following steps:
  • step 701 the ECC decoder 501 and the control signal generation module 504 obtain the codeword C e stored in the memory 108.
  • the length of the codeword C e assume that storage is n bits.
  • Data length information stored in the D e is k bits
  • the length of the ECC parity information is stored P e nk bits.
  • the stored data information obtained by the ECC decoder 501 and the control signal generation module 504 may be shown in parameter FIG. 6B.
  • the stored data information De includes k bits, and each small cell represents one bit. One byte includes consecutive 8 bits.
  • Step 702 The candidate information generation module 503 obtains the error-corrected data information D c generated by the ECC decoder 501.
  • the ECC decoder 502 acquires code words C stored in the E, C E said codeword stored ECC decoding, the generated error correction code word C C, after the error correction code word C c includes the error-corrected data information D c and the error-corrected ECC check information P c .
  • the data information D c after error correction is shown in FIG. 7B.
  • 1 cell represents 1 bit.
  • the 3-5 bits are bits that need to be updated.
  • Step 703 The candidate information generating module 503 obtains an indication of updating data, and generates data information for candidate writing according to the indication of updating data.
  • the indication of the updated data is used to indicate the updated data content and the updated data location.
  • r is a positive integer equal to or greater than 1.
  • Step 704 The ECC encoder 502 obtains the candidate write data information D n generated by the candidate information generating module 503.
  • the candidate information generating module 503 After obtaining the updated data content and the updated data location, the candidate information generating module 503 replaces the corresponding data information Dc with the updated data content according to the updated data location.
  • the controller 106 may further include a sequence generation module 506.
  • the sequence generation module 506 obtains updated data content, and generates updated data information D f according to the updated data content.
  • the updated data information D f is a k-bit data sequence.
  • the content of the 3-5th bit is the updated data content.
  • the candidate information generating module 503 replaces the 3-5 bits in D c with the content of 3-5 bits in D f . D The data in other positions in c is retained, thereby generating the candidate write data information D n .
  • Step 705 The control signal generation module 504 and the mask control module 505 obtain the candidate written codeword C n generated by the ECC encoder 502.
  • the ECC encoder 502 performs ECC encoding on the candidate written data information D n to generate the candidate written code word C n .
  • the candidate-written codeword C n includes the candidate-written data information D n and the candidate-written ECC check information P n .
  • the ECC check information P n of the candidate write is generated by the ECC encoder 502 by performing ECC encoding according to the data information D n of the candidate write.
  • Step 706 The mask control module 505 obtains the mask control signal S generated by the control signal generation module 504.
  • a control signal generation module 504 after obtaining the candidate codeword write C n, C n in accordance with the candidate codeword and a codeword write to the C e stored in step 701 for generating the write candidate
  • the code word C n masks the control signal S.
  • the mask control module 505 generates the mask control signal S for the codeword Cn written by the candidate. Refer to the description of step 606 in the embodiment corresponding to FIG. 6A, and the details of this embodiment of the present invention are not repeated here.
  • Step 707 The mask control module 505 performs a mask operation on the candidate written codeword C n , so that the unmasked content is written into the memory 108.
  • the unmasked content includes unmasked data content and/or unmasked ECC check content.
  • the mask control module 505 After obtaining the mask control signal S generated by the control signal generation module 504, the mask control module 505 performs a mask operation on the candidate written codeword C n according to the mask control signal S.
  • the mask control module 505 may also perform a mask operation in units of one or more bytes.
  • the mask control module 505 may refer to the description of the corresponding embodiment in FIG. 6A for the mask operation in the unit of one or more bytes, and the detailed description of the embodiment of the present invention is omitted here.
  • the mask operation performed on the codeword C n written by the candidate according to the control signal S may be: the mask control module 505 masks the control signal S in the code word C n written by the candidate.
  • the bit with a value of 0 in the candidate codeword C n , or the byte with a value of 0 in all the bits in the control signal S in the code word C n of the candidate write, or the control signal in the code word C n of the candidate write S indicates that all bits in the adjacent multiple bytes are the adjacent multiple bytes with a value of 0.
  • the controller 106 writes the unmasked content of the candidate-written codeword C n into the memory 108.
  • the controller 106 processes the update, the data information D e stored after ECC correction information generating correction data D c.
  • the controller 106 generates the candidate write data information D n according to the updated data content and data position and the error-corrected data information D c, and generates the candidate write data information D n according to the candidate write data information D n
  • C n codeword masking operation controller performs the write candidate 106 pairs, the code word C n written in the candidate content masked is not written into the memory 108.
  • the present invention provides a minimal write operation for data information and corresponding ECC information to be updated.
  • the present invention performs error correction on the stored information before updating, so that the updated content is based on the corrected content, which ensures the accuracy of the updated content.
  • Fig. 8 is a flowchart of a method for updating stored information provided by an embodiment of the present invention.
  • the controller for executing this method may be the controller 106 in Fig. 5. That is, the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, a sequence generation module 506, and a combination module 507.
  • the codeword is stored in the manner shown in FIG. 4, that is, the data information of the codeword and the ECC check information are stored in different memories 108. That is, the data information and ECC check information of the same code word have different read addresses.
  • the embodiment provided in FIG. 8 is similar to that of FIG. 6A, that is, the controller 106 receives updated data content, and generates updated data information according to the updated data content.
  • the data information De and the ECC check information P e in FIG. 8 are stored in different memories 108 respectively.
  • data stored in memory information D e 108-1, ECC parity information P e is stored in the memory 108-2.
  • the controller 106 in FIG. 8 also includes a combination module 507 for combining the data information De and the ECC check information P e stored in different memories into a code word C e .
  • the method provided in Figure 8 includes the following steps:
  • Step 801 a combination module 507 acquires data stored in memory information D e of 108-1.
  • control signal generation module 504 also acquires the data stored in the information memory 108-1 D e.
  • Step 801 ' in combination with the data module 507 acquires information corresponding to the stored D e P e ECC parity information in the memory 108-2.
  • steps 801 and 801' have no order of execution.
  • Step 802 The ECC decoder 501 obtains the combined codeword C e generated by the combination module 507.
  • the combination module 507 combines the stored data information De and the stored ECC check information P e in an existing combination manner, which is not described in detail in this embodiment of the present invention.
  • Step 803 The candidate information generating module 503 obtains the error-corrected codeword C c generated by the ECC decoder 501.
  • the ECC decoder 501 decodes the combined codeword C e to generate an error-corrected codeword C c .
  • the codeword C c after error correction includes data information D c after error correction and ECC check information P c after error correction.
  • Steps 804-1 and 804-2 are the same as steps 603-1 and 603-2.
  • the embodiments of the present invention are not described in detail here.
  • Step 805 The candidate information generating module 503 obtains the updated codeword C f generated by the ECC encoder 502.
  • the ECC encoder 502 After obtaining the updated data information D f , the ECC encoder 502 performs ECC encoding on the updated data information D f to generate an updated codeword C f .
  • the updated codeword C f includes the updated data information D f and the updated ECC check information P f . ECC check the updated information to the updated P f D f data information corresponding to the ECC parity information P f.
  • Step 806 The mask control module 505 and the control signal generation module 504 obtain the candidate write data information D n generated by the candidate information generation module 503.
  • the candidate information generating module 503 After obtaining the error-corrected codeword Cc and the updated codeword Cf , the candidate information generating module 503 generates a candidate according to the error-corrected codeword Cc and the updated codeword Cf The written code word C n . Part of the content of the candidate codeword C n will be written into the memory 108.
  • the candidate-written codeword C n includes candidate-written data information D n and candidate-written ECC check information P n .
  • Step 807 The controller writes the candidate write ECC check information P n into the memory 108-2.
  • the mask control module 505 obtains the candidate write data information D n .
  • the candidate ECC check information P n is written into the memory 108-2.
  • Step 808 The mask control module 505 obtains the mask control signal S generated by the control signal generation module 504.
  • control signal generation module 504 obtains the candidate written codeword C n generated by the candidate information generation module 503, it is based on the candidate written codeword C n and the codeword C e stored in the step 601 Generate mask control signal.
  • control signal generation module 504 to the data information D n and the step 801 said candidate code word written in C n candidates included in the write data stored in the acquired information D e XORed to generate The mask control signal S.
  • the mask control signal S comprises a signal S1 for controlling the mask data information D n the candidate written.
  • the method for the control signal generation module 504 to perform XOR processing on the candidate written data information D n and the stored data information De refers to the description of the above 606, which is not described in detail in this embodiment of the present invention.
  • Step 809 the data information D n performs masking operation masks the candidate control module 505 pairs of written data D n of the candidate mask is not written contents are written to the memory 108-1.
  • the unmasked content is unmasked data content, that is, the value of the unmasked bit.
  • the mask control module 505 obtains the mask control signal S generated by the control signal generation module 504, it performs a mask operation on the candidate write data information D n according to the mask control signal S.
  • D n data mask control information of the candidate block 505 in the write mask control signal S takes A bit with a value of 0, or the mask control module 505 masks the control signal S in the candidate write data information D n indicating all bytes with a value of 0.
  • FIG. 9 is a flowchart of a method for updating stored information provided by an embodiment of the present invention.
  • the controller that executes this method may be the controller 106 in FIG. 5. That is, the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, and a combination module 507.
  • the storage method of the codeword adopts the method shown in FIG. 4, that is, the data information of the codeword and the ECC check information are stored in different memories.
  • the flow of the embodiment provided in Figure 9 is similar to that of Figure 7A.
  • the controller 106 receives the updated data content and data location, and the candidate information generation module 203 generates the updated data content and data location as well as the corrected data information.
  • Candidate write data information Compared with the embodiment provided in FIG. 7A, the data information and ECC check information in FIG. 9 are stored in different memories respectively. For example, data information is stored in the memory 108-1, and ECC verification information is stored in the memory 108-2. Therefore, before the decoder 501 performs decoding, the combination module 507 needs to first combine the stored ECC check information and data information to generate a combined codeword.
  • the method provided in Figure 9 includes the following steps:
  • Step 901 a combination module 507 acquires data stored in memory information D e of 108-1.
  • control signal generation module 504 also acquires the data stored in the information memory 108-1 D e.
  • Step 901' the combination module 507 obtains the ECC verification information P e stored in the memory 108-2 corresponding to the data information.
  • the ECC check information P e corresponding to the stored data information is simply referred to as the stored ECC check information P e .
  • the memory 108-1 and 108-2 of memory data on the same code word (such as C e) information D e P e and the ECC parity information is stored mapping.
  • Step 902 The ECC decoder 501 obtains the combined codeword C e generated by the combining module 507, and the combined codeword C e is also the stored codeword C e .
  • the combination module 507 combines the stored data information De and the stored ECC check information P e in an existing combination manner, which is not described in detail in this embodiment of the present invention.
  • Step 903 The candidate information generating module 503 obtains the error-corrected data information D c generated by the ECC decoder 501.
  • the ECC decoder 501 after obtaining the code word stored in the C e, C e of the codeword stored ECC decoding, the generated error correction code word C c.
  • the codeword C c after error correction includes data information D c after error correction and ECC check information P c after error correction.
  • Step 904 The candidate information generating module 503 obtains an indication of updating data, where the indication of updating data is used to indicate the location of the data to be updated and the content of the data in the stored data information.
  • Step 904 refers to step 703 of the method corresponding to FIG. 7A, which is not described in detail in this embodiment of the present invention.
  • steps 901, 901', and step 904 have no time sequence.
  • Step 905 The ECC encoder 502 obtains the candidate write data information D n generated by the candidate information generating module 503.
  • step 704 of the method corresponding to FIG. 7A the embodiment of the present invention will not be described in detail here.
  • control signal generation module 504 and the mask control module 505 also obtain the candidate write data information D n generated by the candidate information generation module 503.
  • Step 906 The ECC encoder 502 generates candidate write ECC verification information P n , so that the controller writes the candidate write ECC verification information P n into the memory 108-2.
  • the ECC encoder 502 performs ECC encoding on the candidate-written data information D n to generate a candidate-written codeword C n .
  • the candidate-written codeword C n includes the candidate-written data information D n and the candidate-written ECC check information P n . All the contents of the ECC check information P n that is candidate for writing are written into the memory 108-2.
  • Step 907 The mask control module 505 obtains the mask control signal S generated by the control information generation module 504.
  • Control information generation module 504 after acquiring the candidate write data D n, the information data according to the data D n and the information stored in the candidate generating a write mask control signal D e S.
  • the mask control signal S to the mask data information D n for the candidate write control signal S1.
  • Step 908 The mask control module 505 performs a mask operation on the candidate write data information D n , so that the controller 106 writes the unmasked content of the candidate write data information D n into the memory 108 -1 in.
  • step 908 refer to the description of step 808, which is not described in detail in this embodiment of the present invention.
  • the controller performs a minimized write operation for the data content to be updated and the corresponding ECC information.
  • the controller performs a minimized write operation for the data content to be updated and the corresponding ECC information.
  • Fig. 10 is a flowchart of a method for updating stored information provided by an embodiment of the present invention.
  • the controller that executes this method may be the controller 106 in FIG. 5. That is, the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, a sequence generation module 506, and a combination module 507.
  • the storage method of the codeword is as shown in Figure 4, that is, the data information of the codeword and the ECC verification information are stored in different memories.
  • the embodiment provided in FIG. 10 is similar to the embodiment corresponding to FIG. 6A and FIG. 8, that is, the controller 106 receives updated data content, and generates updated data information according to the updated data content.
  • the ECC check information and data information in the embodiment corresponding to FIG. 10 are stored in different memories.
  • the controller 508 in the embodiment provided in FIG. 10 not only masks the data information D n written by candidates, but also masks the ECC check information P n written by candidates operating.
  • the method provided in Figure 10 includes the following steps:
  • Steps 1001, 1001', and 1002 are the same as steps 801, 801', and 802, and will not be described in detail in the embodiment of the present invention.
  • control signal generation module 504 also obtains the combined codeword C e generated by the combination module 507.
  • Step 1003 The candidate information generating module 503 obtains the error-corrected data information D c generated by the ECC decoder 501.
  • step 1003 For a detailed description of step 1003, refer to step 602, and the embodiment of the present invention will not be described in detail here.
  • steps 1004-1 and 1004-2 are the same as the descriptions of steps 804-1 and 804-2, which are not described in detail in this embodiment of the present invention.
  • Step 1005 The candidate information generating module 503 obtains the updated codeword C f generated by the ECC encoder 502.
  • the ECC encoder 502 performs ECC encoding on the updated data information D f to generate an updated codeword C f .
  • the updated codeword C f includes updated data information D f and updated ECC check information P f .
  • ECC check the updated information for the ECC parity information P f P f and the updated data corresponding to the information D f.
  • steps 1002 and 1005 have no time sequence.
  • Steps 1006-1007 are the same as steps 605-606, and are not described in detail in the embodiment of the present invention.
  • the mask control signal S generated in step 1007 includes a mask control signal S1 for the data information written by the candidate and a mask control signal S2 for the ECC check information written by the candidate.
  • Step 1008 The mask control module 505 performs a mask operation on the candidate write data information D n , so that the unmasked content in the candidate write data information D n is written into the memory 108-1 .
  • step 1008 is the same as that of step 808, which is not described in detail in this embodiment of the present invention.
  • Step 1009 the ECC parity information P n performs masking operation masks the candidate control module 505 pairs written, so that the ECC parity information writing candidate P n is not written to the memory contents of the mask 108-2.
  • the mask control module 505 obtains the mask control signal S sent by the control signal generation module 504, it is based on the mask of the ECC check information for the candidate write contained in the mask control signal S.
  • ECC parity information P n performs a masking operation control signal S2 to write the candidate, the candidate is written such that the information P n ECC check not mask the contents are written to the memory 108-2. .
  • the masking operation performed on the codeword C n of the candidate write according to the control signal S may be: the mask control module 505 shields the ECC check information P n of the candidate write.
  • the mask control signal S2 indicates a bit of 0, or the mask control module 505 masks the control signal S2 in the candidate write ECC check information P n to indicate all bytes with a value of 0.
  • the controller 106 performs ECC error correction on the stored data and then combines with the updated data information Df, and then masks and writes. Reduce the amount of written data, reduce the time and power consumption of the write operation.
  • Fig. 11 is a flowchart of a method for updating stored information provided by an embodiment of the present invention. That is, the controller that executes the method may be the controller 106 in FIG. 5. That is, the controller 106 includes an ECC decoder 501, an ECC encoder 502, a candidate information generation module 503, a control signal generation module 504, a mask control module 505, and a combination module 507.
  • the storage method of the codeword is as shown in FIG. 4, that is, the data information of the codeword and the ECC check information are stored in different memories 108.
  • the flow of the embodiment provided in Fig. 11 is similar to the embodiment corresponding to Fig. 7A and Fig. 9, that is, the controller 106 receives updated data content and data location, and the candidate information generating module 203 is based on the updated data content and data location. And the data information after error correction generates data information for candidate writing.
  • the ECC check information and data information in the embodiment corresponding to FIG. 11 are stored in different memories 108.
  • the controller 508 in the embodiment shown in FIG. 11 not only masks the data information D n written by the candidate, but also masks the ECC check information P n written by the candidate. Code processing, so that less data is written into the memory 108.
  • the method provided in Figure 11 includes the following steps:
  • Steps 1101, 1101', and 1102 are the same as steps 801, 801', and 802, and will not be repeated in this embodiment of the present invention.
  • control signal generation module 504 also obtains the combined codeword C e generated by the combination module 507.
  • Step 1103 The candidate information generating module 503 obtains the error-corrected data information D c generated by the ECC decoder 501.
  • step 1103 For a detailed description of step 1103, refer to step 602, which is not described in detail in the embodiment of the present invention.
  • Step 1104 The candidate information generating module 503 obtains updated data content and location, where the updated data content is used to update the content of the corresponding location in the stored data information.
  • Step 1104 refers to step 703 of the method corresponding to FIG. 7A, which is not described in detail in this embodiment of the present invention.
  • Step 1105 The ECC encoder 502 obtains the candidate write data information D n generated by the candidate information generating module 503.
  • step 704 of the method corresponding to FIG. 7A the embodiment of the present invention will not be described in detail here.
  • Steps 1106-1107 are the same as steps 705-706, which are not described in detail in this embodiment of the present invention.
  • steps 1108 and 1109 are the same as the descriptions of steps 1008 and 1009, which are not described in detail in this embodiment of the present invention.
  • the controller 106 when the controller 106 updates the data, it performs ECC error correction on the acquired data, then combines it with the updated data sequence D f , and then masks the write. Reduce the amount of written data, reduce write operation time and power consumption.
  • each module in the controller 106 executes the steps shown in FIG. 6, FIG. 7A, and FIG. 8-11, it can be executed in a software-defined manner or can be executed in hardware.
  • a candidate information generating circuit (such as a combination circuit or an exclusive OR circuit) generates data information for candidate writing.
  • the control signal is generated by a control signal generating circuit (such as an exclusive OR circuit).
  • the mask operation is performed by the mask control circuit.
  • Encoders and decoders can also be implemented by means of circuits.
  • the exclusive OR circuit can be an XOR circuit.
  • the controller 106 may also have the structure of the controller in FIG. As shown in FIG. 12, the controller 106 includes a memory interface circuit 1501, a processing circuit 1502, and a processor interface circuit 1503.
  • the processor interface circuit 1503 provides an interface between the controller 106 and the processor 110.
  • the controller 106 receives a request from the processor 110 through the processor interface circuit 1503, and sends the processing result of the request to the processor 110.
  • the memory interface circuit 1501 provides an interface between the controller 106 and the memory 108. Through the memory interface circuit 1501, commands and addresses are transmitted from the controller 106 to the memory 108, and data is exchanged between the controller 106 and the memory 108. In addition, the information stored in the memory 108 is transferred to the controller 106 through the memory interface circuit 1501.
  • the processing circuit 421 obtains and executes the instructions of the processor 110 in FIG. 1 through the processor interface circuit 450, and executes all the functions performed by the controller 106 in FIGS. 2, 6A, 7A, and 8-11.
  • FIG. 13 is a schematic diagram of another structure of an apparatus including a controller provided by an embodiment of the present invention.
  • the device is used to implement a method for updating stored information.
  • the apparatus 1300 may include at least a processor 1302, a controller 106, and a memory 108. Different from the device 100 shown in FIG. 1, in the device 1300 shown in FIG. 13, the controller 106 and multiple processor cores 1304 are integrated in the processor 1302. It should be noted that, in addition to the devices shown in FIG. 13, the computer system 1300 may also include other devices such as a communication interface and a magnetic disk as an external memory, which is not limited here.
  • the processor 1302 is the computing core and the control core (Control Unit) of the computer system 1300.
  • the processor 1302 may be a chip, such as a system on chip (SOC).
  • the chip 102 may also include multiple processor cores (cores) 104.
  • the processor 1302 may also be a very large-scale integrated circuit.
  • the processor core 104 implements access to the memory 108, cache, and disk through the operating system and other software programs. It is understandable that, in this embodiment of the present invention, the Core 1304 in the processor 1302 may be a central processing unit (CPU), or may also be another specific integrated circuit (ASIC).
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the controller 106 is a bus circuit controller that the device 1300 controls the memory 108 and is used to manage and plan data transmission from the memory 108 to the Core 1304. Through the controller 106, the memory 108 and the Core 1304 can exchange data.
  • the controller 106 may be a separate chip and is connected to the Core 1304 through the system bus.
  • the controller 106 may also be integrated into the processor 1302 (as shown in FIG. 13), or it may be built in other chips.
  • the controller 106 is used to perform any steps performed by the controller 106 in FIGS. 6A, 7A, and 8-11.
  • the controller 106 in FIG. 13 may also adopt any structure of FIG. 2, FIG. 3 or FIG. 12.
  • the memory 108 may be a DRAM 108 and includes multiple channels 1310. Each channel 1310 may include at least one rank, and each rank may include at least one bank. Those skilled in the art may know that rank refers to memory chips connected to the same chip select signal.
  • the controller 106 can write to the chips in the same rank, and the chips in the same rank also share the same control signal.
  • the controller 106 can access the data in the Rank in each channel in the DRAM 108 through the memory bus.
  • the memory 108 shown in FIG. 1 and FIG. 13 is placed outside the processor.
  • the one or more memories 108 may also be integrated in the processor (such as the memory in the SOC chip), and the controller 106 realizes the storage of the memory by controlling the memory 108 integrated in the processor.
  • Information update method is used to control the memory 108 integrated in the processor.
  • FIG. 14 is a schematic diagram of another structure of an apparatus for performing controller functions provided by an embodiment of the application.
  • the device 1400 includes a processor 1401, a communication line 1402, a memory 1403 and at least one communication interface 1404.
  • the processor 1401 may be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the execution of the program of this application. integrated circuit.
  • the processor 1401 may perform any function performed by the aforementioned controller.
  • the communication line 1402 may include a path to transmit information between the aforementioned components.
  • Communication interface 1404 which uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc. .
  • RAN radio access network
  • WLAN wireless local area networks
  • the memory 1403 may be a memory, such as a read-only memory ROM, a random access memory RAM, a flash memory, and the like.
  • the memory may exist independently and is connected to the processor 1401 through a communication line 1402.
  • the memory 1403 may also be integrated with the processor 1401.
  • the memory 1403 is used to store computer-executable instructions for executing the solutions of the present application, and the processor 1401 controls the execution.
  • the processor 1401 is configured to execute computer-executable instructions stored in the memory 1403, so as to implement the method for updating stored information provided in the foregoing embodiment of the present application.
  • the computer-executable instructions in the embodiments of the present application may also be referred to as application program code, which is not specifically limited in the embodiments of the present application.
  • the controller 106 is presented in the form of dividing various functional modules in an integrated manner.
  • the "module” here can refer to application-specific integrated circuits (ASICs), circuits, processors and memories that execute one or more software or firmware programs, integrated logic circuits, and/or other functions that can provide the aforementioned functions Device.
  • ASICs application-specific integrated circuits
  • the controller 106 may adopt any of the forms shown in FIG. 2, FIG. 3, or FIG. 14.
  • the controller 106 may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • a software program it may be implemented in the form of a computer program product in whole or in part.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless means.
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)

Abstract

本申请实施例提供对存储的信息更新的方法和装置。控制器根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息。控制器根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息。控制器根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作，将所述候选写入的数据信息中未掩码的内容写入到内存中。通过本方法，使得候选写入的数据信息中只有没有被掩码的内容需要被写入，从而节省了因为更新数据内容的写入操作的功耗及时延。

Description

对存储信息更新的方法和装置 技术领域
本申请涉及通信技术领域，尤其涉及对存储的信息更新的方法和装置。
背景技术
在计算机领域中，内存是计算机系统的重要组成部分。计算机系统中内存的种类比较多，如随机存储器(random access memory,RAM)、闪存Flash及只读存储器(read only memorty,ROM)等。RAM是最为常见的系统内存，可以随机地对存储单元进行读出和写入操作。根据数据存储方式，RAM可以分为静态随机存取存储器(static RAM,SRAM)和动态随机存取存储器(dynamic RAM,DRAM)。
内存在使用的过程中，受到电路自身影响或者外界干扰,所存储的比特会出现比特翻转导致存储的数据错误。比特翻转是指，写入内存中的正确数据经过一段时间后可能会发生变化，使得正确的数据变为了错误的数据。
针对内存的上述缺陷，目前釆用错误校验码(Error Correcting Code,ECC)的校验机制，对内存中存储的数据进行错误检测及纠正。每当数据写入内存时，ECC使用ECC编码算法对数据进行计算，生成所述数据信息的ECC校验信息。所述数据信息的ECC校验信息简称为ECC校验信息，或校验信息。当写入内存的数据信息从内存中读出时，ECC译码器可以结合所述ECC校验信息采用ECC译码算法进行纠错操作，生成纠错后的数据信息。
传统的对已存储在内存中的数据进行更新方式包括：读出存储的数据信息进行ECC译码后并根据ECC译码生成的纠错后的数据信息进行更新；然后将更新的且包含了ECC纠错后的数据信息进行ECC编码，生成写入的数据信息和写入的ECC校验信息，将编码后生成的所述写入的数据信息和写入的ECC校验信息代替已存储的数据信息和ECC校验信息写入内存。因此，在对存储在内存中的码字(code-word)中数据信息进行更新时，写入内存中的信息为基于一次读出的存储的码字和更新的信息的全部数据信息。但是可能内存中所述存储的码字只有少数的数据(比如1比特或几比特)需要更新，大部分数据可能不需要重新进行写入操作。如果将码字的数据全部重新写入，不但会使得执行写操作过程中会浪费功耗，而且会增加写操作所需的时间。
发明内容
本申请实施例提供了对存储的信息更新的方法和装置，可以实现在对已存储在内存中的数据进行更新时，只需写入与已存储在内存中码字的数据信息不同的数据内容，而不需要将所述码字的数据信中已存储在内存中的所有的数据内容再次写入内存，从而可以减少写入时功耗的浪费以及执行写入操作的时间。
为达到上述目的，本申请实施例提供如下技术方案：
第一方面，本申请实施例提供一种对存储的信息更新的方法。控制器根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息。控制器根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息。控制器根据所述存储的数据信息对所述候选 写入的数据信息执行掩码操作。所述控制器将候选写入的数据信息中未掩码的内容写入到内存。通过本方法，使得写入的数据信息为所述候选写入的数据信息中没有被掩码的数据内容，而对于所述候选写入的数据信息中被掩码掉的数据内容不会写入到内存中，从而节省了因为更新数据内容的写入操作的功耗及时延。此外，本发明在写入信息前对已存储的信息进行了纠错，使得更新的内容基于纠错后的内容，保证了更新内容的准确性。
一种可能的实现方式中，所述更新数据的指示用于指示所述存储的数据信息中需更新的数据位置，所述控制器进一步根据所述更新数据的指示生成更新的数据信息。所述根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息包括：根据所述纠错后的数据信息和所述更新的数据信息生成所述候选写入的数据信息。通过本方法，只需指明需更新的位置，即可完成更新，使得更新更为灵活。
一种可能的实现方式中，所述根据所述纠错后的数据信息和更新的数据信息生成候选写入的数据信息包括：对所述纠错后的数据信息和所述更新的数据信息执行异或处理，生成所述候选写入的数据信息。通过异或处理生成所述候选写入的数据信息，使得操作简单。
一种可能的实现方式中，所述更新数据的指示用于指示更新的数据内容和更新的数据位置，所述根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息包括：根据所述更新的数据位置，使用所述更新的数据内容替换所述纠错后的数据信息中相同位置的数据内容。通过提供另一种更新数据指示，以及通过替换的方式生成所述候选写入的数据信息，使得更新更为灵活。
一种可能的实现方式中，所述控制器进一步对所述存储的数据信息和所述候选写入的数据信息执行异或处理，生成针对所述候选写入的数据信息的掩码控制信号，并根据所述针对所述候选写入的数据信息的掩码控制信号对所述候选写入的数据信息执行掩码操作。通过掩码操作，使得写入的数据信息更少，节省写入时间和消耗。
一种可能的实现方式中，所述控制器组合所述存储的数据信息和所述存储的ECC校验信息，生成存储的码字。通过本方法，为数据信息和ECC校验信息分开存储提供解决方案。
一种可能的实现方式中，所述控制器对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息，以及将所述候选写入的ECC校验信息写入到所述内存中。通过本方法，使得所述候选的ECC校验信息也被写入到所述内存中，有利于更新后的数据信息使用ECC校验信息进行校验，保证信息的准确。
一种可能的实现方式中，所述纠错后的码字进一步包括纠错后的ECC校验信息，所述控制器进一步根据所述纠错后的ECC校验信息和更新的ECC校验信息生成候选写入的ECC校验信息；根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作，以及将所述候选写入的ECC校验信息中未掩码的内容写入到内存中。通过本方法，对候选写入的ECC校验信息也进行掩码操作，减少写入的时间和消耗。
一种可能的实现方式中，所述控制器进一步对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息，以及根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作。所述控制器将所述候选写入的ECC校验信息中未掩码的内容写入到内存中。通过本方法，对候选写入的ECC校验信息也进行掩码操作，减少写入的时间和消耗。
一种可能的实现方式中，所述根据所述纠错后的ECC校验信息和更新的ECC校验信息生成候选写入的ECC校验信息包括：对所述纠错后的ECC校验信息和所述更新的ECC 校验信息执行异或处理，生成候选写入的ECC校验信息。
一种可能的实现方式中，所述控制器进一步对所述候选写入的ECC校验信息和所述存储的ECC校验信息进行异或处理，生成针对所述候选写入的ECC校验信息的掩码控制信号，所述根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作包括：根据所述针对所述候选写入的ECC校验信息的掩码控制信号对所述候选写入的ECC校验信息执行掩码操作。通过本方法，对候选写入的ECC校验信息也进行掩码操作，减少写入的时间和消耗。
第二方面，本发明实施例提供一种装置，该装置包括控制器和内存。所述内存用于存储数据信息和与所述数据信息对应的错误校验码(ECC)校验信息。所述控制器用于执行上述第一方面控制器执行的任何步骤。
第三方面，本发明实施例提供一种芯片，该芯片包括核心处理器和控制器。所述核心处理器用于通过所述控制器与内存交换数据。所述控制器用于执行上述第一方面控制器执行的任何步骤。
一种可能的实现方式中，所述芯片进一步包括内存，所述内存用于存储数据信息和与所述数据信息对应的错误校验码(ECC)校验信息。
第四方面，本发明实施例提供一种控制器。所述控制器包括处理电路和内存接口电路。所述内存接口电路用于提供所述控制器和内存之间的接口。所述处理电路用于通过所述内存接口电路与的内存交互，并执行上述第一方面控制器执行的任何步骤。
第五方面，本发明实施例提供一种装置。所述装置包括处理器和存储器。所述存储器用于存储计算机执行指令；所述处理器用于当该装置运行时，执行所述存储器存储的该计算机执行指令，以使该装置执行上述第一方面控制器执行的任何步骤。
第六方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机可以执行上述第一方面中任意一项所述的数据信息的生成方法。
第七方面，本发明实施例提供了一种装置，该装置包括错误校验码(ECC)译码器、候选信息生成模块和掩码控制模块。所述ECC译码器用于根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的数据信息。所述候选信息生成模块用于根据所述纠错后的数据信息和更新的数据信息生成候选写入的数据信息。所述掩码控制模块根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作，使得所述候选写入的数据信息中未掩码的内容被写入到内存中。
第八方面，本发明实篱例提供了一种计算机程序产品，当该计算机产品被执行时，其用于执行上述方面所述的方法。
通过本发明实施例上述各方面的方法，针对需更新的数据内容，控制器对存储的数据信息进行纠错后再与更新的数据信息进行异或处理，并执行掩码操作生成写入的据信息数，使得写入的数据信息为所述候选写入的数据信息中没有被掩码的数据内容，而对于所述候选写入的数据信息中被掩码掉的数据内容不会写入到内存中，从而节省了单次因为更新数据内容的写入操作的功耗及时延。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为本发明实施例提供的装置的结构示意图；
图2为本申请实施例提供的对存储的信息更新的方法流程图；
图3为本申请实施例提供的在同一内存中存储的数据信息和ECC校验信息的示意图；
图4为本申请实施例提供的在不同内存中分别存储的数据信息和ECC校验信息的示意图；
图5为本申请实施例提供的控制器结构示意图；
图6A为本申请实施例提供的对存储的信息更新的方法的流程示意图；
图6B为本申请实施例提供的存储的数据信息D e的示意图；
图6C为本申请实施例提供的更新的数据信息D f的示意图；
图6D为本申请实施例提供的根据掩码控制信号进行掩码操作并写入数据的示意图；
图6E为本申请实施例提供的根据掩码控制信号进行掩码操作并写入数据的另一示意图；
图7A为本申请实施例提供的对存储的信息更新的方法的另一流程示意图；
图7B为本申请实施例提供的根据纠错的数据信息和更新的数据信息生成候选写入的数据信息的示意图；
图8为本申请实施例提供的对存储的信息更新的方法的另一流程示意图；
图9为本申请实施例提供的对存储的信息更新的方法的另一流程示意图；
图10为本申请实施例提供的对存储的信息更新的方法的另一流程示意图；
图11为本申请实施例提供的对存储的信息更新的方法的另一流程示意图；
图12为本申请实施例提供的控制器的另一结构示意图；
图13为本申请实施例提供的包括控制器的装置的另一结构示意图；
图14为本申请实施例执行控制器功能的装置的另一结构示意图。
具体实施方式
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
在本发明实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本发明实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本发明实施例中数据信息指k比特的数据序列。ECC校验信息为p比特的数据序列。码字为n比特的数据序列。其中，n比特等于k比特加p比特。本发明实施例的数据内容，指特定比特的取值。本发明实施例中的数据位置指在数据信息、ECC校验信息或码字中的比特的位置，如第1比特，第3比特。更新的数据内容指需要更新的比特对应的取值，如针对第3比特和第5比特的取值，如0或1。
本发明实施例，在对存储在内存中的数据信息进行部分更新的场景下，由控制器对存储在内存中的数据信息进行ECC译码后生成纠错后的数据信息。所述控制器根据纠错后的数据信息和更新数据的指示(比如更新的数据位置，或更新的数据内容和位置)生成候选写入的数据信息。所述控制器根据存储的数据信息和所述候选写入的数据信息，确定实际需要更新的比特或字节，以及将所述候选写入的数据信息中所述确定的比特或字节写入到内存 中。通过本方法，避免了将所述候选写入的数据信息的所有内容全部写入到内存中，减少了对已存储的数据信息进行更新时的写入操作的功耗和时延。
作为一个例子，包含ECC校验信息的码字C e为72比特，码字C e包括64比特的数据信息D e和8比特的ECC校验信息P e。所述控制器在对所述存储的数据信息D e进行更新时，如更新其中1个或2个比特，根据ECC校验信息P e对存储的数据信息D e进行ECC译码生成的纠错后的数据信息，再根据更新的1个或2个比特的信息和所述纠错后的数据信息生成64比特的候选写入的数据信息D n。所述控制器根据存储的数据信息D e和所述候选写入的数据信息D n确定实际需要更新的比特或字节(比如只需更新的1个或2个比特的值，或更新的1个或2个比特的值以及在ECC译码时被纠错的比特的值)。因此，只有所述确定的1或2个比特(或字节)的值需要写入内存中，而不需将整个候选写入的数据信息D n的64个比特的全部内容都写入内存中，减少写入操作的功耗和时延。
图1为本发明实施例提供的用以对存储的信息更新的装置的架构示意图。如图1所示，装置100至少可以包括控制器106，处理器110和至少一个内存108。控制器106通过系统总线与处理器110和内存108进行数据交换。
在本实施例中，控制器106可以与处理器110集成在同一芯片，控制器106也可以是单独的芯片。控制器106、处理器110和内存108也可以集成在同一芯片。控制器106可实现对存储在内存中的数据信息和ECC校验信息进行控制和读写。需要说明的是，本发明实施例提供的装置中，除了图1所示的器件外，装置100还可以包括通信接口以及作为外存的磁盘等其他器件，在此不做限制。
处理器110为控制器106提供计算和处理能力，以及能够对内存108、缓存及磁盘的访问实现。
控制器(Controller)106用于控制内存108以及管理与规划从内存108到处理器110间的数据传输的总线电路控制器。控制器106可以由硬件实现，也可以由软件来实现。实际应用中，控制器106可以控制必要的逻辑以将数据写入内存108或从内存108中获取数据。
一个或多个内存108。内存108是装置100的主存。内存108通常用来存放操作系统中各种正在运行的软件、输入和输出数据以及与外存交换的信息等。处理器110能够通过控制器106访问内存108，对内存108进行读操作和写操作。一个或多个内存108用于存储数据信息以及存储所述数据信息的ECC校验信息。所述数据信息和ECC校验信息可如图3所示存储在同一个内存中，还可以如图4所示分别存储在不同的内存中。内存108可以是RAM、Flash、ROM等。
图2为本发明实施例提供的一种对存储的信息更新的方法流程图。执行该方法的控制器可以为图1中的控制器106。该方法包括：
步骤202、控制器106获取存储在内存108中的数据信息和ECC校验信息。
所述数据信息和ECC校验信息可以存储在一个内存108中，也可以存储在不同的内存108中。
步骤204、控制器106对所述存储的数据信息和ECC校验信息进行ECC译码，生成纠错后的数据信息。
步骤206、控制器106接收更新数据的指示，以更新存储在内存108中的数据信息。
所述更新数据的指示用于指示所述存储的数据信息中需更新的数据位置(比如指 示第几比特需要更新)。或所述更新的数据指示用于指示更新的数据内容和更新的数据位置(比如指示需更新的比特位置和取值)。
步骤208、控制器106根据所述纠错后的数据信息和所述更新数据的指示生成候选写入的数据信息。
控制器106可以对所述纠错后的数据信息和所述更新的数据信息执行异或处理，生成所述候选写入的数据信息。或控制器106根据所述更新的数据位置，使用所述更新的数据内容替换所述纠错后的数据信息中相同位置的数据内容，生成所述候选写入的数据信息。
步骤210、控制器106根据所述存储的数据信息和所述候选写入的数据信息，确定实际需要更新的比特或字节；
所述确定实际需要更新的比特或字节可以为：控制器106根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作，所述候选写入的数据信息中没有被掩码的内容为实际需要更新的比特或字节。所述确定实际需要更新的比特或字节还可以为：控制器106比如所述存储的数据信息和所述候选写入的数据信息，所述候选写入的数据信息中与所述存储的数据信息取值不同的比特或字节为实际需要更新的比特或字节。
步骤212、控制器106将所述候选写入的数据信息中所述确定的实际需要更新比特或字节写入到内存中。
在图2对应的方法实施例中，控制器106对所述存储的数据信息进行纠错生成纠错后的数据信息，再根据所述纠错后的数据信息与更新数据的指示生成候选写入的数据信息，并根据所述存储的数据信息对所述候选写入的数据信息确定实际需要更新的比特或字节，将所述所述确定的比特或字节的内容写入到内存中。本发明实施例针对需更新的数据信息，进行最小化的写入操作。在存储的数据信息中只有几个比特甚至一个比特需要更新的场景下，无需更新存储的数据信息中的所有比特的内容，节省了单次写入操作的功耗及时延。此外，本发明在写入信息前对已存储的信息进行了纠错，使得更新的内容基于纠错后的内容，保证了更新内容的准确性。
图3为本发明实施例提供的内存108存储的码字(code-word)的形式。码字包含数据信息以及该数据信息的ECC校验信息。同一码字的数据信息以及该数据信息对应的ECC校验信息存储于同一个内存108中。比如，所述数据信息以及该数据信息对应的ECC校验信息具有相同的读写地址，控制器106可以通过所述读写地址一次性获取所述数据信息和对应的ECC校验信息。图1中的内存108可以为图3的形式，同一码字的数据信息102和ECC校验信息104存储在同一个内存中。
图4为本发明实施例提供的存储的码字的另一种可选方式。在此种可选方式中，码字的数据信息和对应的ECC校验信息存储在不同的内存108之中。比如，内存108-1中存储码字的数据信息，内存108-2存储码字的ECC校验信息。也即数据信息和ECC校验信息具有不同的读写地址。装置100中存储有数据信息和ECC校验信息在不同内存中的存储地址的映射表，或在不同内存中的存储地址(如数据信息的存储地址和ECC校验信息的存储地址)和码字的映射关系表。比如在装置100中的硬盘或flash中存储数据信息和ECC校验信息的存储地址的映射表。控制器106根据所述映射表分别读取所述数据信息和与所述数据信息对应的ECC校验信息。图1的装置示意图中，码字的存储也可以采用图4中的形式，即同一码字的数据信息和所述ECC校验信息存储在不同的内存108中。
图5为本发明实施例提供的控制器的结构示意图。如图5所示，控制器106包含ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控 制模块505、序列生成模块506和组合模块507。控制器106可以是图1中的控制器。
ECC译码器501用于根据存储的数据信息和存储的ECC校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息；
候选信息生成模块503用于根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息；
掩码控制模块505根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作，所述候选写入的数据信息中未掩码的内容被写入到内存中。
进一步的，控制器106中的各模块可以执行图6A、图7A、图8-图11以及上述图4的方法流程中的控制器106的相应模块执行的步骤。
图6A为本发明实施例提供的对存储的信息更新的方法流程示意图。执行该方法的控制器可以为图4或图5中的控制器106。即执行图6A中方法的控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控制模块505以及序列生成模块506。该方法中，码字的存储方式采用图3示意的方式，即码字的数据信息和ECC校验信息储存在同一个内存108中。
在图6A提供的实施例中，控制器106根据更新内容的指示生成更新的码字C f，将根据纠错后的码字C c与所述更新的码字C f生成候选写入的码字C n。然后控制器106根据存储的码字C e对候选写入的码字C n进行掩码操作，将所述候选写入的码字C n中未掩码的内容写入到内存108中。该方法包括如下步骤：
步骤601、ECC译码器501以及控制信号生成模块504获取存储在内存108中的码字C e。所述存储在内存108中的码字简称存储的码字C e。
所述存储的码字C e包含存储的数据信息D e以及与数据信息对应的ECC校验信息P e，即C e＝[D e P e]。
值得说明的是，本发明实施例中的获取可以是读取、主动获取、或接收。
作为一个例子，假设存储的码字C e的长度为n比特。所述存储的数据信息D e的长度为k比特，存储的ECC校验信息P e的长度为p比特。即n＝k+p。
所述存储的数据信息D e可以参考图6B所示。在图6B中，存储的数据信息D e包括k个比特，每一个小格代表一个比特。一个字节包括连续的8个比特。
步骤602、候选信息生成模块503获取ECC译码器501生成的纠错后的码字C c。
ECC译码器501在获取所述存储的码字C e后，对所述存储的码字C e进行ECC译码，生成纠错后的码字C c。所述纠错后的码字C c包括纠错后的数据信息D c和纠错后的ECC校验信息P c。所述纠错后的ECC校验信息为所述纠错后的数据信对应的ECC校验信息。
步骤603-1、序列生成模块506获取更新数据的指示，并根据所述更新数据的指示生成需要更新的数据信息。所述更新数据的指示用于指示所述存储的码字C e中需要更新的数据位置。
内存108中所述存储的码字C e的数据需要更新时，可能只需要更新所述存储的码字C e中部分比特(比如一个或几个比特)的取值。序列生成模块506获取所述更新数据的指示，根据所述更新的数据位置生成更新的数据信息D f。所述更新的数据信息D f为与所述存储的数据信息D e长度相同的比特序列，即所述更新的数据信息D f为长度等于k的比特序列。所述D f中取值为1的比特指示了需要更新的数据位置，比如存储的数据信息D e中第1个比特、第3个比特等。如图6C所示，如果存储的数据信息D e的第3-5个比特的取值需要更新，其他比特不需要更新，在所述更新的数据信息D f中，序列生成模块506将需更新的比特设置 为1，不更新的比特设置为0。则更新的数据信息D f为[0,0,1,1,1,0,…,0]。
值得说明的是，步骤601和603-1没有时间的先后顺序。
步骤603-2、ECC编码器502获取所述更新的数据信息D f。所述更新的数据信息D f为长度等于k的比特序列。所述更新的数据信息D f中取值为1的比特为在存储的码字C e中需要更新的比特。
值得说明的是，步骤601和603-2没有时间的先后顺序。
步骤604、候选信息生成模块503获取ECC编码器502生成的更新的码字C f。
ECC编码器502获取所述更新的数据信息D f后，对所述更新的数据信息D f进行ECC编码，生成更新的码字C f。所述更新的码字C f包括更新的数据信息D f和更新的ECC校验信息P f。所述更新的ECC校验信息P f为所述更新的数据信息D f对应的ECC校验信息P f。
值得说明的是，步骤602和604没有时间的先后顺序。
步骤605、掩码控制模块505以及控制信号生成模块504获取候选信息生成模块503生成的候选写入的码字C n。
在ECC译码器501生成所述纠错后的码字C c以及ECC编码器502生成所述更新的码字C f后，候选信息生成模块503根据所述纠错后的码字C c以及所述更新的码字C f生成候选写入的码字C n。所述候选写入的码字C n的部分内容会被写入到内存108中。所述候选写入的码字C n包含候选写入的数据信息D n和候选写入的ECC校验信息P n。
作为一个例子，候选信息生成模块503可对所述纠错后的码字C c以及所述更新的码字C f执行异或处理，生成所述候选写入的码字C n。即C n＝C f^C c。异或是一种逻辑运算，在执行异或处理a和b(如a^b)时,对a和b的数据序列进行逐比特位比较。如果a、b两个数据在相同比特位的值不同，则异或结果为1。如果a、b两个值相同，异或结果为0。比如，a＝[0011110101],b＝[0000111000],a^b＝[0011001101]。因此，在C f^C c时，C f和C c的相同比特位的值如果相同，由Cn在对应比特的取值为0，反之取值为1。
步骤606、掩码控制模块505获取控制信号生成模块504生成的掩码控制信号S。
控制信号生成模块504在获取候选信息生成模块503生成的所述候选写入的码字C n后，根据所述候选写入的码字C n与所述存储的码字C e生成针对所述候选写入的码字C n的掩码控制信号S。
比如，控制信号生成模块504对所述候选写入的码字C n与所述步骤601中存储的码字C e进行异或处理，生成掩码控制信号S。即S＝C n^C e。所述掩码控制信号简称控制信号。所述掩码控制信号S可用于对候选写入的码字C n执行掩码操作。所述掩码操作指对一串二进制数字，通过与目标数字(即所述候选写入的码字C n)的按位操作，屏蔽当前的输入位。进一步的，所述针对候选写入的码字C n的掩码控制信号S包括针对候选写入的数据信息D n的掩码控制信号S1和针对所述候选写入的ECC校验信息P n的掩码控制信号S2。
所述针对候选写入的码字C n的掩码控制信号S为长度等于n的比特序列，用于指示对具有相同长度的所述候选写入的码字C n执行掩码操作。控制信号生成模块504在对所述候选写入的码字C n与所述存储的码字C e执行处理时(比如异或处理)时，比较所述候选写入的码字C n和所述存储的码字C e。如C n相同位置的数值与C e相同位置的数值相同，则控制信号S的相应位置的内容为0。如C n相同位置的数值与C e相同位置的数值不同，则控制信号S的相应位置的内容为1。
可参考图6D所示，所述候选写入的码字C n的长度为n比特，包括k比特的数据信息，p比特的ECC校验信息。图6D中的掩码控制信号S的长度也为n比特。图6D中所 示的掩码控制信号S中，内容为1的比特指示对于所述候选写入的码字的相应比特不执行掩码操作。内容为0(图中未示出)的比特指示对于所述候选写入的码字的相应比特执行掩码操作。根据图6D中所示的掩码控制信号S，掩码控制模块505对所述候选写入的码字C n的第1比特和第5比特的不执行掩码操作，而对所述候选写入的码字C n的其它比特执行掩码操作。
步骤607、掩码控制模块505对所述候选写入的码字C n执行掩码操作，以使得所述候选写入的码字C n中未掩码的内容被写入内存108中。
所述未掩码的内容包括所述候选写入的码字C n中未掩码的数据内容和/或未掩码的ECC校验内容。所述掩码控制模块505在获取控制信号生成模块504生成的掩码控制信号S后，根据所述掩码控制信号S对所述候选写入的码字C n执行掩码操作。掩码(data mask)技术，可以屏蔽指定位(比如比特或字节)从而达到按位(如比特或字节)操作。所述掩码操作指一串二进制数字，通过与目标数字的按位操作，屏蔽当前的输入位。
掩码控制模块505根据图6D的掩码控制信号S对所述候选写入的码字C n进行掩码操作。如果掩码控制信号S的相应位置(如比特)的内容为为0，则对所述候选写入的码字C n的相应位置执行掩码操作。即所述候选写入的码字C n中的相应位置的内容被屏蔽，不需要写入到存储模块中。如果控制信号S中内容为1的位置，所述候选写入的码字C n中的相应位置的内容不被屏蔽，需要写入到内存108中。仍以图6D为例，控制信号S中的第1,5比特的取值为1，其他比特的取值为0(图中未示出)。所述候选写入的码字C n中的除第1和5个比特以外的比特的内容都被掩码，不用存储到所述存储的码字C e的相应位置中。只有第1和第5个比特的内容需要写入到内存中。
仍以图6D为例，所述n比特的更新后的码字C u中的第1和第5比特的数据内容为写入的更新的数据内容。所述更新后的码字C u的其它位置仍然是所述存储的码字C e的相应位置的信息。因此，通过本方法，当对存储的数据进行部分更新时，只需写入少量的更新的比特(如第1和第5比特)，节省了写入的时间和功耗。
作为另一种可选方式，掩码控制模块505还可以以字节为单位执行掩码操作。掩码控制模块505在收到控制信号生成模块504生成的控制信号S后，确定所述控制信号S中相应字节的所有比特的取值都为0之后，对该字节执行掩码操作。如图6E所示，n比特的掩码控制信号S包含针对m个字节的掩码控制信号。第1字节内的所有比特的取值均为0。第m字节中的第2，4，6，7，8比特为1,其他比特为0。由于第m字节中至少一个比特的取值不为0，因此掩码控制模块505对于第m字节不执行掩码操作，第m字节的内容需要写入到内存108中。因此，在n比特的更新后的码字C u中，第m字节的内容是写入的更新的数据内容。
此外，为了提升掩码效率，掩码控制模块505还可以以多个字节为单位执行掩码操作。比如，只有当相邻两个或多个字节的所有比特的取值都为0时，掩码控制模块505才对所述候选写入的码字的相应位置的内容执行掩码操作。
也就是说，所述根据所述控制信号S对所述候选写入的码字Cn执行掩码操作可以为：掩码控制模块505屏蔽所述候选写入的码字Cn中控制信号S中取值为0的比特，或屏蔽所述候选写入的码字Cn中控制信号S中所有比特取值0的字节，或屏蔽所述候选写入的码字Cn中控制信号S指示相邻的多个字节中所有比特取值为0的所述相邻的多个字节。
通过本发明实施例提供的方法，针对更新数据的位置生成更新的码字，控制器106根据对所述存储的码字进行纠错后生成的纠错后的码字以及根据所述更新的码字生成所述候 选写入的码字。控制器106对所述候选写入的码字执行掩码操作，将所述候选写入的码字中没有被掩码的内容写入到内存中。本发明给出了一种针对需更新的比特序列及相应的ECC信息，进行最小化的写入操作。在存储的字节中只有部分比特甚至一个比特需要更新的场景下，无需更新字节的所有比特，节省了单次写入操作的功耗及时延。此外，本发明在更新前对已存储的信息进行了纠错，使得更新的内容为基于纠错后的内容，保证了更新内容的准确性。
图7A为本发明实施例提供的对存储的信息更新的方法流程示意图。执行该方法的控制器可以为图5中的控制器106。即控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504以及掩码控制模块505。该方法中，码字的存储方式采用图3示意的方式，即码字的数据信息和ECC校验信息储存在同一个内存108中。
与图6A中控制器106接收的是更新数据位置，根据更新的数据位置生成更新的数据信息，并对更新的数据信息ECC编码生成需更新的码字，然后对纠错后的码字以及需要更新的码字生成候选写入的码字C n。而在图7A提供的实施例中，控制器106接收的是更新的数据位置和更新的数据内容，并根据纠错后的数据信息D c与所述更新的数据内容和所述数据位置生成候选写入的数据信息D n。ECC编码器502对所述候选写入的数据信息D n进行ECC编码生成候选写入的码字C n。图7A提供的方法包括如下步骤：
步骤701、ECC译码器501以及控制信号生成模块504获取存储在内存108中的码字C e。所述存储的码字C e包含存储的数据信息D e和与所述数据信息对应的ECC校验信息P e。即C e＝[D e P e]。
作为一个例子，假设存储的码字C e的长度为n比特。所述存储的数据信息D e的长度为k比特，存储的ECC校验信息P e的长度为n-k比特。
ECC译码器501以及控制信号生成模块504获取的存储的数据信息可以参数图6B所示。在图6B中，存储的数据信息D e包括k比特，每一个小格代表一比特。一个字节包括连续的8比特。
步骤702、候选信息生成模503获取ECC译码器501生成的纠错后的数据信息D c。
ECC译码器502在获取所述存储的码字C e后，对所述存储的码字C e进行ECC译码，生成纠错后的码字C c，所述纠错后的码字C c包含所述纠错后的数据信息D c和纠错后的ECC校验信息P c。
作为一个例子，所述纠错后的数据信息D c参考图7B所示。图7B中1小格代表1比特。其中，第3-5比特为需要更新的比特。
步骤703、候选信息生成模块503获取更新数据的指示，并根据所述更新数据的指示生成候选写入的数据信息。所述更新数据的指示用于指示更新的数据内容和更新的数据位置。
当内存中存储的码字的相应位置的数据内容需要进行更新时，在一些逻辑计算操作中，只需要将纠错后的数据信息的部分r个连续比特进行更新，其他数据信息保留。r为等于或大于1的正整数。
值得说明的是，步骤701和703没有时间的先后顺序。
步骤704、ECC编码器502获取候选信息生成模块503生成的候选写入的数据信息D n。
在获取所述更新的数据内容和的所述更新的数据位置后，候选信息生成模块503根据所述更新的数据位置，使用所述更新的数据内容替换所述纠错后的数据信息Dc的相应 位置(比特)的内容。
作为另一种可选方式，控制器106还可以包括序列生成模块506，序列生成模块506获取更新的数据内容，并根据更新的数据内容生成更新的数据信息D f。如图7B所示，所述更新的数据信息D f为k比特的数据序列。在所述更新的数据信息D f中，第3-5个比特的内容为更新的数据内容。候选信息生成模块503在获取所述纠错后的数据信息D c以及更新的数据信息D f以后，将D c中的第3-5比特替换为D f中的3-5比特的内容，D c中的其他位置的数据保留，从而生成所述候选写入的数据信息D n。
步骤705、控制信号生成模块504以及掩码控制模块505获取ECC编码器502生成的所述候选写入的码字C n。
ECC编码器502对所述候选写入的数据信息D n进行ECC编码，生成所述候选写入的码字C n。所述候选写入的码字C n包括所述候选写入的数据信息D n以及候选写入的ECC校验信息P n。所述候选写入的ECC校验信息P n为ECC编码器502根据所述候选写入的数据信息D n进行ECC编码生成的。
步骤706、掩码控制模块505获取控制信号生成模块504生成的掩码控制信号S。
控制信号生成模块504获取到所述候选写入的码字C n后，根据所述候选写入的码字C n与所述步骤701中存储的码字C e生成针对所述候选写入的码字C n掩码控制信号S。掩码控制模块505生成针对所述候选写入的码字Cn的掩码控制信号S可参考图6A对应的实施例中步骤606的描述，本发明实施例在此不再详述。
步骤707、掩码控制模块505对所述候选写入的码字C n执行掩码操作，以使得未掩码的内容被写入内存108中。
所述未掩码的内容包括未掩码的数据内容和/或未掩码的ECC校验内容。所述掩码控制模块505在获取控制信号生成模块504生成的掩码控制信号S后，根据所述掩码控制信号S对所述候选写入的码字C n执行掩码操作。
作为另一种可选方式，掩码控制模块505还可以以一个或多个字节为单位执行掩码操作。掩码控制模块505对以一个或多个字节为单位的掩码操作可以参见图6A对应实施例的描述，本发明实施例在些不再详述。
也就是说，所述根据所述控制信号S对所述候选写入的码字C n执行掩码操作可以为：掩码控制模块505屏蔽所述候选写入的码字C n中控制信号S中取值为0的比特，或屏蔽所述候选写入的码字C n中控制信号S中所有比特取值为0的字节，或屏蔽所述候选写入的码字C n中控制信号S指示相邻的多个字节中所有比特为取值为0的所述相邻的多个字节。
控制器106将所述候选写入的码字C n中未掩码的内容写入到内存108中。
通过图7A所示的方法，控制器106处理更新的数据时，对于存储的数据信息D e进行ECC纠错生成纠错后的数据信息D c。控制器106根据更新的数据内容和数据位置以及所述纠错后的数据信息D c生成所述候选写入的数据信息D n，根据所述候选写入的数据信息D n生成所述候选写入的码字C n。控制器106对所述候选写入的码字C n执行掩码操作，将所述候选写入的码字C n中没有被掩码的内容写入到内存108中。本发明给出了一种针对需更新的数据信息及相应的ECC信息，进行最小化的写入操作。在存储的数据信息D e中只有部分比特的数据甚至一个比特的数据需要更新的场景下，无需更新字节的所有比特，节省了单次写入操作的功耗及时延。此外，本发明在更新前对已存储的信息进行了纠错，使得更新的内容为基于纠错后的内容，保证了更新内容的准确性。
图8为本发明实施例提供的对存储的信息更新的方法流程图。执行该方法的控制 器可以为图5中的控制器106。即控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控制模块505、序列生成模块506以及组合模块507。该方法中，码字的存储方式采用图4示意的方式，即码字的数据信息和ECC校验信息储存在不同的内存108中。即同一码字的数据信息和ECC校验信息具有不同的读取地址。
图8提供的实施例与图6A类似，即控制器106接收的是更新的数据内容，并根据更新的数据内容生成更新的数据信息。与图6A提供的实施例相比，图8中的数据信息D e和ECC校验信息P e分别存储在不同的内存108中。比如，数据信息D e存储在内存108-1，ECC校验信息P e存储在内存108-2中。与图6的控制器106不同的是，图8中的控制器106还包含组合模块507，用于将存储在不同内存中的数据信息D e和ECC校验信息P e组合为码字C e。图8提供的方法包括如下步骤：
步骤801、组合模块507获取存储在内存108-1中的数据信息D e。
此外，控制信号生成模块504也获取存储在内存108-1中所述数据信息D e。
步骤801’、组合模块507获取与所述数据信息D e对应的存储于内存108-2中的ECC校验信息P e。所述存储的数据信息D e对应的ECC校验信息P e简称为存储的ECC校验信息P e。
在本实施例中，内存108-1和内存108-2对同一个码字(比如C e)的数据信息D e和校验信息进行映射存储P e。
值得说明的是，步骤801和801’没有执行的先后顺序。
步骤802、ECC译码器501获取组合模块507生成的组合的码字C e。
组合模块507在获取存储的数据信息D e和存储的ECC校验信息P e后，组合所述存储的数据信息D e和所述存储的ECC校验信息P e，生成组合的码字C e，即C e＝[D e P e]。
组合模块507组合所述存储的数据信息D e和存储的ECC校验信息P e可以采用现有的组合方式，本发明实施例在此不再详述。
步骤803、候选信息生成模块503获取ECC译码器501生成的纠错后的码字C c。
ECC译码器501在获取所述组合的码字C e后，对所述组合的码字C e进行译码，生成纠错后的码字C c。所述纠错后的码字C c包括纠错后的数据信息D c和纠错后的ECC校验信息P c。
步骤804-1,804-2与步骤603-1和603-2相同。本发明实施例在此不再详述。
步骤805、候选信息生成模块503获取ECC编码器502生成的更新的码字C f。
ECC编码器502获取所述更新的数据信息D f后，对所述更新的数据信息D f进行ECC编码，生成更新的码字C f。所述更新的码字C f包括所述更新的数据信息D f和更新的ECC校验信息P f。所述更新的ECC校验信息P f为所述更新的数据信息D f对应的的ECC校验信息P f。
步骤806、掩码控制模块505以及控制信号生成模块504获取候选信息生成模块503生成的候选写入的数据信息D n。
候选信息生成模块503在获取所述纠错后的码字C c以及所述更新的码字C f后，根据所述纠错后的码字C c以及所述更新的码字C f生成候选写入的码字C n。所述候选写入的码字C n的部分内容会被写入到内存108。所述候选写入的码字C n包含候选写入的数据信息D n和候选写入的ECC校验信息P n。
比如，候选信息生成模块503可采用异或的方式，对所述纠错后的码字C c以及所述更新的码字C f执行异或操作，生成候选写入的码字C n。即C n＝C f^C c。
步骤807、控制器将所述候选写入的ECC校验息P n写入至内存108-2中。
在候选信息生成模块503生成候选写入的码字C n后，掩码控制模块505获取所述候选写入的数据信息D n。所述候选写入的ECC校验信息P n被写入内存108-2中。
步骤808、掩码控制模块505获取控制信号生成模块504生成的掩码控制信号S。
控制信号生成模块504在获取候选信息生成模块503生成的所述候选写入的码字C n后，根据将所述候选写入的码字C n与所述步骤601中存储的码字C e生成掩码控制信号。
比如，控制信号生成模块504将所述候选写入的码字C n包含的所述候选写入的数据信息D n与所述步骤801中获取的存储的数据信息D e进行异或处理，生成所述掩码控制信号S。即S＝D n^D e.所述掩码控制信号S包含针对所述候选写入的数据信息D n的掩码控制信号S1。
控制信号生成模块504对候选写入的数据信息D n与存储的数据信息De进行异或处理的方法参考上606的描述，本发明实施例不再详述。
步骤809、掩码控制模块505对所述候选写入的数据信息D n执行掩码操作，将所述候选写入的数据信息D n中未掩码的内容被写入内存108-1中。
所述未掩码的内容为未掩码的数据内容，即未掩码的比特的取值。所述掩码控制模块505在获取控制信号生成模块504生成的掩码控制信号S后，根据所述掩码控制信号S对所述候选写入的数据信息D n执行掩码操作。
也就是说，所述根据所述控制信号S对所述候选写入的数据信息Dn执行掩码操作可以为：掩码控制模块505屏蔽所述候选写入的数据信息D n中控制信号S取值为0的比特，或掩码控制模块505屏蔽所述候选写入的数据信息D n中控制信号S指示所有比特取值0的字节。
图9为本发明实施例提供的对存储的信息更新的方法流程图。执行该方法的控制器可以为图5中的控制器106。即控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控制模块505以及组合模块507。该方法中，码字的存储方式采用图4示意的方式，即码字的数据信息和ECC校验信息储存在不同的内存中。
图9提供的实施例的流程与图7A类似，控制器106接收的是更新的数据内容和数据位置，候选信息生成模块203根据所述更新的数据内容和数据位置以及纠错后的数据信息生成候选写入的数据信息。与图7A提供的实施例相比，图9中的数据信息和ECC校验信息分别存储在不同的内存中。比如，数据信息存储在内存108-1，ECC校验信息存储在内存108-2中。因此，在译码器501进行译码前，组合模块507需要先将存储的ECC校验信息和数据信息组合，生成组合的码字。图9提供的方法包括如下步骤：
步骤901、组合模块507获取存储在内存108-1中的数据信息D e。
此外，控制信号生成模块504也获取存储在内存108-1中所述数据信息D e。
步骤901’、组合模块507获取与所述数据信息对应的存储于内存108-2中的ECC校验信息P e。所述存储的数据信息对应的ECC校验信息P e简称为存储的ECC校验信息P e。
在本实施例中，内存108-1和内存108-2对同一个码字(比如C e)的数据信息D e和ECC校验信息P e进行映射存储。
值得说明的是，步骤901和901’没有执行的先后顺序。
步骤902、ECC译码器501获取组合模块507生成的组合的码字C e，所述组合的码字C e也是存储的码字C e。
组合模块507在获取所述存储的数据信息D e和存储的ECC校验信息P e后，组合所述存储的数据信息D e和存储的ECC校验信息P e，生成组合后的的码字C e，即C e＝[D e P e]。
组合模块507组合所述存储的数据信息D e和存储的ECC校验信息P e可以采用现有的组合方式，本发明实施例在此不再详述。
步骤903、候选信息生成模块503获取ECC译码器501生成的纠错后的数据信息D c。
ECC译码器501在获取所述存储的码字C e后，对所述存储的码字C e进行ECC译码，生成纠错后的码字C c。所述纠错后的码字C c包括纠错后的数据信息D c和纠错后的ECC校验信息P c。
步骤904、候选信息生成模块503获取更新数据的指示，所述更新数据的指示用于指示所述存储的数据信息中需更新的数据位置及需更新的数据内容。
步骤904参考图7A对应方法的步骤703，本发明实施例在此不再详述。
值得说明的是，步骤901、901’、和步骤904没有时间的先后顺序。
步骤905、ECC编码器502获取候选信息生成模块503生成的候选写入的数据信息D n。
参考图7A对应方法的步骤704，本发明实施例在此不再详述。
此外，控制信号生成模块504和掩码控制模块505也获取候选信息生成模块503生成的所述候选写入的数据信息D n。
步骤906、ECC编码器502生成候选写入的ECC校验信息P n，以使得控制器将所述候选写入的ECC校验信息P n被写入内存108-2中。
ECC编码器502对所述候选写入的数据信息D n进行ECC编码，生成候选写入的码字C n。所述候选写入的码字C n包括所述候选写入的数据信息D n以及候选写入的ECC校验信息P n。所述候选写入的ECC校验信息P n的所有内容均被写入到内存108-2中。
步骤907、掩码控制模块505获取控制信息生成模块504生成的掩码控制信号S。
控制信息生成模块504在获取所述候选写入的数据信息D n后，根据将所述候选写入的数据信息D n与所述存储的数据信息D e生成掩码控制信号S。比如，控制信息生成模块504将所述候选写入的数据信息D n与所述存储的数据信息D e进行异或处理，生成所述掩码控制信号S。即S＝D n^D e.所述掩码控制信号S为针对所述候选写入的数据信息D n的掩码控制信号S1。
控制信息生成模块504对所述候选写入的数据信息D n与所述存储的数据信息D e进行异或处理的方法参考上706的描述，本发明实施例不再详述。
步骤908、掩码控制模块505对所述候选写入的数据信息D n执行掩码操作，以使得控制器106将所述候选写入的数据信息D n中未掩码的内容写入内存108-1中。
步骤908可参考步骤808的说明，本发明实施例不再详述。
通过本发明实施例，针对需更新的数据内容及相应的ECC信息，控制器进行最小化的写入操作。在存储的字节中只有部分比特甚至一个比特需要更新的场景，无需更新字节的所有比特，节省了单次写入操作的功耗及时延。
图10为本发明实施例提供的对存储的信息更新的方法流程图。执行该方法的控制器可以为图5中的控制器106。即控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控制模块505、序列生成模块506以及组合模块507。该方法中，码字的存储方式采用图4示意的方式，即码字的数据信息和ECC校 验信息储存在不同的内存中。
图10提供的实施例与图6A和图8对应的实施例类似，即控制器106接收的是更新的数据内容，并根据更新的数据内容生成更新的数据信息。与图6实施例相比，图10对应的实施例中ECC校验信息和数据信息存储在不同的内存中。与图8提供的实施例相比，图10提供的实施例中控制器508不仅对候选写入的数据信息D n进行掩码操作，还对候选写入的ECC校验信息P n进行掩码操作。图10提供的方法包括如下步骤：
步骤1001、1001’和1002与步骤801、801’和802相同，本发明实施例不再详述。
此外，控制信号生成模块504还获取组合模块507生成的组合的码字C e。
步骤1003、候选信息生成模块503获取ECC译码器501生成的纠错后的数据信息D c。
步骤1003的详述描述参见步骤602，本发明实施例在此不再详述
步骤1004-1和1004-2与步骤804-1和804-2的描述相同，本发明实施例不再详述。
步骤1005、候选信息生成模块503获取ECC编码器502生成的更新的码字C f。
ECC编码器502对所述更新的数据信息D f进行ECC编码，生成更新的码字C f。所述更新的码字C f包括更新的数据信息D f和更新的ECC校验信息P f。所述更新的ECC校验信息P f为与所述更新的数据信息D f对应的ECC校验信息P f。
值得说明的是，步骤1002和1005没有时间的先后顺序。
步骤1006-1007与步骤605-606相同，本发明实施例在此不再详述。
步骤1007生成的掩码控制信号S包括针对所述候选写入的数据信息的掩码控制信号S1和针对所述候选写入的ECC校验信息的掩码控制信号S2.
步骤1008、掩码控制模块505对所述候选写入的数据信息D n执行掩码操作，以使得所述候选写入的数据信息D n中未掩码的内容被写入内存108-1中。
步骤1008与步骤808的描述相同，本发明实施例在此不再详述。
步骤1009、掩码控制模块505对所述候选写入的ECC校验信息P n执行掩码操作，以使得所述候选写入的ECC校验信息P n中未掩码的内容被写入内存108-2中。
所述掩码控制模块505在获取控制信号生成模块504发送的掩码控制信号S后，根据所述掩码控制信号S中包含的所述针对所述候选写入的ECC校验信息的掩码控制信号S2对所述候选写入的ECC校验信息P n执行掩码操作，以使得所述候选写入的ECC校验信息P n中未掩码的内容被写入内存108-2中。。
也就是说，所述根据所述控制信号S对所述候选写入的码字C n执行掩码操作可以为：掩码控制模块505屏蔽所述候选写入的ECC校验信息P n中所述掩码控制信号S2指示为0的比特，或掩码控制模块505屏蔽所述候选写入的ECC校验信息P n中控制信号S2指示所有比特取值为0的字节。
通过本方法，控制器106在处理更新的数据的过程中，对于存储的数据进行ECC纠错后再与更新的数据信息Df组合，再掩码写入。减少了写入数据的数量，降低写入操作的时间和功耗。
图11为本发明实施例提供的对存储的信息更新的方法流程图。即执行该方法的控制器可以为图5中的控制器106。即控制器106包括ECC译码器501、ECC编码器502、候选信息生成模块503、控制信号生成模块504、掩码控制模块505以及组合模块507。该方法中，码字的存储方式采用图4示意的方式，即码字的数据信息和ECC校验信息存储在不同的内存108中。
图11提供的实施例的流程与图7A和图9对应的实施例类似，即控制器106接收的是更新的数据内容和数据位置，候选信息生成模块203根据所述更新的数据内容和数据位置以及纠错后的数据信息生成候选写入的数据信息。与图7A对应的实施例相比，图11对应的实施例中ECC校验信息和数据信息存储在不同的内存108中。与图9提供的实施例相比，图11所示的实施例中控制器508不仅对候选写入的数据信息D n进行掩码处理，还对候选写入的ECC校验信息P n进行掩码处理，从而使得写入内存108中的数据更少。图11提供的方法包括如下步骤：
步骤1101、1101’和1102与步骤801、801’和802相同，本发明实施例不再赘述。
此外，控制信号生成模块504还获取组合模块507生成的组合的码字C e。
步骤1103、候选信息生成模块503获取ECC译码器501生成的纠错后的数据信息D c。
步骤1103的详述描述参见步骤602，本发明实施例在此不再详述
步骤1104、候选信息生成模块503获取更新的数据内容和位置，所述更新的数据内容用于更新所述存储的数据信息中相应位置的内容。
步骤1104参考图7A对应方法的步骤703，本发明实施例在此不再详述。
值得说明的是，步骤1101、1101’、和步骤1104没有时间的先后顺序。
步骤1105、ECC编码器502获取候选信息生成模块503生成的候选写入的数据信息D n。
参考图7A对应方法的步骤704，本发明实施例在此不再详述。
步骤1106-1107与步骤705-706相同，本发明实施例在此不再详述。
步骤1108和1109的描述与步骤1008和1009的描述相同，本发明实施例在此不再详述。
通过本方法，控制器106在更新数据时，对于获取后的数据进行ECC纠错后再与更新的数据序更D f组合，再掩码写入。减少了写入数据的数量，降低写入操作时间和功耗。
值得说明的是，控制器106中的各模块执行图6、图7A、图8-11所示的步骤时，可以采用软件定义来方式执行，也可以采用硬件来执行。比如，通过候选信息生成电路(如组合电路或异或电路)生成候选写入的数据信息。通过控制信号生成电路(如异或电路)来生成控制信号。通过掩码控制电路来执行掩码操作。编码器和译码器也可以通过电路的方式来实现。异或电路可以为XOR电路。
此外，上述存储的信息更新的方法流程(比如图2、图6、图7A、图8-11对应的流程中)，控制器106还可以为图12中的控制器的结构。如图12所示，控制器106包含内存接口电路1501、处理电路1502和处理器接口电路1503。处理器接口电路1503提供控制器106和处理器110之间的接口。控制器106通过处理器接口电路1503从处理器110接收请求，并且将所述请求的处理结果发送到处理器110。
内存接口电路1501提供控制器106和内存108之间的接口。通过内存接口电路1501，命令和地址从控制器106传输到内存108，数据在控制器106和内存108之间交换。此外，通过内存接口电路1501，存储在内存108中的信息被传送到控制器106。
处理电路421通过处理器接口电路450获取图1中处理器110的指示并执行，以及执行图2、图6A、图7A、图8-图11中控制器106执行的所有功能。
图13为本发明实施例提供的包括控制器的装置另一结构示意图。该装置用于实现对存储的信息更新的方法。如图13所示，装置1300至少可以包括处理器1302、控制器106 以及内存108。与图1所示装置100不同的是，图13所示的装置1300中，控制器106和多个处理器核1304集成在处理器1302中。需要说明的是，除了图13所示的器件外，计算机系统1300还可以包括通信接口以及作为外存的磁盘等其他器件，在此不做限制。
处理器1302是计算机系统1300的运算核心和控制核心(Control Unit)。处理器1302可以是一个芯片，如系统芯片(system on chip,SOC)。芯片102中还可以包括多个处理器核(core)104。处理器1302还可以是一块超大规模的集成电路。处理器核104通过操作系统和其他软件程序，实现对内存108、缓存及磁盘的访问。可以理解的是，在本发明实施例中，处理器1302中的Core 1304可以是中央处理器(Central Processing unit，CPU)，还可以是其他特定集成电路(Application Specific Integrated Circuit，ASIC)。
控制器(Controller)106是装置1300控制内存108并用于管理与规划从内存108到Core1304间的数据传输的总线电路控制器。通过控制器106，内存108与Core 1304之间可以交换数据。控制器106可以是一个单独的芯片,并通过系统总线与Core 1304连接。控制器106也可以被集成到处理器1302中(如图13所示)，也可以被内置于其它芯片中。控制器106用于执行图6A、图7A、图8-图11中控制器106执行的任何步骤。图13中的控制器106也可以采用图2，图3或图12的任一结构。
内存108可以是DRAM 108，包括多个通道(channel)1310。每个通道1310中可以包括至少一个rank，每个rank中可以包括至少一个bank。本领域技术人员可以知道，rank指的是连接到同一个片选(chip select)信号的内存颗粒(chip)。控制器106能够对同一个rank中的chip进行写操作，而在同一个rank的chip也共享同样的控制信号。控制器106可以通过内存总线分别访问DRAM 108中各个通道内的Rank中的数据。
值得说明的是，图1和图13中示出的内存108置于处理器之外。在本发明实施例中，所述一个或多个内存108还可以是集成在处理器中(如SOC芯片中的内存)，控制器106通过控制集成在处理器中的内存108来实现对存储的信息更新的方法。
图14所示为本申请实施例提供的执行控制器功能的装置的另一结构示意图。该装置1400包括处理器1401，通信线路1402，存储器1403以及至少一通信接口1404。
处理器1401可以是一个通用中央处理器(central processing unit，CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路。处理器1401可以执行上述控制器执行的任一功能。
通信线路1402可包括一通路，在上述组件之间传送信息。
通信接口1404，使用任何收发器一类的装置，用于与其他设备或通信网络通信，如以太网，无线接入网(radio access network，RAN)，无线局域网(wireless local area networks，WLAN)等。
存储器1403可以是内存，如只读存储器ROM、随机存储器RAM、闪存Flash等。存储器可以是独立存在，通过通信线路1402与处理器1401相连接。存储器1403也可以和处理器1401集成在一起。
其中，存储器1403用于存储执行本申请方案的计算机执行指令，并由处理器1401来控制执行。处理器1401用于执行存储器1403中存储的计算机执行指令，从而实现本申请上述实施例提供的对存储的信息更新的方法。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
在本发明的本实施例中，该控制器106以采用集成的方式划分各个功能模块的形 式来呈现。这里的“模块”可以指特定应用集成电路(application-specific integrated circuit，ASIC)，电路，执行一个或多个软件或固件程序的处理器和存储器，集成逻辑电路，和/或其他可以提供上述功能的器件。在一个简单的实施例中，本领域的技术人员可以想到控制器106可以采用图2、图3或图14任一所示的形式。
在上述实施例中，控制器106可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (28)

  1. 一种对存储的信息更新的方法，其特征在于，包括：
    根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息；
    根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息；
    根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作；
    将所述候选写入的数据信息中未掩码的内容写入到内存中。
  2. 如权利要求1所述的方法，其特征在于，所述更新数据的指示用于指示所述存储的数据信息中需更新的数据位置，该方法进一步包括：根据所述需更新的数据位置生成更新的数据信息；
    所述根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息包括：根据所述纠错后的数据信息和所述更新的数据信息生成所述候选写入的数据信息。
  3. 如权利要求2所述的方法，其特征在于：所述根据所述纠错后的数据信息和更新的数据信息生成候选写入的数据信息包括：
    对所述纠错后的数据信息和所述更新的数据信息执行异或处理，生成所述候选写入的数据信息。
  4. 如权利要求1所述的方法，其特征在于，所述更新数据的指示用于指示更新的数据内容和更新的数据位置，所述根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息包括：
    根据所述更新的数据位置，使用所述更新的数据内容替换所述纠错后的数据信息中相同位置的数据内容。
  5. 如权利要求1-3任一所述的方法，其特征在于，该方法进一步包括：对所述存储的数据信息和所述候选写入的数据信息执行异或处理，生成针对所述候选写入的数据信息的掩码控制信号；
    所述根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作包括：根据所述针对所述候选写入的数据信息的掩码控制信号对所述候选写入的数据信息执行掩码操作。
  6. 如权利要求1-5任一所述的方法，其特征在于，该方法进一步包括：组合所述存储的数据信息和所述存储的ECC校验信息，生成存储的码字。
  7. 如权利要求1-6所述的方法，其特征在于，该方法进一步包括：
    对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息；
    将所述候选写入的ECC校验信息写入到所述内存中。
  8. 如权利要求1-6所述的方法，其特征在于，所述纠错后的码字进一步包括纠错后的ECC校验信息，该方法进一步包括：
    对所述更新的数据信息进行ECC编码，生成更新的ECC校验信息；
    根据所述纠错后的ECC校验信息和更新的ECC校验信息生成候选写入的ECC校验信息；
    根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作；
    将所述候选写入的ECC校验信息中未掩码的内容写入到内存中。
  9. 如权利要求1-6任一所述的方法，其特征在于，该方法进一步包括：
    对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息；
    根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作；
    将所述候选写入的ECC校验信息中未掩码的内容写入到内存中。
  10. 如权利要求8所述的方法，其特征在于，所述根据所述纠错后的ECC校验信息和更新的ECC校验信息生成候选写入的ECC校验信息包括：
    对所述纠错后的ECC校验信息和所述更新的ECC校验信息执行异或处理，生成所述候选写入的ECC校验信息。
  11. 如权利要求8-10任一所述的方法，其特征在于，该方法进一步包括：
    对所述候选写入的ECC校验信息和所述存储的ECC校验信息进行异或处理，生成针对所述候选写入的ECC校验信息的掩码控制信号；
    所述根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作包括：根据所述针对所述候选写入的ECC校验信息的掩码控制信号对所述候选写入的ECC校验信息执行掩码操作。
  12. 如权利要求1-11任一所述的方法，其特征在于，该方法进一步包括：
    接收所述更新数据的指示。
  13. 一种装置，其特征在于，包括控制器和内存，
    所述内存用于存储数据信息和与所述数据信息对应的错误校验码(ECC)校验信息；
    所述控制器用于：
    根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息；
    根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息；
    根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作；
    将所述候选写入的数据信息中未掩码的内容写入到内存中。
  14. 如权利要求13所述的装置，其特征在于：所述控制器用于执行权2-11任一所述的方法。
  15. 一种系统芯片，其特征在于包括：核心处理器和控制器，其中
    所述核心处理器用于通过所述控制器与内存交换数据；
    所述控制器用于执行权利要求1-12任一所述的方法。
  16. 一种控制器，其特征在于：包括处理电路和内存接口电路，
    所述内存接口电路用于提供所述控制器和内存之间的接口；
    所述处理电路用于通过所述内存接口电路与的内存交互，并执行执行权利要求1-12任一所述的方法。
  17. 一种装置，其特征，包括：处理器和存储器；
    所述存储器用于存储计算机执行指令；
    所述处理器用于当该装置运行时，执行所述存储器存储的该计算机执行指令，以使该装置执行权利要求1-12任一所述的方法。
  18. 一种装置，其特征在于：包括错误校验码(ECC)译码器、候选信息生成模块、和掩码控制模块，其中，
    所述ECC译码器用于根据存储的数据信息和存储的错误校验码(ECC)校验信息对所述存储的数据信息执行ECC译码，生成纠错后的码字，所述纠错后的码字包括纠错后的数据信息；
    所述候选信息生成模块用于根据所述纠错后的数据信息和更新数据的指示生成候选写入的数据信息；
    所述掩码控制模块根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作,所述候选写入的数据信息中未掩码的内容被写入到内存中。
  19. 如权利要求18所述的装置，其特征在于：所述更新数据的指示用于指示所述存储的码字中需更新的数据位置，该装置进一步包括：序列生成模块，用于根据所述需更新的数据位置生成更新的数据信息。
  20. 如权利要求19所述的装置，其特征在于：
    所述候选信息生成模块用于对所述纠错后的数据信息和所述更新的数据信息执行异或处理，生成所述候选写入的数据信息。
  21. 如权利要求18所述的装置，其特征在于：所述更新数据的指示用于指示更新的数据内容和更新的数据位置。
  22. 如权利要求21所述的装置，其特征在于：
    所述候选信息生成模块用于根据所述更新的数据位置，使用所述更新的数据内容替换所述纠错后的数据信息中与所述更新的数据位置相同位置的数据内容，以生成所述候选写入的数据信息。
  23. 如权利要求21所述的装置，其特征在于，该装置进一步包括：序列生成模块，用于根据所述更新数据的指示生成更新的数据信息；
    所述候选信息生成模块用于根据所述更新的数据信息和所述纠错后的数据信息中的数据内容，生成所述候选写入的数据信息。
  24. 如权利要求18-23任一所述的装置，其特征在于：该装置进一步包括控制信号生成模块，用于对所述存储的数据信息和所述候选写入的数据信息执行异或处理，生成针对所述候选写入的数据信息的掩码控制信号；
    所述根据所述存储的数据信息对所述候选写入的数据信息执行掩码操作包括：根据所述候选写入的数据信息的掩码控制信号对所述候选写入的数据信息执行掩码操作。
  25. 如权利要求18-24任一所述的装置，其特征在于：所述装置进一步包括组合模块，所述组合模块用于,组合所述存储的数据信息和所述存储的ECC校验信息,生成所述存储的码字。
  26. 如权利要求18-24任一所述的装置，其特征在于，所述装置进一步包括ECC编码模块，
    所述ECC编码模块用于对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息，所述候选写入的ECC校验信息被写入到所述内存中。
  27. 如权利要求18-24任一所述的装置，其特征在于，所述装置进一步包括ECC编码模块，
    所述ECC编码模块用于对所述候选写入的数据信息进行ECC编码，生成候选写入的ECC校验信息；
    所述掩码控制模块进一步用于：根据所述存储的ECC校验信息对所述候选写入的ECC校验信息执行掩码操作，所述候选写入的ECC校验信息中未掩码的内容被写入到内存中。
  28. 权利要求24所述的装置，其特征在于,
    所述控制信号生成模块进一步用于对所述候选写入的ECC校验信息和所述存储的ECC校验信息执行异或处理，生成针对所述候选写入的ECC校验信息的掩码控制信号；
    所述掩码控制模块进一步用于根据所述针对候选的ECC校验信息的掩码控制信号对所述候选写入的ECC校验信息执行掩码操作，所述候选写入的ECC校验信息中未掩码的内容被写入到内存中。
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