WO2023179631A1 - 一种数据纠错方法及装置 - Google Patents

一种数据纠错方法及装置 Download PDF

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Publication number
WO2023179631A1
WO2023179631A1 PCT/CN2023/082916 CN2023082916W WO2023179631A1 WO 2023179631 A1 WO2023179631 A1 WO 2023179631A1 CN 2023082916 W CN2023082916 W CN 2023082916W WO 2023179631 A1 WO2023179631 A1 WO 2023179631A1
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Prior art keywords
data
corrected
row
column
error correction
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PCT/CN2023/082916
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English (en)
French (fr)
Inventor
顾新理
唐鲲
杨天文
朱国良
李步蟾
张旭
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华为技术有限公司
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Publication of WO2023179631A1 publication Critical patent/WO2023179631A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the present application relates to the field of data storage technology, and in particular to a data error correction method and device.
  • Storage media can be considered in terms of reliability, availability, and serviceability (reliability, availability, serviceability, RAS).
  • RAS reliability, availability, serviceability, RAS
  • the error correction code (ECC) of the data can be stored in the storage medium to correct the data.
  • Errors that occur in data in storage media can be divided into two types. One is corrected error (CE), that is, this type of error can be corrected based on ECC according to the existing error correction algorithm.
  • CE usually occurs In a storage unit of the storage medium, the size of the data generated is usually 1 bit; for example, a memory particle is a storage unit in the memory, and CE in the memory usually occurs in a memory particle.
  • the other type is uncorrected error (UCE), that is, this type of error cannot be corrected based on ECC according to the existing error correction algorithm.
  • This type of error usually spans multiple storage units of the storage medium. The data size is multiple bits. Therefore, in order to improve the RAS of storage media, an error correction solution that can correct UCE in storage media is urgently needed.
  • the present application provides a data error correction method and device for error correction of UCE of data to be corrected in a storage medium.
  • this application provides a data error correction method, which is applied to data to be corrected in a storage medium.
  • the storage medium can be a memory or a hard disk.
  • This method can be executed by a data error correction device provided in the embodiment of the present application, and the data error correction device can be an electronic device provided by the present application.
  • the methods include:
  • the information includes verification data for each column of data to be corrected, and each column of data includes one bit of data in the first row of data.
  • the present application provides a data error correction method. After it is determined that the first row of the first data includes uncorrectable errors, the column check information of the first data includes a verification of each column of the first data. Check data, and each column of data includes one bit of data in the first row of data, then error correction is performed on each column of the first data based on the column check information of the first data. Finally, for each bit of data in the first row of data, if the bit of data is wrong, then after the column where the bit of data is located is corrected, the bit of data will be corrected, so even if the bit of data in the first row of data is incorrect, Even if there are uncorrectable errors that span multiple storage units, the first row of data can also be corrected bit by bit, thus achieving UCE. Correction.
  • the data structure of the data to be corrected can have various situations.
  • the data to be corrected includes multiple rows of data, and the number of bits in each row of data can be the same or different. Based on this situation, when the first row of data is the only row containing uncorrectable errors among the multiple rows of data, a data error correction method provided by the present application can be executed.
  • verification information can also be set for each row of data in the data to be corrected, so that each row can be checked using the row verification information. Data is verified.
  • the row of data is verified based on the row verification information of the row of data. If it is determined that there are correctable errors in the row of data, the correctable errors in the row of data are corrected. wrong.
  • the error-corrected first row of data is verified according to the row verification information of the first row of data.
  • the column check information can also be set with corresponding check information. After it is determined that the column check information includes correctable errors, the above determination can be responded to and based on the check of the column check information.
  • the verification information is used to correct errors in the column verification information.
  • the column check information can be corrected based on the check information of the column check information, thereby making the column check information more reliable.
  • the data to be corrected in the storage medium may be updated, and the column verification information must also be updated accordingly.
  • the data to be corrected in the storage medium is updated; and the column check information is updated according to the updated data to be corrected.
  • the column verification information can be updated in time as the data to be corrected is updated, ensuring the reliability of the column verification information.
  • this application provides a data error correction device, which includes:
  • a determining module for determining that the first row of data to be corrected includes uncorrectable errors
  • An error correction module configured to perform error correction on each column of the data to be corrected based on the column check information of the data to be corrected, wherein the column check information includes the column check information of the data to be corrected.
  • the check data of each column of data includes one bit of data in the first row of data.
  • the error correction module is also used to:
  • the error-corrected first row of data is verified according to the row verification information of the first row of data.
  • the data to be corrected includes multiple rows of data, and the first row of data is the only row among the multiple rows of data that includes uncorrectable errors.
  • the column verification information has corresponding verification information
  • the error correction module is also used to:
  • the column check information includes correctable errors; in response to the above determination, error correction is performed on the column check information according to the check information of the column check information.
  • the device further includes an update module, which is used to:
  • the column check information is updated according to the updated data to be corrected.
  • the present application provides an electronic device, which includes: one or more processors; one or more memories; wherein the one or more memories store one or more computer instructions.
  • the electronic device is caused to perform the method described in any one of the above first aspects.
  • the present application provides a computer-readable storage medium.
  • the computer-readable storage medium includes computer instructions.
  • the computer instructions When the computer instructions are run on a computer, the computer causes the computer to execute as described in any one of the above-mentioned first aspects. method described.
  • Figure 1 is a schematic diagram of an applicable architecture of a data error correction method provided by an embodiment of the present application
  • Figure 2 is a schematic diagram of the data structure of data to be corrected that can be applied to a data error correction method provided by an embodiment of the present application;
  • Figure 3 is a timing diagram illustrating the synchronization update of column check information in a data error correction method provided by an embodiment of the present application
  • Figure 4 is a timing diagram illustrating the asynchronous update of column check information in a data error correction method provided by an embodiment of the present application
  • Figure 5 is a schematic diagram of storage of the storage address information of the first data block in the case of asynchronous update of column check information in a data error correction method provided by an embodiment of the present application;
  • Figure 6 is a schematic flow chart of a data error correction method provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of a data error correction device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the term “multiple” in the embodiments of this application refers to two or more than two. In view of this, the term “multiple” in the embodiments of this application may also be “Plural” is understood to mean “at least two".
  • “At least one” can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, if at least one of A, B and C is included, then it may include A, B, C, A and B, A and C, B and C, or A and B and C. In the same way, the understanding of descriptions such as "at least one" is similar.
  • “And/or” describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/”, unless otherwise specified, generally indicates that the related objects are in an "or” relationship.
  • ordinal numbers such as “first” and “second” mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.
  • the storage medium can store the data to be corrected and the verification information of the data to be corrected, and the data to be corrected can be corrected using the verification information of the data to be corrected.
  • the current error correction algorithm can correct the CE of the data to be corrected, but cannot correct the UCE of the data to be corrected.
  • this application provides a data error correction method. Taking the storage medium as a memory as an example, Figure 1 shows an applicable architecture diagram of a data error correction method provided by this application.
  • the architecture shown in Figure 1 includes a memory 10 and a central processing unit (CPU) 20.
  • a unified memory controller (UMC) 201, a UCE error correction module 202 and an output module 203 are provided on the CPU 20.
  • UMC201 includes patrol scanning (PS) unit 2011, local agent (home agent, HA) unit 2012 and verification unit 2013.
  • PS patrol scanning
  • HA local agent
  • the UMC 201, UCE error correction module 202, and output module 203 shown in Figure 1 may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application specific integrated circuits, such as Implemented in a computer device.
  • the memory 10 can be connected to the verification unit 2013, and the verification unit 2013 can also be connected to the PS unit 2011, HA unit 2012 and output module 203; the HA unit 2012 and the PS unit 2011 And the output module 203 is connected; the UCE error correction module 202 can be connected with the PS unit 2011, the HA unit 2012 and the output module 203.
  • the memory 10 may include volatile memory, such as random access memory (RAM), dynamic random access memory (DRAM), etc. It can also include non-volatile memory (non-volatile memory), such as storage-class memory (storage-class memory, SCM), etc., or a combination of volatile memory and non-volatile memory.
  • UMC201 may include a digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic devices, discrete gates or Transistor logic devices, discrete hardware components, artificial intelligence chips, on-chip chips, etc. Each unit in UMC201 can be an independent device or a unit built into a device.
  • the form of the UCE error correction module 202 and the output module 203 is not limited.
  • the UCE error correction module 202 and the output module 203 can be FPGA or other programmable logic devices.
  • the memory 10 is used to store data to be corrected.
  • the memory 10 can store the data to be corrected in the form of data blocks.
  • the data to be corrected is the data of any data block in the memory.
  • the verification information of the data to be corrected can be stored together in a data block, or can be stored in other locations.
  • the data structure of the error correction data is not limited.
  • the data to be corrected can be stored in rows and columns, or not in rows and columns.
  • the data to be corrected can be N rows M columns of data, N and M are positive integers.
  • the verification information of the data to be corrected can include row verification information and column verification information of each row of data in the N rows of data.
  • the column verification information includes the correction information of the data to be corrected. Check data for each column of error correction data.
  • the CPU 20 is used to perform error correction on the data to be corrected.
  • PS unit 2011 is used to read the data to be corrected, and can send the first row of data and the row check information of the first row of data to the verification unit 2013, and send the first row of data to the output module 203 , the first row of data is any row of data in the data to be corrected.
  • the verification unit 2013 is configured to perform line verification on the first line of data based on the obtained line verification information of the first line of data. If it is determined that the first line of data is correct, continue to obtain the line data in the data to be corrected and the Row verification information of row data; if it is determined that CE appears in the first row of data, error correction is performed on CE, and the error-corrected data of the first row of data is sent to the output module 203; if it is determined that CE appears in the first row of data UCE, then the verification unit 2013 sends a UCE data transmission message to the PS unit 2011, an error correction notification message to the HA unit 2012, and a data waiting message to the output module 203.
  • the UCE data transmission message is used to instruct the PS unit 2011 to send the first row of data to the UCE error correction module 202.
  • the error correction notification message is used to instruct the HA unit 2012 to read the column verification information of the data to be corrected.
  • the column verification information includes verification data for each column of the data to be corrected, and each column of data includes One bit of data in the first row of data.
  • the data waiting message is used to instruct the output module 203 to obtain the error-corrected data of the first row of data from the UCE error correction module.
  • the PS unit 2011 is configured to send the first row of data to the UCE error correction module 202 after obtaining the UCE data transmission message.
  • the HA unit 2012 is used to read the column check information and send the column check information to the UCE error correction module 202.
  • the UCE error correction module 202 is configured to respond to the determination that the column check information includes correctable errors, check each bit of data in the first row of data according to the column check information, and if it is determined that the bit data is incorrect, then the Error correction is performed on the bit data, and the error-corrected data of the first row of data is sent to the output module 203 .
  • the output module 203 is used to obtain the first row of data from the PS unit 2011, or the error-corrected data of the first row of data from the verification unit 2013, or the error-corrected data of the first row of data from the UCE error correction module 202. .
  • the output module 203 is also used to output the error-corrected data of the first row of data from the PS unit 2011 or the first row of data from the verification unit 2013 when the data waiting message is not obtained within the set time period, or to When the data waiting message is obtained within a certain time period, the error-corrected data of the first row of data from the UCE error correction module 202 is output.
  • each module mentioned above is only used as examples to illustrate each module in the architecture shown in Figure 1 , and are not intended to limit each module in the architecture shown in Figure 1 .
  • the verification unit 2013 may not need to send an error correction notification message to the HA unit 2012 and a data waiting message to the output module 203 .
  • the HA unit 2012 obtains the first row of data from the PS unit 2011 within the set time period, it reads the column check information and sends the column check information to the UCE error correction module 202 .
  • Figure 1 shows that the interaction and collaboration between modules in the architecture can be flexibly adjusted according to actual application scenarios, and is not limited here.
  • the system architecture shown in Figure 1 is only an example. In some other examples, there may be more or fewer components than shown in Figure 1, and two or more components may be combined. Or could have different component configurations.
  • the HA unit and the PS unit do not need to be provided separately.
  • the functions of the HA unit and the PS unit can be performed by one unit, which is a chip.
  • the chip can simultaneously perform the functions of the HA unit and the PS unit.
  • the various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application specific integrated circuits.
  • This application provides a A data error correction method can be applied to the data to be corrected stored in the memory 10, and the data structure of the data to be corrected can have various situations.
  • the possible data structure of the data to be corrected can be as follows:
  • the data to be corrected can be stored in multiple rows of data.
  • the number of bits in each row of data to be corrected can be the same or different.
  • the data to be corrected is N rows and M columns of data, and each row of data can be M-bit data, where N and M are positive integers.
  • column check information can be set for M columns of data, for example, one bit of check data can be set for each column of data, and row check information can also be set for each row of N rows of data.
  • verification information can also be set for the column verification information of the data to be corrected, so as to verify the column verification information of the data to be corrected.
  • each row of data or each column of data has corresponding verification information, making it easier to correct errors.
  • the number of bits in each row of data in the data to be corrected can also be different.
  • the data to be corrected is N rows of data, and the N rows of data include M+1 bits of data and M-1 bits of data.
  • the error correction method is the same when each row of data in the data to be corrected is different and the data in each row of the data to be corrected is the same. You can refer to the situation in which the data in each row of the data to be corrected is the same.
  • the data to be corrected may not be stored in multiple rows of data. In any of these situations, a data error correction method provided by this application can be used, which will not be described again here.
  • the data in each column of the data to be corrected and the column check information of the data in that column can be in the same column or in different columns.
  • the data in each row of data to be corrected and the row check information of the data in that row can be in the same column or different. OK.
  • the content of the verification information of the data to be corrected is also not limited.
  • the row check information of each row of data to be corrected can be ECC
  • the column check information of each column of data can be parity check code.
  • the row check information of each row of data to be corrected can be a parity check code
  • the column check information of each column of data can be ECC. If the row check information or column check information of the data to be corrected is a parity check code, the parity check code can be set to one bit, thereby saving data storage space.
  • the storage medium shown in Figure 2 is a memory, and the data to be corrected in the data block in the memory is N rows and M columns of data.
  • N is 256 and M is 256;
  • the ECC of each row of error-corrected data in the 256 rows of error-corrected data is 32 bits, and the checksum of each column of the error-corrected data in the 256 columns of error-corrected data is
  • the code is the parity check code of the column of data to be corrected, and the parity check code of each column of data to be corrected is a one-bit parity check code.
  • the storage method of data blocks on storage particles is not limited.
  • data blocks can be stored on 8 storage particles, each storage particle is a 32-bit storage particle; it can also be distributed Stored on 4 storage particles, each storage particle is a 64-bit storage particle.
  • Figure 2 only illustrates an example case where the data to be corrected is 256 rows and 256 columns. For other cases of N rows and M columns of data and other cases of data to be corrected, refer to Figure 2 and related descriptions.
  • the data to be corrected and the verification information of the data to be corrected may be updated. Obviously, if the data is corrected, the verification information of the data to be corrected will also be updated accordingly. Taking the data block shown in Figure 2 as an example, if at least one row of data among the 256 rows of data is updated, the verification information of the data to be corrected can also be updated accordingly, for example, the column verification information of the data to be corrected will be updated accordingly.
  • the data update of the error data to be corrected and the verification information can be performed by the PS unit shown in FIG. 1 . The following shows the data structure of the data block in conjunction with Figure 2, and explains in detail the process of data update in the data block.
  • the column verification information of the data to be corrected is generated based on the data to be corrected, and the data to be corrected and the data to be corrected are The column check information of the data is written to the storage medium.
  • Column verification letters can also be generated based on column verification information.
  • the verification information of the column verification information is stored in the storage medium.
  • the specific situation of updating the column verification information of the data to be corrected can be as follows:
  • the column check information of the data to be corrected can be updated synchronously.
  • the synchronous update means that the update of the data to be corrected and the update of the column check information of the data to be corrected are synchronized.
  • the data to be corrected and the column check information of the data to be corrected are synchronized.
  • the validity of the column check information of the data to be corrected is consistent. For example, when the data structure of the data block is shown in Figure 2, after the data to be corrected (256 rows of data) is updated, for example, after any row of data in the data to be corrected is updated, the data can be updated based on the updated data of this row.
  • Column verification information of the data to be corrected and synchronously writes the updated row of data and column verification information to the storage medium.
  • the common valid bits of the data to be corrected and the column check information can be set. While the updated row of data and column check information have not yet been written to the storage medium, The valid bit can indicate that the data to be corrected and the column check information are invalid.
  • the timing process can be shown in Figure 3. When the valid bit indicates that the data to be corrected and the column check information are valid, verification can be performed based on the column check information.
  • the updated data and column check information are synchronously written to the storage medium, which can ensure the correctness of the update of the column check information.
  • the specific synchronous update method can be:
  • the column check information is a parity check code
  • the parity of the column where the updated data is located changes, and the parity is updated.
  • the specific method of the preset operation is not limited.
  • the preset operation can be an XOR operation.
  • the XOR operation is more efficient and can directly indicate the changed bit data.
  • the preset operation can also be other operations, such as bitwise addition and then inversion, and the operation result can also directly indicate the data of the changed bit.
  • the update of the column check information of the data to be corrected can be an asynchronous update.
  • the data to be corrected in the storage medium is read according to a set period; if it is determined that the data to be corrected is If the error correction data is updated within the set period, the column check information is updated according to the updated error data to be corrected.
  • asynchronous update means that the data to be corrected and the column verification information are updated asynchronously. It may happen that the data to be corrected has been updated, but the column verification information has not been updated. For example, when the data structure of the data block shown in Figure 2 is used, after reading the data block according to the set period, it is determined that the two rows of data in the data to be corrected are updated, and based on the updated two rows of data, Update column verification information.
  • the valid bit of the column check information can be set.
  • the valid bit can indicate that the column check information is invalid.
  • the data to be corrected is always valid by default, and its timing process can be shown in Figure 4.
  • the valid bit indicates that the column check information is valid, verification can be performed based on the column check information.
  • it can be determined according to the set period whether the data to be corrected is updated, and when it is determined that the data to be corrected is updated, the column check information is further updated, so that frequent access to the data to be corrected is not required. Even if there is incorrect data, the column verification information can also be updated according to the set period.
  • the set period can be a fixed period or a dynamically changing period.
  • the set period can be updated in the following manner:
  • the frequency interval corresponding to the update frequency of the data to be corrected is R1 ⁇ R5 and R1 ⁇ R5 do not overlap, and the update frequency of the data to be corrected must be in a frequency range from R1 to R5.
  • the five frequency intervals R1 to R5 correspond to the five periods T1 to T5.
  • the median value of the frequency interval can be set to be negatively correlated with the size of the set period.
  • the period corresponding to the frequency interval can be set to be the reciprocal of the median value of the frequency interval. .
  • the setting period can be adjusted by the update frequency of the data to be corrected, so that the update frequency of the column check information is adapted to the update frequency of the data to be corrected, making data error correction more coordinated.
  • the storage medium as a memory as an example, assume that the data block where the error correction data is located is the first data block, and the memory also includes a second data block and a third data block. Before updating the setting period, the third data block The storage address information of the first data block is stored in the second data block.
  • the second data block corresponds to the first frequency interval.
  • the third data block corresponds to the second frequency interval.
  • the first frequency interval is the same as The second frequency intervals do not overlap.
  • the set period is the period corresponding to the first frequency interval, then the process of reading the data to be corrected according to the set period can be:
  • the storage address information is read from the second data block, and the third data block is read according to the storage address information read from the second data block.
  • the storage address information is read from the third data according to the period corresponding to the second frequency interval, and the storage address information is read according to the period corresponding to the second frequency interval. According to the storage address information, the data to be corrected in the first data block is read.
  • each of the data blocks B1 to B5 can store the storage address of the first data block.
  • the corresponding update frequency of B5 is greater than 30 minutes.
  • the storage address information of the first data block can only be retained in the data block corresponding to the update frequency. When the frequency interval corresponding to any data block in B1 to B5 does not match the update frequency, the first data in the data block can be The storage address information of the block is deleted.
  • the frequency interval can be read from different data blocks through the correspondence with the data block and the correspondence with the period.
  • the setting period can be updated more accurately.
  • asynchronous update of column verification information can be as follows:
  • the operation result is used to indicate the updated row of data and the data before the row is updated.
  • Column check information can be updated based on the operation results.
  • the column check information is a parity check code
  • the preset operation may be an XOR operation. The XOR operation is more efficient and can directly indicate the changed bit data. The specific method of the preset operation is not limited.
  • the preset operation can be an XOR operation.
  • the XOR operation is more efficient and can directly indicate the changed bit data.
  • the preset operation can also be other operations, such as bitwise addition and then inversion, and the operation result can also directly indicate the data of the changed bit.
  • the UCE in the data to be corrected can be corrected for various situations and update situations of the data structure of the data to be corrected and the verification information.
  • a data error correction method provided by an embodiment of the present application will be described in detail below with reference to FIG. 6 , which can be executed by the architecture shown in FIG. 1 .
  • the data error correction method shown in Figure 6 takes the data to be corrected as multi-row data as an example.
  • the first row of data does not represent the order in the multi-row data.
  • the first row of data can It is any row of data among multiple rows of data.
  • Step 601 Determine that UCE exists in the first row of data.
  • the way to determine whether a row of data has UCE can be as follows:
  • Step 601 may be performed by the PS unit 2011 shown in FIG. 1 .
  • the first row of data is the only row containing uncorrectable errors among the multiple rows of data, thereby ensuring that even if there are errors in the remaining rows of data, they are CE and can be corrected. error, thereby ensuring the reliability of data error correction.
  • step 602 For any row of data in the data to be corrected, if there is a CE in the row of data, perform error correction on the CE in the row of data according to the row check information stored in the row of data.
  • the row check information can be used to correct CE errors independently without the help of column check information.
  • Step 602 may be performed by the verification unit 2013 shown in FIG. 1 .
  • the CE in the data to be corrected can be corrected first, so that before correcting the UCE error of the first row of data, the CE of the remaining rows can be ensured. Even if there are CEs in the data, they have been corrected. On this basis, the UCEs in the first row of data can be corrected more accurately.
  • Step 602 is an optional step. When the data error correction method shown in FIG. 6 is executed, step 603 or 604 can be directly executed after step 601.
  • step 603 If it is determined that the column check information includes CE; in response to the above determination, perform error correction on the column check information according to the check information of the column check information.
  • Step 603 may be performed by the verification unit 2013 shown in FIG. 1 .
  • the CE in the column check information can be corrected first, so that before correcting the UCE error in the first row of data, the column correction can be ensured. Even if there is a CE in the verification information, it has been corrected. On this basis, the UCE in the first row of data can be corrected more accurately based on more reliable column verification information.
  • Step 603 is an optional step. When the data error correction method shown in FIG. 6 is executed, step 604 can be directly executed after step 601.
  • Step 604 Perform error correction on each column of data to be corrected based on the column check information.
  • the column verification information includes verification data for each column of the data to be corrected, and each column of data includes one bit of data in the first row of data.
  • step 604 may be as follows:
  • Step 604 For the verification data of any column of data to be corrected in the column verification information, it is recorded as the first verification data of the column data.
  • second verification data determine whether the first verification data and the second verification data of the column data are the same; if they are the same, it is determined that the column data is correct; otherwise, it is determined that there is an error in the column data.
  • Step 604 may be performed by UCE error correction module 202.
  • the first verification data can verify the correct situation of a column of data
  • the second verification data can represent the current actual situation of a column of data. Then, when the first verification data and the second verification data are different, it can The number of columns can be determined The data is not stored as it should be, thus determining the data error in the corresponding bit of the column of data in the first row of data.
  • Step 605 Verify the error-corrected first row of data according to the row verification information of the first row of data.
  • step 605 The details of step 605 can be as follows:
  • the row verification information of the first row of data is recorded as the first row of verification information.
  • the row verification information is generated based on the first row of data.
  • the generated row verification information is recorded as the second row of verification information; if the first row of data is verified If the information is the same as the second line of verification information, the verification passes, otherwise the verification fails.
  • Step 605 is an optional step that can further increase the reliability of UCE error correction in the data to be corrected. After step 605 is executed, if the verification passes, it is determined that the UCE error correction in the data to be corrected is successful. Step 605 may be performed by the verification unit 2013 shown in FIG. 1 .
  • each column of the first data is corrected based on the column verification information of the first data.
  • the bit of data in the first row of data if the bit of data is wrong, then after the error correction is performed in the column where the bit of data is located, the bit of data will be corrected, so even if the first row of data is Even if there are uncorrectable errors that span multiple storage units, the first row of data can also be corrected bit by bit, thereby realizing UCE error correction.
  • FIG 7 is a schematic structural diagram of a data error correction device provided by an embodiment of the present application.
  • the above-mentioned data error correction device provided by the embodiment of the present application can implement all the method steps implemented by the embodiment of the above-mentioned data error correction method, and can achieve the same technical effect. The same as the method embodiment in this embodiment will no longer be used. The parts and beneficial effects will be described in detail.
  • the embodiment of the present application provides a data error correction device, including:
  • Determining module 701, used to determine that the first row of data to be corrected includes uncorrectable errors
  • the error correction module 702 is configured to perform error correction on each column of the data to be corrected based on the column check information of the data to be corrected, wherein the column check information includes the column check information of the data to be corrected. Verification data for each column of data, where each column of data includes one bit of data in the first row of data.
  • the error correction module 702 is also used to:
  • the error-corrected first row of data is verified according to the row verification information of the first row of data.
  • the data to be corrected includes multiple rows of data, and the first row of data is the only row among the multiple rows of data that includes uncorrectable errors.
  • the column verification information has corresponding verification information
  • the error correction module 702 is also used to:
  • the column check information includes correctable errors; in response to the above determination, error correction is performed on the column check information according to the check information of the column check information.
  • the device also includes an update module 703, which is used to:
  • the column check information is updated according to the updated data to be corrected.
  • An embodiment of the present application also provides an electronic device, which may have a structure as shown in FIG. 8 .
  • the electronic device may be a computer device, or may be a chip or chip system that can support the computer device to implement the above method.
  • the electronic device as shown in Figure 8 may include at least one processor 801, which is configured to be coupled with a memory, read and execute instructions in the memory to implement the data error correction provided by the embodiments of the present application. steps of method steps.
  • the electronic device may also include a communication interface 802 for supporting the electronic device to receive or send signaling or data.
  • the communication interface 802 in the electronic device can be used to interact with other electronic devices.
  • the processor 801 may be used to implement the steps of the electronic device performing the data error correction method.
  • the electronic device may also include a memory 803 in which computer instructions are stored.
  • the memory 803 may be coupled with the processor 801 and/or the communication interface 802 to support the processor 801 in calling the computer instructions in the memory 803 to implement Steps of the data error correction method; in addition, the memory 803 can also be used to store data involved in the method embodiments of the present application, for example, to store the data and instructions necessary to support the communication interface 802 to implement interaction, and/or to Store the configuration information necessary for the electronic device to execute the method described in the embodiment of this application.
  • Embodiments of the present application also provide a computer-readable storage medium.
  • Computer instructions are stored on the computer-readable storage medium. When these computer instructions are called and executed by a computer, they can cause the computer to complete any one of the above method embodiments and method embodiments. methods involved in possible designs.
  • the computer-readable storage medium is not limited. For example, it may be RAM (random-access memory), ROM (read-only memory), etc.
  • This application also provides a chip, which may include a processor and an interface circuit, for completing the above method embodiments and the methods involved in any possible implementation of the method embodiments, where "coupling" means The two components are coupled to each other directly or indirectly, and this coupling may be fixed or removable.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of computer instructions.
  • the computer instructions When the computer instructions are loaded and executed on a computer, processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber) or wireless (such as infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated.
  • the available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), etc.
  • the steps of the method or algorithm described in the embodiments of this application can be directly embedded in hardware, a software unit executed by a processor, or a combination of the two.
  • the software unit may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, register, hard disk, removable disk, CD-ROM or any other form of storage medium in the art.
  • the storage medium can be connected to the processor, so that the processor can read information from the storage medium and can store and write information to the storage medium.
  • the storage medium can also be integrated into the processor.
  • the processor and the storage medium can be installed in the ASIC, and the ASIC can be installed in the terminal device.
  • the processor and the storage medium may also be provided in different components in the terminal device.
  • These computer instructions may also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on the computer or other programmable device to produce computer-implemented processes, thereby causing the instructions to execute on the computer or other programmable device
  • steps for implementing the functionality specified in a process or processes in a flow diagram and/or in a block or blocks in a block diagram are also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on the computer or other programmable device to produce computer-implemented processes, thereby causing the instructions to execute on the computer or other programmable device.

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Abstract

本发明公开了一种数据纠错方法及装置。其中方法应用于存储介质(如内存)中的待纠错数据，待纠错数据设置了列校验信息，列校验信息包括对所述待纠错数据的每一列数据的校验数据，该方法为：确定待纠错数据中的第一行数据包括不可纠正错误，基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，每一列数据中包括第一行数据中的一位数据。对于第一行数据的每一位数据而言，如果该位数据是错误的，那么该位数据所在列进行纠错后，该位数据便会被纠错，从而可以对第一行数据中的不可纠正错误进行纠错。

Description

一种数据纠错方法及装置
本申请要求于2022年3月21日提交中国专利局、申请号为202210279415.1、发明名称为“一种数据纠错方法及装置”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，尤其涉及一种数据纠错方法及装置。
背景技术
存储介质可以从可靠性、可实用性以及可服务性(reliability，availability，serviceability，RAS)进行考量。随着存储介质技术的发展，存储介质的工艺逐渐微缩，数据存储密度越来越高，如内存的数据存储密度越来越高。然而，存储介质中可能会出现数据错误，因此，随着数据存储密度越来越高，存储介质的RAS要求也越来越高。
已有技术中，为了保障存储介质的RAS，存储介质中可以存储数据的纠错码(error correction code，ECC)对数据进行纠错。存储介质中数据发生的错误可以分为两种，一种为可纠正错误(corrected error，CE)，也即该类错误是可以基于ECC按照已有的纠错算法进行纠错的，CE通常发生在存储介质的一个存储单元中，发生的数据大小通常为1比特；举例来说，内存颗粒便是内存中的一个存储单元，内存中的CE通常发生在一个内存颗粒中。另一种为不可纠正错误(uncorrected error，UCE)，也即该类错误并不能基于ECC按照已有的纠错算法进行纠错，这类错误通常跨了存储介质的多个存储单元，发生的数据大小为多个比特。所以，为了提升存储介质的RAS，亟需一种能够纠错存储介质中UCE的纠错方案。
发明内容
本申请提供一种数据纠错方法及装置，用以对存储介质中待纠错数据的UCE进行纠错。
第一方面，本申请提供了一种数据纠错方法，应用于存储介质中的待纠错数据。举例来说，存储介质可以为内存或硬盘等。该方法可以由本申请实施例提供的一种数据纠错装置执行，数据纠错装置可以为本申请提供的一种电子设备。所述方法包括：
确定待纠错数据的第一行数据包括不可纠正错误；基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，其中，所述列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。
本申请提供了一种数据纠错方法中，确定第一数据的第一行数据包括不可纠正错误后，由于所述第一数据的列校验信息包括对所述第一数据的每一列数据的校验数据，且所述每一列数据中包括所述第一行数据中的一位数据，那么基于所述第一数据的列校验信息对所述第一数据的每一列数据分别进行纠错后，对于第一行数据的每一位数据而言，如果该位数据是错误的，那么该位数据所在列进行纠错后，该位数据便会被纠错，所以即便第一行数据中存在跨了多个存储单元的不可纠正错误，也能对第一行数据逐位地进行纠错，从而实现了UCE 纠错。
待纠错数据的数据结构的情形可以有多种，一种可能的实现方式中，待纠错数据包括多行数据，每行数据的位数既可以相同也可以不同。基于该情形，可以在第一行数据为所述多行数据中唯一包括不可纠正错误的行时，执行本申请提供的一种数据纠错方法。
上述方式下，多行数据中除第一行数据之外的其他行数据都更加可靠，从而基于列校验信息对所述待纠错数据的每一列数据分别进行纠错时，提升了数据纠错的可靠性。
待纠错数据设置校验信息的情形也可以有多种，一种可能的情形中，待纠错数据中的每行数据还可以设置行校验信息，从而可以通过行校验信息对每行数据进行校验。
可选的，在对第一行数据进行纠错之前，还可以先根据行校验信息对出现可纠正错误的一行数据进行纠错，具体可以如下：
针对待纠错数据的任一行数据，根据该行数据的行校验信息对该行数据进行校验，若确定该行数据中存在可纠正错误，则对该行数据中的可纠正错误进行纠错。
可选的，在对第一行数据进行纠错之后，还可以进一步校验纠错是否成功，具体可以如下：
根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
一种可能的实现方式中，列校验信息也可以设置对应的校验信息，在确定所述列校验信息包括可纠正错误后，可以响应上述确定，并根据所述列校验信息的校验信息对所述列校验信息进行纠错。
通过上述方式，即便列校验信息出现了可纠正错误，也可以根据所述列校验信息的校验信息对所述列校验信息进行纠错，从而使得列校验信息的可靠性更强。
显然，存储介质中的待纠错数据可能会更新，相应地也要更新列校验信息。
一种可能的实现方式中，更新所述存储介质中的所述待纠错数据；根据更新后的待纠错数据更新所述列校验信息。
通过上述方式，可以使得列校验信息随着待纠错数据的更新而及时更新，保证了列校验信息的可靠性。
第二方面，本申请提供了一种数据纠错装置，该装置包括：
确定模块，用于确定待纠错数据的第一行数据包括不可纠正错误；
纠错模块，用于基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，其中，所述列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。
可选的，所述纠错模块还用于：
根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
可选的，所述待纠错数据包括多行数据，所述第一行数据为所述多行数据中唯一包括不可纠正错误的行。
可选的，所述列校验信息存在对应的校验信息，所述纠错模块还用于：
确定所述列校验信息包括可纠正错误；响应上述确定，根据所述列校验信息的校验信息对所述列校验信息进行纠错。
可选的，所述装置还包括更新模块，所述更新模块用于：
更新所述存储介质中的所述待纠错数据；
根据更新后的待纠错数据更新所述列校验信息。
第三方面，本申请提供一种电子设备，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机指令，当所述一个或多个计算机指令被所述一个或多个处理器执行时，使得所述电子设备执行如上述第一方面中任一项所述的方法。
第四方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质包括计算机指令，当计算机指令在计算机上运行时，使得所述计算机执行如上述第一方面中任一项所述的方法。
以上第二方面到第四方面的有益效果，请参见第一方面的有益效果，不重复赘述。
附图说明
图1为本申请实施例提供的一种数据纠错方法可应用的架构示意图；
图2为本申请实施例提供的一种数据纠错方法可应用的待纠错数据的数据结构示意图；
图3为本申请实施例提供的一种数据纠错方法中列校验信息同步更新情形的时序示意图；
图4为本申请实施例提供的一种数据纠错方法中列校验信息异步更新情形的时序示意图；
图5为本申请实施例提供的一种数据纠错方法中列校验信息异步更新情形中第一数据块的存储地址信息的存储示意图；
图6为本申请实施例提供的一种数据纠错方法的流程示意图；
图7为本申请实施例提供的一种数据纠错装置的结构示意图；
图8为本申请实施例提供的一种电子设备结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请实施例中，“一个或多个”是指一个或两个以上(包含两个)；“和/或”，描述关联对象的关联关系，表示可以存在三种关系；例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请实施例中的术语多个”是指两个或两个以上，鉴于此，本申请实施例中也可以将 “多个”理解为“至少两个”。“至少一个”，可理解为一个或多个，例如理解为一个、两个或更多个。例如，包括至少一个，是指包括一个、两个或更多个，而且不限制包括的是哪几个。例如，包括A、B和C中的至少一个，那么包括的可以是A、B、C，A和B，A和C，B和C，或A和B和C。同理，对于“至少一种”等描述的理解，也是类似的。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。
除非有相反的说明，本申请实施例提及“第一”、“第二”等序数词用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
为了便于理解，对本申请实施例涉及的术语进行解释说明，该术语的解释说明也作为对本申请实施例发明内容的一部分。
存储介质中可以存储待纠错数据以及待纠错数据的校验信息，通过待纠错数据的校验信息对待纠错数据进行纠错。目前的纠错算法可以对待纠错数据的CE进行纠错，但不能对待纠错数据的UCE进行纠错。为此，本申请提供了一种数据纠错方法。以存储介质为内存为例，图1示出了本申请提供的一种数据纠错方法可应用的架构示意图。
图1示出的架构包括内存10和中央处理器(central processing unit，CPU)20。CPU20上设置了统一内存控制器(unified memory controller，UMC)201、UCE纠错模块202和输出模块203。UMC201包括巡检扫描(patrol scanning，PS)单元2011、本地代理(home agent，HA)单元2012和校验单元2013。图1中示出的UMC201、UCE纠错模块202和输出模块203可以在包括一个或多个信号处理和/或专用集成电路在内的硬件、软件、或硬件和软件的组合中实现，例如可以在一个计算机设备中实现。
其中，在上述各部件由硬件实现的情况下，内存10可以与校验单元2013连接，校验单元2013还可以与PS单元2011、HA单元2012和输出模块203连接；HA单元2012与PS单元2011以及输出模块203连接；UCE纠错模块202可以与PS单元2011、HA单元2012和输出模块203连接。
本申请实施例并不限定上述各部件的具体形态。举例来说，内存10可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)、动态随机存取存储器(dynamic random access memory,DRAM)等。也可以包括非易失性存储器(non-volatile memory)，例如存储级存储器(storage-class memory，SCM)等，或者易失性存储器与非易失性存储器的组合等。UMC201可以包括数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件、人工智能芯片、片上芯片等。UMC201中的各单元可以为独立的器件，也可以为内置在一个器件中的单元。UCE纠错模块202以及输出模块203也可以不限定形态，UCE纠错模块202以及输出模块203可以为FPGA或者其他可编程逻辑器件。
图1示出的架构中各部件的功能具体可以如下：
内存10用于存储待纠错数据。内存10可以通过数据块的方式存储待纠错数据，例如待纠错数据为内存中任一数据块的数据，待纠错数据的校验信息可以一同存储在一个数据块中，也可以存储在其他位置。本申请实施例中对待纠错数据的数据结构也不做限定。待纠错数据可以按行列存储，也可以不按行列存储。举例来说，按行列存储时，待纠错数据可以为N行 M列数据，N和M为正整数，此时待纠错数据的校验信息可以包括N行数据中每行数据的行校验信息和列校验信息，列校验信息包括对所述待纠错数据的每一列数据的校验数据。
下面以待纠错数据为N行M列数据，且待纠错数据的校验信息和待纠错数据存储在同一数据块为例，描述本申请提供的一种数据纠错方法可应用的架构。CPU20用于对待纠错数据进行纠错。在UMC201中，PS单元2011用于读取待纠错数据，可以将第一行数据以及第一行数据的行校验信息发送至校验单元2013，以及将第一行数据发送至输出模块203，第一行数据为待纠错数据中任一行数据。
校验单元2013用于根据获取到的第一行数据的行校验信息对第一行数据进行行校验，若确定第一行数据正确，则继续获取待纠错数据中的行数据以及该行数据的行校验信息；若确定第一行数据中出现CE，则对CE进行纠错，以及将第一行数据纠错后的数据发送至输出模块203；若确定第一行数据中出现UCE，则校验单元2013向PS单元2011发送UCE数据传输消息，向HA单元2012发送纠错通知消息，以及向输出模块203发送数据等待消息。
其中，UCE数据传输消息用于指示PS单元2011将第一行数据发送至UCE纠错模块202。纠错通知消息用于指示HA单元2012读取待纠错数据的列校验信息，列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。数据等待消息用于指示输出模块203获取来自UCE纠错模块的第一行数据纠错后的数据。
PS单元2011用于在获取到UCE数据传输消息后，将第一行数据发送至UCE纠错模块202。
HA单元2012用于读取列校验信息，并将列校验信息发送至UCE纠错模块202。
UCE纠错模块202用于响应列校验信息包括可纠正错误的确定，根据所述列校验信息对第一行数据的每一位数据进行校验，若确定该位数据错误，则对该位数据进行纠错，并将第一行数据纠错后的数据发送至输出模块203。
输出模块203用于获取来自PS单元2011的第一行数据，或者来自校验单元2013的第一行数据纠错后的数据，或者来自UCE纠错模块202的第一行数据纠错后的数据。输出模块203还用于在设定时长内未获取数据等待消息时，将来自PS单元2011的第一行数据或者来自校验单元2013的第一行数据纠错后的数据输出，或者，在设定时长内获取到数据等待消息时，将来自UCE纠错模块202的第一行数据纠错后的数据输出。
需要说明的是，上述各模块的作用仅作为图1示出的架构中各模块的示例说明，并不是对图1示出架构中各模块的限定。举例来说，若确定第一行数据中出现UCE，校验单元2013可以无需向HA单元2012发送纠错通知消息以及向输出模块203发送数据等待消息。HA单元2012若在设定时长内获取来自PS单元2011的第一行数据，便读取列校验信息，并将列校验信息发送至UCE纠错模块202。图1示出架构中各模块间的交互协作方式可以根据实际应用场景灵活调整，在此不进行限定。
应理解，图1示出的系统架构仅为一个示例，在一些其它例子中，可以具有比图1中所示出的更多的或者更少的部件，可以组合两个或更多的部件，或者可以具有不同的部件配置。举例来说，可以不分别设置HA单元和PS单元，HA单元和PS单元的功能可由一个单元执行，该单元为一个芯片，该芯片可以同时执行HA单元和PS单元的功能。图中所示出的各种部件可以在包括一个或多个信号处理和/或专用集成电路在内的硬件、软件、或硬件和软件的组合中实现。
基于图1示出的架构，下面详细介绍本申请提供的一种数据纠错方法。本申请提供的一 种数据纠错方法可以应用于内存10中存储的待纠错数据，待纠错数据的数据结构可以有多种情形。
待纠错数据的数据结构可能的情形可以如下：
待纠错数据可以按照多行数据的方式存储。待纠错数据中每行数据的位数可以相同，也可以不同。待纠错数据中每行数据的位数相同的情形中，举例来说，待纠错数据为N行M列数据，每行数据为可以为M位数据，N，M为正整数。在这种方式设置下，可以为M列数据设置列校验信息，例如每列数据设置一位校验数据，还可以为N行数据的每行数据设置行校验信息。并且，还可以为待纠错数据的列校验信息设置校验信息，用于为待纠错数据的列校验信息进行校验。显然，当待纠错数据既设置有行校验信息又设置有列校验信息时，可以通过每行数据的行校验信息对该行数据进行校验，若出现了UCE，由于还设置有列校验信息，可以进行多维校验，从而增加了数据纠错的效率。并且，采用该例子的方式，每行数据或每列数据都有相应的校验信息，从而更便于纠错。
待纠错数据中每行数据的位数也可以不同，举例来说，待纠错数据为N行数据，N行数据中包括M+1位的数据和M-1位的数据。待纠错数据中每行数据不同的情形与待纠错数据中每行数据相同的情形纠错方式同理，可以参照待纠错数据中每行数据相同的情形。待纠错数据还可以不按照多行数据的方式存储。这些情形均可以运用本申请提供的一种数据纠错方法，在此不再赘述。
待纠错数据的校验信息的数据结构也存在各种情形，且这些情形可以与上述待纠错数据的各种情形相结合。举例来说，待纠错数据的每列数据与该列数据的列校验信息可以同列也可以不同列，待纠错数据的每行数据与该行数据的行校验信息可以同行也可以不同行。
待纠错数据的校验信息的内容也不做限定。举例来说，待纠错数据的每行数据的行校验信息可以为ECC，每列数据的列校验信息可以为奇偶校验码。再例如，待纠错数据的每行数据的行校验信息可以为奇偶校验码，每列数据的列校验信息可以为ECC。若待纠错数据的行校验信息或列校验信息为奇偶校验码时，可以设置奇偶校验码为一位，从而可以节约数据的存储空间。
综合上述待纠错数据以及校验信息的描述，以图2示出的数据块为例进行说明。图2示出的存储介质为内存，内存中数据块的待纠错数据为N行M列数据。在图2的示例中，N取256，M取256；256行待纠错数据中每行待纠错数据的ECC为32位，256列待纠错数据中每列待纠错数据的校验码为该列待纠错数据的奇偶校验码，每列待纠错数据的奇偶校验码为一位奇偶校验码。数据块在存储颗粒上的存储方式不做限定，举例来说，在图2的示例中，数据块可以在8个存储颗粒上存储，每个存储颗粒均为32位的存储颗粒；也可以分布在4个存储颗粒上存储，每个存储颗粒均为64位的存储颗粒。应理解，图2仅以待纠错数据为256行256列数据的示例情形来说明，N行M列数据的其它情形以及待纠错数据的其它情形，都可以参照图2及相关描述。
需要说明的是，待纠错数据以及待纠错数据的校验信息可能会更新。显然，若纠错数据，待纠错数据的校验信息也要随之更新。以图2示出的数据块为例，若256行数据中至少一行数据更新，待纠错数据的校验信息也可以随之更新，如待纠错数据的列校验信息会随之更新。待纠错数据以及校验信息的数据更新可由图1示出的PS单元执行。下面结合图2示出数据块的数据结构，详细说明数据块中数据更新的过程。在待纠错数据更新之前，可能有如下写入存储介质的过程：获取待纠错数据后，根据待纠错数据生成待纠错数据的列校验信息，将待纠错数据、待纠错数据的列校验信息写入至存储介质。还可以根据列校验信息生成列校验信 息的校验信息，并将列校验信息的校验信息存储到存储介质。
待纠错数据的列校验信息更新的具体情形可以如下：
待纠错数据的列校验信息可以为同步更新，需要说明的是，同步更新是待纠错数据的更新与待纠错数据的列校验信息的更新都是同步的，待纠错数据与待纠错数据的列校验信息有效性是一致的。举例来说，当采用图2示出数据块的数据结构时，待纠错数据(256行数据)更新后，例如待纠错数据中任一行数据更新后，可以根据这一行更新的数据，更新待纠错数据的列校验信息，并同步将更新的一行数据和列校验信息写入存储介质。
待纠错数据的列校验信息的同步更新在具体实现时，可以设置待纠错数据及列校验信息共同的有效位，在更新的一行数据与列校验信息尚未写入存储介质期间，有效位可以指示待纠错数据及列校验信息均无效，时序过程可以如图3所示。可以在有效位指示待纠错数据及列校验信息有效的情况下，再根据列校验信息进行校验。在列校验信息同步更新的过程中，同步将更新的数据和列校验信息写入存储介质，可以保证列校验信息的更新正确性。
以待纠错数据中任一行数据与列校验信息的同步更新为例，具体的同步更新方法可以为：
将更新的一行数据与该行更新前的数据进行预设运算，获得运算结果，运算结果用于指示更新的一行数据与该行更新前的数据不同位的数据；从而可以根据运算结果更新列校验信息。举例来说，当列校验信息为奇偶校验码时，对于更新的一行数据中每一位更新的数据而言，该位更新的数据所在列的奇偶性就发生了变化，更新奇偶校验码即可。其中，预设运算的具体方式不做限定，举例来说，预设运算可以为异或运算。异或运算的运算效率较高且能够直接指示出变更位的数据。预设运算还可以为其它运算，如按位相加运算再取反，运算结果也可以直接指示出变更位的数据。
待纠错数据的列校验信息的同步更新方式下，无需根据待纠错数据的所有数据，只需要根据更新的数据，即可通过运算结果表征出列校验信息中需要更新的数据。
待纠错数据的列校验信息的更新可以为异步更新，异步更新的一种可能的情形中，按照设定周期读取所述存储介质中的所述待纠错数据；若确定所述待纠错数据在所述设定周期内发生了更新，则根据更新后的待纠错数据更新所述列校验信息。
需要说明的是，异步更新是指待纠错数据与列校验信息的更新是异步的，可能会出现待纠错数据已更新，但列校验信息未更新的情形。举例来说，当采用图2示出的数据块的数据结构时，按照设定周期读取数据块后，确定待纠错数据中的2行数据更新后，可以根据更新的这2行数据，更新列校验信息。
待纠错数据的列校验信息异步更新的情形中，可以设置列校验信息的有效位，在待纠错数据更新，但列校验信息尚未更新时，有效位可以指示列校验信息无效，而待纠错数据默认为一直有效，其时序过程可以如图4所示。可以在有效位指示列校验信息有效的情况下，再根据列校验信息进行校验。在列校验信息异步更新的过程中，可以按照设定周期确定待纠错数据是否存在更新，并在确定待纠错数据存在更新时进一步更新列校验信息，从而不需要频繁地访问待纠错数据，也能按照设定周期更新列校验信息。设定周期可以为固定不变的周期也可以为动态变化的周期。
在设定周期为动态变化的周期的情形下，设定周期可以按照以下方式更新：
确定待纠错数据的更新频率；若所述更新频率所位于的频率区间发生更新，则根据更新后的频率区间更新所述设定周期。举例来说，待纠错数据的更新频率对应的频率区间为 R1～R5，R1～R5之间并不重叠，待纠错数据的更新频率必然位于R1～R5中一个频率区间。5个频率区间R1～R5与5个周期T1～T5一一对应，可以设置频率区间的中值与设定周期的大小呈负相关，如设置频率区间对应的周期为频率区间的中值的倒数。采用该方式，可以通过待纠错数据的更新频率调整设定周期，从而使得列校验信息的更新频率与待纠错数据的更新频率相适应，使得数据纠错的协调性更强。
列校验信息的异步更新的一种可能的情形中，可以采用以下方式实现设定周期的更新：
以存储介质为内存为例，设待纠错数据所在的数据块为第一数据块，内存中还包括第二数据块和第三数据块，所述更新所述设定周期之前，所述第二数据块中存储了所述第一数据块的存储地址信息，所述第二数据块对应于第一频率区间，所述第三数据块对应于第二频率区间，所述第一频率区间与所述第二频率区间不重叠。
若所述更新频率位于所述第一频率区间，则所述设定周期为所述第一频率区间对应的周期，那么按照设定周期读取所述待纠错数据的过程可以为：
按照所述第一频率区间对应的周期，从所述第二数据块读取所述存储地址信息，并根据从所述第二数据块读取到的所述存储地址信息，读取所述第一数据块。
若所述更新频率由所述第一频率区间更新为所述第二频率区间，则按照所述第二频率区间对应的周期，从所述第三数据读取所述存储地址信息，并根据所述存储地址信息，读取所述第一数据块中的待纠错数据。
举例来说，以图5示出的第一数据块的存储地址信息的存储情形为例，共有5个数据块B1～B5，B1～B5中每个数据块都可以存储第一数据块的存储地址信息；其中，B1对应的更新频率为小于或等于1秒，B2对应的更新频率为大于1秒小于或等于1分钟，B3对应的更新频率为大于1分钟小于或等于10分钟，B4对应的更新频率为大于10分钟小于或等于30分钟，B5对应的更新频率为大于30分钟。可以只在与更新频率对应的数据块中保留第一数据块的存储地址信息，当B1～B5中任一数据块对应的频率区间与更新频率不匹配时，可以将该数据块中第一数据块的存储地址信息删除。
上述方式中，对于任意变更的两个频率区间，以第一频率区间和第二频率区间为例，可以通过频率区间与数据块的对应，以及与周期的对应，通过从不同的数据块中读取第一数据块的存储地址信息，可以更准确地更新设定周期。
一种可能的情形中，列校验信息的异步更新可以如下：
针对所述更新的至少一行数据中每一行数据，将更新的一行数据与该行更新前的数据进行预设运算，获得运算结果，运算结果用于指示更新的一行数据与该行更新前的数据不同位的数据；从而可以根据运算结果更新列校验信息。举例来说，当列校验信息为奇偶校验码时，对于每一列数据而言，若该列更新的数据的行数为奇数，则该列更新的数据所在列的奇偶性就发生了变化，更新奇偶校验码即可。举例来说，预设运算可以为异或运算。异或运算的运算效率较高且能够直接指示出变更的位数据。其中，预设运算的具体方式不做限定，举例来说，预设运算可以为异或运算。异或运算的运算效率较高且能够直接指示出变更位的数据。预设运算还可以为其它运算，如按位相加运算再取反，运算结果也可以直接指示出变更位的数据。
上述方式下，无需频繁访问待纠错数据，按照设定周期，只需要根据待纠错数据中更新的至少一行数据，即可通过运算结果表征列校验信息的变化，并据此更新列校验信息。
需要说明的是，对于列校验信息同步更新或者异步更新的情形，当一行数据发生更新时，该行数据的行校验信息都可以随之更新。
需要说明的是，本申请提供的数据纠错方法中，针对待纠错数据以及校验信息的数据结构的各种情形及更新情形，都可以对待纠错数据中的UCE进行纠错。下面结合图6，详细描述本申请实施例提供的一种数据纠错方法，可以由图1示出的架构执行。图6示出的数据纠错方法以待纠错数据为多行数据为例，其中第一行数据中存在UCE，第一行数据并不代表在多行数据中的顺序，第一行数据可以为多行数据中任一行数据。
步骤601：确定第一行数据中存在UCE。
具体来说，确定一行数据是否存在UCE的方式可以如下：
根据该行数据，计算得到该行数据的行校验信息，将该行数据计算得到的行校验信息与存储的行校验信息进行对比，若不一致，且通过行校验信息不能纠错，则确定该行数据中存在UCE，若一致，则确定该行数据中不存在UCE。步骤601可由图1示出的PS单元2011执行。
需要说明的是，在一些情形下，还可以确定第一行数据为所述多行数据中唯一包括不可纠正错误的行，从而可以确保其余行的数据中即便有错误也是CE，是可以被纠错的，从而可以确保数据纠错的可靠性。
可选的，步骤602：针对待纠错数据中任一行数据，若该行数据中存在CE，则根据该行数据存储的行校验信息对该行数据中的CE进行纠错。对于CE，可以不借助列校验信息，由行校验信息独立对CE纠错。
步骤602可由图1示出的校验单元2013执行。在对第一行数据的UCE纠错之前，通过执行步骤602，可以先对待纠错数据中的CE进行纠错，从而可以使得在对第一行数据中的UCE纠错之前，确保其余行的数据中即便有CE也均已被纠错，在此基础上可以更加准确地对第一行数据中的UCE进行纠错。步骤602为可选的步骤，图6示出的数据纠错方法执行时，可以在步骤601之后，直接执行步骤603或604。
可选的，步骤603：若确定所述列校验信息包括CE；响应上述确定，根据所述列校验信息的校验信息对所述列校验信息进行纠错。
步骤603可由图1示出的校验单元2013执行。在对第一行数据的UCE纠错之前，通过执行步骤603，可以先对列校验信息中的CE进行纠错，从而可以使得在对第一行数据中的UCE纠错之前，确保列校验信息中即便有CE也均已被纠错，在此基础上可以基于更加可靠的列校验信息，更加准确地对第一行数据中的UCE进行纠错。步骤603为可选的步骤，图6示出的数据纠错方法执行时，可以在步骤601之后，直接执行步骤604。
步骤604：根据列校验信息对待纠错数据的每一列数据分别进行纠错。
其中，列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括第一行数据中的一位数据。
具体来说，步骤604可以如下：
针对列校验信息中待纠错数据任一列数据的校验数据，记为该列数据的第一校验数据，计算该列数据重新计算该列数据的校验数据，记为该列数据的第二校验数据；确定该列数据的第一校验数据与第二校验数据是否相同，若相同，则确定该列数据正确，否则确定该列数据中存在错误。显然，若该列数据存在错误，那么确定第一行数据中该列数据对应位的数据错误，便对该位数据进行纠错。步骤604可以由UCE纠错模块202执行。
上述方式下，第一校验数据能够印证一列数据的正确情形，第二校验数据能够表征一列数据当前的实际情形，那么在第一校验数据与第二校验数据不同的情况下，便可以确定列数 据并没有按照应有的正确情形存储，从而确定第一行数据中该列数据对应位的数据错误。
步骤605：根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
步骤605具体可以如下：
第一行数据的行校验信息记为第一行校验信息，根据第一行数据生成行校验信息，生成的行校验信息记为第二行校验信息；若第一行校验信息与第二行校验信息相同，则校验通过，否则校验不通过。
步骤605为可选的步骤，可以进一步增加待纠错数据中UCE纠错的可靠性，步骤605执行之后，若校验通过，则确定对待纠错数据中的UCE纠错成功。步骤605可由图1示出的校验单元2013执行。
通过图6示出的一种数据纠错方法，确定第一数据的第一行数据包括不可纠正错误后，由于所述第一数据的列校验信息包括对所述第一数据的每一列数据的校验数据，且所述每一列数据中包括所述第一行数据中的一位数据，那么基于所述第一数据的列校验信息对所述第一数据的每一列数据分别进行纠错后，对于第一行数据的每一位数据而言，如果该位数据是错误的，那么该位数据所在列进行纠错后，该位数据便会被纠错，所以即便第一行数据中存在跨了多个存储单元的不可纠正错误，也能对第一行数据逐位地进行纠错，从而实现了UCE纠错。
参见图7，为本申请实施例提供的一种数据纠错装置的结构示意图。本申请实施例提供的上述数据纠错装置，能够实现上述数据纠错方法的实施例所实现的所有方法步骤，且能够达到相同的技术效果，在此不再对本实施例中与方法实施例相同的部分及有益效果进行具体赘述。
本申请实施例提供了一种数据纠错装置，包括：
确定模块701，用于确定待纠错数据的第一行数据包括不可纠正错误；
纠错模块702，用于基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，其中，所述列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。
可选的，所述纠错模块702还用于：
根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
可选的，所述待纠错数据包括多行数据，所述第一行数据为所述多行数据中唯一包括不可纠正错误的行。
可选的，所述列校验信息存在对应的校验信息，所述纠错模块702还用于：
确定所述列校验信息包括可纠正错误；响应上述确定，根据所述列校验信息的校验信息对所述列校验信息进行纠错。
可选的，所述装置还包括更新模块703，所述更新模块703用于：
更新所述存储介质中的所述待纠错数据；
根据更新后的待纠错数据更新所述列校验信息。
本申请实施例还提供一种电子设备，该电子设备可以具有如图8所示的结构，该电子设备可以是计算机设备，也可以是能够支持计算机设备实现上述方法的芯片或芯片系统。
如图8所示的电子设备可以包括至少一个处理器801，所述至少一个处理器801用于与存储器耦合，读取并执行所述存储器中的指令以实现本申请实施例提供的数据纠错方法的步 骤。可选的，该电子设备还可以包括通信接口802，用于支持该电子设备进行信令或者数据的接收或发送。电子设备中的通信接口802，可用于实现与其他电子设备的进行交互。处理器801可用于实现电子设备执行数据纠错方法的步骤。
可选的，该电子设备通还可以包括存储器803，其中存储有计算机指令，存储器803可以与处理器801和/或通信接口802耦合，用于支持处理器801调用存储器803中的计算机指令以实现数据纠错方法的步骤；另外，存储器803还可以用于存储本申请方法实施例所涉及的数据，例如，用于存储支持通信接口802实现交互所必须的数据、指令，和/或，用于存储电子设备执行本申请实施例所述方法所必须的配置信息。
本申请实施例还提供了一种计算机可读存储介质，计算机可读存储介质上存储有计算机指令，这些计算机指令被计算机调用执行时，可以使得计算机完成上述方法实施例、方法实施例的任意一种可能的设计中所涉及的方法。本申请实施例中，对计算机可读存储介质不做限定，例如，可以是RAM(random-access memory，随机存取存储器)、ROM(read-only memory，只读存储器)等。
本申请还提供一种芯片，该芯片可以包括处理器以及接口电路，用于完成上述方法实施例、方法实施例的任意一种可能的实现方式中所涉及的方法，其中，“耦合”是指两个部件彼此直接或间接地结合，这种结合可以是固定的或可移动性的。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机指令的形式实现。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。
本申请实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的软件单元、或者这两者的结合。软件单元可以存储于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介中。示例性地，存储媒介可以与处理器连接，以使得处理器可以从存储媒介中读取信息，并可以向存储媒介存写信息。可选地，存储媒介还可以集成到处理器中。处理器和存储媒介可以设置于ASIC中，ASIC可以设置于终端设备中。可选地，处理器和存储媒介也可以设置于终端设备中的不同的部件中。
这些计算机指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管结合具体特征及其实施例对本发明进行了描述，显而易见的，在不脱离本发明的范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所 界定的本发明的示例性说明，且视为已覆盖本发明范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

  1. 一种数据纠错方法，其特征在于，包括：
    确定待纠错数据的第一行数据包括不可纠正错误；
    基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，其中，所述列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。
  2. 如权利要求1所述的方法，其特征在于，还包括：
    根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
  3. 如权利要求1至2任一项所述的方法，其特征在于，所述待纠错数据包括多行数据，所述第一行数据为所述多行数据中唯一包括不可纠正错误的行。
  4. 如权利要求1至3任一项所述的方法，其特征在于，所述列校验信息存在对应的校验信息，所述方法还包括：
    确定所述列校验信息包括可纠正错误；
    响应上述确定，根据所述列校验信息的校验信息对所述列校验信息进行纠错。
  5. 如权利要求1至4任一项所述的方法，其特征在于，所述方法还包括：
    更新所述存储介质中的所述待纠错数据；
    根据更新后的待纠错数据更新所述列校验信息。
  6. 一种数据纠错装置，其特征在于，包括：
    确定模块，用于确定待纠错数据的第一行数据包括不可纠正错误；
    纠错模块，用于基于所述待纠错数据的列校验信息对所述待纠错数据的每一列数据分别进行纠错，其中，所述列校验信息包括对所述待纠错数据的每一列数据的校验数据，所述每一列数据中包括所述第一行数据中的一位数据。
  7. 如权利要求6所述的装置，其特征在于，所述纠错模块还用于：
    根据所述第一行数据的行校验信息对纠错后的第一行数据进行校验。
  8. 如权利要求6至7任一项所述的装置，其特征在于，所述待纠错数据包括多行数据，所述第一行数据为所述多行数据中唯一包括不可纠正错误的行。
  9. 如权利要求6至8任一项所述的装置，其特征在于，所述列校验信息存在对应的校验信息，所述纠错模块还用于：
    确定所述列校验信息包括可纠正错误；
    响应上述确定，根据所述列校验信息的校验信息对所述列校验信息进行纠错。
  10. 如权利要求6至9任一项所述的装置，其特征在于，所述装置还包括更新模块，所述更新模块用于：
    更新所述存储介质中的所述待纠错数据；
    根据更新后的待纠错数据更新所述列校验信息。
  11. 一种电子设备，其特征在于，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机指令，当所述一个或多个计算机指令被所述一个或多个处理器执行时，使得所述电子设备执行如权利要求1-5任一项所述的方法。
  12. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括计算机指令，当所述计算机指令在计算机上运行时，使得所述计算机执行如权利要求1-5任一项所述的方法。
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