WO2023208231A1 - 一种内存数据读写方法、系统以及内存控制器 - Google Patents

一种内存数据读写方法、系统以及内存控制器 Download PDF

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Publication number
WO2023208231A1
WO2023208231A1 PCT/CN2023/091842 CN2023091842W WO2023208231A1 WO 2023208231 A1 WO2023208231 A1 WO 2023208231A1 CN 2023091842 W CN2023091842 W CN 2023091842W WO 2023208231 A1 WO2023208231 A1 WO 2023208231A1
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Prior art keywords
data
check code
memory
channel group
target data
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PCT/CN2023/091842
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English (en)
French (fr)
Inventor
陈智勇
焦慧芳
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华为技术有限公司
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Priority claimed from CN202210841487.0A external-priority patent/CN117009130A/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023208231A1 publication Critical patent/WO2023208231A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the present application relates to the field of storage technology, and in particular to a method, system and memory controller for reading and writing memory data.
  • the DDR5 JEDEC standard introduces the concept of sub-channel (Sub-channel) in the memory.
  • the memory under the DDR5 standard It includes two sub-channels, each sub-channel includes multiple memory particles. These two sub-channels are independent of each other, and each sub-channel independently implements error checking and correcting (ECC), that is, the memory controller needs to independently verify and correct the data stored within each sub-channel.
  • ECC error checking and correcting
  • Each sub-channel implements ECC independently, and each sub-channel is equipped with memory particles for storing check codes. In practical applications, the number of such memory particles for storing check codes in each sub-channel is small, which limits Memory error correction capabilities.
  • This application provides a memory data reading and writing method, system and memory controller to improve memory error correction capabilities.
  • embodiments of the present application provide a method for reading and writing memory data.
  • the method can be executed by a memory controller or a processor integrated with a memory controller.
  • the method is used to read and write memory data.
  • memory includes one or more channel groups, and each channel group includes multiple channels.
  • the memory controller when the memory controller needs to write data to the channel group, the memory controller obtains the target data that needs to be written to the channel group; it calls the ECC algorithm to generate a check code for the target data, and the check code is used to verify the target data. Data is verified and error corrected.
  • the memory controller can write the target data and the check code into the channel group, where the target data is dispersedly stored in the channels of the channel group.
  • the check codes are distributed and stored in each channel of the channel group.
  • the check code of the target data can be dispersedly stored on the memory particles that store the check code in each channel, and the check code of the target data can be stored.
  • the larger number of code memory particles indicates that when generating a check code, a check code with a larger amount of data can be generated.
  • a check code with a large amount of data can ensure that the memory has strong error correction capabilities.
  • this method only needs to implement ECC at the channel group granularity, and does not need to change the number of memory particles that store check codes in the memory, and does not require additional memory costs.
  • each channel includes one or more RANKs, and each RANK includes multiple memory particles.
  • a channel group can include multiple RANKs, ensuring that the channel group has a large storage space to achieve large-grained data storage.
  • the memory controller after the memory controller generates the check code of the target data, when writing the target data and the check code to the channel group, the memory controller can split the target data into multiple target data segments, Among them, the multiple target data The data lengths of segments can be the same or different.
  • the memory controller splits the check code into multiple check code segments, where the data lengths of the multiple check code segments may be the same or different.
  • the memory controller can write multiple target data segments to each channel in the channel group, and write multiple check code segments to each channel in the channel group.
  • the memory controller can also read data from the channel group. Under the instruction of the processor, the memory controller can read the target data and the check code from the channel group, and use the check code to The code performs error correction on the target data. After the error correction is successful, the corrected target data is fed back to the processor.
  • the memory controller reads data from the memory at the channel group granularity and implements data error correction. Reading data at the channel group granularity can improve data reading efficiency.
  • the memory controller can also update the data in the channel group. Under the instruction of the processor, the memory controller can read the target data and check code from the channel group, and then update the target data. After the data is updated, a check code of the updated target data is generated. The memory controller writes the updated target data and the check code of the updated target data into the channel group. The updated target data is distributed and stored in the channels of the channel group. The updated check codes of the target data are distributed and stored in each channel of the channel group.
  • the memory controller updates the data in the memory at the channel group granularity.
  • the updated check code of the target data can be stored in each channel of the channel group. That is to say, before and after the update, the check code The amount of data does not change, and it can still ensure that the memory has strong error correction capabilities.
  • the data that the memory controller writes to the channel group of the memory at one time is equal to the amount of data for one interaction between the memory controller and the processor. , that is, the data that the memory controller writes to the channel group of the memory at one time can be equal to the bit width of the cache in the processor. In some scenarios, the data written by the memory controller to the channel group of the memory at one time can also be equal to a multiple of the amount of data exchanged between processors at one time. In this way, large-grained data reading and writing between the memory controller and the memory can be ensured, and the interaction efficiency between the memory controller and the memory can be improved.
  • the data written by the memory controller to one channel in the channel group at a time is equal to the bit width of the cache in the processor. That is, the memory controller can write data to the channel group at one time equal to a multiple of the bit width of the cache in the processor. In this way, the memory controller can write more data to the channel group at one time, ensuring the efficiency of the interaction between the memory controller and the memory.
  • the embodiment of the present application does not limit the number of channels in the channel group.
  • the number of channels in a channel group equals 2, 3, 4, 6, 8, 12, or 16.
  • the memory controller can call different ECC algorithms or multiple ECC algorithms when generating the check code of the target data.
  • the memory controller can call the RS encoding algorithm, cyclic redundancy check (CRC) algorithm, BCH (bose ray-chaudhuri hocquenghem) algorithm, hash (HASH) algorithm, or redundant array of independent disks (redundant Any algorithm in the array of independent disks (RAID) algorithm (such as RAID 5 algorithm, RAID 6 algorithm) generates the check code of the target data.
  • the memory controller can call any of the RS encoding algorithm, CRC algorithm, BCH algorithm, HASH algorithm, or RAID algorithm to form a two-level or multi-level ECC algorithm to generate a check code for the target data.
  • the memory controller can flexibly call one or more ECC algorithms when generating the check code of the target data, making this method applicable to a variety of different application scenarios.
  • each channel is provided with memory particles for storing check codes.
  • the memory controller sends data to the channel group at a time.
  • the maximum amount of data written in the check code is a multiple of the bit width of this type of memory particle (the value of this multiple is related to the number of memory particles and the time in one clock cycle (related to the number of reads and writes to the memory particles).
  • the data amount of the check code generated by the memory controller can be equal to the maximum data amount, so that the first check code can be distributed on each memory particle storing the check code in the channel group.
  • the data amount of the first check code generated by the memory controller can also be less than the maximum data amount, so that the first check code can be distributed on some memory particles in the channel group that store the check code or the check code only occupies Part of the storage space of the memory particle that stores the check code.
  • the distribution method of check codes is more flexible, which effectively expands the application scenarios.
  • inventions of the present application provide a memory system, which includes a memory and a memory controller.
  • the memory system includes memory and a memory controller.
  • the memory includes one or more channel groups, each channel group includes multiple channels, each channel includes one or more RANKs, and each RANK includes multiple memory particles.
  • the method is executed by the memory controller, and the method includes:
  • the memory controller can obtain the target data that needs to be written to the channel group; generate the check code of the target data, which is used to verify and correct the target data; write the target data and check code into the channel group , the check code is distributedly stored in each channel of the channel group, and the target data is distributedly stored in the channels of the channel group.
  • the memory controller can also read data from the memory.
  • the memory controller can read the target data and check code from the channel group under the instruction of the processor; use the check code to correct the target data; and feed the corrected target data back to the processor.
  • the data written into the channel group at one time is equal to the bit width of the cache in the processor.
  • the data written to one channel in the channel group at one time is equal to the bit width of the cache in the processor.
  • the number of channels in the channel group is equal to 2, 3, 4, 6, 8, 12 or 16.
  • the memory controller may call the RS8 encoding algorithm or the RS16 encoding algorithm to generate the check code of the target data.
  • Other ECC algorithms can also be called to generate check codes for target data.
  • each channel includes one or more RANKs, and each RANK includes multiple memory particles.
  • the memory controller when the memory controller writes the target data and the check code into the channel group, the memory controller can split the target data into multiple target data segments and the check code into multiple Check code segment; write multiple target data segments to each channel in the channel group, and write multiple check code segments to each channel in the channel group.
  • inventions of the present application also provide a memory controller.
  • the memory controller includes a processing unit and a cache unit.
  • the cache unit is used to cache data. For example, to cache data that needs to be written to a channel group, it can also cache the data. Data check code.
  • the processing unit may run a computer program programmed thereon to execute or run acquired computer program instructions to execute the method described in the above-mentioned first aspect and each possible implementation of the first aspect.
  • embodiments of the present application further provide a computing device, which includes the memory system mentioned in the second aspect.
  • the present application also provides a computer-readable storage medium.
  • the computer-readable storage medium stores instructions that, when run on a computer, cause the computer to execute the above-mentioned first aspect and various possibilities of the first aspect. The method described in the embodiment.
  • the present application also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the method described in the above-mentioned first aspect and each possible implementation of the first aspect.
  • this application also provides a computer chip, the chip is connected to a memory, and the chip is used to read and execute the software program stored in the memory to execute the method described in the above first aspect and each possible implementation manner of the first aspect.
  • Figure 1A is a schematic diagram of a memory structure
  • Figure 1B is a schematic diagram of data distribution in memory
  • Figure 2 is a schematic diagram of a memory structure provided by an embodiment of the present application.
  • Figures 3A-3B are schematic structural diagrams of a memory system provided by embodiments of the present application.
  • Figure 4 is a schematic diagram of a memory data reading and writing method provided by an embodiment of the present application.
  • FIGS 5A-5B are schematic diagrams of data writing provided by embodiments of the present application.
  • Figures 6A-6B are schematic diagrams of data reading provided by embodiments of the present application.
  • FIG. 1A it is a schematic structural diagram of a memory under the DDR5 JEDEC standard.
  • the memory under the DDR5 JEDEC standard includes two sub-channels, each channel including one or more RANKs.
  • Each RANK includes multiple memory particles (chips).
  • the memory under the DDR5 JEDEC standard introduces the concept of sub-channels.
  • the memory under the DDR5 JEDEC standard allows two sub-channels. The two sub-channels are independent of each other.
  • the memory controller can communicate with each sub-channel. Perform data interaction separately.
  • Memory under the DDR5 JEDEC standard also needs to ensure the reliability, availability, and serviceability (reliability, availability, serviceability, RAS) of the memory.
  • Memory under the DDR5 JEDEC standard needs to support Error Checking and Correcting (ECC), so that when errors occur in the data in the memory, errors can be located and corrected in a timely manner.
  • ECC Error Checking and Correcting
  • the memory controller When the memory controller needs to write data into the memory, when writing the data, the memory controller calls the ECC algorithm to generate a check code for the data. The memory controller writes the data and the check code of the data. into memory.
  • the ECC algorithm does not specifically refer to a certain algorithm or a certain algorithm.
  • the ECC algorithm is used to characterize a type of algorithm for generating a check code.
  • the memory controller When the memory controller reads data under the instruction of the processor, the memory controller not only reads the data from the memory, but also reads the check code of the data from the memory, and uses the check code to verify the read data. The data is verified to determine whether there are errors in the data. If there are errors in the read data, the memory controller will use the check code to correct the errors in the read data. If the error correction is successful, the corrected data will be Feedback to the processor.
  • the check code of the data in the memory can usually correct single-bit error data in the data.
  • the memory controller can detect multiple bits of error data, but it cannot It may not be possible to correct the error data of multiple bits, especially when the error data of multiple bits are concentrated in one memory particle.
  • the error correction capability that can correct multi-bit errors in a memory particle is called chip kill capability.
  • Being able to correct an X4 particle (X4 particle is a memory particle with a bit width of 4 bits) is called the X4 chipkill capability.
  • being able to correct an X8 particle (an X8 particle is a memory particle with a bit width of 8 bits) is called the X8 chipkill capability.
  • the bit widths of memory particles are different, and the chipkill capabilities of the memory are also different.
  • FIG. 1B it is a schematic diagram of the distribution of data and check codes in memory channels under the DDR5 JEDEC standard.
  • the size of the data and check code in the channel are 256 bits and 64 bits respectively.
  • the memory controller can write 256 bits of data to the channel at a time, and the size of the check code can reach 64 bits.
  • each channel independently implements ECC. That is to say, the check code of the data in a channel is stored in the channel, and the check code stored in a channel is only used to check and correct the data in the channel.
  • the memory particles of a channel are divided into memory particles that store data and memory particles that store check codes.
  • the bit width of each particle is 4 bits.
  • One sub-channel has 10 X4 particles, and the corresponding redundancy ratio is 4:1. That is to say, when setting up 8 X4 particles that store data, configure 2 X4 particles to store the check code at the same time, so that the check codes stored in the 2 X4 particles can be used to verify any of the 8 X4 particles that store data. Multi-bit errors that occur are corrected. This error correction capability is called X4 chipkill capability.
  • the corresponding redundancy ratio of DDR5 memory is 4:1. That is to say, when 4 X8 particles are set up to store data, and 1 X8 particle is configured to store the check code, the check code stored in 1 X8 particle cannot be used to verify the memory of any of the 8 X8 particles storing data. Multi-bit errors occurring in particles are corrected, and the error correction capability of the memory cannot reach the X8 chipkill capability.
  • embodiments of the present application provide a memory error correction method.
  • the memory controller can calculate a check code for the data stored in a channel group composed of multiple channels in the memory.
  • the generated check code The verification code is distributed and stored in each channel of the channel group. Since the check code can be stored in multiple channels, the data volume of the check code can be effectively increased. In this way, there is no need to add new memory particles for storing the check code, and memory error correction can be improved. capabilities while avoiding an increase in memory costs.
  • the memory 100 includes one or more channel groups, and each channel group includes multiple channels.
  • the multiple channels in a channel group may be multiple channels located close together in the memory 100 .
  • Each channel includes one or more RANKs, and each RANK includes multiple memory particles.
  • the multiple memory particles included in each channel can be divided into two types, one is the memory particle that stores data, and the other is the memory particle that stores the check code.
  • the size of data (the data here does not include the check code) that the memory controller 200 writes or reads from the channel at one time is called the size of the channel.
  • the embodiments of the present application do not limit the specific size of the channel.
  • the specific size of the channel is related to the number of RANKs in the channel, the number of memory particles in each RANK, and the type of memory particles.
  • the size of the channel can be equal to the width of the cache in the processor.
  • the size of the channel can be 64 bytes.
  • the size of data (the data here does not include the check code) that the memory controller 200 writes or reads from the channel group at one time is called the size of the channel group.
  • the size of the channel group is related to the number of channels in the channel group, and the specific size of the channel group is related to the processing capability of the memory controller 200 and the error correction capability expected of the memory 100 .
  • This application does not limit the specific size of the channel group.
  • a channel group needs to include more memory particles for storing check codes. In this case , you can set a larger channel group, which includes more channels.
  • ECC is implemented at the channel group granularity. That is to say, when calculating the check code of the data, the memory controller 200 treats the data stored in each channel in the channel group as a whole data, and generates the check code based on the whole data. The generated check codes can be distributed and stored in each channel in the channel group.
  • each channel in a channel group is provided with K memory particles for storing verification codes. If the channel group includes N channels, then the channel group includes N memories for storing verification codes. Particles.
  • the check code of the data in a channel can only be stored in the memory particle used to store the check code in the channel.
  • the check codes generated by the stored data can be stored dispersedly in the N*K memory particles (K and N are both positive integers).
  • embodiments of the present application provide two memory systems. These two memory systems are introduced below.
  • the memory system includes a memory 100 and a memory controller 200 .
  • the structure of the memory 100 is the same as that shown in Figure 2.
  • the memory controller 200 is used to read and write to the memory 100 under the instruction of the processor. When writing data into the memory 100, the memory controller 200 generates a check code of the data. The memory controller 200 stores the data in the channel group, and stores the check codes of the data in various channels in the channel group. When the memory controller 200 reads data from the memory 100, the memory controller 200 reads the data stored in the channel group and the check code of the data, and uses the check code to verify and correct errors on the data.
  • the memory controller 200 includes a processing unit 210 and a cache unit 220 .
  • the processing unit 210 is used to receive instructions from the processor and read and write to the memory 100 under the instructions of the processor.
  • the processing unit 210 is the main execution unit of the memory controller 200 .
  • the cache unit 220 has a cache function and is used to cache data.
  • the amount of data that can be cached in the cache unit 220 may be equal to the total size of the data that the memory controller 200 reads from the channel group at one time and the check code of the data. That is to say, the cache unit 220 can simultaneously cache the data stored in a channel group and the check code of the data.
  • the cache unit 220 includes two data storage areas, one of which is a data area used to store data, and the other data storage area is a check code area used to store check codes.
  • the data area can store the data stored in the channel group, that is, the data area can store the data itself, and the size of the data area is equal to the size of the channel group.
  • the check code area can store the check code of the data in the channel group.
  • the size of the check code area is equal to the data size of the check code of the data.
  • the check code generated by the memory controller 200 based on the 64-byte data is 4 bytes
  • a channel group includes 2 channels.
  • the size of cache unit 220 is 136 bytes.
  • the processing unit 210 may be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, artificial intelligence chips, on-chip chips, etc.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the cache unit 220 may be a volatile memory, such as a random access memory; the memory may also be a non-volatile memory. Memory, such as read-only memory, flash memory.
  • the memory controller 200 is responsible for reading and writing data of the entire memory 100 . Since the concept of channel groups is introduced in the embodiments of this application, in some scenarios, a corresponding memory sub-controller 300 can be set for each channel group, and the memory sub-controller 300 is only responsible for reading data of the corresponding channel group. and write. Thus, the error correction system of the memory 100 shown in FIG. 3B is formed.
  • the memory system includes a memory 100 and multiple memory sub-controllers 300 .
  • the structure of the memory 100 is the same as that shown in Figure 2.
  • the memory sub-controller 300 is responsible for reading and writing data to a channel group in the memory 100, that is, one memory sub-controller 300 corresponds to one channel group. For any memory sub-controller 300, when writing data into the corresponding channel group, the memory sub-controller 300 generates a check code of the data. The memory sub-controller 300 stores the data in the corresponding channel group, and stores the check codes of the data in various channels in the channel group. When the memory sub-controller 300 reads data from the channel group, the memory sub-controller 300 reads the data stored in the channel group and the check code of the data, and uses the check code to verify and correct the data. .
  • the memory sub-controller 300 includes a processing sub-unit 310 and a cache sub-unit 320.
  • the function of the processing subunit 310 is similar to the function of the processing unit 210 in the above description. The difference is that the processing subunit 310 reads and writes data to the corresponding channel group.
  • the processing unit 210 reads and writes data to the corresponding channel group.
  • the function of the cache subunit 320 is similar to the function of the processing unit 210 in the above description. The difference is that the cache subunit 320 is only used to store data and data check codes in the corresponding channel group. For details, please refer to the foregoing description of the cache unit 220, which will not be described again here.
  • processing subunit 310 and the cache subunit 320 are similar to the specific forms of the processing unit 210 and the cache unit 220 in the foregoing description. For details, please refer to the foregoing description and will not be described again here.
  • a memory controller 200 is used to realize data reading and writing of the memory 100.
  • the memory system shown in FIG. 3B can be seen as separating the memory controller 200 into multiple independent memory sub-controllers 300.
  • the functions implemented by multiple independent memory sub-controllers 300 are the same as the functions implemented by the memory controller 200 .
  • a separate ECC interface circuit is set up for each channel in the memory controller.
  • This ECC interface circuit is mainly used to implement ECC on the data in the corresponding channel, such as calculating check codes and updating check codes. Code etc.
  • the memory system shown above implements ECC at the granularity of channel groups, there is no need to set up a separate ECC interface circuit for each channel. Only an ECC interface circuit is set for each channel group. , used to implement ECC for the data in the corresponding channel group, and the ECC interface circuit may be located in the memory sub-controller 300 . Or a unified ECC interface circuit is set for all channel groups to implement ECC for data in all channel groups.
  • the ECC interface circuit can be located in the memory controller 200 . This can effectively reduce the ECC interface circuit in the memory controller, reduce the complexity of the ECC interface circuit, further reduce the area of the memory controller, and save costs.
  • FIG 4 it is a schematic diagram of a memory data reading and writing provided by the embodiment of the present application.
  • the implementation of this application The memory data reading and writing method provided in the example is divided into two stages: data writing (steps 401 to 406) and data reading (steps 407 to 408).
  • the data writing phase can be divided into two scenarios, one is data writing for the first time (steps 401 to 404), and the other is data updating (steps 404 to 406).
  • the memory controller 200 When the memory controller 200 writes data into the memory 100, the memory controller 200 writes the data in batches. To memory 100, the amount of data written to memory 100 each time is fixed. In the embodiment of the present application, the amount of data written by the memory controller 200 to the memory 100 each time may be equal to the size of the channel group. If the amount of data that the memory controller 200 needs to write to the memory 100 is less than the size of the channel group, the memory controller 200 can temporarily cache the data that needs to be written to the memory 100 in the cache unit 220 by using read modify writeback (read modify). write, RMW) method to write data. That is, the memory controller 200 reads the data in the channel group to which the address belongs based on the address of the data in the memory 100 .
  • read modify read modify
  • RMW write
  • the memory controller 200 uses the data to update the read data, obtains the data that needs to be written to the channel group, the data amount is equal to the size of the channel group, and then writes the data to the channel group. If the amount of data that the memory controller 200 needs to write to the memory 100 is greater than the size of the channel group, and the amount of data is a multiple of the size of the channel group, the memory controller 200 can write the data into the memory 100 in batches, each time Write data to a channel group.
  • the following is an example where the amount of data that needs to be written by the memory controller 200 is equal to the channel group size. For details, please refer to the following description:
  • Step 401 The memory controller 200 obtains the data that needs to be written to the memory 100.
  • the memory controller 200 can obtain the data.
  • the embodiment of the present application does not limit the way in which the memory controller 200 obtains the data.
  • the memory controller 200 can obtain the data from the processor or other components (such as a network card and a hard disk).
  • the memory controller 200 may cache the data in the cache unit 220 of the memory controller 200 .
  • the memory controller 200 can write the data into the data area of the cache unit 220 .
  • Step 402 The memory controller 200 calls the ECC algorithm to generate the first check code of the data.
  • each channel in a channel group is provided with a memory particle capable of storing a check code
  • the data amount of the first check code is allowed to be larger. Therefore, in the embodiment of the present application, when the memory controller 200 generates the first check code, it can call a more complex ECC algorithm to generate a first check code with strong error correction capability.
  • the memory controller 200 may call the Reed-Solomon (RS) encoding algorithm to generate the first check code of the data.
  • RS Reed-Solomon
  • the size of the first check code generated by the memory controller 200 by calling the RS8 encoding algorithm for 512-bit data is 32 bits.
  • the channel size as 128 bits as an example, if a channel group includes 4 channels, then the 512-bit data and the 32-bit first check code can be stored in a channel group.
  • the 32-bit first check code can realize the X2chipkill capability, that is, the 32-bit first check code can be used to correct multi-bit errors in an X2 particle (the bit width of the X2 particle is 2 bits).
  • the RS8 coding algorithm refers to the RS coding algorithm in which one symbol is equal to 8 bits.
  • the size of the first check code generated by the memory controller 200 by calling the RS16 encoding algorithm for 512-bit data is 128 bits.
  • the memory meets the DDR5 JEDEC standard, and the channel size is 256 bits. If a channel group includes 2 channels, then the 512-bit data and the 64-bit first check code can be stored in a channel group.
  • the 32-bit first check code can realize two X4 chipkill capabilities, or realize one X8 chipkill capability.
  • the RS16 coding algorithm refers to the RS coding algorithm in which one symbol is equal to 16 bits.
  • the size of the first check code generated by the memory controller 200 by calling the RS16 encoding algorithm for 1024-bit data is 256 bits.
  • the channel size as 256 bits as an example, if a channel group includes 4 channels, then the 1024-bit data and the 256-bit first check code can be stored in a channel group, and the 256-bit first check code can be stored in a channel group.
  • the code can achieve four X4 chipkill capabilities, that is, using a 256-bit first check code to correct multi-bit errors in four X4 chips.
  • the embodiment of the present application does not limit the ECC algorithm called by the memory controller 200 to generate the first check code.
  • the ECC algorithm can be an RS coding algorithm, a cyclic redundancy check (CRC) algorithm, a BCH (bose, ray-chaudhuri, hocquenghem) algorithm, hash (HASH) algorithm, or redundant array of independent disks (RAID) algorithm (such as RAID 5 algorithm, RAID 6 algorithm).
  • the ECC algorithm can also be a combination of multiple algorithms among the aforementioned algorithms. Any algorithm that can be used to generate a check code is applicable to the embodiment of this application.
  • Step 403 The memory controller 200 writes the data and the first check code into the channel group of the memory 100.
  • the check codes of the data are scattered on each channel in the channel group.
  • the memory controller 200 may segment the data to form multiple data segments; segment the first check code to form multiple check code segments.
  • the memory controller 200 distributes multiple data segments and check code segments into each channel in the channel group. Among them, the number of data segments is the same as the number of channels in the channel group, and the number of check code segments is the same as the number of channels in the channel group.
  • the memory controller 200 may store one data segment and one check code segment in one channel.
  • each channel size is 256 bits as an example.
  • the memory controller 200 can divide the 1024-bit data into four data segments, each data segment having a length of 256 bits.
  • the memory controller 200 may divide the 256-bit first check code into four check code segments, and the length of each check code segment is 64 bits.
  • the memory controller 200 writes a data segment and a check code segment in each channel.
  • the memory controller 200 may write a data segment composed of 0 to 255 bits of data in the data and a check code segment composed of 0 to 63 bits of data in the first check code into channel 1 in the channel group.
  • the data segment composed of 767 bits of data and the check code segment composed of 128 to 191 bits of data in the first check code are written to channel 3 in the channel group, and the data segment composed of 768 to 1023 bits of data is written into
  • the data segment and the check code segment consisting of 192 to 255 bits of data in the first check code are written to channel 4 in the channel group.
  • each channel size is 256 bits as an example.
  • the memory controller 200 can divide the 512-bit data into 2 data segments, and the length of each data segment is 256 bits.
  • the memory controller 200 may divide the 128-bit first check code into two check code segments, and the length of each check code segment is 64 bits.
  • the memory controller 200 writes a data segment and a check code segment in each channel.
  • the memory controller 200 may write a data segment composed of 0 to 255 bits of data in the data and a check code segment composed of 0 to 63 bits of data in the first check code into channel 1 in the channel group.
  • the memory controller 200 transfers the data to the channel group of the memory 100 .
  • the memory controller 200 can also update the data written into the memory 100.
  • the processor instructs the memory controller 200 to modify a certain bit or bits in the data.
  • the memory controller 200 uses the RMW method to write data into the memory 100 .
  • the memory controller 200 When the memory controller 200 needs to update the data in the memory 100, it not only needs to update the data itself, but also regenerates the check code.
  • the following uses the memory controller 200 to update the data written in the previous steps as an example to describe the method of the memory controller 200 updating the data in the memory 100 .
  • Step 404 The memory controller 200 reads data and the first check code of the data from the channel group.
  • the memory controller 200 reads multiple data segments and multiple check code segments from multiple channels in the channel group, splices the multiple data segments into original data, and splices the multiple check code segments into The first check code.
  • the memory controller 200 can write the multiple data segments and the multiple check code segments into the cache in the memory controller 200 in unit 220. Among them, multiple data segments are written to the data area in the cache unit 220 , and multiple check code segments are written to the check code area of the cache unit 220 .
  • the sorting positions of the multiple data segments in the data area are consistent with the sorting positions of the multiple data segments in the data, and the sorting positions of the multiple check code segments in the check code area are consistent with the multiple check code segments.
  • the sorting positions in the first check code are consistent.
  • Figure 6A is a schematic diagram of reading data from the channel group provided by an embodiment of the present application.
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 1, write the 256-bit data segment to the 0-255 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the 0 to 63 bit positions in the check code area in the cache unit 220 .
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 2, write the 256-bit data segment to the 256-511 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the 64-127 bit position in the check code area in the cache unit 220 .
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 3, write the 256-bit data segment into the 512-767 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the check code area in the cache unit 220 at positions 128 to 191 bits.
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 4, write the 256-bit data segment to the 768-1023 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the 192-256 bit position in the check code area in the cache unit 220 .
  • Figure 6B is a schematic diagram of reading data from the channel group according to an embodiment of the present application.
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 1, write the 256-bit data segment to the 0-255 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the 0 to 63 bit positions in the check code area in the cache unit 220 .
  • the memory controller 200 can read the 256-bit data segment and the 64-bit check code segment from channel 2, write the 256-bit data segment to the 256-511 bit position in the data area in the cache unit 220, and write the 64-bit data segment to the cache unit 220.
  • the bit check code segment is written into the 64-128 bit position in the check code area in the cache unit 220 .
  • Step 405 The memory controller 200 updates the data and generates a second check code based on the updated data.
  • the memory controller 200 can update the data, such as modifying or deleting some bits in the data. After updating the data, the memory controller 200 generates a second check code for the updated data. The memory controller 200 generates the second check code in a manner similar to the first check code. For details, see step 402. The first check code can be deleted in the memory controller 200 and the second check code can be written into the check code area of the cache unit 220 .
  • Step 406 The memory controller 200 writes the updated data and the second check code into the channel group of the memory 100.
  • the check codes of the data are scattered on each channel in the channel group.
  • Step 406 is similar to step 403, with the only difference being that the data stored by the memory controller 200 and the check code are different. For details, please refer to the relevant description of step 403, which will not be described again here.
  • steps 404 to 406 the data in the memory 100 is updated.
  • the memory controller 200 can also read the data in the memory 100 and feed it back to the processor.
  • the following takes the memory controller 200 that needs to read and write data into the channel group as an example to describe how the memory controller 200 reads the data. For explanation, please refer to steps 407 to 408 for details.
  • Step 407 The memory controller 200 reads data and the second check code from the channel group under the instruction of the processor.
  • the processor When the processor needs to read data, the processor will send an instruction to the memory controller 200 to inform the information of the data to be read, such as the logical address of the data.
  • the memory controller 200 can determine the channel group where the data is located in the memory 100, and read multiple data segments and check codes from the channel group. segments, write the multiple read data segments into the data area of the cache unit 220, form complete data in the data area, and write the multiple read check code segments into the check code of the cache unit 220 area, forming a second check code in the check code area.
  • Step 408 The memory controller 200 uses the second check code to verify and correct errors on the read data.
  • the memory controller 200 After the memory controller 200 reads the second check code and the data, the memory controller 200 uses the second check code to determine whether the read data contains erroneous data, and locates the location of the erroneous data.
  • the error data here refers to the data in the read data that is different from the data written in the channel group (that is, the updated data in step 406).
  • the memory controller 200 may feed back the data to the processor.
  • the memory controller 200 uses the second check code to determine that there is a data error in the read data, the memory controller 200 can use the second check code to locate the location of the data error, and use the second check code to correct the erroneous data. Error correction, and the error-corrected data is fed back to the processor. If the memory controller 200 fails to correct the error data using the second check code, the memory controller 200 may notify the processor that the data reading failed.
  • the way in which the memory controller 200 uses the second check code to verify and correct errors on the read data is related to the way in which the memory controller 200 generates the second check code.
  • the memory controller 200 needs to use an error correction algorithm corresponding to the ECC algorithm called to generate the second check code to verify and correct errors on the read data. For example, in steps 402 and 405, the RS encoding algorithm is used to generate the first check code and the second check code, then in step 408, the memory controller 200 can use the RS error correction algorithm, the second check code Verify and correct errors on the read data.
  • embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

一种内存数据读写方法、系统以及内存控制器，本申请中，内存控制器需要将数据写入到通道组时，内存控制器获取目标数据；调用ECC算法生成目标数据的校验码，校验码用于对目标数据进行校验以及纠错。内存控制器将目标数据以及校验码写入到通道组中，该目标数据分散存储在通道组的通道中。校验码分散存储在通道组的各个通道中。每个通道组中存在能够存储校验码的内存颗粒，该目标数据的校验码分散存储在各个通道中存储校验码的内存颗粒上，存储该目标数据的校验码的内存颗粒数量较多，校验码的数据量更大，保证该内存具备较强的纠错能力。另以通道组为粒度实现ECC，不需要变更内存中存储校验码的内存颗粒的数目，无需额外增加内存成本。

Description

一种内存数据读写方法、系统以及内存控制器
相关申请的交叉引用
本申请要求于2022年4月29日提交中国专利局、申请号为202210475855.4、发明名称为“一种内存系统和内存纠错方法”的中国专利申请的优先权，以及于2022年07月18日提交的申请号为202210841487.0、发明名称为“一种内存数据读写方法、系统以及内存控制器”的中国专利申请的优先权，前述两件专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种内存数据读写方法、系统以及内存控制器。
背景技术
与双倍速率同步动态随机存储器(double data rate synchronous dynamic random access memory，DDR)DDR4 JEDEC标准相比，DDR5 JEDEC标准中在内存中引入了子通道(Sub-channel)的概念，DDR5标准下的内存中包括两个子通道，每个子通道包括多个内存颗粒。这两个子通道相互独立，每个子通道独立实现错误检测和纠错(error checking and correcting，ECC)，也即内存控制器需要独立的对每个子通道内部存储的数据进行校验、以及纠错。
每个子通道独立的实现ECC，每个子通道中设置有用于存储校验码的内存颗粒，在实际应用中，每个子通道中这类用于存储校验码的内存颗粒的数量较少，限制了内存的纠错能力。
发明内容
本申请提供一种内存数据读写方法、系统以及内存控制器，用以提升内存纠错能力。
第一方面，本申请实施例提供了一种内存数据读写方法，方法可以由内存控制器或集成有内存控制器的处理器执行，该方法用于实现对内存的数据读写。在本申请中，内存包括一个或多个通道组，每个通道组包括多个通道。在该方法中，当内存控制器需要将数据写入到通道组时，内存控制器获取需要写入通道组的目标数据；调用ECC算法生成目标数据的校验码，校验码用于对目标数据进行校验以及纠错。内存控制器在生成该目标数据的校验码之后，可以将目标数据以及校验码写入到通道组中，其中，该目标数据分散存储在通道组的通道中。校验码分散存储在通道组的各个通道中。
通过上述方法，每个通道组中存在能够存储校验码的内存颗粒，该目标数据的校验码可以分散存储在各个通道中存储校验码的内存颗粒上，能够存储该目标数据的校验码的内存颗粒数量较多，说明在生成校验码时，可以生成数据量更大的校验码。数据量较大的校验码能够保证该内存具备较强的纠错能力。另外，采用该方法仅需以通道组为粒度实现ECC，并不需要变更内存中存储校验码的内存颗粒的数目，无需额外增加内存成本。
在一种可能的实施方式中，每个通道包括一个或多个RANK，每个RANK中包括多个内存颗粒。也就是说，一个通道组里有可以包括多个RANK，使得保证该通道组具备较大的存储空间，以实现大粒度数据存储。
在一种可能的实施方式中，内存控制器在生成该目标数据的校验码之后，将目标数据以及校验码写入到通道组时，可以将目标数据拆分为多个目标数据段，其中，该多个目标数据 段的数据长度可以相同，也可以不同。内存控制器将校验码拆分为多个校验码段，其中，该多个校验码段的数据长度可以相同，也可以不同。之后，内存控制器可以将多个目标数据段分别写入通道组中的各个通道，将多个校验码段分别写入通道组中的各个通道。
在一种可能的实施方式中，内存控制器还可以从通道组中读取数据，内存控制器在处理器的指示下，可以从通道组中读取目标数据以及校验码，并利用校验码对目标数据进行纠错。在纠错成功后，将纠错后的目标数据反馈至处理器。
通过上述方法，内存控制器以通道组粒度从内存中读取数据并实现数据纠错，以通道组粒度的数据读取能够提升数据读取效率。
在一种可能的实施方式中，内存控制器还可以对通道组中的数据进行更新，内存控制器在处理器的指示下，可以从通道组中读取目标数据以及校验码，在对目标数据更新后，生成更新后的目标数据的校验码。内存控制器将更新后的目标数据以及更新后的目标数据的校验码写入到通道组中。其中，该更新后的目标数据分散存储在通道组的通道中。更新后的目标数据的校验码分散存储在通道组的各个通道中。
通过上述方法，内存控制器对内存中数据的更新也是以通道组为粒度，更新后的目标数据的校验码可以分散存储在通道组的各个通道中，也就是说，更新前后，校验码的数据量并为发生变化，依旧可以保证内存具备较强的纠错能力。
在一种可能的实施方式中，为了便于内存控制器与处理器之间的交互，内存控制器一次写入到内存的通道组中的数据等于内存控制器与处理器之间一次交互的数据量，也就是说，内存控制器一次写入到内存的通道组中的数据可以等于处理器中缓存的位宽。在一些场景中，内存控制器一次写入到内存的通道组中的数据也可以等于处理器之间一次交互的数据量的倍数。这样，能够保证内存控制器与内存之间实现大粒度的数据读写，提升内存控制器与内存之间的交互效率。
在一种可能的实施方式中，为了便于内存控制器与处理器之间的交互，内存控制器一次写入到通道组中一个通道的数据等于处理器中缓存的位宽。也就是说，内存控制器一次写入到通道组的数据可以等于处理器中缓存的位宽的倍数。这样，内存控制器一次能够向通道组中写入的数据较多，保证了内存控制器与内存之间的交互效率。
在一种可能的实施方式中，本申请实施例并不限定该通道组中通道的数量。例如，通道组中通道的数量等于2、3、4、6、8、12、或16。
通过上述方法，通道组中通道的数量存在多种设置方式，适用于不同场景。
在一种可能的实施方式中，内存控制器在生成目标数据的校验码时可以调用不同的ECC算法，也可以调用多种ECC算法。例如，内存控制器可以调用RS编码算法、循环冗余校验(cyclic redundancy check，CRC)算法、BCH(bose ray-chaudhuri hocquenghem)算法、哈希(HASH)算法、或独立磁盘冗余阵列(redundant array of independent disks，RAID)算法(如RAID 5算法、RAID 6算法)中的任一种算法生成目标数据的校验码。又例如，内存控制器可以调用RS编码算法、CRC算法、BCH算法、HASH算法、或RAID算法(中的任多种算法形成两级或者多级ECC算法生成目标数据的校验码。
通过上述方法，内存控制器在生成目标数据的校验码时能够灵活的调用一种或多种ECC算法，使得该方法能够适用于多种不同的应用场景。
在一种可能的实施方式中，每个通道中设置有用于存储校验码的内存颗粒，在每个通道中存储校验码的内存颗粒一定的情况下，内存控制器一次向该通道组中写入的校验码的最大数据量与该类内存颗粒的位宽成倍数(该倍数的取值与内存颗粒的数量以及一个时钟周期内 对内存颗粒读写次数有关)关系。内存控制器生成校验码的数据量可以等于该最大数据量，这样该第一校验码可以分布在通道组中的每个存储校验码的内存颗粒上。内存控制器生成第一校验码的数据量也可以小于该最大数据量，这样该第一校验码可以分布在通道组中的部分存储校验码的内存颗粒上或该校验码只占用存储校验码的内存颗粒的部分存储空间。
通过上述方法，校验码的分布方式较为灵活，有效扩展了应用场景。
第二方面，本申请实施例提供了一种内存系统，该内存系统中包括内存和内存控制器，有益效果可以参见第一方面的相关说明，此处不再赘述。该内存系统中包括内存和内存控制器。
内存包括一个或多个通道组，每个通道组包括多个通道，每个通道包括一个或多个RANK，每个RANK中包括多个内存颗粒，方法由内存控制器执行，方法包括：
内存控制器可以获取需要写入通道组的目标数据；生成目标数据的校验码，校验码用于对目标数据进行校验以及纠错；将目标数据以及校验码写入到通道组中，校验码分散存储在通道组的各个通道中，目标数据分散存储在通道组的通道中。
在一种可能的实施方式中，内存控制器还可以从内存中读取数据。例如，内存控制器可以在处理器的指示下，从通道组中读取目标数据以及校验码；利用校验码对目标数据进行纠错；将纠错后的目标数据反馈至处理器。
在一种可能的实施方式中，一次写入到通道组中的数据等于处理器中缓存的位宽。
在一种可能的实施方式中，一次写入到通道组中一个通道的数据等于处理器中缓存的位宽。
在一种可能的实施方式中，通道组中通道的数量等于2、3、4、6、8、12或16。
在一种可能的实施方式中，内存控制器在生成目标数据的第一校验码时，可以调用RS8编码算法或RS16编码算法生成目标数据的校验码。也可以调用其他ECC算法生成目标数据的校验码。
在一种可能的实施方式中，每个通道包括一个或多个RANK，每个RANK中包括多个内存颗粒。
在一种可能的实施方式中，内存控制器在将目标数据以及校验码写入到通道组中时，可以将目标数据拆分为多个目标数据段，将校验码拆分为多个校验码段；将多个目标数据段分别写入通道组中的各个通道，将多个校验码段分别写入通道组中的各个通道。
第三方面，本申请实施例还提供了一种内存控制器，该内存控制器包括处理单元以及缓存单元，缓存单元用于缓存数据，如缓存需要写入到通道组的数据，还可以缓存该数据的校验码。处理单元可以运行烧写在其上的计算机程序执行或运行获取的计算机程序指令执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
第四方面，本申请实施例还提供了一种计算设备，该计算设备包括第二方面所提及的内存系统。
第五方面，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
第六方面，本申请还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
第七方面，本申请还提供一种计算机芯片，所述芯片与存储器相连，所述芯片用于读取 并执行所述存储器中存储的软件程序，执行上述第一方面以及第一方面的各个可能的实施方式中所述的方法。
附图说明
图1A为一种内存结构示意图；
图1B为一种内存中数据分布示意图；
图2为一种本申请实施例提供的一种内存结构示意图；
图3A～3B为一种本申请实施例提供的一种内存系统结构示意图；
图4为一种本申请实施例提供的一种内存数据读写方法示意图；
图5A～5B为一种本申请实施例提供的一种数据写入示意图；
图6A～6B为一种本申请实施例提供的一种数据读取示意图。
具体实施方式
如图1A所示，为一种DDR5 JEDEC标准下的内存的结构示意图，DDR5 JEDEC标准下的内存包括两个子通道(sub-channel)，每个通道上包括一个或者多个RANK。每个RANK中包括多个内存颗粒(chip)。
相较于DDR4 JEDEC标准，DDR5 JEDEC标准下的内存引入了子通道的概念，DDR5 JEDEC标准下的内存中允许包括两个子通道，这两个子通道之间彼此独立，内存控制器可以与每个子通道分别进行数据交互。
DDR5 JEDEC标准下的内存同样需要保证内存的可靠性、可实用性以及可服务性(reliability，availability，serviceability，RAS)。DDR5 JEDEC标准下的内存需支持错误检测和纠错(Error Checking and Correcting，ECC)，以使得内存中的数据发生错误时，能够及时进行定位、以及纠错。
这里介绍下内存实现ECC的方式：
当内存控制器需要将数据写入到内存中，在将数据写入时，内存控制器调用ECC算法为该数据生成该数据的校验码，内存控制器将数据以及该数据的校验码写入到内存中。
需要说明的是，ECC算法并不特指某一个算法或某一种算法，在本申请实施例中ECC算法用于表征一类用于生成校验码的算法。
当内存控制器在处理器的指示下读取数据时，内存控制器除了从内存中读取数据，还会从内存中读取该数据的校验码，利用该校验码对所读取的数据进行校验，确定该数据中是否出错，若读取的数据存在错误数据，内存控制器会利用校验码对所读取的数据进行纠错，若纠错成功，将纠错后的数据反馈至处理器。
校验码的数据量越大，该校验码具备的纠错能力越强。纠错能力较强的纠错码能够对数据中较多的出错数据进行纠错。考虑到内存内有限的存储空间，在实际应用在中，并不允许校验码占用较多存储空间，校验码只能集中在少量的内存颗粒中。这样限制了内存本身的纠错能力。
内存中数据的校验码通常对数据中存在的单个比特的错误数据可进行纠错，当数据中存在多个比特的出错数据时，内存控制器能够检测到多个比特的出错数据，但并不一定能够对该多个比特的出错数据进行纠错，尤其是该多个比特的出错数据集中在一个内存颗粒。
通常，将能够修正一个内存颗粒中的多比特错误的纠错能力称为芯片删除(chipkill)能力。能够纠正一个X4颗粒(X4颗粒为位宽为4比特的内存颗粒)，称为X4 chipkill能力。 类似的，能够纠正一个X8颗粒(X8颗粒为位宽为8比特的内存颗粒)，称为X8 chipkill能力。内存颗粒的位宽不同，内存的芯片删除(Chipkill)能力也不同。
如1B所示，为一种DDR5 JEDEC标准下的内存中通道中数据与校验码的分布示意图。图1B中，为内存控制器一次向通道写入数据时，通道中数据与校验码的大小分别为256比特、64比特。也就是说，内存控制器一次能够向该通道中写入256比特的数据，校验码的大小可以达到64比特。
但DDR5 JEDEC标准下的内存，每个通道独立实现ECC。也就是说，一个通道中数据的校验码存储在该通道中，一个通道中存储的校验码只用于对该通道内的数据进行校验以及纠错。一个通道的内存颗粒分为存储数据的内存颗粒以及存储校验码的内存颗粒。
若DDR5JEDEC标准下的内存中的内存颗粒为X4颗粒，每个颗粒的位宽为4比特。一个子通道有10个X4颗粒，相应的冗余比为4:1。也就是说，当设置8个存储数据的X4颗粒，同时配置2个X4颗粒存储校验码，这样2个X4颗粒中存储的校验码可以对8个存储数据的X4颗粒中任一内存颗粒出现的多比特错误进行纠错，该纠错能力称为X4 chipkill能力。
若内存中的内存颗粒为X8颗粒，DDR5内存相应的冗余比为4:1。也就是说，当设置4个存储数据的X8颗粒，同时配置1个X8颗粒存储校验码，这样1个X8颗粒中存储的校验码并不能对8个存储数据的X8颗粒中任一内存颗粒出现的多比特错误进行纠错，内存的纠错能力无法达到X8 chipkill能力。
若内存颗粒为X8颗粒，常见的，一个DDR5JEDEC标准下的通道中存储数据的颗粒数与存储校验码的颗粒数的比例为4:1，无法对单个内存颗粒中的出现的多比特错误进行纠错，纠错能力较差。为了将内存的纠错能力提升到X8 chipkill能力，则需要在一个通道中再增加一个存储校验码的X8颗粒，以保证存储数据的内存颗粒的数量与存储校验码的内存颗粒的数量比例与X8 chipkill能力要求比例(也即2:1)，这样无疑会增加内存的成本。
可见，在DDR5 JEDEC标准下甚至后续同样引入子通道或类似子通道的概念的DDR标准下的内存，亟需一种既能够保证内存成本，又能提升纠错能力的内存纠错方法。
为此，本申请实施例提供了一种内存纠错方法，在本申请实施例中，内存控制器可以对内存中多个通道构成的通道组中存储的数据计算校验码，所生成的校验码分散存储到该通道组的各个通道中。由于该校验码能够分散存储在多个通道中，校验码的数据量能够得到有效提升，在这种方式中，无需增加新的用于存储校验码的内存颗粒，在提升内存纠错能力的同时避免了内存成本的提高。
如图2所示，为本申请实施例提供的一种内存的结构示意图，该内存100中包括一个或多个通道组，每个通道组包括多个通道。一个通道组中的多个通道可以为内存100中位置靠近的多个通道。
每个通道包括一个或多个RANK，每个RANK包括多个内存颗粒。每个通道所包括多个内存颗粒可以分为两种，一种为存储数据的内存颗粒，另一种为存储校验码的内存颗粒。
在本申请实施例，将内存控制器200一次从通道中写入或读取的数据(此处的数据不包括校验码)的大小称为通道的大小。本申请实施例并不限定通道的具体大小，通道的具体大小与通道中RANK的数量、每个RANK中内存颗粒的数量、以及内存颗粒的类型有关。例如，通道的大小可以等于处理器中缓存(cacheline)的宽度，如通道的大小可以为64字节。
在本申请实施例中，将内存控制器200一次从通道组中写入或读取的数据(此处的数据不包括校验码)的大小称为通道组的大小。通道组的大小与通道组中通道的数量有关，通道组的具体大小与内存控制器200的处理能力以及期望内存100所具备的纠错能力有关。本申 请实施例并不限定通道组的具体大小。
例如，若期望内存100所具备较强的纠错能力、且内存控制器200具备较佳的性能，那么，一个通道组需要在包括较多的用于存储校验码的内存颗粒，这种情况下，可以设置较大的通道组，通道组中包括较多的通道。
在本申请实施例中以通道组为粒度实现ECC。也就是说，在计算数据的校验码时，内存控制器200将该通道组中各个通道中所存储的数据作为一个整体数据，基于该整体数据生成该校验码。生成的校验码可以分散存储在该通道组中各个通道中。
例如，一个通道组中的每个通道中设置K个用于存储校验码的内存颗粒，若该通道组中包括N个通道，那么，该通道组包括N个用于存储校验码的内存颗粒。与DDR5 JEDEC标准下的内存中，一个通道中数据的校验码只能存储在该通道中用于存储校验码的内存颗粒，本申请实施例中，基于将该通道组中各个通道中所存储的数据生成的校验码可以分散地存储在该N*K个内存颗粒中(K和N均为正整数)。
基于如图2所示的内存100，本申请实施例提供两种内存系统，下面分别介绍这两种内存系统。
如图3A所示，为本申请实施例提供的一种内存系统，该内存系统包括内存100以及内存控制器200。
内存100的结构与图2所示的结构相同，内存100的结构可以参见前述说明。此处不再赘述。
内存控制器200用于在处理器的指示下对该内存100进行读取以及写入。内存控制器200在将数据写入到内存100中时，生成该数据的校验码。内存控制器200将该数据存储在通道组中，将该数据的校验码分散存储在该通道组中的各个通道中。内存控制器200在从内存100中读取数据时，内存控制器200读取通道组中所存储的数据以及数据的校验码，利用该校验码对该数据进行校验、纠错。
内存控制器200包括处理单元210以及缓存单元220。处理单元210用于接收处理器的指示，并在处理器的指示下对内存100进行读取以及写入，该处理单元210是内存控制器200的主要执行单元。缓存单元220具备缓存功能，用于缓存数据。缓存单元220中能够缓存的数据量可以等于内存控制器200一次从通道组读取的数据以及该数据的校验码的总大小。也就是说，缓存单元220能够同时缓存一个通道组中所存储的数据以及该数据的校验码。
缓存单元220包括两个数据存储区域，其中一个数据存储区域为数据区域，该数据区域用于存储数据，另一个数据存储区域为校验码区域，该校验码区域用于存储校验码。数据区域能够存储通道组中所存储的数据，也就是说，该数据区域可以能够存储数据本身，数据区域的大小等于通道组的大小。校验码区域能够存储通道组中数据的校验码。校验码区域的大小等于该数据的校验码的数据量。
例如，若内存100中一个通道的大小为64字节，内存控制器200基于64字节的数据生成的校验码为4字节，一个通道组中包括2个通道，内存控制器200中的缓存单元220的大小为136字节。
处理单元210可以为数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件、人工智能芯片、片上芯片等。
缓存单元220可以为是易失性存储器，例如随机存取存储器；存储器也可以是非易失性 存储器，例如只读存储器，快闪存储器。
在图3A所示的内存100纠错系统中，内存控制器200负责整个内存100的数据读取以及写入。由于本申请实施例中引入了通道组的概念，在一些场景中，可以为每个通道组设置一个对应的内存子控制器300，该内存子控制器300只负责对应的通道组的数据读取以及写入。由此形成如图3B所示的内存100纠错系统。
如图3B所示，为本申请实施例提供的一种内存系统，该内存系统包括内存100以及多个内存子控制器300。
内存100的结构与图2所示的结构相同，内存100的结构可以参见前述说明。此处不再赘述。
内存子控制器300负责对内存100中的一个通道组进行数据的读取以及写入，也即，一个内存子控制器300与一个通道组对应。对于任一内存子控制器300，内存子控制器300在将数据写入到对应的通道组中时，生成该数据的校验码。内存子控制器300将该数据存储在对应的通道组中，将该数据的校验码分散存储在该通道组中的各个通道中。内存子控制器300在从通道组中读取数据时，内存子控制器300读取通道组中所存储的数据以及数据的校验码，利用该校验码对该数据进行校验、纠错。
内存子控制器300包括处理子单元310以及缓存子单元320。处理子单元310的功能与前述说明中处理单元210的功能类似，区别在于，处理子单元310对所述对应的通道组进行数据读取以及写入。具体可以参见前述关于处理单元210的说明，此处不再赘述。
缓存子单元320的功能与前述说明中处理单元210的功能类似，区别在于，缓存子单元320仅用于存储对应的通道组中的数据以及数据校验码。具体可以参见前述关于缓存单元220的说明，此处不再赘述。
处理子单元310以及缓存子单元320的具体形态与前述说明中处理单元210以及缓存单元220的具体形态类似，具体可参见前述说明，此处不再赘述。
硬件形态上，图3A所示的内存系统中，采用一个内存控制器200实现内存100的数据读写。图3B所示的内存系统，可以看做将内存控制器200分离成为多个独立的内存子控制器300。多个独立的内存子控制器300共同实现的功能与内存控制器200所实现的功能是相同的。
此外，一些常见的内存，内存控制器内针对每个通道会设置单独的ECC接口电路，该ECC接口电路主要用于对所对应的通道内的数据实现ECC，如计算校验码、更新校验码等。而在本申请实施例中，如前述所示的内存系统，由于是以通道组为粒度实现ECC，无需针对每个通道设置单独的ECC接口电路，只需针对每个通道组设置的ECC接口电路，用于针对所对应的通道组内的数据实现ECC，该ECC接口电路可以位于内存子控制器300中。或者针对所有通道组设置统一的ECC接口电路，用于针对所有通道组内的数据实现ECC，该ECC接口电路可以位于内存控制器200中。这样能够有效减少内存控制器中ECC接口电路，降低ECC接口电路的复杂度，进一步减少内存控制器的面积，节约成本。
下面以图3A所示的内存系统为例，对本申请实施例提供的内存数据读写方法进行说明，如图4所示，为本申请实施例提供的一种内存数据读写示意图，本申请实施例提供的内存数据读写方法分为数据写入(步骤401～步骤406)、以及数据读取(步骤407～步骤408)两个阶段。数据写入阶段可以分为两种场景，一种场景为数据首次写入(步骤401～步骤404)，一种场景为数据更新(步骤404～步骤406)。
由于内存控制器200在将数据写入到内存100中时，内存控制器200是分次将数据写入 到内存100中，每次写入到内存100的数据量是固定的。在本申请实施例中，内存控制器200每次写入到内存100中的数据量可以等于通道组的大小。若内存控制器200需要写入到内存100的数据量小于通道组的大小，内存控制器200可以将需要写入到内存100的数据暂时缓存在缓存单元220中，采用读修改回写(read modify write，RMW)方式进行数据写入。也即，内存控制器200根据该数据在内存100中的地址读取该地址所属的通道组中的数据。内存控制器200利用该数据更新读取的数据，获得需要写入到通道组的数据，该数据的数据量等于通道组大小的数据，再将数据写入到通道组中。若内存控制器200需要写入到内存100的数据量大于通道组的大小，且数据量与通道组的大小呈倍数关系，内存控制器200可以分次将数据写入到内存100中，每次将数据写入到一个通道组中。
下面以内存控制器200需要写入的数据量等于通道组大小为例进行说明，具体参见如下说明：
步骤401：内存控制器200获取需要写入到内存100的数据。
当存在需要存储至内存100的数据中时，内存控制器200可以获取该数据，本申请实施例并不限定该内存控制器200获取该数据的方式。例如，内存控制器200可以从处理器获取该数据，也可以从其他组件(如网卡、硬盘)获取该数据。
内存控制器200在获取该数据后，可以将该数据缓存在该内存控制器200中缓存单元220中。例如，内存控制器200可以将该数据写入到该缓存单元220的数据区域中。
步骤402：内存控制器200调用ECC算法生成该数据的第一校验码。
由于在一个通道组中每个通道中均设置有能够存储校验码的内存颗粒，允许该第一校验码的数据量更大。故而，在本申请实施例中，内存控制器200生成该第一校验码时，可以调用更加复杂的ECC算法，以生成具备较强纠错能力的第一校验码。例如，内存控制器200可以调用德所罗门(Reed-Solomon，RS)编码算法生成该数据的第一校验码。在内存控制器200内部，生成的第一校验码可以写入到缓存单元220的校验码区域中。
例如，内存控制器200调用RS8编码算法对512比特的数据生成的第一校验码的大小为32比特。以通道大小为128比特为例，若一个通道组中包括4个通道，那么，该512比特的数据以及32比特的第一校验码可以存储在一个通道组中。32比特的第一校验码能够实现X2chipkill能力，也即利用32比特的第一校验码可以纠正一个X2颗粒(X2颗粒的位宽为2比特)存在的多比特错误。RS8编码算法是指算法中一个符号(symbol)等于8比特的RS编码算法。
又例如，内存控制器200调用RS16编码算法对512比特的数据生成的第一校验码的大小为128比特。内存满足DDR5 JEDEC标准，通道大小为256比特，若一个通道组中包括2个通道，那么，该512比特的数据以及64比特的第一校验码可以存储在一个通道组中。32比特的第一校验码能够实现两个X4 chipkill能力，或实现一个X8 chipkill能力。RS16编码算法是指算法中一个符号(symbol)等于16比特的RS编码算法。
又例如，内存控制器200调用RS16编码算法对1024比特的数据生成的第一校验码的大小为256比特。以通道大小为256比特为例，若一个通道组中包括4个通道，那么，该1024比特的数据以及256比特的第一校验码可以存储在一个通道组中，256比特的第一校验码能够实现四个X4 chipkill能力，也即利用256比特的第一校验码可以纠正四个X4颗粒存在的多比特错误。
本申请实施例并不限定内存控制器200生成第一校验码所调用的ECC算法。该ECC算法可以为RS编码算法、循环冗余校验(cyclic redundancy check，CRC)算法、BCH(bose、 ray-chaudhuri，hocquenghem)算法、哈希(HASH)算法、或独立磁盘冗余阵列(redundant array of independent disks，RAID)算法(如RAID 5算法、RAID 6算法)。该ECC算法也可以为前述算法中多种算法的组合。凡是能够用于生成校验码的算法均适用于本申请实施例。
步骤403：内存控制器200将该数据以及第一校验码写入到内存100的通道组中。其中该数据的校验码分散在该通道组中的各个通道上。
内存控制器200在生成第一校验码之后，可以对数据进行分段，形成多个数据段；对第一校验码进行分段，形成多个校验码段。内存控制器200将多个数据段和校验码段分散在该通道组中的各个通道中。其中，数据段的数量与通道组中通道的数量相同，校验码段的数量与通道组中通道的数量相同。
内存控制器200在将该多个数据段和校验码段分散在该通道组中的多个通道时，可以将一个数据段以及一个校验码段存储在一个通道中。
以通道组中包括4个通道，每个通道大小为256比特为例。
如图5A所示，内存控制器200可以将1024比特数据分为四个数据段，每个数据段的长度为256比特。内存控制器200可以将256比特的第一校验码分为四个校验码段，每个校验码段的长度为64比特。
内存控制器200在每个通道中写入一个数据段以及一个校验码段。例如，内存控制器200可以将数据中0到255比特的数据构成的数据段以及第一校验码中0到63比特的数据构成的校验码段写入到该通道组中的通道1中，将数据中256到511比特的数据构成的数据段以及第一校验码中64到127比特的数据构成的校验码段写入到该通道组中的通道2中，将数据中512到767比特的数据构成的数据段以及第一校验码中128到191比特的数据构成的校验码段写入到该通道组中的通道3中，将数据中768到1023比特的数据构成的数据段以及第一校验码中192到255比特的数据构成的校验码段写入到该通道组中的通道4中。
以通道组中包括2个通道，每个通道大小为256比特为例。
如图5B所示，内存控制器200可以将512比特数据分为2个数据段，每个数据段的长度为256比特。内存控制器200可以将128比特的第一校验码分为2个校验码段，每个校验码段的长度为64比特。
内存控制器200在每个通道中写入一个数据段以及一个校验码段。例如，内存控制器200可以将数据中0到255比特的数据构成的数据段以及第一校验码中0到63比特的数据构成的校验码段写入到该通道组中的通道1中，将数据中256到511比特的数据构成的数据段以及第一校验码中64到127比特的数据构成的校验码段写入到该通道组中的通道2中。
至此，内存控制器200将数据进行到了内存100的通道组中。在数据写入到内存100后，内存控制器200还可以对写入到内存100中的数据进行更新。例如，处理器指示内存控制器200对数据中的某个比特或某一个比特进行修改。又例如，内存控制器200采用RMW方法将数据写入到内存100中时。
内存控制器200在需要对内存100中的数据进行更新时，除了需要对数据本身进行更新，还重新生成校验码。下面以内存控制器200对前述步骤中写入的数据进行更新为例对内存控制器200对内存100中的数据进行更新的方式进行说明。
步骤404：内存控制器200从该通道组中读取数据以及数据的第一校验码。
内存控制器200从该通道组中的多个通道中读出多个数据段和多个校验码段，将该多个数据段拼接为原始的数据，将该多个校验码段拼接为第一校验码。
内存控制器200可以将该多个数据段以及多个校验码段写入到内存控制器200中的缓存 单元220中。其中，多个数据段写入到缓存单元220中的数据区域，多个校验码段写入到缓存单元220的校验码区域。该多个数据段在该数据区域的排序位置与该多个数据段在该数据中排序位置一致，该多个校验码段在该校验码区域的排序位置与该多个校验码段在该第一校验码中的排序位置一致。
以图5A所示的数据以及第一校验码写入到通道组的方式为前提，参见图6A，为本申请实施例提供的从通道组中读取数据的示意图。
内存控制器200可以从通道1中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中0～255比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中0～63比特的位置。内存控制器200可以从通道2中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中256～511比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中64～127比特的位置。内存控制器200可以从通道3中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中512～767比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中128～191比特的位置。内存控制器200可以从通道4中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中768～1023比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中192～256比特的位置。
以图5B所示的数据以及第一校验码写入到通道组的方式为前提，参见图6B，为本申请实施例提供的从通道组中读取数据的示意图。
内存控制器200可以从通道1中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中0～255比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中0～63比特的位置。内存控制器200可以从通道2中读取256比特的数据段以及64比特的校验码段，将256比特的数据段写入到缓存单元220中数据区域中256～511比特的位置，将64比特的校验码段写入到缓存单元220中校验码区域中64～128比特的位置。
步骤405：内存控制器200更新数据，并根据更新后的数据生成第二校验码。
内存控制器200可以对数据更新，例如修改或删除该数据中的部分比特。内存控制器200在更新了该数据之后，为该更新后的数据生成第二校验码。内存控制器200生成第二校验码的方式与生成第一校验码的方式类似，具体可以参见步骤402。在内存控制器200中可以删除第一校验码，将第二校验码写入到缓存单元220的校验码区域中。
步骤406：内存控制器200将更新后的数据以及第二校验码写入到内存100的通道组中。其中该数据的校验码分散在该通道组中的各个通道上。步骤406与步骤403类似，区别仅在于内存控制器200所存储的数据以及校验码不同，具体可以参见步骤403的相关说明，此处不再赘述。
通过步骤404～步骤406，实现了内存100中数据的更新。内存控制器200还可以将内存100中的数据读取后反馈给处理器，下面以内存控制器200需要读取写入到通道组中的数据为例，对内存控制器200读取数据的方式进行说明，具体可以参见步骤407～步骤408。
步骤407：内存控制器200在处理器的指示下从该通道组中读取数据以及第二校验码。
当处理器需要读取数据，处理器会向内存控制器200发送指示，告知所需读取的数据的信息，如该数据的逻辑地址等。内存控制器200在接收到处理器发送的指示后，内存控制器200可以确定该数据在该内存100所在的通道组，从该通道组中读取多个数据段以及校验码 段，将读取的多个数据段写入到缓存单元220的数据区域中，在数据区域中形成完整的数据，将读取的多个校验码段写入到缓存单元220的校验码区域，在校验码区域中形成第二校验码。
步骤408：内存控制器200利用该第二校验码对读取的数据进行校验、纠错。
内存控制器200在读取了第二校验码以及数据之后，内存控制器200利用第二校验码确定该所读取的数据是否存在错误数据，并定位错误数据的位置。这里的错误数据是指读取的数据中与写入该通道组中的数据(也即步骤406中更新后的数据)不同的数据。
若内存控制器200利用第二校验码确定该所读取的数据不存在数据错误，内存控制器200可以将该数据反馈给处理器。
若内存控制器200利用第二校验码确定该所读取的数据存在数据错误，内存控制器200可以利用第二校验码定位数据错误的位置，并利用第二校验码对错误数据进行纠错，将纠错后的数据反馈给处理器。若内存控制器200利用第二校验码对错误数据纠错失败，内存控制器200可以通知处理器数据读取失败。
需要说明的是，内存控制器200利用该第二校验码对读取的数据进行校验、纠错的方式与内存控制器200生成第二校验码的方式有关。内存控制器200需要利用与生成第二校验码所调用的ECC算法相对应的纠错算法对读取的数据进行校验、纠错。例如，在步骤402以及步骤405中采用RS编码算法生成了第一校验码以及第二校验码，那么在步骤408中，内存控制器200可以采用RS纠错算法、该第二校验码对读取的数据进行校验、纠错。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种内存数据读写方法，其特征在于，所述方法用于对内存进行数据读写，所述内存包括一个或多个通道组，每个通道组包括多个通道，所述方法由内存控制器执行，所述方法包括：
    获取需要写入通道组的目标数据；
    生成所述目标数据的校验码，所述校验码用于对所述目标数据进行校验以及纠错；
    将所述目标数据以及所述校验码写入到所述通道组中，所述校验码分散存储在所述通道组的各个通道中，所述目标数据分散存储在所述通道组的通道中。
  2. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    在处理器的指示下，从所述通道组中读取所述目标数据以及所述校验码；
    利用所述校验码对所述目标数据进行纠错；
    将纠错后的所述目标数据反馈至所述处理器。
  3. 如权利要求1或2所述的方法，其特征在于，一次写入到所述通道组中的数据等于处理器中缓存的位宽。
  4. 如权利要求1或2所述的方法，其特征在于，一次写入到所述通道组中一个通道的数据等于处理器中缓存的位宽。
  5. 如权利要求1～4任一项所述的方法，其特征在于，所述通道组中通道的数量等于2、3、4、6、8、12或16。
  6. 如权利要求1～5任一项所述的方法，其特征在于，所述生成所述目标数据的第一校验码，包括：
    调用RS8编码算法或RS16编码算法生成所述目标数据的校验码。
  7. 如权利要求1～6任一项所述的方法，其特征在于，每个通道包括一个或多个RANK，每个RANK中包括多个内存颗粒。
  8. 如权利要求1～7任一项所述的方法，其特征在于，所述将所述目标数据以及所述校验码写入到所述通道组中，包括：
    将所述目标数据拆分为多个目标数据段，将所述校验码拆分为多个校验码段；
    将所述多个目标数据段分别写入所述通道组中的所述各个通道，将所述多个校验码段分别写入所述通道组中的所述各个通道。
  9. 一种内存系统，其特征在于，所述系统包括内存控制器以及内存；
    所述内存包括一个或多个通道组，每个通道组包括多个通道；
    所述内存控制器，用于获取需要写入通道组的目标数据；生成所述目标数据的校验码，所述校验码用于对所述目标数据进行校验以及纠错；将所述目标数据以及所述校验码写入到所述通道组中，所述校验码分散存储在所述通道组的各个通道中，所述目标数据分散存储在所述通道组的通道中。
  10. 如权利要求9所述的系统，其特征在于，所述内存控制器，还用于：
    在处理器的指示下，从所述通道组中读取所述目标数据以及所述校验码；
    利用所述校验码对所述目标数据进行纠错；
    将纠错后的所述目标数据反馈至所述处理器。
  11. 如权利要求9或10所述的系统，其特征在于，一次写入到所述通道组中的数据等于处理器中缓存的位宽。
  12. 如权利要求9或10所述的系统，其特征在于，一次写入到所述通道组中一个通道的 数据等于处理器中缓存的位宽。
  13. 如权利要求9～12任一项所述的系统，其特征在于，所述通道组中通道的数量等于2、3、4、或8。
  14. 如权利要求9～13任一项所述的系统，其特征在于，所述内存控制器在生成所述目标数据的第一校验码，用于：
    调用RS8编码算法或RS16编码算法生成所述目标数据的校验码。
  15. 如权利要求9～14任一项所述的系统，其特征在于，每个通道包括一个或多个RANK，每个RANK中包括多个内存颗粒。
  16. 如权利要求9～15任一项所述的系统，其特征在于，所述内存控制器在将所述目标数据以及所述校验码写入到所述通道组中，用于：
    将所述目标数据拆分为多个目标数据段，将所述校验码拆分为多个校验码段；
    将所述多个目标数据段分别写入所述通道组中的所述各个通道，将所述多个校验码段分别写入所述通道组中的所述各个通道。
  17. 一种内存控制器，其特征在于，所述内存控制器包括处理单元和缓存单元；
    所述缓存单元，用于缓存所述目标数据；
    所述处理单元，用于执行如权利要求1～8任一所述的方法。
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