WO2018119741A1 - 数据访问方法及闪存设备 - Google Patents
数据访问方法及闪存设备 Download PDFInfo
- Publication number
- WO2018119741A1 WO2018119741A1 PCT/CN2016/112629 CN2016112629W WO2018119741A1 WO 2018119741 A1 WO2018119741 A1 WO 2018119741A1 CN 2016112629 W CN2016112629 W CN 2016112629W WO 2018119741 A1 WO2018119741 A1 WO 2018119741A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- storage area
- information
- code level
- coding unit
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
Definitions
- the present invention relates to the field of storage technologies, and in particular, to a data access method and a flash memory device.
- flash memory technology has rapidly developed, and storage densities have evolved from single-bit memory elements to the most recent multi-bit memory elements, such as 6 bits.
- the manufacturing process of flash memory is extended from 65 nanometers to the nearest 10 nanometers.
- the flash memory is equipped with an ECC (Error Correcting Code) for each flash page.
- the ECC codes currently used mainly are BCH coding and LDPC coding.
- the BCH is a cyclic code.
- the k-bit information code is encoded by the generator matrix g(x) to obtain n-bit coded information.
- the redundant bit length of the coded information is n-k, and t errors can be corrected.
- the BCH code or the LDPC code with high error correction capability is generally used in the prior art, but the BCH code or the LDPC code with high error correction capability makes the hardware overhead become large, and the codec complexity becomes high. The consumption is also high.
- the present application provides a data access method and a flash memory device, which can adopt ECC coding with weak error correction capability to ensure data reliability.
- the present application provides a data access method.
- the method is performed by a controller in a flash memory device.
- the controller acquires a first shortened code level of the first storage area to be accessed, and the first shortened code level is used to indicate a ratio of shortening information in the first storage area.
- the controller converts the first data to be written into the first storage area into the second data according to the first shortened code level.
- the size of the second data is the same as the size of the first storage area.
- the second data includes a plurality of coding units, and each of the coding units includes partial data in the first data and first padding information.
- the size of the first padding information is based on a ratio of shortening information in the first storage area and a size of the coding unit Calculated obtained.
- the controller encodes each of the second data according to the set BCH encoding to obtain encoding information of the second data.
- the size of each coding unit is the same as the length of the BCH coded information bits.
- the controller writes the second data into the first storage area, and writes the encoded information of the second data into an out-of-band area of the first storage area.
- the data access method provided by the present application shortens the effective information bits in the data to be encoded by using the principle of shortening the BCH code, and uses padding to ensure the reliability of the stored data when using BCH coding with low error correction capability.
- the way to construct the encoded data Since the shortening code is adopted, the data bits actually stored in the flash page are reduced, and since the stuffing code information is known in advance, the uncorrectable error rate in the actually stored data becomes low, and the flash memory device is low. The reliability has been improved. In this way, even with the ECC encoding with low error correction capability, the reliability of the data can be ensured and the service life of the flash memory device can be prolonged.
- the length of the coding unit is the same as the length of the coding unit before the shortening, and therefore, even the coded information is available to the ECC module in the controller.
- the bit is continuously shortened according to the use of the flash memory device, and the interface of the ECC module in the controller can still be maintained. Therefore, the hardware overhead is reduced on the basis of ensuring data reliability.
- the controller may obtain a first shortened code level of the first storage area according to a correspondence between an address of the set flash block and a shortened code level.
- the first shortened code level is a shortened code level of the flash block to which the first storage area belongs.
- the controller may obtain a ratio of the shortening information in the first storage area according to a correspondence between the set first shortening code level and the ratio of the shortening information.
- the controller reads the third data stored in the first storage area and the out-of-band area of the first storage area After the encoding information of the second data, the controller performs verification error correction on the third data according to the encoding information of the second data to obtain the second data. Then, the controller obtains an address of the data in each coding unit in the second data according to the first shortened code level, the length of the coding unit in the second data, and the location information of the set padding information. Information, and acquiring the first data from the second data according to address information of data in each coding unit, wherein the first data The padding information is not included in the data.
- the shortened code level of the first storage area is a shortened code level of a flash block to which the first storage area belongs.
- the controller stores the flash memory to which the first target storage area belongs.
- the shortened code level of the block is adjusted from the first shortened code level to a second shortened code level.
- the ratio of the padding information indicated by the second shortened code level is greater than the proportion of the padding information indicated by the first shortened code level.
- the error in the third data reaching the preset threshold includes: the number of errors in the third data is greater than a set threshold and less than a maximum error correctable bit in the set BCH code. number.
- the controller determines that the shortened code level of the second storage area is the second shortened code level.
- the second storage area and the first storage area belong to the same flash block.
- the controller converts the fourth data into fifth data according to the second shortened code level.
- the size of the fifth data is the same as the size of the second storage area.
- the fifth data includes a plurality of coding units, and each of the coding units includes partial data and second padding information in the fourth data.
- the size of the second padding information in the coding unit in the fifth data is calculated according to the second shortened code level and the size of the coding unit in the fifth data.
- the controller After the controller encodes each of the fifth data according to the BCH encoding to obtain encoding information of the fifth data, the controller writes the fifth data into the a second storage area, and the encoded information of the fifth data is written to the out-of-band area of the second storage area.
- the size of each coding unit in the fifth data is the same as the information bit length of the BCH code.
- the present application provides a flash memory device including a controller and a storage medium coupled to the controller.
- the storage medium is used to provide a plurality of storage areas.
- the controller is for performing the method provided by the first aspect or any one of the possible implementations of the first aspect.
- the present application provides yet another flash memory device comprising a virtual module for implementing the functionality of the method provided by the first aspect or any one of the possible implementations of the first aspect.
- the present application provides a computer program product comprising a computer readable storage medium storing program code, the program code comprising instructions for performing the foregoing first aspect and any one of the first aspects The method described in the implementation.
- FIG. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention.
- FIG. 2 is a flowchart of a data writing method according to an embodiment of the present invention.
- FIG. 3 is a schematic diagram of a coding structure of data to be written according to an embodiment of the present disclosure
- FIG. 5 is a schematic diagram of a correspondence relationship between a shortened code level and a shortened information ratio according to an embodiment of the present invention
- FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention.
- FIG. 7 is a flowchart of still another data writing method according to an embodiment of the present invention.
- FIG. 8 is a schematic structural diagram of still another flash memory device according to an embodiment of the present invention.
- flash device 100 can include controller 102, host interface 106, and flash array 108.
- the host interface 106 is used to connect to the host and communicate with the host. For example, it is used to receive an I/O request issued by the host, or return data read from the flash array 108 to the host.
- the host interface 106 may include a Serial Advanced Technology Attachment (SATA) interface, a Universal Serial Bus (USB) interface, a Fibre Channel (FC) interface, or a fast peripheral interconnection.
- SATA Serial Advanced Technology Attachment
- USB Universal Serial Bus
- FC Fibre Channel
- PCI-E Peripheral Component Interconnect Express
- Flash array 108 for storing data.
- Flash array 108 can be comprised of multiple memory cells.
- flash array 108 may also be referred to as a storage medium, and a storage unit in flash array 108 refers to a minimum storage medium unit for storing data.
- the flash array 108 may use a single-level cell (SLC) or a multi-level cell (MLC), where each SLC cell stores 1 bit of information, and each MLC cell may store More than 1 bit of data.
- the memory cells in the flash array 108 are multi-level memory cells MLC.
- an MLC in which each storage unit stores 2-bit data may be included
- a third-order storage unit Trinary-Level Cel, TLC
- the controller 102 mainly includes a processor 1022, a cache 1024, and a flash interface 1026.
- the processor 1022, the cache 1024, and the flash interface 1026 complete communication with each other over the communication bus.
- the cache 1024 is a temporary memory located between the processor 1022 and the memory. Its capacity is smaller than the memory but the exchange speed is faster than the memory. Cache 1024 is used to cache data that processor 1022 is to write to flash array 108 or to cache data that is read from flash array 108.
- a flash interface 1026 coupled to the flash array 108, is used to communicate with the flash array 108 to control data transfer with the flash array 108. For example, it can be used to manage access commands to the flash array 108 issued by the processor 1022 and to perform data transmission. It can be appreciated that a plurality of communication channels can be included in the flash interface 1026 for connecting different memory cells in the flash array 108.
- flash array 108 is divided into a series of 128 KB (kilobyte) blocks, which are the smallest erasable entities in flash devices.
- Each block includes multiple pages.
- the basic unit of the read operation and the write operation of the flash memory device 100 is a page.
- a page is 4KB.
- Each page can also be divided into multiple sectors.
- Each sector may include a plurality of storage units for storing data.
- a sector can be 512 bytes. Since the capacity of each page determines the amount of data that can be transferred at one time, large-capacity pages have better performance. Moreover, the use of large-capacity pages can reduce the complexity of the circuit.
- one physical page in flash device 100 can be 16 KB or 32 KB.
- a block may also be referred to as a flash block
- a page may also be referred to as a flash page.
- the write operation request issued by the operating system is usually 4KB granularity.
- 4KB is usually used as a logical page. Therefore, in practical applications, for a flash memory device having a page capacity of 16 KB or 32 KB, the size of each sector can be 4 KB.
- a mapping relationship a mapping relationship from a logical address to a physical address is usually established in units of 4 KB.
- the processor 1022 can be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
- a software program is installed in the processor 1022, and different software programs can be regarded as one processing module having different functions.
- the processor 1022 may include a processing module such as a garbage collection module, a verification error correction module, and a bad block management module, so that the processor 1022 can implement an access request to the flash array 108 or manage data in the flash array 108. and many more.
- the processor 1022 can receive the input and output I/O requests forwarded by the host interface 106 through the communication bus, and access the flash array 108 through the flash interface 1026 according to the I/O request issued by the host, and write data to the flash array 108 or Data is read from flash array 108.
- a verification error correction mechanism is set in the flash memory device.
- a verification error correction module 1023 can be included in the processor 1022.
- the parity correction module 1023 performs checksum error correction on the data mainly through an Error Correction Code (ECC).
- ECC Error Correction Code
- the verify error correction module 1023 can encode the data when writing the data and perform error detection and correction when the data is read.
- ECC can be implemented in hardware or software.
- each flash page includes additional storage space, that is, an out of bank (OOB) area.
- OOB out of bank
- the out-of-band area is used to store information such as ECC code or mapping information of a logical address to a physical address.
- the check error correction module 1023 internal to the processor 1022 can generate an ECC signature (which can also be referred to as an ECC code) based on the data in one sector. And save the generated ECC signature in the flash page to which the sector belongs. Out-of-band area.
- the check error correction module 1023 reads the ECC signature, and determines whether it is based on the read data and the ECC signature. A data error has occurred. If it is detected that the read data contains error bits, the corresponding ECC algorithm is needed to correct the detected error.
- the processor 1022 may further include other software modules.
- the verification error correction mechanism in the processor is mainly described in the embodiment of the present invention, only the verification error correction module is illustrated in FIG. 1023.
- the ECC algorithm may include BCH coding or LDPC coding and the like.
- the embodiment of the present invention mainly describes a coding mode using BCH coding.
- the BCH code is a binary linear cyclic code discovered by Bose, Ray-Chaudhuri, and Hocquenghem in 1959, and the cyclic code is named BCH code by their abbreviations.
- the BCH code can correct multiple random errors.
- Common BCH codes may include a Golay code, an extended BCH code, and a shortened BCH code.
- the Golay code is a special non-primitive BCH code that can correct 3 errors.
- the extended BCH code is obtained by extending the BCH code in order to obtain the even digital length and increase the error detection capability. Extending the BCH code is equivalent to adding a one-bit parity to the BCH code, which is no longer cyclic.
- the BCH code shortens the number of bits that can be corrected, but the code length is shorter than the code length of the BCH code.
- the BCH code is BCH(n, k, t)
- the BCH code can encode k information bits to obtain a code of length n, and can correct t errors.
- k is the information bit length of the BCH code
- n may also be referred to as the code length of the BCH code.
- shortening the BCH code can encode k-l information bits to obtain a code of length n-l, and still can correct t errors.
- the BCH code is shortened because the error correction capability is the same as the BCH code, but the code length is shorter.
- the coding unit using the shortened BCH code is more than the coding unit using the BCH code. Therefore, the possibility of shortening the BCH code to make correct decoding is improved.
- the shortened code ratio is a ratio of the length of the shortened code to the length of the error-corrected information bit.
- the shortened code ratio can be expressed as l/k, where l is the shortened information bit length, k is the length of the BCH encoded information bit, and k can also be referred to as BCH code error correctable information bit. length.
- FIG. 2 is a flowchart of a data writing method according to an embodiment of the present invention.
- the method can be performed by controller 1022 in flash device 100 shown in FIG. 1 for writing data into flash array 108.
- the controller 1022 is performing a write operation.
- the data to be written is encoded and then written to the storage array 108.
- the read data can be checked and corrected according to the encoded information.
- the ECC algorithm may include BCH coding or LDPC coding.
- the data writing process using BCH coding is mainly optimized, so that the reliability of the data can be ensured even if the BCH coding with low error correction capability is adopted. Therefore, in the embodiment of the present invention, the data writing method provided by the embodiment of the present invention is described by taking the BCH encoding as an example. The method in Fig. 2 will be described in detail below with reference to Fig. 1.
- the controller 1022 receives a first access request, where the first access request carries an address to be accessed and data to be written.
- the controller 1022 can receive the first access request sent by the operating system of the host through the host interface 106, and the first access request sent by the operating system can carry the address information of the storage area to be accessed.
- the address information carried in the first access request is a logical address of the first storage area to be accessed.
- the first access request may further carry information about the data to be written or the cache address of the data to be written. It can be understood that when the first access request carries the cache address information of the data to be written, the controller 1022 can obtain the data to be written from the cache 1024 according to the cache address information of the data to be written.
- the controller 1022 determines the first storage area according to the to-be-accessed address.
- the access request usually carries the logical address of the storage area to be accessed, and the mapping relationship between the logical address and the physical address of the storage area is maintained in the flash memory device, thereby being able to be accessed according to the The logical address carried in the request finds the physical address to be accessed.
- the controller 1022 may convert the logical address in the first access request into a physical address according to the mapping relationship between the stored logical address and the physical address.
- the flash memory device can determine the storage area to be accessed by the current write operation according to the physical address obtained by the conversion.
- the storage area to be accessed by the first access request is referred to as a first storage area. It can be understood that since the write operation is in units of pages, the first storage area may be one flash page in one flash memory device 100.
- the controller 1022 obtains a shortened code level of the first storage area.
- a BCH code with strong error correction capability can be used.
- the improvement of error correction capability leads to delays, power consumption, etc. of flash memory devices.
- the use of the shortened BCH code can improve the reliability of data stored in the flash memory device 100.
- the BCH coding with lower error correction capability is used to reduce the power consumption of the flash memory device 100, and the application principle of the shortened code is used to improve the reliability of the data while ensuring low overhead of the flash memory device 100.
- different shortened code levels can be set for different blocks. According to this method, different degrees of shortening codes can be used in combination to ensure the reliability of data in different blocks.
- different pages in the same block have the same shortened code level.
- the shortened code level is used to indicate the proportion of information that is shortened in the flash page.
- the shortened code level is used to indicate the amount of data that is reduced in the flash page.
- a shortened code level can be used in an actual application to indicate the reduced number of sectors. Taking a 32 KB flash page as an example, assuming that each sector is 4 KB in size, one flash page can include 8 sectors.
- the shortening code level of the block to which the flash page belongs is 1, and the shortening code level is 1 to indicate that the ratio of the shortened information in the flash page is 1/8, it indicates that the reduced amount of data in the flash page is 1 sector.
- the amount of data, the available space is 7 sectors.
- the shortened code level information of each flash block can be set in the flash device in the form of a record table.
- the shortened code level record table may include location information of the flash block and a shortened code level corresponding to the flash block.
- the shortened code level record table may be stored in the memory of the flash memory device, or may be stored in the cache 1024, and may also be stored in the flash array 108.
- the cache 1024 may include a backup device, and when the shortened code level record table is stored in the cache 1024 of the flash device, the backup device may support the flash device 100 before the power is turned off.
- the shortened code level record table is written back to the flash array 108 to avoid loss.
- the specific storage location of the shortened code level record table is not limited.
- the positional information of the flash memory block and the corresponding relationship of the shortened code level corresponding to the flash memory block may be recorded in the flash memory device in other forms, which is not limited in the embodiment of the present invention.
- the controller 1022 may obtain the information according to the address of the first storage area and the corresponding relationship between the set flash block and the shortened code level.
- the shortened code level of the flash block may also be referred to as the shrinking of the flash page in the flash block.
- the short code level is referred to as a first shortened code level by the shortening level of the first storage area acquired by the controller 1022 in the process of executing the first access request.
- the controller 1022 converts the first data to be written into the first storage area into the second data according to the first shortened code level.
- the size of the second data is the same as the size of the first storage area.
- the second data includes a plurality of coding units, and each of the coding units includes partial data in the first data and first padding information.
- the size of the first padding information is calculated according to a ratio of shortening information in the first storage area and a size of the coding unit.
- the check error correction module 1023 in the controller 1022 needs to adjust the upper and lower interfaces according to the shortened information bit to encode different lengths of data, thereby Increase hardware overhead.
- the flash device can adopt a unified hardware interface, and can use only one generation matrix to encode the data.
- the filling method is adopted.
- the shortened information bits are filled in so that the verification error correction module 1023 in the controller 1022 does not need to perceive changes in the data information bits, and can improve the reliability of the stored data.
- the data method provided by the embodiment of the present invention is transparent to the verification error correction module 1023.
- the controller 1022 performs the write operation with the page as the granularity
- the BCH code is the coding unit as the operation granularity, wherein the data of one sector sector can be used as one coding unit.
- one coding unit may include data of a plurality of sectors or data of a half sector.
- the size of the coding unit is not limited. In this way, a plurality of coding units can be included in one flash page. Taking BCH (n, k, t) encoding as an example, where k is the length of the encoded information bits, it may also be referred to as the length of the coding unit.
- FIG. 3 is a schematic diagram of a structure of a coding unit according to an embodiment of the present invention. In the embodiment of the present invention, assuming that the shortened information bit length is 1, the encoded information bit length (i.e., the length of the encoded data) becomes k-1.
- padding information of length l can be filled to fill information and shorten The sum of the lengths of the subsequent data is still the length k of the coding unit.
- the check error correction module 1023 can still encode the interface and the codec according to the set BCH (n, k, t).
- the coding unit including k bits is encoded to achieve the purpose of correcting t errors, wherein the padded coding unit includes k-1 bit data and 1 bit padding information.
- the padding information may be “0” or “1”.
- the padding information in each coding unit may be located in front of the data or after the data.
- FIG. 3 is a schematic diagram showing a configuration of a coding unit according to an embodiment of the present invention.
- the data of the flash page to be written to the flash array 108 in the embodiment of the present invention will be described below with reference to FIG.
- the received data to be stored may be cached in the cache 1024, and the controller 1022 may obtain the data to be stored in the first storage area from the cache 1024 during the write operation of the controller 1022.
- the first storage area is a flash page
- one coding unit is a sector.
- FIG. 4 is a schematic structural diagram of a flash memory page according to an embodiment of the present invention.
- a cache page 402 to be written into the first storage area is cached, and the cache page includes four sectors: S1, S2, S3, and S4, wherein four fans are included.
- the data in the zone are: D1, D2, D3, and D4.
- the controller 1022 may calculate the length of the shortened information bits of each coding unit in the flash memory page.
- a correspondence relationship between the shortened code level and the shortened information bit ratio may be set.
- one flash memory page includes four sectors, and the coding unit is one sector.
- the shortened code level is 2
- the shortened information ratio is 1/2 (ie, 2/4), which is used to indicate that the length of the shortened information bits in the flash page is 2 sectors. It will be appreciated that the length of the shortened information is less than the length of the flash page.
- the controller 1022 can obtain the shortened in the first storage area by the set shortening code level and the correspondence of the ratio of the shortened information. Information ratio.
- the controller 1022 can further calculate the size of the padding bit information in each coding unit.
- the length of the padding information in each coding unit may be multiplied by the size of the coding unit by the shortened information ratio corresponding to the shortened code level of the first storage area.
- the first storage area is 32 KB, including 4 sectors, and one coding unit is one sector.
- the padding information T1, T2, T3, and T4 in FIG. 4 are both 2 KB in size.
- the data in the cache page 402 is 32 KB, a total of four sectors are included: S1, S2, S3, and S4.
- the data in the cache 402 can be reorganized into a new cache page (see the first page 404 in FIG. 4). Specifically, as shown in FIG. 4, the obtained new cache page 404 still includes 4 sectors (ie, 4 coding units).
- the first coding unit includes partial data in the sector S1 in the cache page 402 (ie, 6 KB of data in D1) and padding information T1.
- the second coding unit includes the remaining 2 KB of data in the sector S1 in the cache page 402 and the 4 KB data in the sector S2 and the padding information T2 (the size is 2 KB).
- the third coding unit includes the remaining 4 KB of data in the sector S2 in the cache page 402 and the 2 KB data in the sector S3 and the padding information T3 (the size is 2 KB).
- the fourth coding unit includes the remaining 6 KB of data in the sector S3 in the cache page 402 and the padding information T4 (the size is 2 KB).
- the data of sector S4 in cache page 402 can be recombined with other data to be written to form a new flash page (e.g., second page 406 in FIG. 4). It should be noted that in FIG. 5, other data in the second page 406 is not illustrated.
- the padding information may be “0” or “1”, and the padding information may be located at a preset position of the coding unit. For convenience, padding information can be placed at the front or the tail of each coding unit (as shown in Figure 4).
- the first data to be written into the first storage area may only represent part of the data in the cache page 402.
- the first data may be the first three sectors in the cache page 402.
- the data of the reorganized flash page becomes the second data.
- all data in the first page 404 in FIG. 4 can be referred to as second data.
- the second data includes a plurality of coding units, and each of the coding units includes partial data and padding information in the first data.
- the controller 1022 can reorganize the data to be written at the software conversion layer to obtain data to be written to the physical page.
- the controller 1022 encodes each of the second data in accordance with the set BCH encoding to obtain encoding information of the second data.
- the length of each coding unit is the same as the length of the BCH coded information bits.
- the controller 1022 may encode each coding unit in the first page 404 according to the set BCH coding to obtain coding information of each coding unit. Taking BCH (n, k, l) coding as an example, each coding unit in the second data has a length of k.
- the check error correction module 1023 in the controller 1022 can encode the information in the coding units S1, S2, S3, and S4 in the first page 404 to obtain the coding information of each coding unit.
- the coding information of each coding unit may be collectively referred to as the coding information of the second data.
- step 212 the controller 1022 writes the second data into the first storage area, and writes the encoded information of the second data into the out-of-band area of the first storage area.
- each flash page includes an out-of-band area for storing ECC encoded information, so in this step, after obtaining the first page 404 containing the second data, the controller 1022 can respectively perform the first The second data in page 404 is stored in the first storage area, and the encoded information of the second data obtained in step 210 is stored in an out-of-band area of the first storage area.
- the data writing method applied to the flash memory device proposes to construct the encoded information in a padding manner. Since the shortening code is adopted, the data bits actually stored in the flash page are reduced, and since the stuffing code information is known in advance, the uncorrectable error rate in the actually stored data becomes low, and the flash device is Reliability has been improved. And, since the shortened portion of the encoded data is filled with the padding information, the length of the coding unit is the same as the length of the coding unit before the shortening, and therefore, even for the ECC module, the information bits that can be encoded are according to the flash device. The use is constantly shortened, and the interface of the ECC module in the flash memory device can still be maintained. Therefore, the hardware overhead is reduced on the basis of ensuring data reliability. In this way, even if ECC encoding with low error correction capability can also ensure data reliability and extend the life of flash memory devices.
- FIG. 6 is a schematic diagram of data reading according to an embodiment of the present invention. For clarity of description, FIG. 6 still describes how to read data written during the aforementioned write operation from the first storage area.
- step 602 the controller 1022 reads the third data stored in the first storage area and the encoded information of the second data.
- the flash device 100 converts the logical address carried in the read request into the physical address to be accessed, thereby being able to determine the flash page to which the data to be read belongs.
- the flash page described in detail on how to determine the data to be read is not described in the embodiment of the present invention, and how the data is read from the flash page will be described.
- the data in the first storage area is still taken as an example, and the first storage area is any one of the flash memory devices. page.
- the controller may read data from the first storage area according to the acquired physical address to be accessed. Since the data read in the first storage area may be in error, in the embodiment of the present invention, the data in the reading is referred to as the third data.
- the controller 1022 can read the data stored in the first storage area when the data is read from the first storage area, and the controller 1022 also reads the first storage from the out-of-band area of the first storage area.
- the encoded information of the data stored in the area In the embodiment shown in FIG. 2, the data written in the first storage area is the second data, and the encoded information of the second data written in the first storage area is taken as an example.
- the control is performed.
- the device 1022 can read data from the first storage area and read encoded information of the second data from an out-of-band area of the first storage area.
- the controller 1022 can also cache the data read from the first storage area in the cache 1024.
- step 604 the controller 1022 performs check error correction on the third data according to the encoding information of the second data to obtain the second data.
- the check error correction module 1023 in the controller 1022 performs check error correction on the data read from the flash page.
- the data read by the controller 1022 from the data area of the first storage area is called for clarity of description.
- the verification error correction module 1023 in the controller 1022 The third data read from the first storage area may be subjected to check error correction by the encoding information of the second data to obtain the second data stored in step 212 of FIG.
- the third data may be correspondingly determined according to a decoding method corresponding to the preset BCH coding mode. Test and correct. Thereby the second data can be obtained.
- the BCH coding mode and the decoding method used in the embodiments of the present invention are the same as those in the prior art, and a specific decoding process is not described herein.
- the controller 1022 calculates address information of data in each of the coding units in the second data according to the first shortened code level and the length of the coding unit in the second data.
- the controller 1022 may be configured according to the ratio of the padding information indicated by the shortened code level of the first storage area to the first storage area, the length of the coding unit in the second data, and the set padding information.
- the padding location determines the first address of the data in each sector and the size of the data.
- the first address of the data of the i-th coding unit is the first address of the i-th coding unit. It can be understood that if one sector is a coding unit, the first address of the i-th coding unit is the first address of the i-th sector.
- the controller 1022 may further obtain the size of the padding information in each coding unit according to the shortened code level of the first storage area, and further The position of the data in each coding unit can be determined according to the position of the set padding information and the size of the padding information, so that data can be read from each coding unit.
- there may be multiple methods for determining the location of the data in the coding unit which is not limited in the embodiment of the present invention, as long as the shortened code level of the first storage area and the size of each coding unit can be determined. Calculate the data in each coding unit.
- step 608 the controller 1022 acquires the first data from the second data according to the address information of the data in each coding unit, where the padding information is not included in the first data. Specifically, after obtaining the offset and size of the data in each coding unit in the second data in step 606, the controller 1022 may obtain the first to be read from the second data. Data, wherein the first data does not include the padding information.
- step 604 when the controller 1022 performs error correction on the third data according to the encoding information of the second data, it may be determined in the third data. Whether the number of errors is greater than the set threshold m, where m is less than the maximum number of correctable bits t in the set BCH (n, k, t) encoding. When the number of errors in the third data is greater than the set threshold m and less than t, it is determined that the current shortened code level of the first storage area is not reliable enough, and the available space needs to be further shortened. Specifically, the controller 1022 can record the maximum number of error correction bits of the first storage area at this time.
- the shortened code level of the flash block to which the first storage area belongs is re-adjusted, and according to this manner, the shortening code of the first storage area may be re-adjusted grade.
- the current shortened code level of the first storage area is the first shortened code level
- the adjusted shortened code level is the second shortened code level.
- the controller when the number of errors in the third data is greater than a set threshold and less than a maximum number of correctable bits in the set BCH code, the controller records the first storage area here. The maximum number of error correction bits. After the flash block to which the first storage area belongs is erased, the controller adjusts the shortened code level of the associated flash block of the first storage area from the first shortened code level to the second Reduce the code level. The ratio of the padding information indicated by the second shortened code level is greater than the proportion of the padding information indicated by the first shortened code level.
- the corresponding relationship between the set flash block and the shortened code level may be updated according to the adjusted second shortened code level. According to this manner, in the adjusted first storage area, the available space for storing data is further reduced. The data information in the coding unit is further reduced, so that the reliability of data subsequently stored in the first storage area can be further improved.
- the fourth data to be stored in the second storage area is received, wherein the second storage area and the first If a storage area belongs to the same flash block, the fourth data can be written to the second storage area according to the data writing method described in FIG. Specifically, the following steps as shown in FIG. 7 may be included.
- step 702 the controller 1022 receives fourth data to be written to the second storage area.
- the second storage area and the first storage area belong to the same flash block.
- the controller 1022 may also cache the fourth data in the cache 1024.
- step 704 the controller 1022 determines that the shortened code level of the second storage area is the second shortened code level. Since the shortened code level of the flash block to which the adjusted first storage area belongs is the second level, the second storage and the first storage area belong to the same flash block, and therefore, the shortening code of the second storage area The rating is the shortened code level of the flash block. In an actual application, the controller 1022 may query the shortened code level of the second storage area according to the corresponding relationship between the set flash block and the shortened code level.
- the controller 1022 adjusts the shortened code level of the first storage area from the first shortened code level to the second shortened code level, and updates the correspondence between the flash block and the shortened code level. relationship. Therefore, in this step, the controller 1022 can obtain the shortened code level of the second storage area as the second shortened code level by querying the corresponding relationship between the updated flash block and the shortened code level.
- step 706 the controller 1022 converts the fourth data into fifth data according to the second shortened code level.
- the size of the fifth data is the same as the size of the second storage area, and the fifth data includes a plurality of coding units, each of the coding units includes a part of the data in the fourth data and a second Filling the information, the size of the second padding information in the coding unit in the fifth data is calculated according to the second shortened code level and the size of the coding unit in the fifth data.
- the process of how the controller 1022 obtains the fifth data to be written into the second storage area according to the second shortened code level of the second storage area and the fourth data may participate in the steps in FIG. 2 . Description of 208.
- step 708 the controller 1022 encodes the coding information of the fifth data for each coding unit in the fifth data according to the BCH coding, where each coding unit of the fifth data
- the size is the same as the information bit length of the BCH encoding.
- the check error correction module 1023 in the controller 1022 can encode each of the fifth data with the set BCH (n, k, t) encoding.
- the specific coding mode is not changed. Therefore, in the embodiment of the present invention, the data of the coding unit according to the BCH coding is not specifically described.
- step 710 the controller 1022 writes the fifth data into the second storage area, and writes the encoded information of the fifth data into the out-of-band area of the second storage area.
- FIG. 8 is a schematic structural diagram of still another flash memory device according to an embodiment of the present invention.
- the flash memory device 800 can include a receiving module 802, an information acquiring module 804, a data processing module 806, a check error correction module 808, and a writing module 810.
- the receiving module 802 is configured to receive data to be written. In an actual application, the receiving module 802 can put the received data into a cache for caching.
- the information obtaining module 804 is configured to acquire a first shortened code level of the first storage area to be accessed, where the first shortened code level is used to indicate a ratio of shortening information in the first storage area.
- the data processing module 806 is configured to convert the first data to be written into the first storage area into second data according to the first shortened code level, wherein a size of the second data is different from the first storage
- the size of the area is the same
- the second data includes a plurality of coding units
- each of the coding units includes partial data in the first data and first padding information
- the size of the first padding information is according to the first
- the ratio of the shortened information in the storage area and the size of the coding unit are calculated.
- a verification error correction module 808, configured to encode each coding unit in the second data according to the set BCH coding to obtain coding information of the second data, where the size and location of each coding unit The information bits of the BCH code are the same length.
- the writing module 810 is configured to write the second data into the first storage area, and write the encoded information of the second data into an out-of-band area of the first storage area.
- the flash memory device 800 can also include a read module 812.
- the reading module 812 is configured to read third data stored in the first storage area and encoding information of the second data stored in an out-of-band area of the first storage area.
- the check error correction module 808 is further configured to perform check error correction on the third data according to the encoding information of the second data to obtain the second data.
- the data processing module 806 is further configured to obtain, according to the first shortened code level, the length of the coding unit in the second data, and the location information of the set padding information, in each coding unit in the second data. Address information of the data; and acquiring the first data from the second data according to address information of the data in each coding unit, wherein the padding information is not included in the first data.
- the shortened code level of the first storage area is a shortened code level of the flash block to which the first storage area belongs.
- the flash memory device 800 can also include an adjustment module 814.
- the adjusting module 814 is configured to: when the error in the third data reaches a preset threshold in the process of performing the check and error correction on the third data, the flash block to which the first target storage area belongs.
- the shortening code level is adjusted by the first shortening code level to a second shortening code level, wherein a ratio of the filling information indicated by the second shortening code level is greater than a ratio of the filling information indicated by the first shortening code level.
- the receiving module 802 is further configured to receive fourth data to be written into the second storage area, where the second storage area and the first storage area belong to the same flash block.
- the information obtaining module 804 is further configured to determine that the shortened code level of the second storage area is the second shortened code level.
- the data processing module 806 is further configured to convert the fourth data into fifth data according to the second shortened code level.
- the size of the fifth data is the same as the size of the second storage area.
- the fifth data includes a plurality of coding units, and each of the coding units includes partial data and second padding information in the fourth data.
- the size of the second padding information in the coding unit in the fifth data is calculated according to the second shortened code level and the size of the coding unit in the fifth data.
- the check error correction module 808 is further configured to encode each coding unit in the fifth data according to the BCH code to obtain coding information of the fifth data, where the fifth data is The size of each coding unit is the same as the length of the information bits of the BCH coding.
- the writing module 810 is further configured to write the fifth data into the second storage area, and write the encoded information of the fifth data into an out-of-band area of the second storage area.
- each module in the flash memory device 800 is each used to perform the various steps in the various method embodiments described above.
- the embodiment of the invention further provides a computer program product for a data access method, comprising a computer readable storage medium storing program code, the program code comprising instructions for executing the method flow described in any one of the foregoing method embodiments.
- a person skilled in the art can understand that the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a random access memory (RAM), a solid state disk (SSD), or a nonvolatile.
- a non-transitory machine readable medium that can store program code, such as a non-volatile memory.
- each component in the above embodiment may have another division manner in actual implementation.
- multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed.
- the coupling or direct coupling or communication connection of the components shown or discussed may be through some communication interface, indirect coupling or communication connection of the modules, and may include electrical, mechanical, or other forms of connection.
Landscapes
- Physics & Mathematics (AREA)
- Algebra (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
一种数据访问方法及闪存设备。所述闪存设备在存储数据时,可以缩短待编码数据中的有效信息位,并用设置的填充信息填充的方式重新构造被编码数据。之后,所述控制器根据设置的BCH编码对构造后的数据进行编码,并将编码后的数据进行存储。根据这种方式,即使采用的是纠错能力较低的ECC编码,也能够保证数据的可靠性,延长闪存设备的使用寿命。
Description
本发明涉及存储技术领域,尤其涉及一种数据访问方法及闪存设备。
近年来,闪存技术迅速发展,存储密度由单比特存储元发展到最近的多比特存储元,如6比特。并且,闪存的制造工艺由65纳米展到最近的10纳米。这些发展使得闪存的存储密度快速增加,同时也使得闪存的可靠性大大降低,闪存的可靠性因此而变差。
为了解决闪存的可靠性问题,闪存为每个闪存页配备了ECC(Error Correcting Code,纠错码)。现在主要使用的ECC编码为BCH编码和LDPC编码。其中,BCH是一种循环码,通过生成矩阵g(x)对k位信息码进行编码得到n位的编码信息,这个编码信息的冗余位长度为n-k,可以纠正t个错误。随着闪存可靠性的降低,现有技术中通常采用具有高纠错能力BCH码或LDPC码,但是具有高纠错能力BCH码或LDPC码使得硬件开销变大,编解码复杂度变高,能耗也变高。
发明内容
本申请提供了一种数据访问方法及闪存设备,能够采用纠错能力较弱的ECC编码来保证数据的可靠性。
第一方面,本申请提供一种数据访问方法。该方法由闪存设备中的控制器来执行。在所述方法中,所述控制器获取待访问的第一存储区域的第一缩短码等级,所述第一缩短码等级用于指示所述第一存储区域中缩短信息的比例。在获得所述第一存储区域中缩短信息的比例之后,所述控制器根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据。其中,所述第二数据的大小与所述第一存储区域的大小相同。所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息。所述第一填充信息的大小是根据第一存储区域中缩短信息的比例以及所述编码单元的大小
计算获得的。在获得所述第二数据之后,所述控制器根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息。其中,所述每个编码单元的大小与所述BCH编码的信息位长度相同。之后,所述控制器将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。
本申请提供的数据访问方法,为了在采用纠错能力较低的BCH编码时依然保证存储的数据的可靠性,借鉴缩短BCH码的原理缩短待编码数据中的有效信息位,并用填充(padding)的方式来构造被编码数据。由于采用了缩短码的方式,使得实际存储到闪存页中的数据位变少,并且,由于填充码信息都是预先可知的,因此使得实际存储的数据中不可纠正的错误率变低,闪存设备的可靠性得到了提高。通过这种方式,即使采用纠错能力较低的ECC编码,也能够保证数据的可靠性,延长闪存设备的使用寿命。
进一步的,由于被编码的数据中缩短的部分填充了填充信息,使得编码单元的长度和未缩短前的编码单元的长度相同,因此,对控制器中的ECC模块来说,即使可编码的信息位根据闪存设备的使用不断缩短,也依然能够保持所述控制器中的ECC模块的接口不变。从而在保证数据可靠性的基础上,降低了硬件的开销。
实际应用中,所述控制器可以根据设置的闪存块的地址与缩短码等级的对应关系获得所述第一存储区域的第一缩短码等级。其中所述第一缩短码等级为所述第一存储区域所属的闪存块的缩短码等级。
在一种可能的实现方式中,所述控制器可以根据设置的第一缩短码等级与缩短信息的比例的对应关系获得所述第一存储区域中的缩短信息的比例。
在一种可能的实现方式中,在读取数据的过程中,在所述控制器读取所述第一存储区域中存储的第三数据以及所述第一存储区域的带外区域中存储的所述第二数据的编码信息之后,所述控制器根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据。然后,所述控制器根据所述第一缩短码等级、所述第二数据中的编码单元的长度以及设置的填充信息的位置信息获得所述第二数据中每个编码单元中的数据的地址信息,并根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一
数据中不包括所述填充信息。
在又一种可能的实现方式中,所述第一存储区域的缩短码等级为所述第一存储区域所属的闪存块的缩短码等级。在所述控制器对所述第三数据进行校验纠错的过程中,当所述第三数据中的错误达到预设阈值时,所述控制器将所述第一目标存储区域所属的闪存块的缩短码等级由所述第一缩短码等级调整为第二缩短码等级。其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。通过这种方式,可以根据闪存块使用的情况调整闪存块的缩短码等级,从而进一步的缩短被编码信息中的有效数据位,以进一步提高存储的数据的可靠性。
在一种可能的实现方式中,所述第三数据中的错误达到预设阈值包括:所述第三数据中的出错位数大于设置的阈值且小于设置的BCH编码中的最大可纠错位数。
在又一种可能的实现方式中,当所述第三数据中的出错位数大于设置的阈值且小于设置的BCH编码中的最大可纠错位数时,所述控制器记录所述第一存储区域在此时的最大纠错位数。在所述第一存储区域所属的闪存块被擦除后,所述控制器将所述第一存储区域的所属的闪存块的缩短码等级由所述第一缩短码等级调整为所述第二缩短码等级。
在又一种可能的实现方式中,当所述控制器接收待写入第二存储区域的第四数据之后,所述控制器确定所述第二存储区域的缩短码等级为第二缩短码等级,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块。然后,所述控制器根据所述第二缩短码等级将所述第四数据转换为第五数据。其中,所述第五数据的大小与所述第二存储区域的大小相同。所述第五数据中包括多个编码单元,每个编码单元中包括所述第四数据中的部分数据以及第二填充信息。所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的。在所述控制器根据所述BCH编码对所述第五数据中的每个编码单元进行编码以得到所述第五数据的编码信息之后,所述控制器将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同。
第二方面,本申请提供了一种闪存设备,所述闪存设备包括控制器以及与所述控制器连接的存储介质。其中,所述存储介质用于提供多个存储区域。所述控制器用于执行上述第一方面或第一方面的任意一种可能的实现方式提供的方法。
第三方面,本申请提供了又一种闪存设备,包括用于实现上述第一方面或第一方面的任意一种可能的实现方式提供的方法的功能的虚拟模块。
第四方面,本申请提供了一种计算机程序产品,包括存储了程序代码的计算机可读存储介质,所述程序代码包括的指令用于执行前述第一方面以及第一方面的任意一种可能的实现方式中所述的方法。
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例。
图1为本发明实施例提供的一种闪存设备的结构示意图;
图2为本发明实施例提供的一种数据写入方法的流程图;
图3为本发明实施例提供的一种待写入数据的编码结构示意图;
图4为本发明实施例提供的一种待写入数据组织示意图;
图5为本发明实施例提供的一种缩短码等级与缩短信息比例的对应关系示意图;
图6为本发明实施例提供的一种数据读取方法的流程图;
图7为本发明实施例提供的又一种数据写入方法的流程图;
图8为本发明实施例提供的又一种闪存设备的结构示意图。
为了使本领域的技术人员更好地理解本发明方案,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分的实施例,而不是全部的实施例。
图1为本发明实施例提供的一种闪存设备的硬件结构图。闪存设备为基
于闪存的存储设备,例如可以为固态硬盘(Solid State Drive,SSD)。如图1所示,闪存设备100可以包括控制器102、主机接口106以及闪存阵列108。
主机接口106用于连接主机,与主机进行通信。例如,用于接收主机下发的I/O请求,或将从闪存阵列108中读出的数据返回给主机。其中,主机接口106可以包括串行高级技术附件(Serial Advanced Technology Attachment,SATA)接口、通用串行总线(Universal Serial Bus,USB)接口、光纤通道技术(Fibre Channel,FC)接口或快捷外设互联标准(Peripheral Component Interconnect Express,PCI-E)接口等。
闪存阵列108,用于存储数据。闪存阵列108可以是多个存储单元组成。在本发明实施例中,闪存阵列108又可以被称为存储介质,闪存阵列108中的存储单元是指用于存储数据的最小存储介质单元。闪存阵列108可以使用单阶存储单元(Single-level cell,SLC)或多阶存储单元(Multi-level cell,MLC),其中,每个SLC单元存储1比特的信息,每个MLC单元则可以存储1比特以上的数据。在本发明实施例中,闪存阵列108中的存储单元为多阶存储单元MLC。例如,可以包括每个存储单元存储2比特数据的MLC,还可以包括每个单元存储3比特数据的三阶存储单元(Trinary-Level Cel,TLC)。
控制器102主要包括处理器(processor)1022、缓存(cache)1024以及闪存接口(flash interface)1026。处理器1022、缓存1024、以及闪存接口1026通过通信总线完成相互间的通信。
缓存1024是位于处理器1022与内存之间的临时存储器,它的容量比内存小但是交换速度却比内存要快。缓存1024用于缓存处理器1022待写入闪存阵列108的数据或者用于缓存从闪存阵列108读取的数据。
闪存接口1026,与闪存阵列108连接,用于与闪存阵列108进行通信,控制与闪存阵列108之间的数据传输。例如,可以用于管理对处理器1022下发的对闪存阵列108的访问命令以及进行数据传输。可以理解的是,闪存接口1026中可以包括多个通信通道,用于连接闪存阵列108中不同的存储单元。
实际应用中,闪存阵列108被分为一系列128KB(kilobyte)的块(block),这些块是闪存器件中最小的可擦除实体。每个block中包括多个页(page)。闪存设备100的读操作和写操作的基本单位是页(page)。通常,一个page为4KB。
每个page还可以被划分为多个扇区(sector)。每个sector可以包括多个用于存储数据的存储单元。通常,一个sector可以为512字节。由于每一页的容量决定了一次可以传输的数据量,因此大容量的页有更好的性能。并且,采用大容量的页可以降低电路的复杂度。随着技术的发展,闪存设备100中的一个物理页可以为16KB或32KB。为了描述方便,在本发明实施例中,一个block也可以被称为一个闪存块,一个page也可以被称为一个闪存页。
由于操作系统下发的写操作请求通常以4KB为粒度。换一种表达方式,操作系统下发的操作请求中,通常以4KB为一个逻辑页。因此,实际应用中,对于具有一个页可容纳16KB或32KB的大页容量的闪存设备,每个扇区的大小可以为4KB。闪存设备在建立映射关系时通常以4KB为单位建立从逻辑地址到物理地址的映射关系。
处理器1022可以是一个中央处理器CPU,或者是特定集成电路(Application Specific Integrated Circuit,ASIC),或者是被配置成实施本发明实施例的一个或多个集成电路。在处理器1022中安装有软件程序,不同的软件程序可以视作一个处理模块,具有不同的功能。通常,处理器1022中可以包括垃圾回收模块、校验纠错模块、坏块管理模块等处理模块,从而处理器1022可以实现对闪存阵列108的访问请求,或者对闪存阵列108中的数据进行管理等等。例如,处理器1022可以通过通信总线接收主机接口106转发的输入输出I/O请求,并根据主机下发的I/O请求通过闪存接口1026访问闪存阵列108,向闪存阵列108中写入数据或者从闪存阵列108中读取数据。
本领域技术人员可以知道,为了保证数据的准确性,在闪存设备中设置有校验纠错机制。如图1所示,处理器1022中可以包括校验纠错模块1023。校验纠错模块1023主要通过纠错码(Error Correction Code,ECC)对数据进行校验和纠错。校验纠错模块1023可以在写入数据是对数据进行编码,并在读取数据时进行差错检测和修正。ECC能够通过硬件或软件实现。具体的,每个闪存页上都包括额外的存储空间,也就是带外(out of bank,OOB)区域。带外区域用于存储ECC代码或逻辑地址到物理地址的映射信息等信息。当数据写入的时候,处理器1022内部的校验纠错模块1023可以根据一个扇区中的数据生成ECC签名(也可称为ECC代码)。并将生成的ECC签名保存于该扇区所属闪存页中
的带外区域。当从一个闪存页中读取数据的时候,该闪存页的带外区域中的ECC签名也被读出,校验纠错模块1023读取ECC签名,并根据读取的数据和ECC签名判断是否出现数据错误。如果检测到读取的数据包含错误比特,就需要使用相应的ECC算法来修正检测到的错误。需要说明的是,处理器1022中还可以包括其他软件模块,由于在本发明实施例中主要对处理器中的校验纠错机制进行描述,因此图1中只图示了校验纠错模块1023。如前所述,ECC算法可以包括BCH编码或LDPC编码等。本发明实施例主要对采用BCH编码的编码方式进行描述。
本领域技术人员可以知道,BCH码是1959年由Bose、Ray-Chaudhuri及Hocquenghem发现的二元线性循环码,人们用他们的名字的缩写将该循环码命名为BCH码。BCH码能纠正多个随机错误。常见的BCH码可以包括戈雷(Golay)码、扩展BCH码以及缩短BCH码。其中,戈雷(Golay)码是一个特殊的非本原BCH码,能纠正3个错误。扩展BCH码是为了得到偶数码长,并增加检错能力,在BCH码的基础上扩展得到的。扩展BCH码相当于将BCH码再加上一位的偶校验,它不再有循环性。缩短BCH码与BCH码相比,其可纠错的位数不变,但其码长比BCH码的码长短。例如,假设BCH码为BCH(n,k,t),则该BCH码可以对k个信息位进行编码,以得到长度为n的编码,并且可以纠正t个错误。其中,k即为BCH编码的信息位长度,n也可以被称为BCH码的码长。则缩短BCH码可以对k-l个信息位进行编码,得到长度为n-l的编码,并且依然可以纠正t个错误。缩短BCH码由于纠错能力和BCH码相同,但码长较短。换一种表达方式,对于同样的数据,采用缩短BCH码的编码单元比采用BCH码的编码单元更多。因此,采用缩短BCH码使得正确解码的可能性得到了提高。研究表明,当缩短码比例增加时,闪存设备的错误率会下降,从而闪存设备中存储的数据的可靠性得到了提高。其中,缩短码比例为缩短码的长度与纠错的信息位长度的比值。例如,根据上述示例,缩短码比例可以表示为l/k,其中,l为缩短的信息位长度,k为BCH编码的信息位的长度,也可以将k称为BCH编码可纠错的信息位的长度。
图2为本发明实施例提供的一种数据写入方法的流程图。该方法可以由图1所示的闪存设备100中的控制器1022来执行,用于将数据写入闪存阵列108中。如前所述,为了保证存储的数据的准确性,控制器1022在执行写操作的过
程中,会将待写入的数据进行编码,然后再写入存储阵列108。在读取数据时,可以根据编码的信息对读取的数据进行校验纠错。其中,ECC算法可以包括BCH编码或LDPC编码等。在本发明实施例,主要对采用BCH编码的数据写入过程进行优化,使得即使采用纠错能力较低的BCH编码,依然能够保证数据的可靠性。因此在本发明实施例中,以BCH编码为例对本发明实施例提供的数据写入方法进行描述。下面将结合图1对图2中的方法进行详细描述。
在步骤202中,控制器1022接收第一访问请求,其中,所述第一访问请求中携带有待访问的地址以及待写入的数据。实际应用中,控制器1022可以通过主机接口106接收主机的操作系统下发的第一访问请求,在操作系统下发的第一访问请求中可以携带有待访问存储区域的地址信息。第一访问请求中携带的地址信息为待访问的第一存储区域的逻辑地址。实际应用中,当第一访问请求为写请求时,第一访问请求中还可以携带有待写入的数据或者待写入数据的缓存地址的信息。可以理解的是,当第一访问请求中携带有待写入数据的缓存地址信息时,控制器1022能够根据待写入数据的缓存地址信息从缓存1024中获取待写入数据。
在步骤204中,控制器1022根据所述待访问地址确定第一存储区域。本领域技术人员可以知道,由于闪存设备无法进行覆盖写,也就是说,闪存设备执行写操作时不能将数据直接覆盖闪存设备中已经存储的旧数据,必须把旧数据擦除后,才能在该存储位置写入新的数据,因此,访问请求中通常携带的是待访问存储区域的逻辑地址,并且,在闪存设备中维护有存储区域的逻辑地址和物理地址的映射关系,从而能根据待访问请求中携带的逻辑地址查找到待访问的物理地址。在本发明实施例中,在接收到第一访问请求后,控制器1022可以根据存储的逻辑地址和物理地址的映射关系将第一访问请求中的逻辑地址转换为物理地址。从而闪存设备能够根据转换获得的物理地址确定本次写操作待访问的存储区域。为了描述方便,将第一访问请求待访问的存储区域称为第一存储区域。可以理解的是,由于写操作是以page为操作单位,因此,所述第一存储区域可以是一个闪存设备100中的一个闪存页。
在步骤206中,控制器1022获得所述第一存储区域的缩短码等级。本领域技术人员可以知道,为了提高存储的数据的可靠性,可以采用纠错能力较强的BCH码。然而,实际应用中,纠错能力的提升会导致闪存设备的时延、功耗等
呈指数的增加。因此,实际应用中,采用纠错能力较强的BCH码并不是提高数据可靠性的最优解决方案。如前所述,使用缩短BCH码能够使闪存设备100中存储的数据的可靠性得到提升。因此,在本发明实施例中,采用纠错能力较低的BCH编码来降低闪存设备100的功耗,并且,配合缩短码的应用原理在保证闪存设备100低开销的同时提高数据的可靠性。
在本发明实施例中,可以为不同的block设置不同的缩短码等级。根据这种方式,能够配合使用不同程度的缩短码,保证不同block中的数据的可靠性。在本发明实施例中,同一个block中的不同页均具有相同的缩短码等级。缩短码等级用于指示闪存页中缩短信息的比例。换一种表达方式,缩短码等级用于指示闪存页中减少的数据量。例如,实际应用中可以使用缩短码等级来指示减少的扇区数量。以32KB的闪存页为例,假设每个扇区大小为4KB,则一个闪存页可以包括8个扇区。如果该闪存页所属的block的缩短码等级为1,缩短码等级为1用于指示该闪存页中缩短信息的比例为1/8,则表明该闪存页中减少的数据量为1个扇区的数据量,可用空间为7个扇区。
在本发明实施例中,由于闪存设备中闪存块的磨损程度不同,因此不同的闪存块可以有不同的缩短码等级。每个闪存块的缩短码等级信息可以以记录表的形式设置在闪存设备中。具体的,缩短码等级记录表中可以包括闪存块的位置信息以及该闪存块对应的缩短码等级。缩短码等级记录表可以存储于闪存设备的内存中,也可以存储于缓存1024中,还可以存储在闪存阵列108中。可以理解的是,实际应用中,缓存1024可以包括备电装置,当将缩短码等级记录表存储于闪存设备的缓存1024中时,该备电装置可以支持在闪存设备100掉电之前将所述缩短码等级记录表写回闪存阵列108中,以避免丢失。在本发明实施例中,不对缩短码等级记录表的具体存储位置进行限定。并且,实际应用中,闪存块的位置信息以及该闪存块对应的缩短码等级的对应关系还可以以其他形式记录在闪存设备中,在本发明实施例中不进行限定。
当控制器1022根据所述待访问地址确定第一存储区域之后,在本步骤中,控制器1022可以根据所述第一存储区域的地址以及设置的闪存块与缩短码等级的对应关系获取所述第一存储区域所属的闪存块的缩短码等级。在本发明实施例中,为了描述方便,也可以将闪存块的缩短码等级称为该闪存块中的闪存页的缩
短码等级,将控制器1022在执行第一访问请求的过程中获取的第一存储区域的缩短等级称为第一缩短码等级。
在步骤208中,控制器1022根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据。其中,所述第二数据的大小与所述第一存储区域的大小相同。所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息。所述第一填充信息的大小是根据所述第一存储区域中缩短信息的比例以及所述编码单元的大小计算获得的。
在本发明实施例中,为了提高数据的可靠性,在存储数据的过程中采用缩短信息位的方式对数据进行存储。然而,若直接采用缩短BCH码对待存储的数据进行编码,则控制器1022中的校验纠错模块1023需要根据缩短的信息位的变化调整上下层接口以对不同长度的数据进行编码,从而会增加硬件开销。为了不改变硬件接口的设计,使得即使缩短的信息位不断变化闪存设备均可以采用统一的硬件接口,并且可以只采用一个生成矩阵来对数据进行编码,在本发明实施例中,采用填充的方式来补齐缩短的信息位,使得控制器1022中的校验纠错模块1023无需感知数据信息位的变化,并且又能提升存储的数据的可靠性。换一种表达方式,本发明实施例提供的数据方法对校验纠错模块1023是透明的。
本领域技术人员可以知道,控制器1022执行写操作时是以page为粒度,BCH编码是以编码单元为操作粒度,其中,可以将一个扇区sector的数据作为一个编码单元。当然,一个编码单元可以包括多个扇区的数据或半个扇区的数据。在本发明实施例中,不对编码单元的大小进行限定。根据这种方式,一个闪存页中可以包括多个编码单元。以BCH(n,k,t)编码为例,其中,k为编码的信息位的长度,也可以称为编码单元的长度。n为编码后获得的编码信息的长度,或者也可以称为BCH码的码长。t为可纠正信息位中的错误的数量。如图3所示,图3为本发明实施例提供的一种编码单元构造方式示意图。在本发明实施例中,假设缩短的信息位长度为l,则编码的信息位长度(即被编码的数据的长度)变为k-l。为了在缩短信息位后依然能够使用设置的BCH(n,k,t)编码实现纠正t个错误的目的,在本发明实施例中,可以填充长度为l的填充信息,以使得填充信息和缩短后的数据的长度的总和依然为编码单元的长度k。通过这种方式,校验纠错模块1023依然能够按照设置的BCH(n,k,t)编码接口以及编译码器
对包含k位的编码单元进行编码,实现纠正t个错误的目的,其中,填充后的编码单元中包括k-l位数据以及l位的填充信息。在本发明实施例中,填充信息可以为“0”或“1”。且每个编码单元中的填充信息可以位于数据的前面也可以位于数据的后面。
图3对本发明实施例提出的编码单元的构造方式进行了示意。下面将结合图4对本发明实施例中获得待写入闪存阵列108的闪存页的数据进行描述。在本发明实施例中,可以先将接收的待存储数据缓存在缓存1024中,在控制器1022执行写操作的过程中,控制器1022可以从缓存1024中获取待存储到所述第一存储区域中的数据,并根据所述第一存储区域的缩短码等级对存储于所述第一存储区域中的数据进行构造。具体的,以第一存储区域为一个闪存页,一个编码单元为一个扇区为例。图4为本发明实施例提供的一种闪存页结构示意图。如图4所示,以缓存1024中缓存有待写入所述第一存储区域的缓存页402为例,缓存页中包含有4个扇区:S1、S2、S3和S4,其中,四个扇区中的数据分别为:D1、D2、D3和D4。在本发明实施例中,控制器1022在获得第一存储区域的缩短码等级后,可以计算该闪存页中每个编码单元缩短的信息位的长度。
具体的,在本发明实施例中,可以设置缩短码等级与缩短的信息位的比例的对应关系。如图5所示,以一个闪存页包括4个扇区,且编码单元为1个扇区为例。当缩短码等级为1时,缩短信息的比例为:缩短信息的长度/闪存页的长度=1/4,则说明该闪存页中缩短的信息位的长度为1个扇区的长度。依次类推,当缩短码等级为2时,缩短信息的比例为1/2(即2/4),用于指示闪存页中缩短的信息位的长度为2个扇区的长度。可以理解的是,缩短的信息的长度小于闪存页的长度。由于闪存页中包括多个编码单元,且编码单元的大小相等。因此,闪存页的缩短信息的比例也等于该闪存页中的编码单元中缩短信息的比例。根据这种方式,当控制器1022在步骤206中获得第一存储区域的缩短码等级之后,控制器1022可以通过设置的缩短码等级以及缩短信息的比例的对应关系获得第一存储区域中缩短的信息比例。在本发明实施例中,由于缩短的信息位都需要通过填充信息的方式补齐,因此,在本步骤中,控制器1022可以进一步计算获得每个编码单元中填充位信息的大小。具体的,每个编码单元中的填充信息的长度可以通过编码单元的大小乘以第一存储区域的缩短码等级对应的缩短信息比例。例
如,以所述第一存储区域为32KB,包括4个扇区,且一个编码单元为一个扇区为例。则每个编码单元的大小8KB,为若所述第一存储区域的缩短码等级为1,则可以获得第一存储区域中缩短的信息的长度为32*1/4=8KB,也就是说,第一存储区域中需要缩短一个扇区的数据。每个编码单元需要缩短:8KB*1/4=2KB的数据。根据这种方式可以获得每个编码单元中需要填充2KB的填充信息,例如,图4中的填充信息T1、T2、T3和T4的大小均为2KB。
本领域技术人员可以知道,由于闪存设备的写操作是以页为粒度,因此在缓存中数据也是以页的粒度进行组织。如图4所示,若缓存页402中的数据为32KB,共包括4个扇区:S1、S2、S3和S4。在本发明实施例中,在获得每个编码单元中填充信息的大小之后,可以将缓存402中的数据重新进行组织,组织成新的缓存页(见图4中的第一页404)。具体的如图4所示,获得的新的缓存页404中仍然包括4个扇区(即4个编码单元)。其中,第一编码单元包括缓存页402中的扇区S1中的部分数据(即D1中的6KB的数据)以及填充信息T1。第二编码单元包括缓存页402中的扇区S1中的剩余2KB数据与扇区S2中的4KB数据以及填充信息T2(大小为2KB)。依次类推,第三编码单元包括缓存页402中的扇区S2中的剩余4KB数据与扇区S3中的2KB数据以及填充信息T3(大小为2KB)。第四编码单元包括缓存页402中的扇区S3中的剩余的6KB数据以及填充信息T4(大小为2KB)。缓存页402中的扇区S4的数据,则可以和其他待写入数据重新组成新的闪存页(例如图4中的第二页406)。需要说明的是,在图5中,并没有将第二页406中的其他数据图示出来。实际应用中,填充信息可以为“0”或“1”,且填充信息可以位于编码单元的预设位置。为了实现方便,可以将填充信息设置于每个编码单元的前部或尾部(如图4所示)。
在本发明实施例中,为了描述方便,待写入第一存储区域的第一数据可以只表示缓存页402中的部分数据,例如,第一数据可以为缓存页402中的前三个扇区的数据。将重新组织后的闪存页的数据成为第二数据。例如可以将图4中的第一页404中的所有数据称为第二数据。其中,第二数据包括多个编码单元,每个编码单元中包括第一数据中的部分数据以及填充信息。本领域技术人员可以理解的是,上层操作系统下发写操作指令时是以闪存页为粒度下发给控制器1022,以便控制器1022能够在软件转换层对待写入的数据分配合理的写入点,
因此,在本发明实施例中,控制器1022可以在软件转换层对待写入的数据重新进行组织,以获得待写入物理页的数据。
在步骤210中,控制器1022根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息。其中,所述每个编码单元的长度与所述BCH编码的信息位长度相同。例如,控制器1022可以按照设置的BCH编码对第一页404中的每个编码单元进行编码,以得到各个编码单元的编码信息。以BCH(n,k,l)编码为例,所述第二数据中的每个编码单元的长度均为k。具体的,控制器1022中的校验纠错模块1023可以对第一页404中的编码单元S1、S2、S3以及S4中的信息进行编码,分别得到每个编码单元的编码信息。在本发明实施例中,为了描述方便,可以将各个编码单元的编码信息总称为第二数据的编码信息。
在步骤212中,控制器1022将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。如前所述,每个闪存页都包括用于存储ECC编码信息的带外区域,因此在本步骤中,在获得包含有第二数据的第一页404之后,控制器1022可以分别将第一页404中的所述第二数据存储于所述第一存储区域,将在步骤210中获得的第二数据的编码信息存储于所述第一存储区域的带外区域。
可以理解的是,实际应用中,在将包含填充信息的第一缓存页404中的数据写入闪存阵列108之后,可以建立缓存页402中各个扇区与闪存阵列108中的第一存储区域404中的各个扇区之间的对应关系。从而在读取数据时,能够根据建立的映射关系读取相应扇区的数据。
本发明实施例提供的应用于闪存设备中的数据写入方法,提出用填充(padding)的方式来构造被编码信息。由于采用了缩短码的方式,使得实际存储到闪存页中的数据位变少,并且由于填充码信息都是预先可知的,因此使得实际存储的数据中不可纠正的错误率变低,闪存设备的可靠性得到了提高。并且,由于被编码的数据中缩短的部分填充了填充信息,使得编码单元的长度和未缩短前的编码单元的长度相同,因此,对ECC模块来说,即使可编码的信息位根据闪存设备的使用不断缩短,也依然能够保持闪存设备中的ECC模块的接口不变。从而在保证数据可靠性的基础上,降低了硬件的开销。通过这种方式,即使采用
纠错能力较低的ECC编码,也能够保证数据的可靠性,延长闪存设备的使用寿命。
上面对本发明实施例提供的闪存设备100如何进行写操作进行了描述,下面将对闪存设备100如何进行读操作进行描述。图6为本发明实施例提供的一种数据读取方法。为了描述清楚,图6仍然以如何从第一存储区域中读取前述写操作过程中写入的数据进行描述。
在步骤602中,控制器1022读取所述第一存储区域中存储的第三数据以及所述第二数据的编码信息。本领域技术人员可以知道,当闪存设备100接收到读请求时,闪存设备100会将读请求中携带的逻辑地址转换为待访问的物理地址,从而能够确定待读取的数据所属的闪存页。在本发明实施例中不对具体如何确定待读取的数据所述的闪存页进行描述,而将对具体如何从闪存页中读取数据进行描述。由于闪存设备中读操作也是以页为操作单位,因此,在本发明实施例中,仍以待读取第一存储区域中的数据为例,且第一存储区域为闪存设备中的任意一个闪存页。在本步骤中,控制器可以根据获取的待访问的物理地址从所述第一存储区域中读取出数据。由于第一存储区域中读取的数据可能出错,因此在本发明实施例中,将读取中的数据称为第三数据。
实际应用中,控制器1022从第一存储区域中读取数据时可以读出第一存储区域存储的数据,并且,控制器1022还会从第一存储区域的带外区域读取出第一存储区域中存储的数据的编码信息。以图2所示的实施例在所述第一存储区域写入的数据为第二数据,在第一存储区域写入的所述第二数据的编码信息为例,则在本步骤中,控制器1022可以从所述第一存储区域读取数据以及从所述第一存储区域的带外区域读取第二数据的编码信息。实际应用中,控制器1022还可以将从第一存储区域读取出的数据缓存在缓存1024中。
在步骤604中,控制器1022根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据。如前所述,为了保证读取的数据的可靠性,控制器1022中的校验纠错模块1023会对从闪存页中读取出的数据进行校验纠错。在本步骤中,由于存储于第一存储区域的第二数据在存储过程中可能会发生错误,因此,为了描述清楚,将控制器1022从所述第一存储区域的数据区域读取的数据称为第三数据。在本步骤中,控制器1022中的校验纠错模块1023
可以通过第二数据的编码信息对从所述第一存储区域中读取的第三数据进行校验纠错,得到在图2的步骤212中存储的所述第二数据。具体的,在利用第二数据的校验信息对所述第三数据进行校验纠错的过程中,可以根据预设的BCH编码方式对应的译码方法对所述第三数据进行相应的校验和纠错。从而能够得到所述第二数据。本发明实施例中使用的BCH编码方式和译码方法与现有技术相同,在此不进行具体的译码过程进行详细描述。
在步骤606中,控制器1022根据所述第一缩短码等级以及所述第二数据中的编码单元的长度计算所述第二数据中每个编码单元中的数据的地址信息。在本发明实施例中,由于在数据写入过程中,写入闪存页中的数据中包括了填充信息,因此在读出数据后,需要对数据进行恢复,以去除存储的数据中的填充信息,得到正确的数据。具体的,控制器1022可以根据所述第一存储区域的缩短码等级所指示的填充信息在所述第一存储区域的比例、所述第二数据中的编码单元的长度以及设置的填充信息的填充位置确定每个扇区中的数据的首地址以及数据的大小。假设一个编码单元的长度为L,所述第一缩短码等级指示的填充信息在所述第一存储区域中的比例为r,且填充信息位于每个编码单元的尾部。则第i个编码单元的数据的首地址即为第i个编码单元的首地址。可以理解的是,若以一个扇区为一个编码单元,则第i个编码单元的首地址为第i个扇区的首地址。每个编码单元的数据的大小可以根据公式:size=(1-r)*L获得。其中,i的值不超过第一存储区域中的编码单元的数量。可以理解的是,第二数据中的每个编码单元的长度及为设置的BCH编码的信息位长度。
实际应用中,在步骤604中得到所述第二数据之后,在本步骤中,控制器1022还可以根据所述第一存储区域的缩短码等级获得每个编码单元中的填充信息的大小,进而能够根据设置的填充信息的位置以及填充信息的大小确定每个编码单元中的数据的位置,从而能够从各编码单元中读取数据。实际应用中,对编码单元中的数据位置的确定还可以有多种方法,在本发明实施例中不进行限定,只要能够根据所述第一存储区域的缩短码等级以及每个编码单元的大小计算出每个编码单元中的数据即可。
在步骤608中,控制器1022根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一数据中不包括所述填充信息。
具体的,在步骤606中获得所述第二数据中的每个编码单元中的数据的偏移量和大小后,控制器1022可以从所述第二数据中获取待读取的所述第一数据,其中所述第一数据不包括所述填充信息。
进一步的,实际应用中,在步骤604中,当所述控制器1022对根据所述第二数据的编码信息对所述第三数据进行校验纠错时,可以判断所述第三数据中的出错位数是否大于设置的阈值m,其中,m小于设置的BCH(n,k,t)编码中的最大可纠错位数t。当所述第三数据中的出错位数大于设置的阈值m且小于t时,确定所述第一存储区域当前的缩短码等级已经不够可靠,需要进一步缩短可用空间。具体的,控制器1022可以记录所述第一存储区域在此时的最大纠错位数。在所述第一存储区域所属的闪存块被擦除后,重新调整所述第一存储区域所属的闪存块的缩短码等级,根据这种方式,可以重新调整所述第一存储区域的缩短码等级。为了描述方便,以所述第一存储区域当前的缩短码等级为第一缩短码等级,调整后的缩短码等级为第二缩短码等级为例进行描述。
换一种表达方式,当所述第三数据中的出错位数大于设置的阈值且小于设置的BCH编码中的最大可纠错位数时,所述控制器记录所述第一存储区域在此时的最大纠错位数。在所述第一存储区域所属的闪存块被擦除后,所述控制器将所述第一存储区域的所属的闪存块的缩短码等级由所述第一缩短码等级调整为所述第二缩短码等级。其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。
可以理解的是,当调整了所述第一存储区域所属的闪存块的缩短码等级之后,可以根据调整后的第二缩短码等级更新设置的闪存块与缩短码等级的对应关系。根据这种方式,调整后的第一存储区域中,用于存储数据的可用空间进一步减少。编码单元中的数据信息也进一步减少,从而能够进一步提高后续存储于所述第一存储区域的数据的可靠性。
进一步的,当所述第一存储区域所述的闪存块的缩短码等级被调整后,若接收到待存储于第二存储区域的第四数据,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块,则可以按照图2所述的数据写入方法将所述第四数据写入所述第二存储区域。具体的可以包括如图7所示的下述步骤。
在步骤702中,控制器1022接收待写入所述第二存储区域的第四数据。
其中,所述第二存储区域与所述第一存储区域属于同一个闪存块。实际应用中,控制器1022也可以将所述第四数据缓存于缓存1024中。
在步骤704中,控制器1022确定所述第二存储区域的缩短码等级为所述第二缩短码等级。由于调整后的第一存储区域所属的闪存块的缩短码等级为第二等级,所述第二存储与所述第一存储区域属于同一个闪存块,因此,所述第二存储区域的缩短码等级即为所述闪存块的缩短码等级。实际应用中,控制器1022可以根据设置的闪存块与缩短码等级的对应关系查询所述第二存储区域的缩短码等级。如前所述,若在读取所述第一存储区域的过程中,所述第一存储区域中存储的第二数据的出错位数大于预设阈值,则在擦除所述第一存储区域所属的闪存块之后,控制器1022会将所述第一存储区域的缩短码等级由所述第一缩短码等级调整为所述第二缩短码等级,并且会更新闪存块与缩短码等级的对应关系。因此,在本步骤中,控制器1022通过查询更新后的闪存块与缩短码等级的对应关系,可以获得所述第二存储区域的缩短码等级为所述第二缩短码等级。
在步骤706中,控制器1022根据所述第二缩短码等级将所述第四数据转换为第五数据。其中,所述第五数据的大小与所述第二存储区域的大小相同,所述第五数据中包括多个编码单元,每个编码单元中包括所述第四数据中的部分数据以及第二填充信息,所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的。具体的,关于控制器1022如何根据所述第二存储区域的第二缩短码等级以及所述第四数据获得待写入所述第二存储区域的第五数据的过程可以参加图2中的步骤208的描述。
在步骤708中,控制器1022根据所述BCH编码对所述第五数据中的每个编码单元进行编码所述第五数据的编码信息,其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同。例如,控制器1022中的校验纠错模块1023可以用设置的BCH(n,k,t)编码对所述第五数据中的每个编码单元进行编码。在本发明实施例中,并没有对具体的编码方式进行改变,因此在本发明实施例中不对具体如何根据BCH编码对编码单元的数据进行描述。
在步骤710中,控制器1022将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。
可以理解的是,图7所示的如何将接收的第四数据写入第二存储区域的过程与图2所示的如何将第一数据写入第一存储区域的过程类似,图7中每个步骤的相关描述可以参见前述对图2的相应步骤的描述。
需要说明的是,本发明实施例中的“第一”、“第二”等表述只是用于区分不同的对象,不对本发明实施例作其它限定。
图8为本发明实施例提供的又一种闪存设备的结构示意图。如图8所示,闪存设备800可以包括接收模块802、信息获取模块804、数据处理模块806、校验纠错模块808、写入模块810。其中,接收模块802,用于接收待写入的数据。实际应用中,接收模块802可以将接收的数据放入缓存中进行缓存。
信息获取模块804,用于获取待访问的第一存储区域的第一缩短码等级,所述第一缩短码等级用于指示所述第一存储区域中缩短信息的比例。
数据处理模块806,用于根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据,其中,所述第二数据的大小与所述第一存储区域的大小相同,所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息,所述第一填充信息的大小是根据第一存储区域中缩短信息的比例以及所述编码单元的大小计算获得的。
校验纠错模块808,用于根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息,其中所述每个编码单元的大小与所述BCH编码的信息位长度相同。
写入模块810,用于将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。
所述闪存设备800还可以包括读取模块812。所述读取模块812用于读取所述第一存储区域中存储的第三数据以及所述第一存储区域的带外区域中存储的所述第二数据的编码信息。所述校验纠错模块808还可以用于根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据。所述数据处理模块806还用于根据所述第一缩短码等级、所述第二数据中的编码单元的长度以及设置的填充信息的位置信息获得所述第二数据中每个编码单元中的数据的地址信息;以及根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一数据中不包括所述填充信息。
实际应用中,所述第一存储区域的缩短码等级为所述第一存储区域所属的闪存块的缩短码等级。所述闪存设备800还可以包括调整模块814。所述调整模块814用于在对所述第三数据进行校验纠错的过程中,当所述第三数据中的错误达到预设阈值时,将所述第一目标存储区域所属的闪存块的缩短码等级由所述第一缩短码等级调整为第二缩短码等级,其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。
在又一种情形下,所述接收模块802还可以用于接收待写入第二存储区域的第四数据,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块。所述信息获取模块804还用于确定所述第二存储区域的缩短码等级为所述第二缩短码等级。
所述数据处理模块806还用于根据所述第二缩短码等级将所述第四数据转换为第五数据。其中,所述第五数据的大小与所述第二存储区域的大小相同。所述第五数据中包括多个编码单元,每个编码单元中包括所述第四数据中的部分数据以及第二填充信息。所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的。
所述校验纠错模块808还用于根据所述BCH编码对所述第五数据中的每个编码单元进行编码以得到所述第五数据的编码信息,其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同。
所述写入模块810还用于将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。
可以理解的是,闪存设备800中的各个模块分别用于执行前述各方法实施例中的各个步骤。具体对闪存设备800中各个模块的描述可以参见前述图2-图7中的方法实施例中各步骤的详细描述。
本发明实施例还提供一种数据访问方法的计算机程序产品,包括存储了程序代码的计算机可读存储介质,所述程序代码包括的指令用于执行前述任意一个方法实施例所述的方法流程。本领域普通技术人员可以理解,前述的存储介质包括:U盘、移动硬盘、磁碟、光盘、随机存储器(Random-Access Memory,RAM)、固态硬盘(Solid State Disk,SSD)或者非易失性存储器(non-volatile memory)等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
需要说明的是,本申请所提供的实施例仅仅是示意性的。例如,上述实施例中各部件的划分,实际实现时还可以有另外的划分方式。例如多个模块或组件可以结合或者可以集成到另一个设备中,或一些特征可以忽略,或不执行。另外,所显示或讨论的部件相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口、模块的间接耦合或通信连接,可以包括电性连接、机械连接或其它的连接形式。
所属领域的技术人员可以清楚地了解到,为了描述的方便和简洁,在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。在本发明实施例、权利要求以及附图中揭示的特征可以独立存在也可以组合存在。在本发明实施例中以硬件形式描述的特征可以通过软件来执行,反之亦然。在此不做限定。
Claims (13)
- 一种数据访问方法,所述方法由闪存设备中的控制器来执行,包括:获取待访问的第一存储区域的第一缩短码等级,所述第一缩短码等级用于指示所述第一存储区域中缩短信息的比例;根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据,其中,所述第二数据的大小与所述第一存储区域的大小相同,所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息,所述第一填充信息的大小是根据第一存储区域中缩短信息的比例以及所述编码单元的大小计算获得的;根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息,其中所述每个编码单元的大小与所述BCH编码的信息位长度相同;将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。
- 根据权利要求1所述的方法,其特征在于,还包括:读取所述第一存储区域中存储的第三数据以及所述第一存储区域的带外区域中存储的所述第二数据的编码信息;根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据;根据所述第一缩短码等级、所述第二数据中的编码单元的长度以及设置的填充信息的位置信息获得所述第二数据中每个编码单元中的数据的地址信息;根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一数据中不包括所述填充信息。
- 根据权利要求2所述的方法,其特征在于,所述第一存储区域的缩短码等级为所述第一存储区域所属的闪存块的缩短码等级,所述方法还包括:在对所述第三数据进行校验纠错的过程中,当所述第三数据中的错误达到预设阈值时,将所述第一目标存储区域所属的闪存块的缩短码等级由所述第一缩短 码等级调整为第二缩短码等级,其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。
- 根据权利要求3所述的方法,其特征在于,还包括:接收待写入第二存储区域的第四数据,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块;确定所述第二存储区域的缩短码等级为所述第二缩短码等级;根据所述第二缩短码等级将所述第四数据转换为第五数据,其中,所述第五数据的大小与所述第二存储区域的大小相同,所述第五数据中包括多个编码单元,每个编码单元中包括所述第四数据中的部分数据以及第二填充信息,所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的;根据所述BCH编码对所述第五数据中的每个编码单元进行编码以得到所述第五数据的编码信息,其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同;将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。
- 一种闪存设备,包括控制器以及与所述控制器连接的存储介质,其特征在于:所述存储介质用于提供多个存储区域;所述控制器用于:获取待访问的所述多个存储区域中的第一存储区域的第一缩短码等级,所述第一缩短码等级用于指示所述第一存储区域中缩短信息的比例;根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据,其中,所述第二数据的大小与所述第一存储区域的大小相同,所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息,所述第一填充信息的大小是根据第一存储区域中缩短信息的比例以及所述编码单元的大小计算获得的;根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息,其中所述每个编码单元的大小与所述BCH编码的信息位长度相同;将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。
- 根据权利要求5所述的闪存设备,其特征在于,所述控制器还用于:读取所述第一存储区域中存储的第三数据以及所述第一存储区域的带外区域中存储的所述第二数据的编码信息;根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据;根据所述第一缩短码等级、所述第二数据中的编码单元的长度以及设置的填充信息的位置信息获得所述第二数据中每个编码单元中的数据的地址信息;根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一数据中不包括所述填充信息。
- 根据权利要求5所述的闪存设备,其特征在于,所述第一存储区域的缩短码等级为所述第一存储区域所属的闪存块的缩短码等级,所述控制器还用于:在对所述第三数据进行校验纠错的过程中,当所述第三数据中的错误达到预设阈值时,将所述第一目标存储区域所属的闪存块的缩短码等级由所述第一缩短码等级调整为第二缩短码等级,其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。
- 根据权利要求7所述的闪存设备,其特征在于,所述控制器还用于:接收待写入所述多个存储区域中的第二存储区域的第四数据,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块;确定所述第二存储区域的缩短码等级为所述第二缩短码等级;根据所述第二缩短码等级将所述第四数据转换为第五数据,其中,所述第五数据的大小与所述第二存储区域的大小相同,所述第五数据中包括多个编码单元, 每个编码单元中包括所述第四数据中的部分数据以及第二填充信息,所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的;根据所述BCH编码对所述第五数据中的每个编码单元进行编码以得到所述第五数据的编码信息,其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同;将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。
- 一种闪存设备,包括:信息获取模块,用于获取待访问的第一存储区域的第一缩短码等级,所述第一缩短码等级用于指示所述第一存储区域中缩短信息的比例;数据处理模块,用于根据所述第一缩短码等级将待写入所述第一存储区域的第一数据转换为第二数据,其中,所述第二数据的大小与所述第一存储区域的大小相同,所述第二数据中包括多个编码单元,每个编码单元中包括所述第一数据中的部分数据以及第一填充信息,所述第一填充信息的大小是根据第一存储区域中缩短信息的比例以及所述编码单元的大小计算获得的;校验纠错模块,用于根据设置的BCH编码对所述第二数据中的每个编码单元进行编码以获得所述第二数据的编码信息,其中所述每个编码单元的大小与所述BCH编码的信息位长度相同;写入模块,用于将所述第二数据写入所述第一存储区域,并且将所述第二数据的编码信息写入所述第一存储区域的带外区域。
- 根据权利要求9所述的闪存设备,其特征在于,还包括:读取模块,用于读取所述第一存储区域中存储的第三数据以及所述第一存储区域的带外区域中存储的所述第二数据的编码信息;所述校验纠错模块,还用于根据所述第二数据的编码信息对所述第三数据进行校验纠错,以获得所述第二数据;所述数据处理模块,还用于根据所述第一缩短码等级、所述第二数据中的编 码单元的长度以及设置的填充信息的位置信息获得所述第二数据中每个编码单元中的数据的地址信息;以及根据所述每个编码单元中的数据的地址信息从所述第二数据获取所述第一数据,其中,所述第一数据中不包括所述填充信息。
- 根据权利要求10所述的闪存设备,其特征在于,所述第一存储区域的缩短码等级为所述第一存储区域所属的闪存块的缩短码等级,还包括:调整模块,用于在对所述第三数据进行校验纠错的过程中,当所述第三数据中的错误达到预设阈值时,将所述第一目标存储区域所属的闪存块的缩短码等级由所述第一缩短码等级调整为第二缩短码等级,其中,所述第二缩短码等级指示的填充信息的比例大于所述第一缩短码等级指示的填充信息的比例。
- 根据权利要求11所述的闪存设备,其特征在于,还包括:接收模块,用于接收待写入第二存储区域的第四数据,其中,所述第二存储区域与所述第一存储区域属于同一个闪存块;所述信息获取模块,还用于确定所述第二存储区域的缩短码等级为所述第二缩短码等级;所述数据处理模块,还用于根据所述第二缩短码等级将所述第四数据转换为第五数据,其中,所述第五数据的大小与所述第二存储区域的大小相同,所述第五数据中包括多个编码单元,每个编码单元中包括所述第四数据中的部分数据以及第二填充信息,所述第五数据中的编码单元中的第二填充信息的大小是根据所述第二缩短码等级以及所述第五数据中的编码单元的大小计算获得的;所述校验纠错模块,还用于根据所述BCH编码对所述第五数据中的每个编码单元进行编码以得到所述第五数据的编码信息,其中,所述第五数据中的每个编码单元的大小与所述BCH编码的信息位长度相同;所述写入模块,还用于将所述第五数据写入所述第二存储区域,并且,将所述第五数据的编码信息写入所述第二存储区域的带外区域。
- 一种计算机程序产品,包括存储了程序代码的计算机可读存储介质,所述程序代码包括的指令用于执行如权利要求1-4任意一项所述的方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201680091824.1A CN110383698B (zh) | 2016-12-28 | 2016-12-28 | 数据访问方法及闪存设备 |
PCT/CN2016/112629 WO2018119741A1 (zh) | 2016-12-28 | 2016-12-28 | 数据访问方法及闪存设备 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2016/112629 WO2018119741A1 (zh) | 2016-12-28 | 2016-12-28 | 数据访问方法及闪存设备 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018119741A1 true WO2018119741A1 (zh) | 2018-07-05 |
Family
ID=62707580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2016/112629 WO2018119741A1 (zh) | 2016-12-28 | 2016-12-28 | 数据访问方法及闪存设备 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN110383698B (zh) |
WO (1) | WO2018119741A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116884464A (zh) * | 2023-09-06 | 2023-10-13 | 上海芯存天下电子科技有限公司 | flash芯片的擦除方法、装置及flash芯片 |
WO2023208231A1 (zh) * | 2022-04-29 | 2023-11-02 | 华为技术有限公司 | 一种内存数据读写方法、系统以及内存控制器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101675631A (zh) * | 2007-03-12 | 2010-03-17 | 三星电子株式会社 | 使用缩短的最终码字处理无线高清晰度视频数据的系统和方法 |
CN102545914A (zh) * | 2010-12-27 | 2012-07-04 | 联芯科技有限公司 | Bch编译码方法及装置 |
CN102981924A (zh) * | 2012-11-08 | 2013-03-20 | 杭州士兰微电子股份有限公司 | 适用于动态编码的数据存储方法及装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8533550B2 (en) * | 2010-06-29 | 2013-09-10 | Intel Corporation | Method and system to improve the performance and/or reliability of a solid-state drive |
US8458568B2 (en) * | 2010-09-24 | 2013-06-04 | International Business Machines Corporation | Systems and methods for memory devices |
US8892809B2 (en) * | 2010-10-25 | 2014-11-18 | Marvell World Trade Ltd. | Data compression and encoding in a memory system |
KR101791477B1 (ko) * | 2011-10-10 | 2017-10-30 | 삼성전자주식회사 | 통신/방송 시스템에서 데이터 송수신 장치 및 방법 |
KR101730497B1 (ko) * | 2011-11-04 | 2017-04-27 | 삼성전자 주식회사 | 에러 정정 성능 신장 방법 및 이를 이용한 저장 장치 |
US20150067436A1 (en) * | 2013-09-03 | 2015-03-05 | Sandisk Technologies Inc. | Nonvolatile Memory System Compression |
CN104639919B (zh) * | 2013-11-14 | 2017-11-03 | 杭州海康威视数字技术股份有限公司 | 用于数字视频光端机系统的数据传输方法及其系统 |
WO2016140509A1 (en) * | 2015-03-02 | 2016-09-09 | Samsung Electronics Co., Ltd. | Transmitter and shortening method thereof |
-
2016
- 2016-12-28 CN CN201680091824.1A patent/CN110383698B/zh active Active
- 2016-12-28 WO PCT/CN2016/112629 patent/WO2018119741A1/zh active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101675631A (zh) * | 2007-03-12 | 2010-03-17 | 三星电子株式会社 | 使用缩短的最终码字处理无线高清晰度视频数据的系统和方法 |
CN102545914A (zh) * | 2010-12-27 | 2012-07-04 | 联芯科技有限公司 | Bch编译码方法及装置 |
CN102981924A (zh) * | 2012-11-08 | 2013-03-20 | 杭州士兰微电子股份有限公司 | 适用于动态编码的数据存储方法及装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023208231A1 (zh) * | 2022-04-29 | 2023-11-02 | 华为技术有限公司 | 一种内存数据读写方法、系统以及内存控制器 |
CN116884464A (zh) * | 2023-09-06 | 2023-10-13 | 上海芯存天下电子科技有限公司 | flash芯片的擦除方法、装置及flash芯片 |
CN116884464B (zh) * | 2023-09-06 | 2023-12-05 | 上海芯存天下电子科技有限公司 | flash芯片的擦除方法、装置及flash芯片 |
Also Published As
Publication number | Publication date |
---|---|
CN110383698B (zh) | 2022-02-11 |
CN110383698A (zh) | 2019-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10740175B2 (en) | Pool-level solid state drive error correction | |
US10901840B2 (en) | Error correction decoding with redundancy data | |
US10372534B2 (en) | Method of operating memory device using a compressed party difference, memory device using the same and memory system including the device | |
US10474527B1 (en) | Host-assisted error recovery | |
US10727867B2 (en) | Error correction decoding augmented with error tracking | |
TW201314449A (zh) | 儲存資料之系統及方法 | |
EP2666091A2 (en) | Higher-level redundancy information computation | |
US20120254694A1 (en) | Redundant storage in non-volatile memory by storing redundancy information in volatile memory | |
US11550663B2 (en) | Changing of error correction codes based on the wear of a memory sub-system | |
US11734112B2 (en) | Memory system | |
WO2021106514A1 (ja) | コントローラおよび記憶装置 | |
KR20220045343A (ko) | 데이터 처리 시스템 내 데이터 전송에서 발생한 에러를 정정하는 장치 및 방법 | |
US20230082008A1 (en) | Parity protection in non-volatile memory | |
US11169873B2 (en) | Method and system for extending lifespan and enhancing throughput in a high-density solid state drive | |
US9430375B2 (en) | Techniques for storing data in bandwidth optimized or coding rate optimized code words based on data access frequency | |
WO2018119741A1 (zh) | 数据访问方法及闪存设备 | |
US11177012B1 (en) | Fast copy through controller | |
JP7177338B2 (ja) | メモリコントローラ装置、メモリコントローラ装置を有するメモリ装置及びメモリコントロール方法 | |
TWI709850B (zh) | 資料寫入方法、記憶體控制電路單元與記憶體儲存裝置 | |
US11204834B1 (en) | Implementation of keeping data integrity in multiple dimensions | |
US11740961B1 (en) | Data recovery using dynamic segment ordering | |
US11870461B2 (en) | Failure-tolerant error correction layout for memory sub-systems | |
US20240062839A1 (en) | Performing block-level media management operations for block stripes in a memory device | |
TW202336756A (zh) | 編碼控制方法、記憶體儲存裝置及記憶體控制電路單元 | |
CN114613420A (zh) | 编码控制方法、存储器存储装置及存储器控制电路单元 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16925754 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16925754 Country of ref document: EP Kind code of ref document: A1 |