WO2020232634A1 - 柔性电子基板的制作方法及基板结构 - Google Patents

柔性电子基板的制作方法及基板结构 Download PDF

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Publication number
WO2020232634A1
WO2020232634A1 PCT/CN2019/087822 CN2019087822W WO2020232634A1 WO 2020232634 A1 WO2020232634 A1 WO 2020232634A1 CN 2019087822 W CN2019087822 W CN 2019087822W WO 2020232634 A1 WO2020232634 A1 WO 2020232634A1
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Prior art keywords
substrate
separation layer
manufacturing
tin
layer
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PCT/CN2019/087822
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English (en)
French (fr)
Inventor
赵策
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京东方科技集团股份有限公司
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Priority to US16/765,056 priority Critical patent/US11529802B2/en
Priority to CN201980000696.9A priority patent/CN110383460B/zh
Priority to PCT/CN2019/087822 priority patent/WO2020232634A1/zh
Publication of WO2020232634A1 publication Critical patent/WO2020232634A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B43/00—Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
    • B32B43/006—Delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/20—Displays, e.g. liquid crystal displays, plasma displays
    • B32B2457/206—Organic displays, e.g. OLED
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the embodiments of the present disclosure relate to a method for manufacturing a flexible electronic substrate and a substrate structure.
  • the non-display area of the display device can be bent; or for the convenience of carrying, the electronic device can also be bent.
  • the performance of flexible electronic devices is closely related to the manufacturing process technology, and how to improve the flexible electronic process technology is a concern in this field.
  • At least some embodiments of the present disclosure provide a method for manufacturing a flexible electronic substrate, including: providing a first substrate, the first substrate including a first surface and a second surface opposed to each other; on the first surface of the first substrate A separation layer is formed, and the separation layer is in the shape of a film layer; a second substrate is provided on the separation layer, and the second substrate is a flexible substrate; the separation layer is processed so that at least part of the separation layer is separated from the film Laminar cracks separate the second substrate from the first substrate.
  • the processing is physical processing.
  • the cracking of at least part of the separation layer from the membrane layer shape includes: at least part of the separation layer changes from the membrane layer shape to a powder shape.
  • the treatment includes cooling treatment.
  • the separation layer includes one or more of tin and tin alloy.
  • the temperature reduction treatment includes lowering the temperature of the separation layer to below 13.2°C.
  • the treatment includes: using a nucleating agent to contact the separation layer to crack the separation layer.
  • the nucleating agent includes one or more of gray tin, cadmium telluride, and indium antimonide.
  • the alloy elements in the tin alloy include one or more of aluminum, copper, magnesium, manganese, zinc, bismuth, lead, antimony, silver, gold, and germanium in addition to tin.
  • the mass percentage of tin element in the separation layer is not less than 30%.
  • the separation layer cracking from the film layer includes: the tin is changed from white tin to gray tin.
  • the separation layer includes a groove or a hollow structure.
  • the area percentage of the groove or hollow structure is 10%-50%.
  • the planar structure of the groove or hollow structure includes a circle, a diamond, a rectangle, a triangle, or an irregular polygon.
  • the second substrate includes opposite third and fourth surfaces, the third surface is closer to the first substrate, and the manufacturing method further includes: before processing the separation layer , Preparing a first working circuit on the fourth surface of the second substrate.
  • the manufacturing method further includes: preparing a second working circuit on the second surface of the first substrate before processing the separation layer.
  • Some embodiments of the present disclosure further provide a substrate structure, including a first substrate, a second substrate, and a separation layer.
  • the second substrate is a flexible substrate, and the separation layer is located between the first substrate and the second substrate.
  • the first substrate and the second substrate are connected, and at least a part of the separation layer is configured to be cracked from the film layer to separate the first substrate and the second substrate.
  • the separation layer includes one or more of tin and tin alloy.
  • the alloy elements in the tin alloy include one or more of aluminum, copper, magnesium, manganese, zinc, bismuth, lead, antimony, silver, gold, and germanium in addition to tin.
  • the separation layer includes a groove or a hollow structure.
  • FIG. 1 is a flowchart of a manufacturing method of a flexible electronic substrate provided by some embodiments of the disclosure
  • FIG. 2 is a schematic diagram of a substrate structure provided by some embodiments of the disclosure.
  • 3A is a schematic diagram of the separation layer provided by some embodiments of the present disclosure cracked into fragments
  • 3B is a schematic diagram of the separation layer provided by some embodiments of the disclosure cracking into powder
  • Figure 3C shows the change curve of interfacial mobility with temperature during the conversion of white tin to gray tin
  • FIG. 3D is a schematic diagram of contact between a separation layer and a nucleating agent according to an embodiment of the present disclosure
  • 4A-4B are schematic diagrams of the planar structure of the separation layer provided by some embodiments of the disclosure.
  • FIG. 5A is a schematic plan view of a flexible electronic substrate provided by some embodiments of the present disclosure, and FIG. 5B is a schematic cross-sectional view of FIG. 5A along the section line A-A';
  • FIG. 6A is a schematic plan view of a flexible electronic substrate provided by other embodiments of the present disclosure
  • FIG. 6B is a schematic cross-sectional view of FIG. 6A along the section line B-B';
  • FIG. 7 is a schematic diagram of a substrate structure provided by other embodiments of the disclosure.
  • a flexible base substrate may be prepared or adhered to the surface of a rigid carrier substrate (such as a glass substrate), and then a display device may be prepared on the flexible base substrate. After the display device is prepared, the flexible substrate and the carrier substrate are peeled off.
  • a rigid carrier substrate such as a glass substrate
  • One peeling method is to use laser irradiation to reduce the adhesion between the flexible base substrate and the carrier substrate, thereby separating the flexible base substrate from the carrier substrate.
  • the laser irradiation lift-off method requires the use of high-energy lasers for scanning, which results in low production efficiency and high cost of laser equipment.
  • high-energy laser scanning may also cause damage to the devices already prepared on the flexible substrate, thereby affecting the performance of the flexible electronic device.
  • Another peeling method is to use a chemical solution (reaction liquid) to react on the contact surface between the flexible base substrate and the carrier substrate, thereby separating the flexible base substrate from the carrier substrate.
  • reaction liquid reaction liquid
  • the chemical liquid easily corrodes the flexible substrate and the devices formed thereon, and also affects the performance of the flexible electronic device.
  • At least one embodiment of the present disclosure provides a method for manufacturing a flexible electronic substrate.
  • a layered separation layer that combines the first substrate and the second substrate is processed to make the separation The layer cracks from the film layer, thereby separating the second substrate from the first substrate.
  • the manufacturing method can reduce damage to the second substrate, the first substrate and the working circuit formed thereon.
  • FIG. 1 shows a flowchart of a method for manufacturing a flexible electronic substrate provided by some embodiments of the present disclosure
  • FIG. 2 shows a schematic diagram of a substrate structure provided by some embodiments of the present disclosure.
  • the manufacturing method of the flexible electronic substrate provided by the embodiment of the present disclosure will be exemplarily described below with reference to FIGS. 1 and 2. As shown in Figure 1, the manufacturing method at least includes steps S101-S104.
  • Step S101 Provide a first substrate 100.
  • the first substrate 100 includes a first surface 121 and a second surface 122 opposite to each other.
  • the first substrate 100 may be a rigid substrate, such as a glass substrate, a plastic substrate, a stainless steel substrate, etc.
  • the first substrate 100 can provide stable support for the subsequent preparation of the working circuit on the second substrate.
  • Step S102 forming a separation layer 110 on the first surface 121 of the first substrate 100, and the separation layer 110 is a film layer.
  • the separation layer 110 uniformly covers the first surface 121 of the first substrate 100 and is a continuous film layer.
  • the thickness of the separation layer 110 ranges from 10 nm to 10 ⁇ m, such as 50 nm to 500 nm, such as 150 nm.
  • the separation layer 110 may be formed on the first surface 121 of the first substrate 100 through a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the separation layer 110 includes tin or tin alloy.
  • the alloying elements in the tin alloy include one or more of aluminum, copper, magnesium, manganese, zinc, bismuth, lead, antimony, silver, gold, and germanium in addition to tin.
  • the mass percentage of tin element in the separation layer 110 is not less than 30%, for example, 50%-100%.
  • Step S103 providing a second substrate 130 on the separation layer 110.
  • the second substrate 130 is a flexible substrate and includes a third surface 131 and a fourth surface 132 opposite to each other.
  • the third surface 131 is closer to the first substrate 100.
  • the material of the second substrate 130 is, for example, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (polyether sulfone). , PES), polycarbonate (PC) or polyimide (PI) and its derivatives, etc., according to the application, have appropriate flexibility, so that it can be bent or folded as needed.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PC polycarbonate
  • PI polyimide
  • the second substrate 130 can be adhered to the surface of the separation layer 110 through the adhesive layer 120, thereby being combined with the first substrate 100 to obtain the support of the first substrate 100 .
  • the material of the adhesive layer 120 is acrylic or epoxy.
  • the second substrate 130 may be directly formed on the separation layer 110.
  • the second substrate 130 may be directly formed on the separation layer 110 through processes such as spin coating, curing, etc., thereby being combined with the first substrate 100 to obtain the support of the first substrate 100.
  • the embodiment of the present disclosure does not limit the manner of providing the second substrate 130 on the separation layer 110.
  • Step S104 processing the separation layer 110 so that at least part of the separation layer 110 is cracked from the film layer shape, and the second substrate 130 is separated from the first substrate 100.
  • the treatment is a physical treatment, that is, the separation layer 110 is cracked from the film layer by physical means.
  • the lift-off layer is burned by a high-energy laser and decomposed into a gas or a chemical reaction liquid. It decomposes by reaction, which avoids damage to the second substrate 130 and the device structure (such as the first working circuit 140 below) caused by the stimulation caused by the chemical reaction used in the chemical treatment.
  • the physical treatment is cooling treatment, heating treatment, or light treatment.
  • FIG. 3A shows a schematic diagram of cracking of the separation layer 110.
  • the layered separation layer 110 is cracked to form a plurality of block fragments.
  • the average size (average side length) of the block fragments is several hundred nanometers to several micrometers, for example, 500 nm-5 ⁇ m.
  • the separation layer 110 is cracked from a film layer to a powder, for example, the average particle size of the powder is in the range of 10 nm to 500 nm.
  • the separation layer 110 includes one or more of tin and tin alloy, and the separation layer may be subjected to a cooling treatment to cause the separation layer 110 to crack.
  • Tin is a metal with an allotrope. Tin has a stable body-centered tetragonal crystal structure at 13.2-161°C, white, with a density of 7.28g/cm3, and is called “white tin” (also called ⁇ -Sn); when the temperature drops below 13.2°C, tin will It transforms from a body-centered tetragonal crystal structure to a diamond cubic structure with a density of 5.75g/cm3 and is called “gray tin” (also called ⁇ -Sn).
  • the lattice structure of gray tin is similar to that of silicon, so it has semiconductor characteristics and intrinsic brittleness. In the process of converting white tin to gray tin, there is a volume expansion of 26%-27%, which causes the tin film to crack after the conversion and can be completely crushed (as shown in FIG. 3B).
  • the separation layer 110 includes a tin film.
  • the first substrate 100 carrying the second substrate 130 is placed at 13.2°C In the following environment (such as an operation cabinet with refrigeration function), that is, when the separation layer 110 is cooled to below 13.2°C, the tin film cracks and becomes powdery due to the allotropic transformation of white tin to gray tin.
  • the second substrate 130 is separated from the first substrate 100.
  • This method is not only simple in operation and low in cost, but also does not cause damage to the second substrate 130 and the device structure thereon.
  • the difference in Gibbs free energy between the ⁇ phase of tin (corresponding to white tin) and the ⁇ phase (corresponding to gray tin) increases as the temperature decreases, so that the driving force for the ⁇ phase to transform into the ⁇ phase also increases;
  • the lower temperature also reduces the thermal energy of the atoms in the crystal lattice, reducing the power, making it less likely that the required atoms pass through the adjacent interface.
  • Figure 3C shows the change curve of the interface mobility with temperature during the conversion of white tin to gray tin.
  • the peak velocity is about -2.5°C
  • the interface mobility decreases rapidly as the temperature decreases.
  • the first substrate 100 carrying the flexible electronic device may be placed at a low temperature (such as -40°C) to form an ⁇ -Sn phase nucleation in the separation layer 110, and then the first substrate 100 Placing at an appropriate temperature (for example, -2.5° C.) makes the ⁇ -Sn phase crystal grains have a faster growth rate, so that the separation layer 110 cracks from the film layer to the powder shape more quickly.
  • gray tin transformation has spreading characteristics.
  • nucleating agents such as gray tin
  • it will accelerate the transformation of white tin to gray tin.
  • the above-mentioned tin-containing separation layer 110 may be subjected to low-temperature treatment and at the same time, a nucleating agent is used to contact the separation layer 110 to accelerate the conversion of white tin to gray tin.
  • the nucleating agent includes one or more of gray tin, cadmium telluride (CdTe), and indium antimonide (InSb).
  • a groove or a hollow structure 112 is formed on the separation layer 110, and then a nucleating agent 113 is filled in the groove or the hollow structure to separate the nucleating agent from The tin in layer 110 contacts.
  • the groove or hollow structure 112 is formed by performing a patterning process (such as photolithography) on the separation layer 110.
  • the area percentage of the groove or hollow structure 112 in the separation layer is 10%-50%. If the percentage is too large, it will affect the adhesion stability of the second substrate 130. If the percentage is too small, it will not be possible to form a sufficient contact area between the nucleating agent 113 and the separation layer 110.
  • the nucleating agent 113 is one or more of gray tin powder, cadmium telluride powder, and indium antimonide powder.
  • the surface of the nucleating agent 113 is approximately flush with the surface of the separation layer 110 or lower than the surface of the separation layer 110.
  • a second substrate 130 is provided on the separation layer 110 and subsequent processes are performed. In the subsequent cooling treatment, this setting can accelerate the allotropic transformation of tin. Since the ambient temperature does not reach the transformation temperature of tin in the subsequent process, the setting of the nucleating agent 113 does not affect the stability of the separation layer 110, nor does it adversely affect the subsequent process.
  • a region (such as the peripheral region) where no devices are formed on the second substrate 130 may be punched to expose at least part of the separation layer 110, and then the hole
  • the above-mentioned nucleating agent is arranged to make the nucleating agent contact the tin in the separation layer 110, thereby accelerating the conversion of white tin to gray tin.
  • a laser can be used to perforate the second substrate 130. Since the perforated area can be selected as an area where no device is formed, the performance of the device structure on the second substrate 130 will not be affected.
  • the separation layer 110 may also include a tin alloy.
  • the alloying elements in the tin alloy include one or more of aluminum, copper, magnesium, manganese, zinc, bismuth, lead, antimony, silver, gold, and germanium in addition to tin.
  • the alloying elements in the separation layer 110 include one or more of aluminum, copper, magnesium, manganese, and zinc in addition to tin to accelerate the transformation of white tin to gray tin.
  • the separation layer 110 includes tin aluminum alloy, tin One or more of copper alloy, tin-magnesium alloy, tin-manganese alloy, and tin-zinc alloy.
  • the mass percentage of tin element in the separation layer 110 is not less than 30%, for example, 50%-100%.
  • the separation layer 110 includes a plurality of grooves or hollow structures.
  • the groove or hollow structure can create space for the deformation (expansion) of the tin in the direction parallel to the surface of the first substrate 100, reducing the amount of deformation in the direction perpendicular to the first substrate 100, thereby reducing the effect of the deformation on the subsequent provision.
  • the maximum depth of the groove or hollow structure (the direction perpendicular to the first substrate 100) can be selected according to the thickness of the separation layer itself, for example, it can be 50% to 100% of the thickness of the separation layer, that is, the separation layer is very thin.
  • the groove has a hollow structure, for example, the maximum depth of the groove or hollow structure is less than 1 micron. This arrangement prevents the unevenness of the contact interface between the second substrate 130 and the separation layer 110 caused by the arrangement of the groove or the hollow structure from adversely affecting the subsequent preparation of the device structure.
  • planar structure of the groove or hollow structure 111 includes a circle, a diamond, a rectangle, a triangle, or an irregular polygon.
  • a plurality of grooves or hollow structures 111 are evenly distributed in the separation layer 110.
  • the separation layer 110 has a mesh shape, that is, includes a plurality of hollow structures 111 distributed in an array.
  • the area percentage of the groove or hollow structure in the separation layer is 10%-50%. If the percentage is too large, it will affect the adhesion stability of the second substrate 130, and if the percentage is too small, it will not create sufficient deformation space.
  • the groove or hollow structure may be formed by performing a patterning process on the separation layer 110, for example, the patterning process includes a conventional photolithography process.
  • the manufacturing method of the flexible electrode substrate may further include: preparing the first working circuit 140 on the fourth surface 132 of the second substrate 130 before processing the separation layer 110 (step S104).
  • the first working circuit 140 may include a display circuit or a touch circuit, so as to form a flexible electronic substrate with a display function or a touch function.
  • the first working circuit 140 may include a display circuit and a touch circuit at the same time, and the display circuit and the touch circuit are on different layers relative to the second substrate 130, for example, may be at least partially overlapped.
  • the touch circuit may be of various types, for example, a resistive touch circuit or a capacitive touch circuit, and the capacitive touch circuit may be a self-capacitive touch circuit or a mutual capacitive touch circuit.
  • the first working circuit 140 may include a thin film transistor array, a gate driving circuit, a data driving circuit, etc.; for example, in a case where the first working circuit 140 includes a touch circuit Below, the first working circuit 140 may include a scan driving circuit, a sensing circuit, a touch electrode, and so on.
  • FIG. 5A is a schematic plan view of a flexible electronic device provided by some embodiments of the present disclosure
  • FIG. 5B is a cross-sectional view of FIG. 5A along the section line A-A'.
  • the first working circuit 140 includes a plurality of pixel units 20 and a plurality of gate lines 71 and a plurality of data lines 61 arranged in an array on a second substrate 130.
  • the plurality of gate lines 71 and the data lines 61 cross each other to define a plurality of pixel regions, and the plurality of pixel units 20 are distributed in the plurality of pixel regions in a one-to-one correspondence.
  • Each pixel unit 20 includes an organic light emitting diode and a pixel circuit that drives the organic light emitting diode to emit light.
  • the pixel circuit for example, It may include multiple thin film transistors, such as driving transistors and switching transistors.
  • the first working circuit 140 may further include a data driving circuit 6 and a gate driving circuit 7.
  • the data driving circuit 6 is used to provide data signals for the pixel unit 20; the gate driving circuit 7 is used to provide Scan signal;
  • the flexible substrate may also include other circuits or devices to further provide other various control signals.
  • the data driving circuit and the gate driving circuit are respectively connected to the pixel unit 20 through the data line 61 and the gate line 71, and each pixel unit 20 is connected to the gate line 71, the data line 61, etc., to receive corresponding electrical signals to emit light, Realize display operation.
  • the manufacturing method of the first working circuit 140 will be exemplarily described below with reference to FIG. 5B.
  • the organic light emitting diode 104 in the pixel unit 20 and the thin film transistor 102 directly connected to the organic light emitting diode 104 are shown in FIG. 5B.
  • the thin film transistor 102 may be a driving transistor configured to work in a saturated state and control the magnitude of the current for driving the organic light emitting diode 104 to emit light.
  • the thin film transistor 102 may also be a light emitting control transistor, which is used to control whether the current for driving the organic light emitting diode 104 to emit light flows. The embodiment of the present disclosure does not limit this.
  • a buffer layer 101 is first formed on the second substrate 130, and the buffer layer is used to improve the surface flatness of the second substrate, and can also prevent impurities (such as metal ions) in the second substrate 130 from diffusing to
  • the first working circuit affects the performance of the device. For example, water vapor can also be prevented from entering the first working circuit 140 through the second substrate 130 to cause corrosion.
  • the buffer layer 101 may include a single layer of insulating material or multiple layers of insulating material.
  • the insulating material is an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide.
  • the buffer layer 101 may be formed on the second substrate 130 by chemical vapor electrode (CVD).
  • CVD chemical vapor electrode
  • the thickness of the buffer layer is 200-400 nanometers, for example, 250-300 nanometers.
  • a pixel array including a plurality of thin film transistors is formed on the buffer layer 101.
  • the thin film transistor 102 is formed as an example.
  • the manufacturing process includes, for example, forming the active layer 121 of the thin film transistor 102 and the gate insulating layer.
  • the material of the active layer 121 may be amorphous silicon, polysilicon, metal oxide semiconductor material, etc.
  • the metal oxide semiconductor material may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), aluminum oxide.
  • the active layer 121 may be a single layer structure or a multilayer structure.
  • the material of the gate insulating layer 122 and the interlayer insulating layer 124 may include inorganic insulating materials such as silicon nitride, silicon oxynitride, and aluminum oxide, or organic insulating materials such as acrylic acid and polymethylmethacrylate (PMMA).
  • the gate insulating layer may have a single-layer structure or a multilayer structure.
  • the material of the gate electrode 123 and the source and drain electrode layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), Hafnium (Hf), thallium (Ta), chromium (Cr) or alloy materials of the above metals.
  • an insulating layer can be formed by a chemical vapor deposition process
  • an organic insulating layer can be formed by a spin coating or inkjet printing process
  • a conductive layer and a semiconductor layer can be formed by a sputtering process
  • a patterning process for the material layer can be realized by a photolithography process, etc. .
  • a planarization layer 103 and a first electrode 141 are formed on the source and drain electrode layer.
  • the first electrode 141 is connected to the drain 126 of the thin film transistor through a via hole penetrating the planarization layer 103.
  • the planarization layer may be an organic insulating material (such as acrylic material) or an inorganic insulating material (such as silicon oxide or nitride) or a laminated structure of an organic insulating material and an inorganic insulating material.
  • the planarization layer may include a single-layer material structure or a multilayer material structure.
  • the first electrode 141 is the anode of the organic light emitting diode 104, and may be a metal, a conductive metal oxide (such as ITO, AZO), or a laminated structure of a metal and a conductive metal oxide, for example.
  • a metal such as ITO, AZO
  • a conductive metal oxide such as ITO, AZO
  • laminated structure of a metal and a conductive metal oxide for example.
  • the source and drain of the thin film transistor are physically symmetrical, the source and drain of the thin film transistor can be interchanged as needed when used for electrical connection.
  • a pixel defining layer 105 is formed on the first electrode 141, and an opening is formed on the pixel defining layer 105 through a patterning process to define a light-emitting area, and the opening exposes at least part of the first electrode 141.
  • the pixel defining layer is formed of organic materials, such as polyimide (PI), or other organic resins.
  • the process of forming the pixel defining layer includes, for example, coating a PI solution and curing the PI solution to form a PI layer, and then performing a patterning process on the PI layer to form the pixel defining layer.
  • an organic light emitting layer 142 and a second electrode 143 are sequentially formed corresponding to the openings on the pixel defining layer 105, thereby forming the organic light emitting diode 104.
  • the organic light emitting layer and the second electrode are formed by an evaporation process.
  • the organic light emitting layer 142 may be a polymer light emitting material or a small molecule light emitting material.
  • the light-emitting element 104 has a top emission structure
  • the first electrode 141 has reflectivity
  • the second electrode 143 has transmissive or semi-transmissive properties.
  • the first electrode 141 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminated structure
  • the second electrode 143 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • a thin film encapsulation layer may also be formed on the second electrode 143 to encapsulate the organic light emitting diode, so as to prevent external moisture and oxygen from penetrating and causing damage to the device.
  • the thin film encapsulation layer includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked.
  • a water absorbing layer (not shown) can also be formed between the thin film encapsulation layer and the organic light emitting diode, and is configured to absorb residual water vapor or sol in the pre-production process of the organic light emitting diode.
  • the first working circuit 140 may also include a touch circuit.
  • Fig. 6A shows a schematic plan view of a flexible electronic device provided by other embodiments of the present disclosure
  • Fig. 6B is a cross-sectional view of Fig. 6A along the section line B-B'.
  • the method for preparing the first working circuit 140 provided by other embodiments of the present disclosure will be exemplarily described below in conjunction with FIGS. 6A-6B.
  • the first working circuit 140 includes a touch circuit formed on the second substrate 130.
  • the touch circuit includes a plurality of first touch electrodes 16 extending along the first direction D1 and along the second direction.
  • a plurality of second touch electrodes 17 extending from D2.
  • the first direction D1 and the second direction D2 cross each other, for example, are orthogonal.
  • the first touch electrode 16 includes a first touch electrode portion 160 and a first connection line 161 that are alternately connected
  • the second touch electrode 17 includes a second touch electrode portion 170 and a second connection line 171 that are alternately connected.
  • the first connection line 161 and the second connection line 171 overlap each other in a direction perpendicular to the surface of the first substrate 100.
  • the first touch electrode 16 and the second touch electrode 17 form a mutual capacitance with each other, one of which is a driving electrode and the other is a sensing electrode.
  • the touch electrode as the touch driving electrode is applied with a driving signal.
  • the touch electrode as the touch sensing electrode senses the change in capacitance value and outputs the corresponding electrical signal, so that it can detect the input signal such as touch or gesture to realize touch sensing Features.
  • the manufacturing method of the first working circuit 140 will be exemplarily described below in conjunction with FIG. 6B.
  • a hard coating (or planarization layer) 181 may be formed on the fourth surface 132 of the second substrate 130 first, and the hard coating 181 may be touch-sensitive on the second substrate 130.
  • the formation of the circuit provides a flat interface.
  • the hardened layer 181 may be formed by forming an organic material layer on the fourth surface 132 and then curing the organic material layer.
  • the material of the hardened layer is optical glue.
  • the organic material is at least one of polyimide (PI), acrylate, and epoxy.
  • the curing method is UV light curing.
  • an Index Margin layer 182 may be formed on the hardened layer 181.
  • the anti-imaging layer can reduce the difference in light reflectivity between the transparent electrode area and the non-transparent electrode area, so that the transparent electrode lines become lighter after etching, and the visual effect is improved.
  • the material of the anti-imaging layer 182 is, for example, a laminated structure of niobium oxide (Nb 2 O 5 ) and silicon oxide.
  • a sputtering process may be used to form the erasing layer 182.
  • a niobium target and a silicon target are respectively used and oxygen gas is passed through continuous sputtering to obtain the anti-imaging layer 182 of a composite layer structure including a niobium oxide layer and a silicon oxide layer.
  • the thickness of the niobium oxide layer and the silicon oxide layer can be adjusted by adjusting process conditions such as sputtering power, pressure, and temperature.
  • a first conductive layer is formed on the erasing layer 182 and a patterning process is performed on the first conductive layer to form a plurality of first connecting lines 161.
  • the material of the first conductive layer is aluminum, molybdenum, copper, silver and other metal materials or alloy materials.
  • the material of the first conductive layer is silver-palladium-copper alloy (APC) material.
  • the patterning process is a conventional photolithography process, including the steps of photoresist coating, exposure, development, drying, and etching.
  • each first connecting line 161 forms two first via holes 180 correspondingly.
  • the material for forming the insulating layer 183 is an organic insulating material to obtain good bending resistance so as to be compatible with the function of the flexible electronic substrate.
  • the organic insulating material is a transparent material.
  • the organic insulating material is OCA optical glue.
  • the organic insulating material may include polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and the like.
  • the material forming the insulating layer is a photosensitive material.
  • forming the insulating layer includes: forming a photosensitive material layer, exposing and developing the photosensitive material layer to form the via 180, and then drying and curing to form the insulating layer 183 .
  • a second conductive layer is formed on the insulating layer 183, and a patterning process is performed on the second conductive layer to form the first touch electrode portion 160, the second touch electrode portion 170, and the second connecting line 171 to form a first touch.
  • the first touch electrode portion 160 is correspondingly formed between every two first connection lines 161, and is electrically connected to the two first connection lines 161 through the via 180, thereby forming an A plurality of first touch electrodes 16 extending in one direction D1.
  • the second touch electrode 17 extends along the second direction D2 and includes a plurality of second touch electrode portions 170 and second connecting lines 171 that are alternately connected.
  • the first connection line 161 and the second connection line 171 overlap each other in a direction perpendicular to the first substrate 100.
  • the material of the second conductive layer is a transparent conductive material
  • the transparent conductive material includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), and indium gallium oxide.
  • Transparent conductive metal oxide materials such as zinc (IGZO).
  • a protective layer 184 can also be formed on the second conductive layer to cover the touch electrode structure.
  • the material of the protective layer 184 is transparent optical glue.
  • the first working circuit 140 may include the above-mentioned display circuit and touch circuit at the same time.
  • the touch circuit is formed on the display circuit, so that the flexible electronic substrate has both a display function and a touch function.
  • the first substrate 100 may also be a flexible substrate.
  • the first substrate 100 and the second substrate 130 support each other.
  • FIG. 7 shows a schematic diagram of a substrate structure provided by another embodiment of the present disclosure.
  • the manufacturing method of the flexible electronic substrate may further include: before step S104, preparing a second working circuit 150 on the second surface 121 of the first substrate 100.
  • the second working circuit 150 may include a display circuit and/or a touch control circuit, for example.
  • the preparation method of the second working circuit 150 for example, reference may be made to the preparation method of the first working circuit 140 described above, which will not be repeated here.
  • the embodiment of the present disclosure does not limit the order in which the first working circuit 140 and the second working circuit 150 are formed.
  • the manufacturing method may further include cleaning the second substrate 130 to remove residues of the separation layer 110 and/or the adhesive layer 120 remaining on the third surface 131 of the second substrate 130.
  • the substrate structure 200 includes a first substrate 100, a second substrate 130 and a separation layer 110. At least one of the first substrate 100 and the second substrate 130 is a flexible substrate, for example, the first substrate 100 is a supporting substrate, and the second substrate 130 is a flexible substrate.
  • the separation layer 110 is located between the first substrate 100 and the second substrate 130 and connects the first substrate 100 and the second substrate 130.
  • the first substrate 100 and the second substrate 130 are fixed to each other through the separation layer 110.
  • the substrate structure 200 may further include an adhesive layer 120 between the separation layer 110 and the second substrate 130, and the second substrate 130 may also be adhered to the separation layer 110 through the adhesive layer 120. The surface is thus combined with the first substrate 100.
  • At least part of the separation layer 110 is configured to be cracked from the film layer to separate the first substrate 100 and the second substrate 130 from each other.
  • the separation layer 110 is configured to be cracked from a film layer to a powder shape so that the first substrate 100 and the second substrate 130 can be separated from each other.
  • the separation layer 110 includes one or more of tin and tin alloy.
  • the alloy elements in the tin alloy include one or more of aluminum, copper, magnesium, manganese, zinc, bismuth, lead, antimony, silver, gold, and germanium in addition to tin.
  • the separation layer includes grooves or hollow structures.
  • the substrate structure 200 may further include a first working circuit 140 located on the side of the second substrate 130 away from the first substrate 100.
  • the substrate structure 200 may further include a second working circuit 150 located on the side of the first substrate 100 away from the second substrate 130.
  • the first working circuit 140 and the second working circuit 150 may respectively include a display circuit or a touch circuit.

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Abstract

一种柔性电子基板的制作方法及基板结构，该制作方法包括：提供第一基板，该第一基板包括相对的第一表面和第二表面；在该第一基板的第一表面上形成分离层，该分离层为膜层状；在该分离层上提供第二基板，该第二基板为柔性基板；对该分离层进行处理使得该分离层从膜层状开裂，从而使该第二基板与该第一基板分离。该制作方法可以降低对第一基板、第二基板及其上的器件结构的损伤。

Description

柔性电子基板的制作方法及基板结构 技术领域
本公开实施例涉及一种柔性电子基板的制作方法及基板结构。
背景技术
随着柔性电子技术的发展，具有可折叠性能的柔性电子装置逐渐受到人们的青睐。例如，为了实现显示装置的窄边框甚至无边框显示，可以对显示装置的非显示区进行弯折处理；或者为了便于携带，也可以对电子装置进行弯曲处理。柔性电子装置的性能与制备工艺技术息息相关，如何改善柔性电子工艺技术，是本领域关注的问题。
发明内容
本公开至少一些实施例提供一种柔性电子基板的制作方法，包括：提供第一基板，所述第一基板包括相对的第一表面和第二表面；在所述第一基板的第一表面上形成分离层，所述分离层为膜层状；在所述分离层上提供第二基板，所述第二基板为柔性基板；对所述分离层进行处理使得所述分离层的至少部分从膜层状开裂，从而使所述第二基板与所述第一基板分离。
在一些示例中，所述处理为物理处理。
在一些示例中，所述分离层的至少部分从膜层状开裂包括：所述分离层的至少部分从膜层状变为粉末状。
在一些示例中，所述处理包括降温处理。
在一些示例中，所述分离层包括锡和锡合金中的一种或多种。
在一些示例中，在所述处理包括降温处理的情形下，所述降温处理包括将所述分离层降温至13.2℃以下。
在一些示例中，所述处理包括：使用形核剂与所述分离层接触使得所述分离层开裂。
在一些示例中，所述形核剂包括灰锡、碲化镉、锑化铟中的一种或多种。
在一些示例中，所述锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。
在一些示例中，所述分离层中的锡元素质量百分比不低于30％。
在一些示例中，所述分离层从膜层状开裂包括：所述锡从白锡转变为灰锡。
在一些示例中，所述分离层包括凹槽或镂空结构。
在一些示例中，所述凹槽或镂空结构的面积百分比例为10％-50％。
在一些示例中，所述凹槽或镂空结构的平面结构包括圆形、菱形、矩形、三角形或不规则多边形。
在一些示例中，所述第二基板包括相对的第三表面和第四表面，所述第三表面更靠近所述第一基板，所述制作方法还包括：在对所述分离层进行处理之前，在所述第二基板的第四表面上制备第一工作电路。
在一些示例中，所述制作方法还包括：在对所述分离层进行处理之前，在所述第一基板的第二表面制备第二工作电路。
本公开一些实施例还提供一种基板结构，包括第一基板、第二基板以及分离层，所述第二基板为柔性基板，所述分离层位于所述第一基板与第二基板之间且连接所述第一基板和所述第二基板，所述分离层的至少部分配置为能从膜层状开裂以使得所述第一基板和所述第二基板分离。
在一些示例中，所述分离层包括锡和锡合金中的一种或多种。
在一些示例中，所述锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。
在一些示例中，所述分离层包括凹槽或镂空结构。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本公开一些实施例提供的柔性电子基板的制作方法的流程图；
图2为本公开一些实施例提供的基板结构的示意图；
图3A为本公开一些实施例提供的分离层开裂为碎片的示意图；
图3B为本公开一些实施例提供的分离层开裂为粉末的示意图；
图3C示出了白锡转变为灰锡过程中界面迁移率随温度的变化曲线；
图3D为本公开一实施例提供的分离层与形核剂接触的示意图；
图4A-4B为本公开一些实施例提供的分离层的平面结构示意图；
图5A为本公开一些实施例提供的柔性电子基板的平面示意图，图5B为图5A沿剖面线A-A’的剖面示意图；
图6A为本公开另一些实施例提供的柔性电子基板的平面示意图，图6B为图6A沿剖面线B-B’的剖面示意图；
图7为本公开另一些实施例提供的基板结构的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
在柔性电子装置的制备过程中，以柔性显示器为例，可以先将柔性衬底基板制备于或粘附于硬性的承载基板(例如玻璃基板)表面，再在柔性衬底基板上制备显示器件。当显示器件制备完成后，将柔性衬底基 板与承载基板剥离。
一种剥离方法是利用激光照射降低柔性衬底基板与承载基板的附着力，从而使得柔性衬底基板与承载基板分离。然而，激光照射剥离方法需要使用高能激光进行扫描，这导致生产效率较低，且激光设备的成本也很高。同时，高能激光扫描还有可能对柔性基板上已经制备的器件造成损伤，进而影响柔性电子装置的性能。
另一种剥离方法是使用药液(反应液)在柔性衬底基板与承载基板的接触面发生反应，从而使得柔性衬底基板与承载基板分离。然而，药液容易腐蚀柔性衬底基板以及其上形成的器件，也会影响柔性电子装置的性能。
本公开至少一个实施例提供一种柔性电子基板的制作方法，在该制作方法中，对第一基板与第二基板之间将二者结合在一起的膜层状的分离层进行处理使得该分离层从膜层状开裂，从而使该第二基板与该第一基板分离。该制作方法可以降低对第二基板、第一基板及其上形成的工作电路的损伤。
图1示出了本公开一些实施例提供的柔性电子基板的制作方法的流程图；图2示出了本公开一些实施例提供的基板结构的示意图。
以下结合图1和图2对本公开实施例提供的柔性电子基板的制作方法进行示例性说明。如图1所示，该制作方法至少包括步骤S101-S104。
步骤S101：提供第一基板100。
第一基板100包括相对的第一表面121和第二表面122。
例如，该第一基板100可以为刚性基板，如玻璃基板、塑料基板、不锈钢基板等。例如，第一基板100可以为后续第二基板上工作电路的制备提供稳固的支持。
步骤S102：在第一基板100的第一表面121上形成分离层110，该分离层110为膜层状。
例如，分离层110均匀地覆盖在第一基板100的第一表面121上，为连续的膜层状。
例如，该分离层110的厚度范围为10nm-10μm，例如50nm-500nm，例如150nm。
例如，可以通过物理气相淀积(PVD)或化学气相淀积(CVD)工艺，在第一基板100的第一表面121上形成分离层110。
在一些示例中，分离层110包括锡或者锡合金。例如，该锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。例如，分离层110中的锡元素质量百分比不低于30％，例如，为50％-100％。
步骤S103：在分离层110上提供第二基板130。
第二基板130为柔性基板，且包括相对的第三表面131和第四表面132，第三表面131更靠近第一基板100。
例如，该第二基板130的材料例如为聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等，可根据应用，具有适当的柔性，从而可以根据需要弯曲或折叠等。
例如，在图2所示的基板结构200中，第二基板130可以通过黏胶层120黏贴于分离层110的表面，由此与第一基板100结合在一起从而得到第一基板100的支撑。例如，该黏胶层120的材料为丙烯酸或环氧树脂。
在另一些示例中，第二基板130可以直接形成于分离层110上。例如，可以通过旋涂、固化等工艺在分离层110上直接形成第二基板130，由此与第一基板100结合在一起，从而得到第一基板100的支撑。本公开实施例对于在分离层110上提供第二基板130的方式不作限定。
步骤S104：对分离层110进行处理使得该分离层110的至少部分从膜层状发生开裂，使该第二基板130与第一基板100分离。
例如，该处理为物理处理，也即通过物理手段使得分离层110从膜层状开裂，相较于常规的激光剥离手段中剥离层被高能量激光灼烧而分解为气体、或者与化学反应液反应而分解，这避免了化学处理采用的化学反应导致的刺激对第二基板130及其上的器件结构(如后文的第一工作电路140)所造成的损伤。
例如，该物理处理为降温处理、升温处理或光照处理等。
图3A示出了分离层110发生开裂的一种示意图。如图3A所示，膜层状的分离层110开裂形成多个块状碎片，例如，该块状碎片的平均尺寸(平均边长)为几百纳米到几微米，例如为500nm-5μm。
在另一些示例中，如图3B所示，分离层110从膜层状发生开裂变为粉末状，例如该粉末的平均粒径范围为10nm-500nm。
在一些示例中，分离层110包括锡和锡合金中的一种或多种，可以对该分离层进行降温处理使得分离层110发生开裂。锡是一种具有同素异形体的金属。锡在13.2-161℃具有稳定的体心四方晶体结构，呈白色，密度为7.28g/cm3,称作“白锡”(也称β-Sn)；当温度降至13.2℃以下时，锡会从体心四方晶体结构转变为金刚石立方结构，密度为5.75g/cm3，称作“灰锡”(也称α-Sn)。灰锡的晶格结构和硅类似，因此它具有半导体特性，并具有本征脆性。在由白锡转变为灰锡的过程中，伴随有26％-27％的体积膨胀，这导致锡的薄膜在转变后发生开裂，并可以完全粉碎(如图3B所示)。
例如，分离层110包括锡薄膜，例如，在第二基板130上制备完成器件结构(例如后文中的第一工作电路140)后，将承载有第二基板130的第一基板100置于13.2℃以下的环境(例如具有制冷功能的操作柜)中，也即将分离层110降温至13.2℃以下，锡薄膜因锡发生白锡-灰锡的同素异形转变而发生开裂并变为粉末状，从而使得第二基板130与第一基板100分离。
这种方法不仅操作简单，成本较低，而且不会对第二基板130及其上的器件结构造成损伤。
例如，锡的β相(对应白锡)和α相(对应灰锡)之间的吉布斯自由能之差随着温度降低而增大，使得β相转变为α相的驱动力也变大；但是，更低的温度也使得晶格中原子的热能降低，减小了动力，使得所需原子穿过相邻界面的可能性变小。
图3C示出了白锡转变为灰锡过程中界面迁移率随温度的变化曲线。如图3C所示，峰值速率约在-2.5℃处，然后该界面迁移率随着温度的降低迅速减小。例如，在实际操作中，可以将承载有该柔性电子装置的第一基板100放置在低温(如-40℃)下以便分离层110中形成 α-Sn相形核，然后再将该第一基板100放置于适当的温度(如-2.5℃)使得α-Sn相晶粒具有较快的生长速度，从而使得分离层110更为快速地从膜层状开裂为粉末状。
例如，灰锡转变具有蔓延特性，当白锡与灰锡等形核剂接触时，会促使白锡加快向灰锡的转变。例如，可以对上述含锡的分离层110进行低温处理并同时使用形核剂与分离层110接触以加速白锡到灰锡的转变。例如，该形核剂包括灰锡、碲化镉(CdTe)、锑化铟(InSb)中的一种或多种。
例如，如图3D所示，在形成分离层110后，在分离层110上形成凹槽或镂空结构112，然后在该凹槽或镂空结构中填充形核剂113以使得该形核剂与分离层110中的锡接触。例如，通过对分离层110进行构图工艺(如光刻)形成该凹槽或镂空结构112。例如，该凹槽或镂空结构112在该分离层中所占的面积百分比例为10％-50％。该百分比例过大会影响第二基板130的附着稳定性，过小则无法使得形核剂113与分离层110之间形成足够的接触面积。
例如该形核剂113为灰锡粉末、碲化镉粉末、锑化铟粉末中的一种或多种。例如，该形核剂113的表面与分离层110的表面大致齐平或者低于分离层110的表面。然后，在分离层110上提供第二基板130并进行后续工艺。在后续降温处理中，这种设置可以加速锡的同素异形转变。由于在后续工艺中，环境温度并不达到白锡的转变温度，因此该形核剂113的设置并不影响分离层110的稳定性，也不会对后续工艺产生不利影响。
在另一些示例中，还可以在该柔性电子基板制作完成后，在第二基板130上未形成器件的区域(如周边区)打孔以暴露出分离层110的至少部分，然后在该孔中设置上述形核剂以使得该形核剂与分离层110中的锡接触，从而加速白锡到灰锡的转变。例如，可以使用激光在第二基板130上打孔。由于该打孔区域可以选择为未形成器件的区域，因此不会影响到第二基板130上的器件结构的性能。
例如，分离层110也可以包括锡合金。例如，该锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一 种或多种。
研究表明，在锡中引入少量其它金属元素可以对锡的上述同素异形转变起到促进或抑制作用，并且还会对转变温度产生影响。例如，铝、铜、镁、锰、锌等元素的引入可加速这一转变；铋、铅、锑、银、金等元素的引入可使转变减慢。
例如，分离层110中的合金元素除锡之外包括铝、铜、镁、锰、锌中的一种或多中以加速白锡到灰锡的转变，例如分离层110包括锡铝合金、锡铜合金、锡镁合金、锡锰合金、锡锌合金中的一种或多种。
例如，为了保证该同素异形转变的顺利进行，分离层110中的锡元素质量百分比不低于30％，例如为50％-100％。
在上述实施例的基础上，例如，在一些示例中，分离层110包括多个凹槽或镂空结构。该凹槽或镂空结构可以为锡的形变(膨胀)在平行于第一基板100板面的方向创造空间，降低了垂直于第一基板100方向上的形变量，从而降低了该形变对后续提供第二基板130的影响。
例如，该凹槽或镂空结构的最大深度(垂直于第一基板100的方向)可以根据分离层本身的厚度来选择，例如可以为分离层厚度的50％～100％，即，分离层很薄的情况下，凹槽得到镂空结构，例如，该凹槽或镂空结构的最大深度小于1微米。这种设置避免了由于该凹槽或镂空结构的设置造成的第二基板130与分离层110的接触界面的不平整为后续器件结构的制备带来的不利影响。
图4A和图4B示出了该分离层110的几种示例性的平面结构。例如，该凹槽或镂空结构111的平面结构包括圆形、菱形、矩形、三角形或不规则多边形。例如，多个凹槽或镂空结构111均匀分布于该分离层110中。例如，该分离层110呈网状，也即包括阵列分布的多个镂空结构111。
例如，该凹槽或镂空结构在该分离层中所占的面积百分比例为10％-50％。该百分比例过大会影响第二基板130的附着稳定性，过小则无法创造足够的形变空间。
例如，该凹槽或镂空结构可以通过对分离层110进行构图工艺形成，例如该构图工艺包括常规的光刻工艺。
在另一些示例中，该柔性电极基板的制作方法还可以包括：在对分离层110进行处理(步骤S104)之前，在第二基板130的第四表面132上制备第一工作电路140。
当第二基板130结合在第一基板100上之后，得到第一基板100支撑，由此可以在第二基板130更准确地执行电路形成工艺，例如，半导体工艺或印刷电路工艺等。例如，该第一工作电路140可以包括显示电路或触控电路，从而形成具有显示功能或触控功能的柔性电子基板。又例如，该第一工作电路140可以同时包括显示电路和触控电路，该显示电路和触控电路相对于第二基板130在不同层上，例如可以至少部分重叠设置。例如，该触控电路可以为各种类型，例如，电阻型触控电路或电容型触控电路，而电容型触控电路可以为自电容型触控电路或互电容型触控电路。
例如，在第一工作电路140包括显示电路的情形下，第一工作电路140可以包括薄膜晶体管阵列、栅极驱动电路和数据驱动电路等；例如，在第一工作电路140包括触控电路的情形下，第一工作电路140可以包括扫描驱动电路、感测电路、触控电极等。
以下结合图5A-5B以形成应用于有机发光二极管显示装置的第一工作电路为例对本公开实施例中的制备第一工作电路140的方法进行示例性说明。图5A为本公开一些实施例提供的柔性电子装置的平面示意图，图5B为图5A沿剖面线A-A’的剖视图。
如图5A所示，该第一工作电路140包括阵列排布于第二基板130上的多个像素单元20以及多条栅线71和多条数据线61，该多条栅线71和数据线61彼此交叉定义出多个像素区，多个像素单元20一一对应分布于多个像素区内，每个像素单元20包括有机发光二极管及驱动该有机发光二极管发光的像素电路，该像素电路例如可以包括多个薄膜晶体管，如驱动晶体管和开关晶体管等。
例如，该第一工作电路140还可以包括数据驱动电路6和栅极驱动电路7，该数据驱动电路6用于为像素单元20提供数据信号；该栅极驱动电路7用于为像素单元20提供扫描信号；此外，该柔性基板还可以包括其他电路或器件以进一步用于提供其他各种控制信号。该数据驱 动电路和栅极驱动电路分别通过数据线61和栅线71与像素单元20连接，每个像素单元20与栅线71、数据线61等连接，以接收相应的电信号以进行发光，实现显示操作。
以下结合图5B对该第一工作电路140的制作方法进行示例性说明。为了清楚起见，图5B中仅示出了该像素单元20中的有机发光二极管104和与该有机发光二极管104直接连接的薄膜晶体管102。
例如，该薄膜晶体管102可以是驱动晶体管，配置为工作在饱和状态下并控制驱动有机发光二极管104发光的电流的大小。例如，该薄膜晶体管也102也可以为发光控制晶体管，用于控制驱动有机发光二极管104发光的电流是否流过。本公开的实施例对此不作限制。
如图5B所示，先在第二基板130上形成缓冲层101，该缓冲层用于改善该第二基板的表面平整度，也可以防止第二基板130中的杂质(如金属离子)扩散到该第一工作电路中从而影响器件的性能，例如也可以防止水汽通过第二基板130进入到第一工作电路140中从而造成腐蚀。
例如，该缓冲层可101可以包括单层绝缘材料或多层绝缘材料，例如该绝缘材料为氮化硅、氧化硅、氮氧化硅、氧化铝等绝缘材料。
例如，可以通过化学气相电极(CVD)在第二基板130上形成该缓冲层101。例如，该缓冲层的厚度为200-400纳米，例如，为250纳米-300纳米。
接着，在缓冲层101上形成包括多个薄膜晶体管的像素阵列，如图5B所示，以形成该薄膜晶体管102为例，该制作过程例如包括形成薄膜晶体管102的有源层121、栅极绝缘层122、栅极123、层间绝缘层124、源漏电极层(包括源极125和漏极126)。
例如，该有源层121的材料可以是非晶硅、多晶硅、金属氧化物半导体材料等，例如，金属氧化物半导体材料可以为铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、氧化铝锌(AZO)、氧化铟锡锌(ITZO)、氢化铟锌氧化物(HIZO)、掺铝氧化锡锌铟(ATZIO)、掺铝氧化锡锌(ATZO)、氧化锌锡(ZTO)、掺镉氧化锡(GTO)、铟镉锡氧化物(IGTO)等。例如，该有源层121可以是单层结构或多层结构。
例如，该栅极绝缘层122和层间绝缘层124的材料可以包括氮化硅、硅氮氧化物、氧化铝等无机绝缘材料或者丙烯酸、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，该栅极绝缘层可以是单层结构也可以是多层结构。
例如，该栅极123和源漏电极层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钛(Ti)、铪(Hf)、铊(Ta)、铬(Cr)或者以上金属的合金材料。
例如，可以通过化学气相淀积工艺形成绝缘层、通过旋涂或喷墨打印工艺形成有机绝缘层、通过溅射工艺形成导电层和半导体层、以及通过光刻工艺实现对材料层的构图工艺等。这些方法此处不再赘述。
然后，在该源漏电极层上形成平坦化层103和第一电极141。该第一电极141经贯穿平坦化层103的过孔与薄膜晶体管的漏极126连接。
例如，该平坦化层可以为有机绝缘材料(如亚克力材料)或者无机绝缘材料(如硅的氧化物或者氮化物)或者有机绝缘材料与无机绝缘材料的叠层结构。例如，该平坦化层可以包括单层材料结构或者多层材料结构。
例如，该第一电极141为有机发光二极管104的阳极，例如可以为金属、导电金属氧化物(如ITO、AZO)或者金属与导电金属氧化物的叠层结构。
值得注意的是，由于薄膜晶体管的源极和漏极在物理结构上具有对称性，因此薄膜晶体管的源极和漏极在用于电连接时可以根据需要互换。
接着，在第一电极141上形成像素界定层105，并通过构图工艺在像素界定层105上形成开口从而定义发光区，该开口暴露出第一电极141的至少部分。
例如，该像素界定层为有机材料形成，例如为聚酰亚胺(Polyimide,PI)，或者其他有机树脂等。该形成像素界定层的工艺例如包括涂布PI溶液并对该PI溶液进行固化从而形成PI层，然后对该PI层进行构图工艺从而形成该像素界定层。
然后，对应该像素界定层105上的开口依次形成有机发光层142 和第二电极143，从而形成该有机发光二极管104。
例如，通过蒸镀工艺形成该有机发光层和第二电极。
例如，有机发光层142可以为高分子发光材料或小分子发光材料等。例如，发光元件104为顶发射结构，第一电极141具有反射性而第二电极143具有透射性或半透射性。例如，第一电极141为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极143为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，还可以在第二电极143上形成薄膜封装层以对有机发光二极管进行封装，从而防止外界的湿气和氧的渗透而造成对器件的损坏。例如，该薄膜封装层包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，还可以在该薄膜封装层与与有机发光二极管之间形成吸水层(未示出)，配置为吸收该有机发光二极管在前期制作工艺中残余的水汽或者溶胶。
在另一些示例中，该第一工作电路140还可以包括触控电路。图6A示出了本公开另一些实施例提供的柔性电子装置的平面示意图，图6B为图6A沿剖面线B-B’的剖视图。
以下结合图6A-图6B对本公开另一些实施例提供的制备第一工作电路140的方法进行示例性说明。
如图6A所示，该第一工作电路140包括形成于第二基板130上的触控电路，该触控电路包括沿第一方向D1延伸的多条第一触控电极16以及沿第二方向D2延伸的多条第二触控电极17。第一方向D1与第二方向D2彼此交叉，例如正交。第一触控电极16包括交替连接的第一触控电极部160和第一连接线161，第二触控电极17包括交替连接的第二触控电极部170与第二连接线171。第一连接线161与第二连接线171在垂直于第一基板100板面的方向上彼此交叠。第一触控电极16与第二触控电极17彼此形成互电容，其中之一驱动电极，另一条为感应电极，作为触控驱动电极的触控电极被施加驱动信号，当目标物体(例如手指或者触控笔)靠近或接触触摸面板时，作为触控感应电极的触控电极感测到电容值的变化并输出相应的电信号，从而能够检测到触摸或 者手势等输入信号，实现触控感应功能。
以下结合图6B对该第一工作电路140的制作方法进行示例性说明。
如图6B所示，例如，可以先在第二基板130的第四表面132上形成硬化(Hard Coating)层(或平坦化层)181，该硬化层181可以在第二基板130上为触控电路的形成提供一个平整的界面。
例如，可以通过在该第四表面132上形成有机材料层，然后对该有机材料层进行固化形成该硬化层181。例如，该硬化层的材料为光学胶。例如该有机材料例如为聚酰亚胺(PI)、丙烯酸酯和环氧树脂中的至少一种。例如，该固化方式为UV光照固化。
然后，可以在硬化层181上形成消影(Index Margin)层182。例如，该消影层可以降低透明电极区与非透明电极区的光反射率之差，使得刻蚀后透明电极线条变淡，改善视觉效果。
例如，消影层182的材料例如为氧化铌(Nb 2O 5)和氧化硅的叠层结构。例如，可以采用溅射工艺形成消影层182。例如，分别使用铌靶和硅靶并通入氧气连续溅射，而得到包括氧化铌层和氧化硅层的复合层结构的消影层182。例如，通过调节溅射的功率、压强以及温度等工艺条件来调节氧化铌层和氧化硅层的厚度。
接着，在消影层182上形成第一导电层并对该第一导电层进行构图工艺形成多条第一连接线161。例如，该第一导电层的材料和为铝、钼、铜、银等金属材料或者合金材料。例如，该第一导电层的材料为银钯铜合金(APC)材料。例如，该构图工艺为常规的光刻工艺，包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
然后，在该第一导电层上形成绝缘层183以及该绝缘层183中的过孔180，该过孔180对应第一连接线161形成并暴露第一连接线161的部分。例如，如图4B所示，每个第一连接线161对应形成两个第一过孔180。
例如，形成该绝缘层183的材料为有机绝缘材料，以获得良好的耐弯折性从而与柔性电子基板的功能相适应。例如，该有机绝缘材料为透明材料。例如，该有机绝缘材料为OCA光学胶。例如，该有机绝缘材 料可以包括聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等。
例如，形成该绝缘层的材料为光敏材料，此时形成该绝缘层包括：形成光敏材料层，并对该光敏材料层进行曝光、显影形成该过孔180，然后烘干固化形成该绝缘层183。
接着，在绝缘层183上形成第二导电层，并对该第二导电层进行构图工艺形成第一触控电极部160、第二触控电极部170及第二连接线171以形成第一触控电极16和第二触控电极17。
例如，如图6B所示，第一触控电极部160对应形成于每两个第一连接线161之间，并通过过孔180与该两个第一连接线161电连接，从而形成沿第一方向D1延伸的多条第一触控电极16。例如，第二触控电极17沿第二方向D2延伸，包括交替连接的多个第二触控电极部170和第二连接线171。第一连接线161与第二连接线171在垂直于第一基板100的方向上彼此交叠。
例如，该第二导电层的材料为透明导电材料，该透明导电材料例如包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)、氧化铟镓锌(IGZO)等透明导电金属氧化物材料。
例如，还可以在第二导电层上形成一层保护层184覆盖上述触控电极结构。例如，该保护层184的材料为透明光学胶。
在另一些示例中，该第一工作电路140可以同时包括上述显示电路和触控电路。例如，该触控电路形成于该显示电路上，从而使得该柔性电子基板同时具备显示功能和触控功能。
在另一些示例中，例如，第一基板100也可以是柔性基板，在这种情形下，第一基板100和第二基板130互为支撑。
图7示出了本公开另一实施例提供的基板结构的示意图。例如，如图7所示，该柔性电子基板的制作方法还可以包括：在步骤S104之前，在第一基板100的第二表面121上制备第二工作电路150。该第二工作电路150例如可以包括显示电路和/或触控电路。该第二工作电路150的制备方法例如可以参考上述第一工作电路140的制备方法，在此不再赘述。本公开实施例对第一工作电路140和第二工作电路150的形成顺 序不作限制。
在这种制作方法中，可以一次性处理两块柔性电子基板，因此生产能力大大提升，并且可以节约生产成本，提高产品良率和生产效率。
例如，在步骤S104之后，该制作方法还可以包括对第二基板130进行清洗，以除去第二基板130的第三表面131上残留的分离层110和/或黏胶层120的残渣。
本公开实施例还提供一种基板结构，如图2所示，该基板结构200包括第一基板100、第二基板130以及分离层110。第一基板100和第二基板130中至少之一为柔性基板，例如，第一基板100为支撑基板，第二基板130为柔性基板。
该分离层110位于第一基板100与第二基板130之间且连接第一基板100和第二基板130。例如，第一基板100与第二基板130通过分离层110彼此固定。例如，如图2所示，该基板结构200还可以包括位于分离层110与第二基板130之间的黏胶层120，第二基板130也可以通过黏胶层120黏贴于分离层110的表面，由此与第一基板100结合在一起。
分离层110的至少部分配置为能从膜层状开裂以使得第一基板100和第二基板130彼此分离。
例如，分离层110的至少部分配置为能从膜层状开裂为粉末状从而能够使得第一基板100和第二基板130彼此分离。
在一些示例中，分离层110包括锡和锡合金中的一种或多种。例如，所述锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。
例如，分离层包括凹槽或镂空结构。
例如，如图2所示，该基板结构200还可以包括位于第二基板130远离第一基板100一侧的第一工作电路140。
在另一些示例中，如图7所示，该基板结构200还可以包括位于第一基板100远离第二基板130一侧的第二工作电路150。
例如，第一工作电路140和第二工作电路150可以分别包括显示电路或触控电路。
关于基板结构200的其它描述，可以参照上文关于图2和图7的相关描述，此处不再赘述。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种柔性电子基板的制作方法，包括：
    提供第一基板，所述第一基板包括相对的第一表面和第二表面；
    在所述第一基板的第一表面上形成分离层，所述分离层为膜层状；
    在所述分离层上提供第二基板，所述第二基板为柔性基板；
    对所述分离层进行处理使得所述分离层的至少部分从膜层状开裂，从而使所述第二基板与所述第一基板分离。
  2. 如权利要求1所述的制作方法，其中，所述处理为物理处理。
  3. 如权利要求1或2所述的制作方法，其中，所述分离层的至少部分从膜层状开裂包括：
    所述分离层的至少部分从膜层状变为粉末状。
  4. 如权利要求1-3任一所述的制作方法，其中，所述处理包括降温处理。
  5. 如权利要求1-4任一所述的制作方法，其中，所述分离层包括锡和锡合金中的一种或多种。
  6. 如权利要求5所述的制作方法，其中，在所述处理包括降温处理的情形下，所述降温处理包括将所述分离层降温至13.2℃以下。
  7. 如权利要求5所述的制作方法，其中，所述处理包括：使用形核剂与所述分离层接触使得所述分离层开裂。
  8. 如权利要求7所述的制作方法，其中，所述形核剂包括灰锡、碲化镉、锑化铟中的一种或多种。
  9. 如权利要求5-8任一所述的制作方法，其中，所述锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。
  10. 如权利要求9所述的制作方法，其中，所述分离层中的锡元素质量百分比不低于30％。
  11. 如权利要求5-10任一所述的制作方法，其中，所述分离层从膜层状开裂包括：
    所述锡从白锡转变为灰锡。
  12. 如权利要求1-11任一所述的制作方法，其中，所述分离层包括凹槽或镂空结构。
  13. 如权利要求12所述的制作方法，其中，所述凹槽或镂空结构的面积百分比例为10％-50％。
  14. 如权利要求12或13所述的制作方法，其中，所述凹槽或镂空结构的平面结构包括圆形、菱形、矩形、三角形或不规则多边形。
  15. 如权利要求1-14任一所述的制作方法，其中，所述第二基板包括相对的第三表面和第四表面，所述第三表面更靠近所述第一基板，
    所述制作方法还包括：在对所述分离层进行处理之前，在所述第二基板的第四表面上制备第一工作电路。
  16. 如权利要求15所述的制作方法，还包括：在对所述分离层进行处理之前，在所述第一基板的第二表面制备第二工作电路。
  17. 一种基板结构，包括第一基板、第二基板以及分离层，
    其中，所述第二基板为柔性基板，所述分离层位于所述第一基板与第二基板之间且连接所述第一基板和所述第二基板，
    所述分离层的至少部分配置为能从膜层状开裂以使得所述第一基板和所述第二基板分离。
  18. 如权利要求17所述的基板结构，其中，所述分离层包括锡和锡合金中的一种或多种。
  19. 如权利要求18所述的基板结构，其中，所述锡合金中的合金元素除锡之外包括铝、铜、镁、锰、锌、铋、铅、锑、银、金、锗中的一种或多种。
  20. 如权利要求17-19任一所述的基板结构，其中，所述分离层包括凹槽或镂空结构。
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