WO2020232595A1 - 像素单路及其驱动方法、像素单元和显示装置 - Google Patents

像素单路及其驱动方法、像素单元和显示装置 Download PDF

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Publication number
WO2020232595A1
WO2020232595A1 PCT/CN2019/087592 CN2019087592W WO2020232595A1 WO 2020232595 A1 WO2020232595 A1 WO 2020232595A1 CN 2019087592 W CN2019087592 W CN 2019087592W WO 2020232595 A1 WO2020232595 A1 WO 2020232595A1
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Prior art keywords
node
transistor
electrically connected
response
switch circuit
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PCT/CN2019/087592
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English (en)
French (fr)
Inventor
刘英明
王海生
丁小梁
王雷
王鹏鹏
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/087592 priority Critical patent/WO2020232595A1/zh
Priority to CN201980000680.8A priority patent/CN110326038B/zh
Publication of WO2020232595A1 publication Critical patent/WO2020232595A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a pixel circuit and a driving method thereof, a pixel unit and a display device.
  • the frame of the display device is becoming narrower and narrower.
  • the fingerprint recognition function in the display device is usually set in the non-display area surrounding the display area, resulting in a larger area of the frame area.
  • a pixel circuit including: a light-emitting element including an anode electrically connected to a first node and a cathode electrically connected to a first voltage terminal; a first transistor, the first transistor The control terminal of the first transistor is electrically connected to the second node, the first terminal of the first transistor is electrically connected to the second voltage terminal, and the second terminal of the first transistor is electrically connected to the first node; an acoustic fingerprint identification element, It includes a driving electrode and a sensing electrode electrically connected to the second node; a capacitor, the first end of the capacitor is electrically connected to the second node, and the second end of the capacitor is electrically connected to the third node; first The switch circuit is electrically connected to the data line and the third node, and is configured to transmit the voltage from the data line to the third node in response to the first scan signal; the second switch circuit is connected to the first A node is electrically connected to the second node, and
  • the third switch circuit includes a second transistor, a control terminal of the second transistor is configured to receive the third scan signal, and a first terminal of the second transistor is connected to the first transistor.
  • the node is electrically connected, and the second terminal of the first transistor is electrically connected to the output terminal.
  • the pixel circuit further includes: a first control circuit, electrically connected to the anode of the light-emitting element and the first node, and configured to be turned on or off in response to a first control signal.
  • the pixel circuit further includes: a second control circuit, electrically connected to the second voltage terminal and the third node, and configured to change the voltage of the second voltage terminal in response to a second control signal The potential is transferred to the third node.
  • the pixel circuit further includes a reset circuit configured to reset the potential of the second node to an initial potential in response to a reset signal.
  • the second switch circuit includes a third transistor, the control terminal of the third transistor is configured to receive the second scan signal, and the first terminal of the third transistor is connected to the second transistor.
  • the node is electrically connected, and the second end of the third transistor is electrically connected to the first node.
  • the first switch circuit includes a fourth transistor, the control terminal of the fourth transistor is configured to receive the first scan signal, and the first terminal of the fourth transistor is connected to the third transistor.
  • the node is electrically connected, and the second end of the fourth transistor is electrically connected to the data line.
  • the first control circuit includes a fifth transistor, the control terminal of the fifth transistor is configured to receive the first control signal, and the first terminal of the fifth transistor is connected to the light emitting element The anode of the fifth transistor is electrically connected, and the second end of the fifth transistor is electrically connected to the first node.
  • the second control circuit includes a sixth transistor, the control terminal of the sixth transistor is configured to receive the second control signal, and the first terminal of the sixth transistor is connected to the second control signal.
  • the voltage terminal is electrically connected, and the second terminal of the sixth transistor is electrically connected to the third node.
  • the reset circuit includes a seventh transistor, the control terminal of the seventh transistor is configured to receive the reset signal, the first terminal of the seventh transistor is electrically connected to the reset terminal, and the The second end of the seven transistor is electrically connected to the second node.
  • a pixel unit including: the pixel circuit described in any one of the above embodiments.
  • the pixel unit includes: a substrate; a driving circuit layer disposed on one side of the substrate; and a planarization layer disposed on a side of the driving circuit layer away from the substrate; wherein: The first transistor, the first switch circuit, the second switch circuit, and the third switch circuit are arranged in the drive circuit layer; the anode and the sensing electrode are arranged in the flat On the layer.
  • the pixel unit includes a pixel defining layer on the anode and the sensing electrode, the pixel defining layer has a first opening and a second opening spaced apart, and the first opening is located on the The projection on the substrate and the projection of the anode on the substrate at least partially overlap, and the projection of the second opening on the substrate and the projection of the sensing electrode on the substrate at least partially overlap;
  • the light emitting element includes a functional layer provided in the first opening
  • the acoustic fingerprint recognition element includes a piezoelectric material layer provided in the second opening.
  • a display device including a plurality of pixel units, and at least one of the plurality of pixel units includes the pixel unit described in any one of the foregoing embodiments.
  • the display device further includes: an encapsulation layer covering the plurality of pixel units; and a cover plate disposed on a side of the encapsulation layer away from the plurality of pixel units.
  • a method for driving a pixel circuit wherein the pixel circuit includes a light-emitting element including an anode electrically connected to a first node and a cathode electrically connected to a first voltage terminal A first transistor, the control terminal of the first transistor is electrically connected to the second node, the first terminal of the first transistor is electrically connected to the second voltage terminal, and the second terminal of the first transistor is electrically connected to the second node A node is electrically connected; an acoustic fingerprint identification element includes a driving electrode and a sensing electrode electrically connected to the second node; a capacitor, the first end of the capacitor is electrically connected to the second node, and the second node of the capacitor The terminal is electrically connected to a third node; a first switch circuit, which is electrically connected to the data line and the third node, is configured to transmit the voltage from the data line to the third node in response to the first scan signal; A second switch circuit, electrically connected to a first switch circuit, which is electrically connected to the
  • the second stage includes a first substage and a second substage after the first substage; in the first substage, the first alternating current is applied to the driving electrode Voltage signal, wherein the first switch circuit is turned on in response to the first scan signal to transmit the first data voltage from the data line to the third node, and the second switch circuit is in response to the The second scan signal is turned on, and the third switch circuit is not turned on in response to the third scan signal; in the second sub-phase, the sensing electrode induces the second AC voltage signal, and the first A switch circuit is not turned on in response to the first scan signal, the second switch circuit is turned on in response to the second scan signal, and the third switch circuit is turned on in response to the third scan signal.
  • the pixel circuit further includes a second control circuit, electrically connected to the second voltage terminal and the third node, and configured to change the potential of the second voltage terminal in response to a second control signal Is transmitted to the third node;
  • the second phase also includes a third subphase located between the first subphase and the second subphase; in the first subphase and the second subphase In the phase, the second control circuit is not turned on in response to the second control signal; in the third subphase, the second control circuit is turned on in response to the second control signal, and the first switch The circuit does not conduct in response to the first scan signal, the second switch circuit does not conduct in response to the second scan signal, and the third switch circuit does not conduct in response to the third scan signal.
  • the second phase further includes a fourth subphase before the first subphase; in the fourth subphase, the second node potential is reset to the first initial potential, wherein , The first switch circuit does not conduct in response to the first scan signal, the second switch circuit does not conduct in response to the second scan signal, and the third switch circuit responds to the third scan The signal is not conducting.
  • the pixel circuit further includes a second control circuit, electrically connected to the second voltage terminal and the third node, and configured to change the potential of the second voltage terminal in response to a second control signal Transmitted to the third node;
  • the first phase includes a fifth subphase, a sixth subphase after the fifth subphase, and a seventh subphase between the sixth subphase; in the In the fifth sub-stage, the first switch circuit is turned on in response to the first scan signal to transmit the second data voltage from the data line to the third node, and the second switch circuit is in response to the The second scan signal is turned on, the third switch circuit is not turned on in response to the third scan signal, and the second control circuit is not turned on in response to the second control signal; In the phase, the first switch circuit does not conduct in response to the first scan signal, the second switch circuit does not conduct in response to the second scan signal, and the third switch circuit does not conduct in response to the third scan signal.
  • the second control circuit When the scan signal is not conducting, the second control circuit is conducting in response to the second control signal; in the seventh sub-phase, the first switch circuit is not conducting in response to the first scan signal, so The second switch circuit does not conduct in response to the second scan signal, the third switch circuit does not conduct in response to the third scan signal, and the second control circuit does not conduct in response to the second control signal. Conduction.
  • the first stage further includes an eighth sub-stage before the fifth sub-stage; in the eighth sub-stage, the second node potential is reset to a second initial potential, wherein , The first switch circuit does not conduct in response to the first scan signal, the second switch circuit does not conduct in response to the second scan signal, and the third switch circuit responds to the third scan The signal is not conducting.
  • FIG. 1 is a schematic diagram showing the structure of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the structure of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic flowchart showing a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram showing the first stage and the second stage according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram showing the structure of a pixel circuit according to another embodiment of the present disclosure.
  • 6A is a timing control signal diagram showing a second stage of a pixel circuit according to an embodiment of the present disclosure
  • 6B is a timing control signal diagram showing a pixel circuit in the first stage according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram showing the structure of a pixel unit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram showing the structure of a display device according to an embodiment of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intermediate component, or may not be directly connected to the other component but with an intermediate component.
  • FIG. 1 is a schematic diagram showing the structure of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit may include a light-emitting element 11, a first transistor T1, an acoustic fingerprint recognition element 12, a capacitor C, a first switch circuit 13, a second switch circuit 14 and a third switch circuit 15.
  • the light emitting element 11 includes an anode electrically connected to the first node N1 and a cathode electrically connected to the first voltage terminal ELVSS.
  • the light emitting element 11 may include an organic light emitting diode.
  • the control terminal of the first transistor T1 is electrically connected to the second node N2, the first terminal of the first transistor is electrically connected to the second voltage terminal ELVDD, and the second terminal of the first transistor is electrically connected to the first node N1.
  • the potential of the second voltage terminal ELVDD is higher than the potential of the first voltage terminal ELVSS.
  • the second voltage terminal ELVDD is a power supply voltage terminal, and the first voltage terminal ELVSS can be grounded.
  • the acoustic fingerprint recognition element 12 includes a driving electrode 121 and a sensing electrode 122 electrically connected to the second node N2.
  • the acoustic fingerprint recognition element 12 is configured to generate a first acoustic wave when a first AC voltage signal is applied to the driving electrode 121, and to generate a second AC voltage signal based on the second acoustic wave after the first acoustic wave is reflected .
  • the first AC voltage signal may be applied to the driving electrode 121 through the input terminal IN. It should be understood that the direction of the first AC voltage signal alternately changes, and the magnitude may be changed or unchanged.
  • the first AC voltage signal may be a square wave signal.
  • the first AC voltage signal may be a trigonometric function signal, such as a sine signal or a cosine signal.
  • the acoustic fingerprint identification element 12 may include a piezoelectric material layer between the driving electrode 121 and the sensing electrode 122.
  • the material of the piezoelectric material layer may include one or more of the following: polyvinylidene fluoride (PVDF), aluminum nitride (AlN), piezoelectric ceramics (for example, lead zirconate titanate piezoelectric ceramics (PZT)).
  • PVDF polyvinylidene fluoride
  • AlN aluminum nitride
  • PZT lead zirconate titanate piezoelectric ceramics
  • the second sound wave is incident on the piezoelectric material layer to generate a second AC voltage signal and is induced by the sensing electrode 122.
  • the second acoustic wave reflected by the valley of the fingerprint is incident on the piezoelectric material layer and the second AC voltage signal generated after the positive potential is higher than that of the second acoustic wave reflected by the ridge of the fingerprint.
  • the positive potential of the second AC voltage signal generated after the second sound wave is incident on the piezoelectric material layer. Therefore, the valley and the ridge of the fingerprint can be distinguished according to the level of the positive potential of the second AC voltage signal.
  • the valleys and ridges of the fingerprint can also be distinguished according to the level of the negative potential of the second AC voltage signal.
  • the first end of the capacitor C is electrically connected to the second node N2, and the second end of the capacitor C is electrically connected to the third node N3.
  • the first switch circuit 13 is electrically connected to the data line DL and the third node N3.
  • the first switch circuit 13 is configured to transmit the voltage from the data line DL to the third node N3, that is, to the second end of the capacitor C, in response to the first scan signal S1.
  • the second switch circuit 14 is electrically connected to the first node N1 and the second node N2.
  • the second switch circuit 14 is configured to transmit the potential of the second node N2 to the first node N1 in response to the second scan signal S2.
  • the potential of the second node N2 is related to the potential of the second AC voltage signal induced by the sensing electrode 122.
  • the level of the potential of the second node N2 can reflect the level of the potential of the second AC voltage signal induced by the sensing electrode 122.
  • the third switch circuit 15 is electrically connected to the first node N1 and the output terminal Vout.
  • the third switch circuit 15 is configured to output the potential of the second node N2 to the output terminal Vout in response to the third scan signal S3.
  • the potential of the second AC voltage signal induced by the sensing electrode 122 can be determined, so that the corresponding fingerprint can be identified.
  • the fingerprint can be identified based on the potential of the second node N2 in the time period corresponding to the positive potential of the second AC voltage signal.
  • the fingerprint can be identified according to the potential of the second node N2 in the half period corresponding to the positive potential of the sinusoidal signal. In the time period corresponding to the positive potential of the second AC voltage signal, if the potential of the second node N2 is higher, the positive potential of the second AC voltage signal induced by the sensing electrode 122 is higher; on the contrary, if the second node N2 The lower the potential of, the lower the positive potential of the second AC voltage signal induced by the sensing electrode 122.
  • the fingerprint can also be identified according to the potential of the second node N2 in the time period corresponding to the negative potential of the second AC voltage signal.
  • the pixel circuit includes not only the light-emitting element 11 but also the acoustic fingerprint recognition element 12.
  • the third switch circuit 15 can output the potential of the second node N2 to the output terminal Vout.
  • the second AC voltage signal induced by the sensing electrode 122 can be determined according to the potential of the second node N2, so that the fingerprint corresponding to the pixel circuit can be identified.
  • FIG. 2 is a schematic diagram showing the structure of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit shown in FIG. 2 may further include at least one of the first control circuit 16, the second control circuit 17 and the reset circuit 18.
  • the respective functions of the first control circuit 16, the second control circuit 17, and the reset circuit 18 are described in detail below.
  • the first control circuit 16 is electrically connected to the anode of the light emitting element 11 and the first node N1. That is, the anode of the light-emitting element 11 is electrically connected to the first node N1 via the first control circuit 16.
  • the first control circuit 16 is configured to be turned on or off in response to the first control signal EM1.
  • the first control signal EM1 may be a pulse width adjustment (PWM) signal. By adjusting the pulse width of the PWM signal, the brightness of the light-emitting element 11 can be adjusted.
  • PWM pulse width adjustment
  • the second control circuit 17 is electrically connected to the second voltage terminal ELVDD and the third node N3.
  • the second control circuit 17 is configured to transmit the potential of the second voltage terminal ELVDD to the third node N3, that is, to the second terminal of the capacitor C, in response to the second control signal EM2.
  • the reset circuit 18 is electrically connected to the second node N2.
  • the reset circuit 18 is configured to reset the potential of the second node N2 to an initial potential that turns off the first transistor T1, for example, a zero potential in response to the reset signal R.
  • FIG. 3 is a schematic flowchart showing a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit may be the pixel circuit of any one of the above embodiments.
  • the driving method may include step 302 and step 304.
  • step 302 in the first phase M1, the potential of the second node N2 is stabilized at a first fixed potential that turns on the first transistor T1 to drive the light-emitting element 11 to emit light.
  • step 304 in the second phase M2, the potential of the second node N2 is stabilized at a second fixed potential that turns off the first transistor T1, and the second fixed potential is output to the output terminal Gout.
  • the second fixed potential is related to the potential of the second AC voltage signal induced by the sensing electrode 122. According to the second fixed potential, the potential of the second AC voltage signal induced by the sensing electrode 122 can be determined.
  • the first stage M1 may also be called the display stage, and the second stage M2 may also be called the fingerprint recognition stage. It should be understood that the first stage M1 may be before the second stage M2 or after the second stage. In some embodiments, the second stage M2 may be between two first stages M1.
  • the potential of the second node N2 is stabilized at different fixed potentials at different stages to drive the light-emitting element to emit light or output the potential of the second node N2 to the output terminal Gout.
  • the pixel circuit can realize both the display function and the fingerprint recognition function.
  • FIG. 4 is a schematic diagram showing the first stage M1 and the second stage M2 according to an embodiment of the present disclosure.
  • Fig. 4 schematically shows a situation where the second stage M2 is between two first stages M1.
  • the second stage M2 may include a first substage T11 and a second substage T12 after the first substage T11.
  • a first AC voltage signal is applied to the driving electrode 121.
  • the sensing electrode 122 subsequently senses a second AC voltage signal corresponding to the first AC voltage signal.
  • the first switch circuit 13 is turned on in response to the first scan signal S1 to transmit the first data voltage Vd from the data line DL to the third node N3, that is, to the second terminal of the capacitor C .
  • the second switch circuit 14 is turned on in response to the second scan signal S2, and the third switch circuit 15 is not turned on in response to the third scan signal S3.
  • the first data voltage Vd causes the potential of the second node N2 to change, so that the first transistor T1 is turned on.
  • the second switch circuit 14 since the second switch circuit 14 is turned on, the potential of the second node N2 gradually stabilizes at Vdd-Vth.
  • Vdd is the potential of the second voltage terminal ELVDD
  • Vth is the threshold voltage of the first transistor T1.
  • the sensing electrode 121 induces a second AC voltage signal.
  • the first switch circuit 13 does not conduct in response to the first scan signal S1
  • the second switch circuit 14 conducts in response to the second scan signal S2
  • the third switch circuit 15 responds to the third scan signal S3. Conduction.
  • the second fixed potential at which the potential of the second node N2 is stable is Vdd-Vth+Vs.
  • the second fixed potential Vdd-Vth+Vs of the second node N2 is transmitted to the output terminal Vout via the second switch circuit 14 and the third switch circuit 15.
  • the second stage M2 may further include a third sub-stage T13 located between the first sub-stage T11 and the second sub-stage T12.
  • the pixel circuit may further include the second control circuit 17 shown in FIG. 2 which is electrically connected to the second voltage terminal ELVDD and the third node N3.
  • the second control circuit 17 does not conduct in response to the second control signal EM2. Refer to the above description for other circuits.
  • the second control circuit 17 is turned on in response to the second control signal EM2 to transfer the potential Vdd of the second voltage terminal ELVSS to the third node N3.
  • the first switch circuit 13 does not conduct in response to the first scan signal S1
  • the second switch circuit 14 does not conduct in response to the second scan signal S2
  • the third switch circuit 15 does not conduct in response to the third scan signal S3.
  • the potential of the third node N3 is Vdd
  • the potential of the second node N2 is 2Vdd-Vth-Vd.
  • the second control circuit 17 does not conduct in response to the second control signal EM2.
  • the stable second fixed potential of the second node N2 is 2Vdd-Vth-Vd+Vs.
  • a third sub-phase T13 is additionally added, so that the finally obtained second fixed potential is related to the first data voltage Vd.
  • the value of the second fixed potential can be adjusted by adjusting the value of the first data voltage Vd, so that the value of the second fixed potential is within a desired range, which is more conducive to identifying the second AC voltage induced by the sensing electrode 121 Signal potential Vs.
  • the second stage M2 may also be in the fourth sub-stage T14 before the first sub-stage T11.
  • the potential of the second node N2 is reset to the first initial potential.
  • the first switch circuit 13 does not conduct in response to the first scan signal S1
  • the second switch circuit 14 does not conduct in response to the second scan signal S2
  • the third switch circuit 15 does not conduct in response to the third scan signal S3.
  • the potential of the second node N2 is first reset to the first initial potential. In this way, the potential of the second node N2 can more accurately reflect the potential Vs of the second AC voltage signal induced by the sensing electrode 121.
  • the first stage M1 may include a fifth substage T15, a sixth substage T16 after the fifth substage T15, and a seventh substage after the fifth substage T16. T17.
  • the pixel circuit may further include the second control circuit 17 shown in FIG. 2 electrically connected to the second voltage terminal ELVDD and the third node N3.
  • the first switch circuit 13 is turned on in response to the first scan signal S1 to transmit the second data voltage Vdata from the data line DL to the third node N3.
  • the second switch circuit 14 is turned on in response to the second scan signal S2, and the third switch circuit 15 is not turned on in response to the third scan signal S3.
  • the second control circuit 17 does not conduct in response to the second control signal EM2.
  • the second data voltage Vdata causes the potential of the second node N2 to change, so that the first transistor T1 is turned on. Since the second switch circuit 14 is turned on, the potential of the second node N2 gradually stabilizes at Vdd-Vth.
  • the second control circuit 17 is turned on in response to the second control signal EM2, the first switch circuit 13 is not turned on in response to the first scan signal S1, and the second switch circuit 14 is turned on in response to the second scan signal S2. Not conducting, the third switch circuit 15 is not conducting in response to the third scan signal S3.
  • the first switch circuit 13 does not conduct in response to the first scan signal S1
  • the second switch circuit 14 does not conduct in response to the second scan signal S2
  • the third switch circuit 15 responds to the third scan signal.
  • S3 is not conductive
  • the second control circuit 17 is not conductive in response to the second control signal EM2.
  • the first fixed potential at which the potential of the second node N2 is stable is 2Vdd-Vth-Vdata, thereby driving the light-emitting element 11 to emit light.
  • the first stage M1 may also include an eighth substage T18 before the fifth substage T15.
  • the potential of the second node N2 is reset to the second initial potential.
  • the first switch circuit 13 does not conduct in response to the first scan signal S1
  • the second switch circuit 14 does not conduct in response to the second scan signal S2
  • the third switch circuit 15 does not conduct in response to the third scan signal S3.
  • the potential of the second node N2 before the potential of the second node N2 is stabilized at the first fixed potential, the potential of the second node N2 is first reset to the second initial potential.
  • This method can drive the light-emitting element to emit light more accurately.
  • the implementation process of the first stage M1 is described above when the driving circuit includes the second control circuit. However, this is not restrictive. The specific implementation of the first stage M1 is described below in conjunction with the driving circuit shown in FIG. 1.
  • the first switch circuit 13 is turned on in response to the first scan signal S1 to transmit the reference voltage Vref from the data line DL to the third node N3.
  • the second switch circuit 14 is turned on in response to the second scan signal S2, and the third switch circuit 15 is not turned on in response to the third scan signal S3.
  • the reference voltage Vref causes the potential of the second node N2 to change, so that the first transistor T1 is turned on. Since the second switch circuit 14 is turned on, the potential of the second node N2 gradually stabilizes at Vdd-Vth.
  • the first switch circuit 13 is turned on in response to the first scan signal S1 to transmit the data voltage Vdata' from the data line DL to the third node N3.
  • the second switch circuit 14 does not conduct in response to the second scan signal S2, and the third switch circuit 15 does not conduct in response to the third scan signal S3.
  • the potential of the second node N2 becomes Vdd-Vth+Vdata'-Vref, so that the light-emitting element 11 can be driven to emit light under the control of the data voltage Vdata'.
  • FIG. 5 is a schematic diagram showing the structure of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 5 shows the specific implementation of each circuit in the pixel circuit
  • the circuits in the pixel circuit are not necessarily all implemented in accordance with the implementation shown in FIG. 5 achieve.
  • part of the circuits in the pixel circuit may be implemented in the implementation manner shown in FIG. 5, and other circuits may be implemented in other implementation manners.
  • the third switch circuit 15 may include a second transistor T2.
  • the control terminal of the second transistor T2 is configured to receive the third scan signal S3, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the output terminal Gout.
  • the second switch circuit 14 may include a third transistor T3.
  • the control terminal of the third transistor T3 is configured to receive the second scan signal S2, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first node N1.
  • the first switch circuit 13 may include a fourth transistor T4.
  • the control terminal of the fourth transistor T4 is configured to receive the first scan signal S1, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the data line DL.
  • the first control circuit 16 may include a fifth transistor T5.
  • the control terminal of the fifth transistor T5 is configured to receive the first control signal EM1, the first terminal of the fifth transistor T5 is electrically connected to the anode of the light emitting element 11, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1.
  • the second control circuit 17 may include a sixth transistor T6.
  • the control terminal of the sixth transistor T6 is configured to receive the second control signal EM2, the first terminal of the sixth transistor T6 is electrically connected to the second voltage terminal ELVDD, and the second terminal of the sixth transistor T6 is electrically connected to the third node N3.
  • the reset circuit 18 may include a seventh transistor T7.
  • the control terminal of the seventh transistor T7 is configured to receive the reset signal R, the first terminal of the seventh transistor T7 is electrically connected to the reset terminal Vi, and the second terminal of the seventh transistor T7 is electrically connected to the second node N2.
  • the transistors in the pixel circuit of FIG. 5 may all be N-type thin film transistors (TFT) or all P-type thin film transistors. In other embodiments, part of the transistors in the pixel circuit shown in FIG. 5 may be N-type TFTs, and other transistors may be P-type TFTs. In some embodiments, the active layer of each transistor may include but is not limited to Low Temperature Poly-silicon (LTPS).
  • LTPS Low Temperature Poly-silicon
  • FIG. 6A is a timing control signal diagram showing the second stage of the pixel circuit according to an embodiment of the present disclosure. The working process of the pixel circuit shown in FIG. 5 in the second stage will be described below in conjunction with FIG. 6A. In the following description, it is assumed that each transistor in the pixel circuit shown in FIG. 5 is an N-type TFT.
  • the reset signal R is at a high level VGH
  • the first scan signal S1, the second scan signal S2, the third scan signal S3, the first control signal EM1 and the second control signal EM2 are at low level.
  • Level VGL. Therefore, the seventh transistor T7 is turned on to reset the potential of the second node N2 to the first initial potential.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off.
  • the first initial potential may, for example, turn off the first transistor T1.
  • the first scan signal S1 and the second scan signal S2 are at the high level VGH, and the third scan signal S3, the reset signal R, the first control signal EM1 and the second control signal EM2 are at the low level VGL. Therefore, the third transistor T3 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. Since the third transistor T3 is turned on, the first data voltage Vd from the data line DL can be transferred to the third node N3 to charge the capacitor C. Under the action of the capacitor C, the first data voltage Vd causes the potential of the second node N2 to change, so that the first transistor T1 is turned on. In addition, since the third transistor T3 is turned on, the potential of the second node N2 can be stabilized at Vdd-Vth.
  • the second control signal EM2 is at the high level VGH, and the first scan signal S1, the second scan signal S2, the third scan signal S3, the reset signal R and the first control signal EM1 are at the low level VGL. Therefore, the sixth transistor T6 is turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. Under the action of the capacitor C, the potential of the second node N2 can be stabilized at 2Vdd-Vth-Vd.
  • the first scan signal S2 and the second scan signal S3 are at the high level VGH, and the first scan signal S1, the reset signal R, the first control signal EM1 and the second control signal EM2 are at the low level VGL. Therefore, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the sensing electrode 122 senses the second AC voltage signal
  • the first fixed potential at which the potential of the second node N2 is finally stabilized is 2Vdd-Vth-Vd+Vs.
  • the second transistor T2 and the third transistor T3 are turned on, the first fixed potential 2Vdd-Vth-Vd+Vs can be transmitted to the output terminal Vout.
  • FIG. 6B is a timing control signal diagram showing the pixel circuit in the first stage according to an embodiment of the present disclosure. The working process of the pixel circuit shown in FIG. 5 in the first stage will be described below in conjunction with FIG. 6B. In the following description, it is assumed that each transistor in the pixel circuit shown in FIG. 5 is an N-type TFT.
  • the reset signal R is at a high level VGH
  • the first scan signal S1, the second scan signal S2, the third scan signal S3, the first control signal EM1, and the second control signal EM2 are at low level.
  • Level VGL. Therefore, the seventh transistor T7 is turned on to reset the potential of the second node N2 to the second initial potential.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off.
  • the second initial potential and the first initial potential may be the same or different.
  • the second initial potential may, for example, turn off the first transistor T1.
  • the first scan signal S1 and the second scan signal S2 are at the high level VGH, and the third scan signal S3, the reset signal R, the first control signal EM1 and the second control signal EM2 are at the low level VGL. Therefore, the third transistor T3 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. Since the third transistor T3 is turned on, the second data voltage Vdata from the data line DL can be transmitted to the third node N3 to charge the capacitor C. Under the action of the capacitor C, the potential of the second node N2 changes, so that the first transistor T1 is turned on. The potential of the second node N2 can be stabilized at Vdd-Vth.
  • the second control signal EM2 is at the high level VGH, and the first scan signal S1, the second scan signal S2, the third scan signal S3, the reset signal R and the first control signal EM1 are at the low level VGL. Therefore, the sixth transistor T6 is turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. Under the action of the capacitor C, the final stable second fixed potential of the second node N2 is 2Vdd-Vth-Vdata.
  • the first control signal EM1 is at the high level VGH
  • the first scan signal S1, the second scan signal S2, the third scan signal S3, the reset signal R, and the second control signal EM2 are at the low level VGL. Therefore, the fifth transistor T5 is turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off. Since the fifth transistor T5 is turned on, the current from the first transistor T1 can drive the light-emitting element 11 to emit light.
  • each transistor in the pixel circuit is an N-type TFT. It should be understood that when each transistor in the pixel circuit is a P-type TFT, the timing control signal can be adjusted accordingly to drive the light-emitting element 11 in the pixel circuit to emit light or output the potential of the second node N2.
  • FIG. 7 is a schematic diagram showing the structure of a pixel unit according to an embodiment of the present disclosure.
  • a pixel unit may also be referred to as a sub-pixel, and three pixel units may constitute one pixel.
  • the pixel unit may include the pixel circuit of any one of the above embodiments.
  • the pixel unit includes a substrate 71, a driving circuit layer 72, a planarization layer 73 and a pixel defining layer 74.
  • the positional relationship between the components in the pixel circuit and the substrate 71, the driving circuit layer 72, the planarization layer 73 and the pixel defining layer 74 will be described below.
  • the substrate 71 may be a flexible substrate, for example.
  • the material of the substrate 71 may include, for example, polyacetamide or the like.
  • the driving circuit layer 72 is provided on one side of the substrate 71.
  • the first transistor T1, the first switch circuit 13, the second switch circuit 14, and the third switch circuit 15 in the pixel circuit are all provided in the driving circuit layer 72.
  • the planarization layer 73 is provided on the side of the driving circuit layer 72 away from the substrate 71.
  • the material of the planarization layer 73 may include, for example, organic resin or the like.
  • the anode 112 of the light-emitting element 11 and the sensing electrode 122 of the acoustic fingerprint identification element 12 are spaced apart on the planarization layer 73. It should be understood that the anode 112 of the light-emitting element 11 may be connected to the drain of the first transistor T1, that is, the second end, through the via 731 penetrating the planarization layer 73.
  • the anode 112 and the sensing electrode 122 may be made of the same material, for example, both may include indium tin oxide (ITO) or the like.
  • the anode 111 and the sensing electrode 122 may be formed by the same patterning process, that is, they may be formed by performing a patterning process on the same material once.
  • the present disclosure is not limited to this.
  • the anode 112 and the sensing electrode 122 when the anode 112 and the sensing electrode 122 are made of the same material, the anode 112 and the sensing electrode 122 can also be formed by different patterning processes.
  • the materials of the anode 112 and the sensing electrode 122 may also be different.
  • the pixel defining layer 74 is located on the anode 112 and the sensing electrode 122.
  • the pixel defining layer 74 has a first opening 741 and a second opening 742 that are spaced apart.
  • the projection of the first opening 741 on the substrate 71 and the projection of the anode 112 on the substrate 71 at least partially overlap.
  • the projection of the second opening 742 on the substrate 71 and the projection of the sensing electrode 122 on the substrate 71 at least partially overlap.
  • the first opening 741 may expose at least part of the anode 112
  • the second opening 742 may expose at least part of the sensing electrode 122.
  • the functional layer 113 of the light emitting element 11 is disposed in the first opening 741.
  • the piezoelectric material layer 123 of the acoustic fingerprint identification element 12 is disposed in the second opening 742.
  • the functional layer 113 includes at least a light-emitting layer.
  • the material of the light-emitting layer may include, for example, organic electroluminescent materials and the like.
  • the functional layer 123 may further include at least one of a hole transport layer, an electron transport layer, a hole injection layer, and an electron injection layer.
  • the cathode 111 of the light-emitting element 11 is arranged on the side of the functional layer 113 away from the anode 112.
  • the driving electrode 121 of the acoustic fingerprint identification element 12 is arranged on the side of the piezoelectric material layer 123 away from the sensing electrode 122.
  • the material of the cathode 111 and the driving electrode 121 may be the same, for example, both may include a metal material.
  • the cathode 111 and the driving electrode 121 may be formed through the same patterning process. However, the present disclosure is not limited to this.
  • the cathode 111 and the driving electrode 121 can also be formed by different patterning processes.
  • the materials of the anode 112 and the sensing electrode 122 may also be different.
  • the sensing electrode 122 of the acoustic fingerprint identification element 12 and the anode 112 of the light-emitting element 11 may be arranged on the same layer.
  • the functional layer 113 of the light emitting element 11 is disposed in the first opening 741.
  • the piezoelectric material layer 123 of the acoustic fingerprint identification element 12 is disposed in the second opening 742.
  • the embodiment of the present disclosure also provides a display device.
  • the display device may include a plurality of pixel units, such as a red pixel unit (R), a green pixel unit (G), and a blue pixel unit (B). At least one of the plurality of pixel units may include the pixel unit of any one of the above embodiments.
  • At least one pixel unit in the display device includes a pixel circuit provided with an acoustic fingerprint identification element, so that a fingerprint identification function can be implemented in part or all of the display area of the display device.
  • each of the plurality of pixel units may include the pixel unit of any one of the foregoing embodiments, so that the full-screen fingerprint recognition function of the display area can be realized. It should be understood that the relative magnitude of the potential of the second AC voltage signal induced by the sensing electrode 122 in the multiple pixel circuits can be determined according to the potential of the second node N2 in the pixel circuits of the multiple pixel units, so that multiple pixels can be identified. The fingerprint corresponding to the circuit.
  • the display device may include, for example, a display panel, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, a virtual reality system, and any other products or components with display functions.
  • FIG. 8 is a schematic diagram showing the structure of a display device according to an embodiment of the present disclosure.
  • the display device may include an encapsulation layer 81 and a cover plate 82 covering a plurality of pixel units.
  • FIG. 8 only schematically shows one pixel unit.
  • the cover 82 is disposed on the side of the encapsulation layer 81 away from the plurality of pixel units.
  • the encapsulation layer 81 and the cover plate 82 can be glued by optical glue OCA.
  • the encapsulation layer 81 may include a thin film encapsulation layer.
  • the encapsulation layer 81 may include a stack of organic layers, inorganic layers, and organic layers alternately.
  • the cover 82 may include a glass cover, for example.

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Abstract

一种像素电路及其驱动方法、像素单元和显示装置，像素电路包括：发光元件（11），包括与第一节点（N1）电连接的阳极和与第一电压端（ELVSS）电连接的阴极；第一晶体管（T1），其控制端、第一端、第二端分别与第二节点（N2）、第二电压端（ELVDD）、第一节点（N1）电连接；声波指纹识别元件（12），包括驱动电极（121）和与第二节点（N2）电连接的感应电极（122）；电容器（C），电容器（C）的第一端与第二节点（N2）电连接，电容器（C）的第二端与第三节点（N3）电连接；第一开关电路（13），被配置为响应于第一扫描信号（S1）将来自数据线（DL）的电压传输至第三节点（N3）；第二开关电路（14），被配置为响应于第二扫描信号（S2）将第二节点（N2）的电位传输至第一节点（N1）；第三开关电路（15），被配置为响应于第三扫描信号（S3）将第二节点（N2）的电位输出至输出端（Vout）。

Description

像素单路及其驱动方法、像素单元和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、像素单元和显示装置。
背景技术
随着显示技术的发展，显示装置的边框呈现越来越窄的趋势。
相关技术中，显示装置中的指纹识别功能通常设置在围绕显示区的非显示区，导致边框区域的面积较大。
发明内容
根据本公开实施例的一方面，提供一种像素电路，包括：发光元件，包括与第一节点电连接的阳极、以及与第一电压端电连接的阴极；第一晶体管，所述第一晶体管的控制端与第二节点电连接，所述第一晶体管的第一端与第二电压端电连接，所述第一晶体管的第二端与所述第一节点电连接；声波指纹识别元件，包括驱动电极和与所述第二节点电连接的感应电极；电容器，所述电容器的第一端与所述第二节点电连接，所述电容器的第二端与第三节点电连接；第一开关电路，与数据线和所述第三节点电连接，被配置为响应于第一扫描信号将来自所述数据线的电压传输至所述第三节点；第二开关电路，与所述第一节点和所述第二节点电连接，被配置为响应于第二扫描信号将所述第二节点的电位传输至所述第一节点；和第三开关电路，与所述第一节点和输出端电连接，被配置为响应于第三扫描信号将所述第二节点的电位输出至所述输出端。
在一些实施例中，所述第三开关电路包括第二晶体管，所述第二晶体管的控制端被配置为接收所述第三扫描信号，所述第二晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述输出端电连接。
在一些实施例中，所述像素电路还包括：第一控制电路，与所述发光元件的阳极和所述第一节点电连接，被配置为响应于第一控制信号导通或截止。
在一些实施例中，所述像素电路还包括：第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所 述第三节点。
在一些实施例中，所述像素电路还包括：复位电路，被配置为响应于复位信号将所述第二节点的电位复位到初始电位。
在一些实施例中，所述第二开关电路包括第三晶体管，所述第三晶体管的控制端被配置为接收所述第二扫描信号，所述第三晶体管的第一端与所述第二节点电连接，所述第三晶体管的第二端与所述第一节点电连接。
在一些实施例中，所述第一开关电路包括第四晶体管，所述第四晶体管的控制端被配置为接收所述第一扫描信号，所述第四晶体管的第一端与所述第三节点电连接，所述第四晶体管的第二端与所述数据线电连接。
在一些实施例中，所述第一控制电路包括第五晶体管，所述第五晶体管的控制端被配置为接收所述第一控制信号，所述第五晶体管的第一端与所述发光元件的阳极电连接，所述第五晶体管的第二端与所述第一节点电连接。
在一些实施例中，所述第二控制电路包括第六晶体管，所述第六晶体管的控制端被配置为接收所述第二控制信号，所述第六晶体管的第一端与所述第二电压端电连接，所述第六晶体管的第二端与所述第三节点电连接。
在一些实施例中，所述复位电路包括第七晶体管，所述第七晶体管的控制端被配置为接收所述复位信号，所述第七晶体管的第一端与复位端电连接，所述第七晶体管的第二端与所述第二节点电连接。
根据本公开实施例的另一方面，提供一种像素单元，包括：上述任意一个实施例所述的像素电路。
在一些实施例中，所述像素单元包括：基板；驱动电路层，设置在所述基板的一侧；和平坦化层，设置在所述驱动电路层远离所述基板的一侧；其中：所述第一晶体管、所述第一开关电路、所述第二开关电路和所述第三开关电路设置在所述驱动电路层中；所述阳极和所述感应电极间隔开地设置在所述平坦化层上。
在一些实施例中，所述像素单元包括位于所述阳极和所述感应电极上的像素界定层，所述像素界定层具有间隔开的第一开口和第二开口，所述第一开口在所述基板上的投影与所述阳极在所述基板上的投影至少部分重叠，并且，所述第二开口在所述基板上的投影与所述感应电极在所述基板上的投影至少部分重叠；所述发光元件包括设置在所述第一开口中的功能层，所述声波指纹识别元件包括设置在所述第二开口中的压电材料层。
根据本公开实施例的又一方面，提供一种显示装置，包括多个像素单元，所述多个像素单元中的至少一个包括上述任意一个实施例所述的像素单元。
在一些实施例中，所述显示装置还包括：封装层，覆盖所述多个像素单元；和盖板，设置在所述封装层远离所述多个像素单元一侧。
根据本公开实施例的再一方面，提供一种像素电路的驱动方法，其中，所述像素电路包括：发光元件，包括与第一节点电连接的阳极、以及与第一电压端电连接的阴极；第一晶体管，所述第一晶体管的控制端与第二节点电连接，所述第一晶体管的第一端与第二电压端电连接，所述第一晶体管的第二端与所述第一节点电连接；声波指纹识别元件，包括驱动电极和与所述第二节点电连接的感应电极；电容器，所述电容器的第一端与所述第二节点电连接，所述电容器的第二端与第三节点电连接；第一开关电路，与数据线和所述第三节点电连接，被配置为响应于第一扫描信号将来自所述数据线的电压传输至所述第三节点；第二开关电路，与所述第一节点和所述第二节点电连接，被配置为响应于第二扫描信号将所述第二节点的电位传输至所述第一节点；和第三开关电路，与所述第一节点和输出端电连接，被配置为响应于第三扫描信号将所述第二节点的电位输出至所述输出端；所述驱动方法包括：在第一阶段，使所述第二节点的电位稳定在使得所述第一晶体管导通的第一固定电位，以驱动所述发光元件发光；和在第二阶段，使所述第二节点的电位稳定在使得所述第一晶体管截止的第二固定电位，并将所述第二固定电位输出到所述输出端。
在一些实施例中，所述第二阶段包括第一子阶段和在所述第一子阶段之后的第二子阶段；在所述第一子阶段，向所述驱动电极施加所述第一交流电压信号，其中，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的第一数据电压传输至所述第三节点，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号不导通；在所述第二子阶段，所述感应电极感应所述第二交流电压信号，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号导通。
在一些实施例中，所述像素电路还包括第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所述第三节点；所述第二阶段还包括位于所述第一子阶段和所述第二子阶段之间的第三子阶段；在所述第一子阶段和所述第二子阶段，所述第二控制电路响应于所述第二控制 信号不导通；在所述第三子阶段，所述第二控制电路响应于所述第二控制信号导通，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
在一些实施例中，所述第二阶段还包括在所述第一子阶段之前的第四子阶段；在所述第四子阶段，将所述第二节点电位复位到第一初始电位，其中，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
在一些实施例中，所述像素电路还包括第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所述第三节点；所述第一阶段包括第五子阶段、在所述第五子阶段之后的第六子阶段和所述第六子阶段之间的第七子阶段；在所述第五子阶段，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的第二数据电压传输至所述第三节点，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号不导通；在所述第六子阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号导通；在所述第七子阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号不导通。
在一些实施例中，所述第一阶段还包括在所述第五子阶段之前的第八子阶段；在所述第八子阶段，将所述第二节点电位复位到第二初始电位，其中，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的像素电路的结构示意图；
图2是示出根据本公开另一个实施例的像素电路的结构示意图；
图3是示出根据本公开一个实施例的像素电路的驱动方法的流程示意图；
图4是示出根据本公开一个实施例的第一阶段和第二阶段的示意图；
图5是示出根据本公开又一个实施例的像素电路的结构示意图；
图6A是示出根据本公开一个实施例的像素电路在第二阶段的时序控制信号图；
图6B是示出根据本公开一个实施例的像素电路在第一阶段的时序控制信号图；
图7是示出根据本公开一个实施例的像素单元的结构示意图；
图8是示出根据本公开一个实施例的显示装置的结构示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应 用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
图1是示出根据本公开一个实施例的像素电路的结构示意图。
如图1所示，像素电路可以包括发光元件11、第一晶体管T1、声波指纹识别元件12、电容器C、第一开关电路13、第二开关电路14和第三开关电路15。
发光元件11包括与第一节点N1电连接的阳极、以及与第一电压端ELVSS电连接的阴极。在一些实施例中，发光元件11可以包括有机发光二极管。
第一晶体管T1的控制端与第二节点N2电连接，第一晶体管的第一端与第二电压端ELVDD电连接，第一晶体管的第二端与第一节点N1电连接。在一些实施例中，第二电压端ELVDD的电位高于第一电压端ELVSS的电位。例如，第二电压端ELVDD为电源电压端，第一电压端ELVSS可以接地。
声波指纹识别元件12包括驱动电极121和与第二节点N2电连接的感应电极122。例如，声波指纹识别元件12被配置为在驱动电极121被施加第一交流电压信号的情况下产生第一声波，并且，基于第一声波被反射后的第二声波产生第二交流电压信号。例如，可以通过输入端IN来向驱动电极121施加第一交流电压信号。应理解，第一交流电压信号的方向交替变化，大小可以变化，也可以不变。例如，第一交流电压信号可以是方波信号。又例如，第一交流电压信号可以是三角函数信号，例如正弦信号或余弦信号。
在一些实现方式中，声波指纹识别元件12可以包括位于驱动电极121与感应电极122之间的压电材料层。压电材料层的材料可以包括下列中的一种或多种：聚偏氟乙烯(PVDF)、氮化铝(AlN)、压电陶瓷(例如，锆钛酸铅压电陶瓷(PZT))。在驱动电极121被施加第一交流电压信号的情况下，压电材料层会发生变形，从而产生第一声波，例如超声波。第一声波经指纹的谷或脊反射后的第二声波入射到压电材料层后产生第二交流电压信号，并被感应电极122感应。可以理解的是，以方波信号的正电位为例，经指纹的谷反射后的第二声波入射到压电材料层后产生的第二交流电压信号的正电位高于经指纹的脊反射后的第二声波入射到压电材料层后产生的第二交流电压信号的正电位。故，根据第二交流电压信号的正电位的高低可以区分出指纹的谷和脊。当然，类似地，也可以根据第二交流电压信号的负电位的高低可以区分出指纹的谷和脊。
电容器C的第一端与第二节点N2电连接，电容器C的第二端与第三节点N3电连接。
第一开关电路13与数据线DL和第三节点N3电连接。第一开关电路13被配置为响应于第一扫描信号S1将来自数据线DL的电压传输至第三节点N3，也即传输至电容器C的第二端。
第二开关电路14与第一节点N1和第二节点N2电连接。第二开关电路14被配置为响应于第二扫描信号S2将第二节点N2的电位传输至第一节点N1。这里，第二节点N2的电位与感应电极122感应到的第二交流电压信号的电位相关。换言之，第二节点N2的电位的高低可以反映感应电极122感应到的第二交流电压信号的电位的高低。
第三开关电路15与第一节点N1和输出端Vout电连接。第三开关电路15被配置为响应于第三扫描信号S3将第二节点N2的电位输出至输出端Vout。
根据第二节点N2的电位可以确定感应电极122感应到的第二交流电压信号的电位，从而可以识别出对应的指纹。
例如，可以根据第二节点N2在第二交流电压信号的正电位对应的时间段内的电位来识别指纹。以第二交流电压信号为正弦信号为例，可以根据第二节点N2在正弦信号的正电位对应的半个周期内的电位来识别指纹。在第二交流电压信号的正电位对应的时间段内，如果第二节点N2的电位越高，则感应电极122感应到的第二交流电压信号的正电位越高；反之，如果第二节点N2的电位越低，则感应电极122感应到的第二交流电压信号的正电位越低。类似地，也可以根据第二节点N2在第二交流电压信号的负电位对应的时间段内的电位来识别指纹。
上述实施例中，像素电路不仅包括发光元件11，还包括声波指纹识别元件12。第三开关电路15可以将第二节点N2的电位输出至输出端Vout。根据第二节点N2的电位可以确定感应电极122感应到的第二交流电压信号，从而可以识别出像素电路对应的指纹。
图2是示出根据本公开另一个实施例的像素电路的结构示意图。
与图1所示像素电路相比，图2所示像素电路还可以包括第一控制电路16、第二控制电路17和复位电路18中的至少一个。
下面详细介绍第一控制电路16、第二控制电路17和复位电路18各自的功能。
第一控制电路16与发光元件11的阳极和第一节点N1电连接。即，发光元件11 的阳极经由第一控制电路16与第一节点N1电连接。第一控制电路16被配置为响应于第一控制信号EM1导通或截止。在一些实施例中，第一控制信号EM1可以是脉冲宽度调整(PWM)信号。通过调整PWM信号的脉冲宽度，可以调节发光元件11的亮度。
第二控制电路17与第二电压端ELVDD和第三节点N3电连接。第二控制电路17被配置为响应于第二控制信号EM2将第二电压端ELVDD的电位传输至第三节点N3，也即传输至电容器C的第二端。
复位电路18与第二节点N2电连接。复位电路18被配置为响应于复位信号R将第二节点N2的电位复位到使得第一晶体管T1截止的初始电位，例如0电位。
图3是示出根据本公开一个实施例的像素电路的驱动方法的流程示意图。像素电路可以是上述任意一个实施例的像素电路。
如图3所示，驱动方法可以包括步骤302和步骤304。
在步骤302，在第一阶段M1，使第二节点N2的电位稳定在使得第一晶体管T1导通的第一固定电位，以驱动发光元件11发光。
在步骤304，在第二阶段M2，使第二节点N2的电位稳定在使得第一晶体管T1截止的第二固定电位，并将第二固定电位输出到输出端Gout。这里，第二固定电位与感应电极122感应到的第二交流电压信号的电位相关。根据第二固定电位可以确定感应电极122感应到的第二交流电压信号的电位。
这里，第一阶段M1也可以称为显示阶段，第二阶段M2也可以称为指纹识别阶段。应理解，第一阶段M1可以在第二阶段M2之前，也可以在第二阶段之后。在某些实施例中，在第二阶段M2可以在两个第一阶段M1之间。
上述实施例中，在不同的阶段使第二节点N2的电位稳定在不同的固定电位，以驱动发光元件发光或者将第二节点N2的电位输出到输出端Gout。这样的方式使得像素电路既可以实现显示功能，也可以实现指纹识别功能。
图4是示出根据本公开一个实施例的第一阶段M1和第二阶段M2的示意图。图4示意性地示出了第二阶段M2在两个第一阶段M1之间的情况。
首先结合图4和图1介绍根据本公开不同实施例的第二阶段M2。
在一些实施例中，如图4所示，第二阶段M2可以包括第一子阶段T11和在第一子阶段T11之后的第二子阶段T12。
在第一子阶段T11，向驱动电极121施加第一交流电压信号。感应电极122后续 会感应到与第一交流电压信号对应的第二交流电压信号。在第一子阶段T11，第一开关电路13响应于第一扫描信号S1导通以将来自数据线DL的第一数据电压Vd传输至第三节点N3，也即传输至电容器C的第二端。另外，第二开关电路14响应于第二扫描信号S2导通，第三开关电路15响应于第三扫描信号S3不导通。
在电容器C的作用下，第一数据电压Vd使得第二节点N2的电位发生变化，从而使得第一晶体管T1导通。另外，由于第二开关电路14导通，从而使得第二节点N2的电位逐渐稳定在Vdd-Vth。在本文中，除非特别指出，否则所提到的Vdd均为第二电压端ELVDD的电位，Vth均为第一晶体管T1的阈值电压。
在第二子阶段T12，感应电极121感应第二交流电压信号。在第二子阶段T12，第一开关电路13响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2导通，第三开关电路15响应于第三扫描信号S3导通。第二节点N2的电位稳定的第二固定电位为Vdd-Vth+Vs。第二节点N2的第二固定电位Vdd-Vth+Vs经由第二开关电路14和第三开关电路15传输到输出端Vout。
在另一些实施例中，如图4所示，第二阶段M2还可以包括位于第一子阶段T11和第二子阶段T12之间的第三子阶段T13。这种情况下，像素电路还可以包括图2所示的与第二电压端ELVDD和第三节点N3电连接的第二控制电路17。
在第一子阶段T11，第二控制电路17响应于第二控制信号EM2不导通。其他电路参照以上描述。
在第三子阶段T13，第二控制电路17响应于第二控制信号EM2导通，以将第二电压端ELVSS的电位Vdd传输至第三节点N3。另外，第一开关电路13响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通。
在电容器C的作用下，在第三子阶段T13，第三节点N3的电位为Vdd，第二节点N2的电位为2Vdd-Vth-Vd。
在第二子阶段T12，第二控制电路17响应于第二控制信号EM2不导通。其他电路参照以上描述。第二节点N2稳定的第二固定电位为2Vdd-Vth-Vd+Vs。
上述实施例中，额外增加了第三子阶段T13，使得最终得到的第二固定电位与第一数据电压Vd相关。如此，可以通过调节第一数据电压Vd的数值来调节第二固定电位的数值，以使得第二固定电位的数值处于期望的范围内，从而更有利于识别出感应电极121感应的第二交流电压信号的电位Vs。
在又一些实施例中，如图4所示，第二阶段M2还可以在第一子阶段T11之前的第四子阶段T14。
在第四子阶段T14，将第二节点N2电位复位到第一初始电位。第一开关电路13响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通。
上述实施例中，在第二节点N2电位稳定在第二固定电位之前，先将第二节点N2电位复位到第一初始电位。这样的方式使得第二节点N2电位可以更准确地反映感应电极121感应到的第二交流电压信号的电位Vs。
接下来结合图4和图2介绍根据本公开不同实施例的第一阶段M1。
在一些实施例中，如图4所示，第一阶段M1可以包括第五子阶段T15、在第五子阶段T15之后的第六子阶段T16和在第五子阶段T16之后的第七子阶段T17。像素电路还可以包括图2所示的与第二电压端ELVDD和第三节点N3电连接的第二控制电路17。
在第五子阶段T15，第一开关电路13响应于第一扫描信号S1导通以将来自数据线DL的第二数据电压Vdata传输至第三节点N3。第二开关电路14响应于第二扫描信号S2导通，第三开关电路15响应于第三扫描信号S3不导通。第二控制电路17响应于第二控制信号EM2不导通。
在电容器C的作用下，第二数据电压Vdata使得第二节点N2的电位发生变化，从而使得第一晶体管T1导通。由于第二开关电路14导通，从而使得第二节点N2的电位逐渐稳定在Vdd-Vth。
在第六子阶段T16，第二控制电路17响应于第二控制信号EM2导通，第一开关电路13响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通。
在第七子阶段T17，第一开关电路13响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通，第二控制电路17响应于第二控制信号EM2不导通。第二节点N2的电位稳定的第一固定电位为2Vdd-Vth-Vdata，从而驱动发光元件11发光。
在另一些实施例中，如图4所示，第一阶段M1还可以包括在第五子阶段T15之前的第八子阶段T18。
在第八子阶段T18，将第二节点N2电位复位到第二初始电位。第一开关电路13 响应于第一扫描信号S1不导通，第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通。
上述实施例中，在第二节点N2电位稳定在第一固定电位之前，先将第二节点N2电位复位到第二初始电位。这样的方式可以更准确地驱动发光元件发光。
需要说明的是，虽然上文在驱动电路包括第二控制电路的情况下介绍了第一阶段M1的实现过程。但是，这并非是限制性的。下文结合图1所示驱动电路介绍第一阶段M1的具体实现方式。
首先，第一开关电路13响应于第一扫描信号S1导通以将来自数据线DL的参考电压Vref传输至第三节点N3。第二开关电路14响应于第二扫描信号S2导通，第三开关电路15响应于第三扫描信号S3不导通。
在电容器C的作用下，参考电压Vref使得第二节点N2的电位发生变化，从而使得第一晶体管T1导通。由于第二开关电路14导通，从而使得第二节点N2的电位逐渐稳定在Vdd-Vth。
然后，第一开关电路13响应于第一扫描信号S1导通以将来自数据线DL的数据电压Vdata’传输至第三节点N3。第二开关电路14响应于第二扫描信号S2不导通，第三开关电路15响应于第三扫描信号S3不导通。
在电容器C的作用下，第二节点N2的电位变为Vdd-Vth+Vdata’-Vref，从而可以在数据电压Vdata’的控制下驱动发光元件11发光。
图5是示出根据本公开又一个实施例的像素电路的结构示意图。
需要说明的是，虽然图5示出了像素电路中各电路的具体实现方式，但是，应理解，在某些实施例中，像素电路中的电路并非必然全部按照图5所示的实现方式来实现。例如，像素电路中的部分电路可以按照图5所示的实现方式来实现，而其他电路按照其他的实现方式来实现。
参见图5，在一些实现方式中，第三开关电路15可以包括第二晶体管T2。第二晶体管T2的控制端被配置为接收第三扫描信号S3，第二晶体管T2的第一端与第一节点N1电连接，第一晶体管T1的第二端与输出端Gout电连接。
参见图5，在一些实现方式中，第二开关电路14可以包括第三晶体管T3。第三晶体管T3的控制端被配置为接收第二扫描信号S2，第三晶体管T3的第一端与第二节点N2电连接，第三晶体管T3的第二端与第一节点N1电连接。
参见图5，在一些实现方式中，第一开关电路13可以包括第四晶体管T4。第四 晶体管T4的控制端被配置为接收第一扫描信号S1，第四晶体管T4的第一端与第三节点N3电连接，第四晶体管T4的第二端与数据线DL电连接。
参见图5，在一些实现方式中，第一控制电路16可以包括第五晶体管T5。第五晶体管T5的控制端被配置为接收第一控制信号EM1，第五晶体管T5的第一端与发光元件11的阳极电连接，第五晶体管T5的第二端与第一节点N1电连接。
参见图5，在一些实现方式中，第二控制电路17可以包括第六晶体管T6。第六晶体管T6的控制端被配置为接收第二控制信号EM2，第六晶体管T6的第一端与第二电压端ELVDD电连接，第六晶体管T6的第二端与第三节点N3电连接。
参见图5，在一些实现方式中，复位电路18可以包括第七晶体管T7。第七晶体管T7的控制端被配置为接收复位信号R，第七晶体管T7的第一端与复位端Vi电连接，第七晶体管T7的第二端与第二节点N2电连接。
在一些实施例中，图5的像素电路中的各晶体管可以均为N型薄膜晶体管(Thin Film Transistor，TFT)或均为P型薄膜晶体管。在另一些实施例中，图5所示的像素电路中的一部分晶体管可以为N型TFT，其他的晶体管可以为P型TFT。在一些实施例中，各晶体管的有源层可以包括但不限于低温多晶硅(Low Temperature Poly-silicon，LTPS)。
图6A是示出根据本公开一个实施例的像素电路在第二阶段的时序控制信号图。下面结合图6A对图5所示的像素电路在第二阶段的工作过程进行说明。在下面的说明中，假设图5所示的像素电路中的各晶体管均为N型TFT。
如图6A所示，在T14阶段，复位信号R处于高电平VGH，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3、第一控制信号EM1和第二控制信号EM2处于低电平VGL。因此，第七晶体管T7导通，以将第二节点N2的电位复位到第一初始电位。另外，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均截止。第一初始电位例如可以使得第一晶体管T1截止。
在T11阶段，第一扫描信号S1和第二扫描信号S2处于高电平VGH，第三扫描信号S3、复位信号R、第一控制信号EM1和第二控制信号EM2处于低电平VGL。因此，第三晶体管T3和第四晶体管T4导通，第二晶体管T2、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。由于第三晶体管T3导通，从而可以将来自数据线DL的第一数据电压Vd传输至第三节点N3，以对电容器C进行充电。在电容器C的作用下，第一数据电压Vd使得第二节点N2的电位发生变化，以使得第一晶体管T1 导通。另外，由于第三晶体管T3导通，故第二节点N2的电位可以稳定在Vdd-Vth。
在T13阶段，第二控制信号EM2处于高电平VGH，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3、复位信号R和第一控制信号EM1处于低电平VGL。因此，第六晶体管T6导通，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第七晶体管T7截止。在电容器C的作用下，第二节点N2的电位可以稳定在2Vdd-Vth-Vd。
在T12阶段，第一扫描信号S2和第二扫描信号S3处于高电平VGH，第一扫描信号S1、复位信号R、第一控制信号EM1和第二控制信号EM2处于低电平VGL。因此，第二晶体管T2和第三晶体管T3导通，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。
由于感应电极122感应到第二交流电压信号，故第二节点N2的电位最终稳定的第一固定电位为2Vdd-Vth-Vd+Vs。另外，由于第二晶体管T2和第三晶体管T3导通，故可以将第一固定电位2Vdd-Vth-Vd+Vs传输至输出端Vout。
图6B是示出根据本公开一个实施例的像素电路在第一阶段的时序控制信号图。下面结合图6B对图5所示的像素电路在第一阶段的工作过程进行说明。在下面的说明中，假设图5所示的像素电路中的各晶体管均为N型TFT。
如图6B所示，在T18阶段，复位信号R处于高电平VGH，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3、第一控制信号EM1和第二控制信号EM2处于低电平VGL。因此，第七晶体管T7导通，以将第二节点N2的电位复位到第二初始电位。另外，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均截止。第二初始电位与第一初始电位可以相同，也可以不同。第二初始电位例如可以使得第一晶体管T1截止。
在T15阶段，第一扫描信号S1和第二扫描信号S2处于高电平VGH，第三扫描信号S3、复位信号R、第一控制信号EM1和第二控制信号EM2处于低电平VGL。因此，第三晶体管T3和第四晶体管T4导通，第二晶体管T2、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。由于第三晶体管T3导通，从而可以将来自数据线DL的第二数据电压Vdata传输至第三节点N3，以对电容器C充电。在电容器C的作用下，第二节点N2的电位发生变化，以使得第一晶体管T1导通。第二节点N2的电位可以稳定在Vdd-Vth。
在T16阶段，第二控制信号EM2处于高电平VGH，第一扫描信号S1、第二扫 描信号S2、第三扫描信号S3、复位信号R和第一控制信号EM1处于低电平VGL。因此，第六晶体管T6导通，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第七晶体管T7截止。在电容器C的作用下，第二节点N2的电位最终稳定的第二固定电位为2Vdd-Vth-Vdata。
在T17阶段，第一控制信号EM1处于高电平VGH，第一扫描信号S1、第二扫描信号S2、第三扫描信号S3、复位信号R和第二控制信号EM2处于低电平VGL。因此，第五晶体管T5导通，第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6和第七晶体管T7截止。由于第五晶体管T5导通，故来自第一晶体管T1的电流可以驱动发光元件11发光。
上文以像素电路中各晶体管均为N型TFT为例介绍了像素电路在第一阶段和第二阶段的工作过程。应理解，在像素电路中各晶体管为P型TFT的情况下，可以相应调整时序控制信号，以驱动像素电路中的发光元件11发光或输出第二节点N2的电位。
图7是示出根据本公开一个实施例的像素单元的结构示意图。在本文中，像素单元也可以称为子像素，三个像素单元可以组成一个像素。
在一些实施例中，像素单元可以包括上述任意一个实施例的像素电路。
如图7所示，像素单元包括基板71、驱动电路层72、平坦化层73和像素界定层74。下面介绍像素电路中的各部件与基板71、驱动电路层72、平坦化层73和像素界定层74之间的位置关系。
基板71例如可以是柔性基板。基板71的材料例如可以包括聚乙酰胺等。
驱动电路层72设置在基板71的一侧。这里，像素电路中的第一晶体管T1、第一开关电路13、第二开关电路14和第三开关电路15均设置在驱动电路层72中。
平坦化层73设置在驱动电路层72远离基板71的一侧。平坦化层73的材料例如可以包括有机树脂等。发光元件11的阳极112和声波指纹识别元件12的感应电极122间隔开地设置在平坦化层73上。应理解，发光元件11的阳极112可以通过贯穿平坦化层73的过孔731与第一晶体管T1的漏极，即第二端连接。
在一些实现方式中，阳极112和感应电极122的材料可以相同，例如均可以包括氧化铟锡(ITO)等。例如，阳极111和感应电极122可以通过同一构图工艺来形成，即，可以通过对相同的材料进行一次图案化工艺来形成。然而，本公开不限于此。在其他的实施例中，在阳极112和感应电极122的材料相同的情况下，阳极112和感应 电极122也可以通过不同的构图工艺来形成。另外，在某些实施例中，阳极112和感应电极122的材料也可以不同。
像素界定层74位于阳极112和感应电极122上。像素界定层74具有间隔开的第一开口741和第二开口742。第一开口741在基板71上的投影与阳极112在基板71上的投影至少部分重叠。第二开口742在基板71上的投影与感应电极122在基板71上的投影至少部分重叠。换言之，第一开口741可以使得阳极112的至少部分露出，第二开口742可以使得感应电极122的至少部分露出。
发光元件11的功能层113设置在第一开口741中。声波指纹识别元件12的压电材料层123设置在第二开口742。功能层113至少包括发光层。发光层的材料例如可以包括有机电致发光材料等。在一些实施例中，功能层123还可以包括空穴传输层、电子传输层、空穴注入层和电子注入层中的至少一层。
发光元件11的阴极111设置在功能层113远离阳极112的一侧。声波指纹识别元件12的驱动电极121设置在压电材料层123远离感应电极122的一侧。在一些实现方式中，阴极111和驱动电极121的材料可以相同，例如均可以包括金属材料。例如，阴极111和驱动电极121可以通过同一构图工艺来形成。然而，本公开不限于此。在其他的实施例中，在阴极111和驱动电极121的材料相同的情况下，阴极111和驱动电极121也可以通过不同的构图工艺来形成。另外，在某些实施例中，阳极112和感应电极122的材料也可以不同。
上述实施例的像素单元中，声波指纹识别元件12的感应电极122与发光元件11的阳极112可以设置在同一层。发光元件11的功能层113设置在第一开口741中。声波指纹识别元件12的压电材料层123设置在第二开口742中。这样的像素单元不仅可以实现正常显示功能，还可以实现指纹识别功能。并且，声波指纹识别元件12不会影响显示功能的正常实现。
本公开实施例还提供了一种显示装置。显示装置可以包括多个像素单元，例如红色像素单元(R)、绿色像素单元(G)、蓝色像素单元(B)。多个像素单元中的至少一个可以包括上述任意一个实施例的像素单元。
上述实施例中，显示装置中的至少一个像素单元包括设置有声波指纹识别元件的像素电路，从而可以在显示装置的显示区的部分或全部区域实现指纹识别功能。
在一些实施例中，多个像素单元中的每一个均可以包括上述任意一个实施例的像素单元，从而可以实现显示区的全屏指纹识别功能。应理解，根据多个像素单元的像 素电路中的第二节点N2的电位可以确定多个像素电路中感应电极122感应到的第二交流电压信号的电位的相对大小，从而可以识别出多个像素电路对应的指纹。
在一些实施例中，显示装置例如可以包括显示面板、移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸、虚拟现实系统等任何具有显示功能的产品或部件。
图8是示出根据本公开一个实施例的显示装置的结构示意图。
如图8所示，显示装置可以包括覆盖多个像素单元的封装层81和盖板82。这里，图8仅示意性地示出了一个像素单元。盖板82设置在封装层81远离多个像素单元的一侧。例如，封装层81和盖板82可以通过光学胶OCA胶合。
封装层81可以包括薄膜封装层。例如，封装层81可以包括有机层、无机层、有机层交替的叠层。盖板82例如可以包括玻璃盖板。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种像素电路，包括：
    发光元件，包括与第一节点电连接的阳极、以及与第一电压端电连接的阴极；
    第一晶体管，所述第一晶体管的控制端与第二节点电连接，所述第一晶体管的第一端与第二电压端电连接，所述第一晶体管的第二端与所述第一节点电连接；
    声波指纹识别元件，包括驱动电极和与所述第二节点电连接的感应电极；
    电容器，所述电容器的第一端与所述第二节点电连接，所述电容器的第二端与第三节点电连接；
    第一开关电路，与数据线和所述第三节点电连接，被配置为响应于第一扫描信号将来自所述数据线的电压传输至所述第三节点；
    第二开关电路，与所述第一节点和所述第二节点电连接，被配置为响应于第二扫描信号将所述第二节点的电位传输至所述第一节点；和
    第三开关电路，与所述第一节点和输出端电连接，被配置为响应于第三扫描信号将所述第二节点的电位输出至所述输出端。
  2. 根据权利要求1所述的像素电路，其中，所述第三开关电路包括第二晶体管，所述第二晶体管的控制端被配置为接收所述第三扫描信号，所述第二晶体管的第一端与所述第一节点电连接，所述第一晶体管的第二端与所述输出端电连接。
  3. 根据权利要求1所述的像素电路，还包括：
    第一控制电路，与所述发光元件的阳极和所述第一节点电连接，被配置为响应于第一控制信号导通或截止。
  4. 根据权利要求1所述的像素电路，还包括：
    第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所述第三节点。
  5. 根据权利要求1所述的像素电路，还包括：
    复位电路，被配置为响应于复位信号将所述第二节点的电位复位到初始电位。
  6. 根据权利要求1-5任意一项所述的像素电路，其中，所述第二开关电路包括第三晶体管，所述第三晶体管的控制端被配置为接收所述第二扫描信号，所述第三晶体管的第一端与所述第二节点电连接，所述第三晶体管的第二端与所述第一节点电连接。
  7. 根据权利要求1-5任意一项所述的像素电路，其中，所述第一开关电路包括第四晶体管，所述第四晶体管的控制端被配置为接收所述第一扫描信号，所述第四晶体管的第一端与所述第三节点电连接，所述第四晶体管的第二端与所述数据线电连接。
  8. 根据权利要求3所述的像素电路，其中，所述第一控制电路包括第五晶体管，所述第五晶体管的控制端被配置为接收所述第一控制信号，所述第五晶体管的第一端与所述发光元件的阳极电连接，所述第五晶体管的第二端与所述第一节点电连接。
  9. 根据权利要求4所述的像素电路，其中，所述第二控制电路包括第六晶体管，所述第六晶体管的控制端被配置为接收所述第二控制信号，所述第六晶体管的第一端与所述第二电压端电连接，所述第六晶体管的第二端与所述第三节点电连接。
  10. 根据权利要求5所述的像素电路，其中，所述复位电路包括第七晶体管，所述第七晶体管的控制端被配置为接收所述复位信号，所述第七晶体管的第一端与复位端电连接，所述第七晶体管的第二端与所述第二节点电连接。
  11. 一种像素单元，包括：如权利要求1-10任意一项所述的像素电路。
  12. 根据权利要求11所述的像素单元，其中，所述像素单元包括：
    基板；
    驱动电路层，设置在所述基板的一侧；和
    平坦化层，设置在所述驱动电路层远离所述基板的一侧；
    其中：
    所述第一晶体管、所述第一开关电路、所述第二开关电路和所述第三开关电路设置在所述驱动电路层中；
    所述阳极和所述感应电极间隔开地设置在所述平坦化层上。
  13. 根据权利要求12所述的像素单元，其中：
    所述像素单元包括位于所述阳极和所述感应电极上的像素界定层，所述像素界定层具有间隔开的第一开口和第二开口，所述第一开口在所述基板上的投影与所述阳极在所述基板上的投影至少部分重叠，并且，所述第二开口在所述基板上的投影与所述感应电极在所述基板上的投影至少部分重叠；
    所述发光元件包括设置在所述第一开口中的功能层，所述声波指纹识别元件包括设置在所述第二开口中的压电材料层。
  14. 一种显示装置，包括多个像素单元，所述多个像素单元中的至少一个包括如权利要求11-13任意一项所述的像素单元。
  15. 一种像素电路的驱动方法，其中，所述像素电路包括：
    发光元件，包括与第一节点电连接的阳极、以及与第一电压端电连接的阴极；
    第一晶体管，所述第一晶体管的控制端与第二节点电连接，所述第一晶体管的第一端与第二电压端电连接，所述第一晶体管的第二端与所述第一节点电连接；
    声波指纹识别元件，包括驱动电极和与所述第二节点电连接的感应电极；
    电容器，所述电容器的第一端与所述第二节点电连接，所述电容器的第二端与第三节点电连接；
    第一开关电路，与数据线和所述第三节点电连接，被配置为响应于第一扫描信号将来自所述数据线的电压传输至所述第三节点；
    第二开关电路，与所述第一节点和所述第二节点电连接，被配置为响应于第二扫描信号将所述第二节点的电位传输至所述第一节点；和
    第三开关电路，与所述第一节点和输出端电连接，被配置为响应于第三扫描信号将所述第二节点的电位输出至所述输出端；
    所述驱动方法包括：
    在第一阶段，使所述第二节点的电位稳定在使得所述第一晶体管导通的第一固定电位，以驱动所述发光元件发光；和
    在第二阶段，使所述第二节点的电位稳定在使得所述第一晶体管截止的第二固定电位，并将所述第二固定电位输出到所述输出端。
  16. 根据权利要求15所述的驱动方法，其中，所述第二阶段包括第一子阶段和在所述第一子阶段之后的第二子阶段；
    在所述第一子阶段，向所述驱动电极施加所述第一交流电压信号，其中，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的第一数据电压传输至所述第三节点，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号不导通；
    在所述第二子阶段，所述感应电极感应所述第二交流电压信号，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号导通。
  17. 根据权利要求16所述的驱动方法，其中，所述像素电路还包括第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所述第三节点；
    所述第二阶段还包括位于所述第一子阶段和所述第二子阶段之间的第三子阶段；
    在所述第一子阶段和所述第二子阶段，所述第二控制电路响应于所述第二控制信号不导通；
    在所述第三子阶段，所述第二控制电路响应于所述第二控制信号导通，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
  18. 根据权利要求17所述的驱动方法，其中，所述第二阶段还包括在所述第一子阶段之前的第四子阶段；
    在所述第四子阶段，将所述第二节点电位复位到第一初始电位，其中，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
  19. 根据权利要求15-18任意一项所述的驱动方法，其中，所述像素电路还包括第二控制电路，与所述第二电压端和所述第三节点电连接，被配置为响应于第二控制信号将所述第二电压端的电位传输至所述第三节点；
    所述第一阶段包括第五子阶段、在所述第五子阶段之后的第六子阶段和所述第六 子阶段之间的第七子阶段；
    在所述第五子阶段，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的第二数据电压传输至所述第三节点，所述第二开关电路响应于所述第二扫描信号导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号不导通；
    在所述第六子阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号导通；
    在所述第七子阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通，所述第二控制电路响应于所述第二控制信号不导通。
  20. 根据权利要求19所述的驱动方法，其中，所述第一阶段还包括在所述第五子阶段之前的第八子阶段；
    在所述第八子阶段，将所述第二节点电位复位到第二初始电位，其中，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号不导通，所述第三开关电路响应于所述第三扫描信号不导通。
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