WO2020232586A1 - 一种半导体发光元件及发光装置 - Google Patents

一种半导体发光元件及发光装置 Download PDF

Info

Publication number
WO2020232586A1
WO2020232586A1 PCT/CN2019/087486 CN2019087486W WO2020232586A1 WO 2020232586 A1 WO2020232586 A1 WO 2020232586A1 CN 2019087486 W CN2019087486 W CN 2019087486W WO 2020232586 A1 WO2020232586 A1 WO 2020232586A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
type semiconductor
semiconductor layer
conductivity type
electrode
Prior art date
Application number
PCT/CN2019/087486
Other languages
English (en)
French (fr)
Inventor
张东炎
吴俊毅
刘�文
王晶
郭桓邵
李慧文
王笃祥
Original Assignee
天津三安光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 天津三安光电有限公司 filed Critical 天津三安光电有限公司
Priority to PCT/CN2019/087486 priority Critical patent/WO2020232586A1/zh
Priority to CN201980004732.9A priority patent/CN111164767B/zh
Priority to TW108145797A priority patent/TWI728595B/zh
Publication of WO2020232586A1 publication Critical patent/WO2020232586A1/zh
Priority to US17/527,033 priority patent/US20220077370A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds

Definitions

  • the present invention relates to LED light-emitting elements.
  • LED light-emitting elements have been widely used in equipment in many fields such as lighting, display, traffic signal, data storage, and medical equipment. There are many factors that affect the light efficiency of LED light-emitting elements, including the internal quantum efficiency of the epitaxial structure, the heat dissipation of the substrate, the light-emitting efficiency of the light-emitting side, and so on.
  • the epitaxial growth substrate can be replaced with a higher thermal conductivity substrate, because the thermal conductivity of silicon or silicon carbide or metal substrates is higher than that of gallium arsenide.
  • the current commercial method is to use bonding
  • the combined process realizes the transfer of the substrate to the silicon or silicon carbide or metal substrate.
  • the N-type epitaxial layer reverses upward, and a contact layer and electrode layer need to be designed on the N-type GaAs epitaxial layer, which will cause the problem of shading the electrode.
  • a metal reflective layer can be provided.
  • the combination of the metal reflective layer and the low refractive index electrical insulating layer will improve the reflection effect more significantly.
  • the refractive index of the semiconductor sequence is about 2.5 to 3.0.
  • a transparent electrical insulating layer lower than the refractive index of the semiconductor sequence is usually set between the metal reflective layer and the semiconductor sequence. The light radiated from the semiconductor sequence will be electrically insulated by the low refractive index.
  • the refractive index of the currently used electrical insulating layer is generally lower than 2.0, and at least one of silicon nitride, silicon oxide, magnesium fluoride, calcium fluoride, etc. is mainly used.
  • fluorides such as calcium fluoride and magnesium fluoride have a lower refractive index, lower than 1.5, and a high light transmittance. Therefore, the use of such fluorides can significantly improve the light extraction efficiency.
  • the present invention provides the following semiconductor light emitting device, including:
  • a semiconductor light emitting sequence includes a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer;
  • the electrically insulating layer covers a part of the area on one side of the second conductive type semiconductor layer to form an electrically insulating area, and the uncovered part of the area on the side of the second conductive type semiconductor layer is an electrical contact area,
  • the second conductivity type semiconductor layer includes a fluorine-containing region.
  • the fluorine-containing region is located at the interface between the second conductive type semiconductor layer and the insulating layer, and extends into the second conductive type semiconductor layer.
  • the electrically insulating layer is fluoride.
  • the fluorine-containing region is formed by diffusion of fluorine element in the electrical insulating layer.
  • the thickness of the fluorine-containing region in the second conductive type semiconductor layer is 1 to 1000 nm, and more preferably, the thickness of the fluorine-containing region is 10 to 100 nm.
  • the fluorine-containing element concentration of the fluorine-containing region is between 1E17 and 1E21/cm 3 .
  • the second conductivity type semiconductor layer includes a current spreading layer, and the fluorine-containing region is located at the interface between the current spreading layer and the electrically insulating layer, and extends into the current spreading layer of the second conductivity type semiconductor layer.
  • the current spreading layer is GaP or GaAs or AlGaInP.
  • the thickness of the fluorine-containing region is not higher than the thickness of the current spreading layer.
  • the thickness of the fluorine-containing region is higher than the thickness of the current spreading layer.
  • the fluorine-containing area and the laterally surrounding area are homogeneous areas.
  • the first conductive type semiconductor layer has a first electrode on one side, the first electrode includes a main pad electrode for external wiring, and the fluorine-containing region is located at least in the vertical direction of the main pad electrode On the second conductivity type semiconductor layer.
  • the first conductive type semiconductor layer has a first electrode on one side, the first electrode includes a main pad electrode for external wiring, and the fluorine-containing region is mainly located in the vertical direction of the main pad electrode On the second conductivity type semiconductor layer.
  • the first conductivity type semiconductor layer, the light emitting layer and the second conductivity type semiconductor layer are AlxInyGa1-x-yP (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) and or AlzGa1-zAs (0 ⁇ z ⁇ 1).
  • a second electrode is provided on the side of the electrically insulating layer away from the second conductive type semiconductor layer.
  • the electrically insulating layer has a plurality of openings passing through its thickness, and the electrical contact area is inside the opening.
  • an electrical contact is formed between the second electrode and one side of the second conductive type semiconductor layer through an ohmic contact layer, and the ohmic contact layer is made of a transparent conductive layer, covering at least the electrical contact area.
  • an electrical contact is formed between the second electrode and one side of the second conductive type semiconductor layer through an ohmic contact layer, and the ohmic contact layer material is a combination of at least two metals.
  • a metal reflective layer is included between the second electrode and one side of the second conductive type semiconductor layer.
  • the present invention also provides the following method for manufacturing a semiconductor light-emitting element, which includes:
  • Obtain a semiconductor light emitting sequence including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;
  • fluorine element diffuses into the second conductivity type semiconductor layer to form a fluorine-containing region
  • the first electrode is made to be electrically connected to the first conductivity type semiconductor layer, and the second electrode is to be electrically connected to the second conductivity type semiconductor layer.
  • the temperature of the high-temperature diffusion treatment is 360-600°C, and the time is 0.01-60 min.
  • an ohmic contact is formed on the side of the second conductive type semiconductor layer not covered by the electrical insulating layer.
  • the ohmic contact is a block formed by a transparent conductive layer or a combination of multiple metals.
  • the first electrode is located on the side of the semiconductor layer of the first conductivity type and includes a main pad electrode for external wiring.
  • the high-temperature diffusion treatment causes the fluorine-containing region to be mainly formed on the main electrode for external wiring.
  • the disk electrode is in the second conductivity type semiconductor layer in the vertical direction.
  • an ohmic contact material is grown on the side of the second conductivity type semiconductor layer not covered by the electrical insulating layer, and the ohmic contact material is a combination of at least two metals.
  • the step of forming the ohmic contact between the ohmic contact material and the second conductivity type semiconductor layer is the same step as the high temperature diffusion treatment.
  • the second electrode includes a metal reflective layer.
  • the present invention also provides the following method for manufacturing a semiconductor light-emitting element, which includes:
  • Obtain a semiconductor light emitting sequence including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;
  • the fluorine element of the metal fluoride salt diffuses into the second conductivity type semiconductor layer to form a fluorine-containing region
  • the first electrode is made to be electrically connected to the first conductivity type semiconductor layer, and the second electrode is to be connected to the second conductivity type semiconductor layer.
  • the high-temperature fusion step of the ohmic contact block and the second conductive type semiconductor layer is the same step as the high-temperature diffusion treatment step of the electrical insulating layer.
  • the high-temperature fusion step on the side of the ohmic contact block and the second conductive type semiconductor layer is earlier than the high-temperature diffusion treatment step of the electrical insulating layer.
  • the light-emitting device is a package or a lighting device or a display device.
  • the fluorine-containing area is formed at least in the second conductivity type semiconductor layer vertically below the main pad electrode of the first electrode, which increases the local sheet resistance of the area and improves the resistance under the main pad electrode of the first electrode.
  • the current dispersion in the second conductivity type semiconductor layer promotes the lateral diffusion of the current to the surrounding area of the main pad electrode away from the first electrode, thereby reducing the light emission under the first electrode, thereby reducing the light shielding of the first electrode. Improve the uniform dispersion of light.
  • the fluorine-containing region comes directly from the electrical insulating layer and can be formed by high-temperature diffusion treatment, the process is simple, and the feasibility is high.
  • the fluorine-containing region is located at least vertically below the main pad electrode of the first electrode, and can be formed only in the current spreading layer included in the second conductive type semiconductor layer, effectively blocking the current in the current spreading layer.
  • the fluorine-containing region may be formed only vertically below or near the periphery of the main pad electrode of the first electrode. This prevents the current from being concentrated under the main pad electrode of the first electrode, promotes the lateral diffusion of the current to the surrounding area of the main pad electrode of the first electrode, and prevents the voltage from rising too high.
  • Fig. 1 is a schematic diagram of a conventional semiconductor light-emitting element structure.
  • Fig. 2 is a schematic diagram of the structure of a first electrode of a conventional semiconductor light emitting element.
  • 3-6 are schematic diagrams of the structure of the semiconductor light-emitting element of the first embodiment.
  • FIG. 7 is a SIMS element analysis diagram of the semiconductor light-emitting device of Example 1.
  • FIG. 7 is a SIMS element analysis diagram of the semiconductor light-emitting device of Example 1.
  • FIGS 8-11 are schematic diagrams of the structure of the semiconductor light-emitting element of the first embodiment.
  • Fig. 12 is a flow chart of the manufacturing method of the light-emitting element of the first embodiment.
  • FIGS 13-20 are schematic diagrams of the structure of the semiconductor light-emitting element of the second embodiment.
  • FIG. 21 is a flow chart of the manufacturing method of the light-emitting element of the second embodiment.
  • 22-26 are schematic diagrams of the structure of the semiconductor light-emitting element of the third embodiment.
  • Fig. 27 is a flow chart of the manufacturing method of the light-emitting element of the third embodiment.
  • Fig. 1 is a traditional semiconductor light-emitting element as described in the background art, including:
  • a semiconductor light emitting sequence includes a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8;
  • a partial area on one side of the second conductivity type semiconductor layer 8 is covered by the electrical insulating layer 7 to form an electrical contact area, and a partial area on the side not covered by the electrical insulating layer 7 is an electrical contact area.
  • the electrically insulating layer is usually silicon oxide or silicon nitride or calcium fluoride or magnesium fluoride.
  • a plurality of openings are usually formed on the electrical insulating layer, and the electrical contact areas are inside the openings.
  • the first electrode 11 includes a main pad electrode (generally circular or elliptical) for external wiring and extended extended electrode strips, which are arranged on the side of the first conductivity type semiconductor layer 10, as shown in FIG. 2.
  • An ohmic contact layer 6 or ohmic contact block is usually arranged in the electrical contact area, and a second electrode 1 is arranged on one side of the electrical insulating layer 7 and the same side of the ohmic contact layer 6 or ohmic contact block.
  • the line marked with an arrow in FIG. 1 indicates the transmission path of the current.
  • the external current flows from the second electrode 1 through the ohmic contact area on the side of the second conductivity type semiconductor into the semiconductor light emitting sequence and reaches the main pad electrode of the first electrode 11. And flow out.
  • the main pad electrode of the first electrode 11 is a current concentrated area, in order to block the current from flowing vertically under the main pad electrode of the first electrode through the semiconductor light emitting sequence to the side of the second electrode 1, the main pad electrode of the first electrode is vertical There is no opening design on the electrical insulation layer directly below, that is, an electrical insulation barrier area is formed under the main pad electrode of the first electrode.
  • the present invention provides the following semiconductor light-emitting element, which can further improve the uniform dispersion of current compared with the traditional design, as shown in FIG. 3, which includes:
  • a semiconductor light emitting sequence includes a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8;
  • a partial area on one side of the second conductivity type semiconductor layer 8 covers the electrical insulating layer 7 to form an electrical insulating area, and the uncovered partial area is an electrical contact area.
  • the electrically insulating layer 7 is fluoride, and the electrically insulating layer 7 partially covers one side of the second conductive type semiconductor layer 8 through a plurality of openings.
  • the second conductive type semiconductor layer 8 includes a fluorine-containing region 802 therein.
  • the fluorine-containing region is formed by high-temperature diffusion of fluoride into the second conductivity type semiconductor layer 8. After testing, the fluorine-containing region can increase the local sheet resistance of the second conductivity type semiconductor layer 8 to form a high resistance region.
  • the first electrode 11, including the main pad electrode for external wiring, is arranged on the side of the first conductivity type semiconductor layer 10, and the fluorine-containing region 802 is located at least vertically below the main pad electrode of the first electrode of the second conductivity type In the semiconductor layer 8.
  • the approximate current path indicated by the arrowed line As shown in FIG. 3, the approximate current path indicated by the arrowed line. Since the fluorine-containing region 802 increases the local sheet resistance, the current flowing in the second conductivity type semiconductor layer 8 under the main pad electrode of the first electrode is further increased. Blocking, thereby avoiding current concentration under the main pad electrode of the first electrode, promoting the current to spread laterally to the surrounding area of the main pad electrode of the first electrode, facilitating uniform current distribution, thereby improving uniform light dispersion.
  • the light-emitting element provided by this embodiment will be described in detail below.
  • FIG. 4 it includes a substrate 2; a conductive bonding layer 3 is formed on the substrate; a metal reflective layer 5 located on the conductive bonding layer 3, and the metal reflective layer 5 is located on the barrier layer 4, the electrical insulating layer is located on the metal reflective layer 5; the semiconductor sequence is located on the electrical insulating layer, the first electrode 11 is located on the semiconductor sequence; and the back metal layer 1 is located on the lower side of the substrate.
  • the semiconductor layer sequence has a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8.
  • the first conductivity type is n-type or p-type
  • the second conductivity type is p-type or n-type
  • the first conductivity type is different from the second conductivity type.
  • the first conductivity type is n-type
  • the second conductivity type is p-type
  • the first conductivity type semiconductor layer 10 includes at least an n-type cladding layer
  • the second conductivity type semiconductor layer 8 that is different from the first conductivity type includes at least a p-type cladding layer 81, sandwiched between the p-type cladding layer and the n-type cladding layer.
  • the light-emitting layer 9 of the active layer that can emit light of a predetermined wavelength between the type cladding layers; the light-emitting layer, the n-type cladding layer, and the p-type cladding layer are respectively formed of III-V group compound semiconductors.
  • it can be formed by using compound semiconductors such as GaAs, GaP, and InP, ternary compound semiconductors such as InGaAs, AlInP, and AlGaAs, or quaternary compound semiconductors such as AlGaInP.
  • compound semiconductors such as GaAs, GaP, and InP
  • ternary compound semiconductors such as InGaAs, AlInP, and AlGaAs
  • quaternary compound semiconductors such as AlGaInP.
  • the light-emitting layer 10 (which is formed by the body of undoped AlGaInP, AlInP, or AlGaAs-based compound semiconductors) is an n-type cladding layer and a p-type cladding layer (both are made of p-type AlGaInP, AlInP Or AlGaAs) sandwiched, the region where the emission wavelength is controlled by the composition of the light-emitting layer can be between visible light such as red, yellow, and green, and invisible light such as infrared light.
  • the semiconductor sequence further includes a current spreading layer 82 located on the surface side of the second conductive semiconductor layer, such as a p-GaP layer or p-GaAs.
  • the doping concentration is at least 8E17 or more, and the doping material can be Mg, Zn, and C.
  • the substrate 2 can be used to support the light-emitting sequence of the semiconductor layer and other layers or structures on it, and its material is a conductive material.
  • Conductive materials include but are not limited to metals, metal alloys, silicon, silicon carbide, graphite, etc.
  • the conductive bonding layer 3 is a bonding layer used in conventional bonding processes such as gold-gold bonding, gold-tin bonding, or gold-indium bonding layer.
  • the metal reflective layer 5 can reflect light from the semiconductor sequence, and its material can be a metal material, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead ( Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W) or alloys of the above materials.
  • a barrier layer 4 may also be included between the reflective layer and the substrate, which is located on the lower surface of the reflective layer. The barrier layer 4 can prevent the material of the reflective layer from diffusing to the electrode layer, destroying the structure of the reflective layer, and avoid reducing the reflectivity of the reflective layer.
  • the reflective layer such as silver is selected, and the thickness is 250-750 nm.
  • the electrically insulating layer 7 covers a partial area on one side of the second conductive type semiconductor layer 8 to form an electrically insulating area.
  • the electrically insulating layer 7 is made of a material with a low refractive index, more preferably 1.2 to 1.5.
  • materials are specifically fluorides, such as magnesium fluoride (MgF2) and calcium fluoride (GaF2). It can be obtained by electron beam evaporation or high temperature evaporation methods. Among them, different evaporation processes, such as evaporation temperature, will have slightly different refractive indices.
  • Fluoride generally has a lower refractive index than oxides or nitrides such as silicon oxide or silicon nitride.
  • the light emitted by the semiconductor light emitting sequence When the light emitted by the semiconductor light emitting sequence is directed to the translucent electrically insulating layer, it is at the interface between the semiconductor sequence and the electrically insulating layer The proportion of total reflection is increased.
  • the light that does not form total reflection at the interface between the semiconductor sequence and the electrically insulating layer passes through the electrically insulating layer to the metal reflective layer 5 side, and is reflected on the metal reflective layer 5 back to the semiconductor sequence, from the light emitting side or from the side of the semiconductor sequence
  • the wall emits light, thereby improving the light-emitting efficiency of the light-emitting element.
  • the thickness of the electrically insulating layer is 0.1 to 500 nm, more preferably 10 to 100 nm.
  • the electrical insulation layer 7 includes a plurality of through holes penetrating through the thickness direction, and the plurality of through holes are independently, uniformly or non-uniformly distributed in the electrical insulation.
  • the area on the side of the second conductivity type semiconductor layer exposed by the opening of the through hole is the electrical contact area
  • the area covered by the electrical insulating layer 7 is the electrical insulating area.
  • the opening size of the through hole on the side of the semiconductor sequence is less than or equal to the size of the opening on the opposite side away from the side of the semiconductor sequence.
  • the size of the opening on the side of the semiconductor sequence of the through hole is smaller than the size of the opening on the opposite side away from the side of the semiconductor sequence.
  • the through hole is on the side of the semiconductor sequence.
  • the first opening size D1 is smaller than the second opening size D2, and the first opening size D1 is 1-20 ⁇ m.
  • the side walls of the plurality of through holes of the electrical insulating layer 7 are vertical or the side walls are relatively inclined planes or relatively inclined curved surfaces, and the electrical insulating layer 7 and the metal reflective layer 5 are adjacent to each other.
  • the included angle between the surface and the surface of the side wall of the hole is greater than 90°, more preferably, greater than 90°C and less than or equal to 170°.
  • the ohmic contact layer 6 can be a transparent conductive layer, such as a well-known inorganic metal oxide, ITO or IZO, etc., with a thickness of 0.0001 ⁇ m-0.6 ⁇ m, 0.0001 ⁇ m-0.5 ⁇ m, 0.0001 ⁇ m-0.4 ⁇ m, 0.0001 ⁇ m-0.3 ⁇ m , 0.0001 ⁇ m-0.2 ⁇ m, 0.2 ⁇ m-0.5 ⁇ m, 0.3 ⁇ m-0.5 ⁇ m, 0.4 ⁇ m-0.5 ⁇ m, 0.2 ⁇ m-0.4 ⁇ m, or 0.2 ⁇ m-0.3 ⁇ m.
  • a transparent conductive layer such as a well-known inorganic metal oxide, ITO or IZO, etc.
  • the sidewalls of the hole of the electrically insulating layer 7 and the front surface close to the reflective layer are covered by a transparent conductive layer.
  • the transparent conductive layer can be used as an adhesion layer to ensure the adhesion between the metal reflective layer and the electrically insulating layer. Sex.
  • the first electrode 11 is formed on the semiconductor sequence in contact with and electrically connected to the first conductive type semiconductor layer 10.
  • the first electrode 11 includes a main pad electrode for external wiring and an extended electrode 1103 extending from the independent pad electrode.
  • the main pad electrode for external wiring uses a multilayer metal, including at least an ohmic contact layer 1101 that forms an ohmic contact with the first conductivity type semiconductor layer 10, which is made of gold germanium, gold beryllium, gold germanium nickel, gold zinc, etc. At least one type of formation, and also includes a wire bonding layer 1102 for external wire bonding and metal fusion.
  • the wire bonding layer 1102 is formed of at least one of gold, aluminum, copper, etc.
  • the extended electrode is preferably gold germanium nickel, gold germanium, etc. Combination formation.
  • the bonding layer 1102 and the ohmic contact layer 1101 may also include other layers, such as a diffusion barrier layer, to prevent elements in the ohmic contact layer from diffusing into the bonding layer.
  • the back metal layer 1 of the substrate 2 can be defined as a second electrode for external electrical connection.
  • the first electrode and the second electrode provide different electrode polarities to form current input and output terminals, respectively.
  • the hole of the electrically insulating layer 7 is not located vertically below the main pad electrode for external wiring.
  • the electrically insulating layer 7 not only covers the area on the side of the second conductivity type semiconductor layer perpendicular to the main pad electrode of the first electrode, but also covers other positions on the side of the second conductivity type semiconductor layer to provide multiple openings. Multiple electrical contact areas are formed, so the fluorine-containing area 821 is not only formed vertically below the main pad electrode of the first electrode, but also formed at the interface between the electrical insulating layer 7 and the second conductive type semiconductor layer 8 on the entire surface , And extend from the interface to a certain thickness in the second conductivity type semiconductor layer 8. Specifically, the fluorine element of the electrically insulating layer 7 diffuses into the second conductive type semiconductor layer 8 to form a fluorine-containing region 821.
  • the fluorine-containing region 821 may be formed by the electrically insulating layer 7 in the second conductive type semiconductor layer 9 through a high temperature treatment process.
  • the temperature of the high-temperature treatment process is 300°C or higher, more preferably 360-600°C, and the time is 0.01-60 min, more preferably 420°C or higher, and more preferably 460-500°C, and the time is 1 min-30 min.
  • the fluorine element can be diffused into the second conductive semiconductor layer, resulting in the increase of the sheet resistance of the material of the second conductive type semiconductor layer, and the formation of the second conductive type semiconductor layer at the interface covered by the electrical insulating layer 7
  • the high-resistance area of a certain thickness will block the lateral and vertical diffusion of current, especially the barrier function is formed vertically below the main pad electrode of the first electrode, which can improve the blocking current to the current diffusion under the main pad electrode of the first electrode
  • the effect is to promote the dispersion of current to the openings of the electrical insulating layer and improve the uniform dispersion of light.
  • the fluorine-containing region 821 formed from the side of the electrically insulating layer 7 is located at least in the current spreading layer 82 of the second conductive type semiconductor layer 8.
  • the fluorine element will diffuse into other layers belonging to the second conductivity type semiconductor layer 8, such as reaching the transition layer of aluminum gallium indium phosphorus or further reaching the p-type cladding layer.
  • the thickness of the fluorine-containing region 821 does not exceed the thickness of the current spreading layer 82 or the thickness of the fluorine-containing region 821 is lower than the thickness of the current spreading layer 82.
  • the current spreading layer is p-GaP.
  • the thickness of the current spreading layer p-GaP is 5 nm to 2 ⁇ m.
  • the fluorine concentration in the fluorine-containing region is not less than 1E17/cm 3 , and more preferably, the fluorine concentration in the fluorine-containing region is between 1E17 and 1E21/cm 3 .
  • FIGS. 5-11 are schematic structural diagrams corresponding to each step. It includes the following steps:
  • Obtain a semiconductor light emitting sequence on a growth substrate including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer.
  • the semiconductor light emitting sequence is obtained by MOCVD epitaxial growth method on the growth substrate 101.
  • the growth substrate 101 is gallium arsenide in this embodiment. It should be noted that the substrate is not limited to gallium arsenide. It can be other substrates that can implement growth semiconductor light-emitting sequences can also be used instead.
  • the semiconductor sequence on the gallium arsenide substrate includes a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8 which are sequentially grown and stacked.
  • the first conductivity type semiconductor layer 10 includes an n-type capping layer
  • the second conductivity type semiconductor layer includes a p-type capping layer.
  • the n-type capping layer and the p-type capping layer may specifically be aluminum indium phosphorous, and the light emitting layer is aluminum gallium indium phosphorous.
  • a buffer layer, an over layer, an etching stop layer, etc. may be selectively included between the growth substrate and the semiconductor sequence.
  • the first conductivity type semiconductor layer may further include n-type gallium arsenide as an ohmic contact layer for subsequent ohmic contact of the first electrode.
  • the second conductivity type semiconductor layer 8 includes a p-type current spreading layer 82. Due to the current spreading and ohmic contact on one side of the second conductivity type semiconductor layer, the current spreading layer 82 in this embodiment is p-type gallium phosphide.
  • An electrical insulating layer is vapor-deposited on one side of the second conductive type semiconductor layer 8.
  • the electrical insulating layer 7 is preferably magnesium fluoride or calcium fluoride.
  • the thickness of the electrically insulating layer 7 ranges from 10 nm to 500 nm.
  • the temperature of the vapor deposition is at least 20°C, or preferably 200°C. The higher the temperature, the denser the deposited fluoride.
  • the electrical insulating layer is formed with openings through the thickness, and the openings are preferably multiple, and the openings are not formed vertically below the main pad electrode of the first electrode.
  • a plurality of mask patterns can be formed on the side of the second conductivity type semiconductor layer.
  • the mask patterns are block-shaped, or preferably have a wide top and a narrow bottom.
  • the pattern can be a metal or insulating layer or a combination of both.
  • the sidewall of the opening can be obtained to be inclined, so that the subsequent ohmic contact layer and reflective layer can cover the surface of the insulating layer as smoothly and uniformly as possible, especially the through hole
  • the angle between the sidewall of the opening and the surface of the insulating layer is as smooth as possible.
  • FIG. 6 provides a schematic plan view from the side of the electrical insulating layer 7.
  • the shape of the opening is a circle, an oval, a square, or a polygon.
  • the high-temperature treatment After the electrical insulating layer is formed, a high-temperature treatment is carried out.
  • the conditions of the high-temperature treatment the gas atmosphere is preferably an inert gas, the temperature is 460-500°C, and the time is 10-30 min.
  • the high temperature treatment realizes the diffusion of fluorine ions in the electrical insulating layer 7 into the current spreading layer 82 of the second conductive semiconductor layer 8. It should be noted here that by controlling different temperatures and times, the thickness of fluoride ion diffusion can be adjusted.
  • Figure 8 provides the SIMS element analysis of the local thickness direction of the structure shown in Figure 7, including the concentration analysis of Ga, P, F, C and Mg elements, where the abscissa is the thickness and the left ordinate is the element concentration.
  • the three vertical lines in the figure indicate different thickness positions.
  • the first line shows the position at the interface between the electrical insulating layer fluoride and GaP
  • the second line shows the position corresponding to the depth of fluorine diffusion
  • the third line The position indicated by the straight line corresponds to that the interface between the highly doped GaP contact layer and the non-highly doped GaP is another interface of GaP. It can be seen from the figure that the thickness of GaP is not less than 500nm, and the diffusion of F element into GaP is not more than 40nm.
  • the ohmic contact layer 6 such as ITO or IZO is preferably made by sputtering or evaporation.
  • the ohmic contact layer 6 covers the opening of the electrical insulating layer 7 and contacts the second conductivity type semiconductor layer, and covers the surface side of the electrical insulating layer 7, and the thickness of the ohmic contact layer is 1-500 nm.
  • the reflective layer 5 is vapor-deposited or electroplated, and the material of the reflective layer 5 is silver.
  • the vapor deposition barrier layer 4 prevents metallic silver from diffusing into the bonding layer.
  • the material of the barrier layer 4 is preferably at least one of titanium, platinum, chromium, and the like.
  • the bonding layer 3 is formed by evaporation, and the bonding layer 3 can be composed of materials such as gold, indium, or tin.
  • a supporting substrate 2 is selected, and the bonding layer 3 on the semiconductor light emitting sequence on the growth substrate 101 is bonded to the supporting substrate 2, and the bonding adopts a high temperature and high pressure method.
  • the supporting substrate 2 is a silicon substrate.
  • the growth substrate 101 is removed; the growth substrate 101 can be removed by grinding or wet etching.
  • the first electrode 11 is formed on the front surface, and the back metal layer 1 is formed on the supporting substrate 2 as the second electrode.
  • the first electrode 11 includes a main pad electrode, the main pad electrode includes an ohmic contact layer 1101 and a wire bonding layer 1102, and includes an extension electrode 1103 extending around the main pad electrode.
  • the ohmic contact layer 1101 gallium arsenide of the first conductive type semiconductor layer 10 preferably remains under the extended electrode 1103 of the first electrode 11, and the remaining ohmic contact layer 101 is etched away.
  • the back metal layer 1 is usually made of materials such as gold or platinum.
  • the surface and the rear sidewall of the semiconductor light-emitting sequence can be further etched to form a roughened surface or pattern to facilitate light emission.
  • the semiconductor light-emitting sequence is separated into a plurality of unit regions through a separation process, and the sidewall and surface of the semiconductor light-emitting sequence are covered with an insulating protective layer.
  • the reflective layer, the barrier layer, the bonding layer, and the substrate are further separated to form a plurality of single light-emitting elements.
  • FIG. 12 provides a flow chart of the manufacturing method of the light-emitting element of this embodiment.
  • a semiconductor light emitting element which includes a semiconductor light emitting sequence, and the semiconductor light emitting sequence includes a first conductivity type semiconductor layer 10 and a light emitting layer 9. And the second conductivity type semiconductor layer 8;
  • the electrically insulating layer 7 on the side of the second conductive type semiconductor layer 8 has multiple openings, and the side of the second conductive type semiconductor layer is set as an electrical contact area and an electrically insulating area.
  • the opening is filled with ohmic contact blocks 14.
  • ohmic contact blocks 14 There are multiple ohmic contact blocks 14 but not formed under the main pad electrode for injecting current outside the first electrode.
  • the ohmic contact block 14 has a block shape, and the metal material is at least one of gold germanium, gold germanium nickel, gold zinc, gold beryllium, and the like.
  • the horizontal width of each ohmic contact block 14 is 1-10 ⁇ m, and the thickness of the ohmic contact block 14 is 1-500 nm.
  • the metal reflective layer 5 covers the ohmic contact block 14 and one side of the electrically insulating layer 7.
  • the electrically insulating layer 7 is fluoride, specifically magnesium fluoride and calcium fluoride.
  • the electrical insulating layer 7 is subjected to high temperature treatment to promote the diffusion of fluorine ions into the second conductive type semiconductor layer 8 to form a fluorine-containing region, which has a current blocking effect.
  • the fluorine ions diffuse at most to the entire thickness direction of the current spreading layer 82p-GaP included in the second conductive type semiconducting layer.
  • a sequence of semiconductor layers is obtained on the growth substrate 101 by the MOCVD epitaxial growth method.
  • the semiconductor light emitting sequence includes a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer.
  • the growth substrate 101 in this embodiment is gallium arsenide, and the semiconductor sequence on the gallium arsenide substrate includes a first conductive type semiconductor layer 10, a light emitting layer 9 and a second conductive type semiconductor layer 8 grown and stacked in sequence.
  • the first conductivity type semiconductor layer 10 includes an n-type covering layer, in this embodiment, aluminum indium phosphorous, and the second conductivity type semiconductor layer includes a p-type covering layer made of aluminum indium phosphorous, and the light emitting layer is aluminum gallium indium phosphorous. More preferably, the first conductivity type semiconductor layer may further include n-type gallium arsenide as an ohmic contact layer for subsequent ohmic contact of the first electrode. More preferably, the second conductivity type semiconductor layer 8 in this embodiment includes a p-type current spreading layer, and the current spreading layer is p-type gallium phosphide for ohmic contact of the second electrode.
  • a layer forming the ohmic contact block 141 is evaporated on one side of the second conductive type semiconductor layer and a layer of silicon oxide or silicon nitride 15 is formed by CVD. Then a layer of photoresist pattern 16 is produced.
  • the silicon oxide or silicon nitride layer 15 is etched by BOE to form a plurality of blocks.
  • an etching solution is selected to etch the gold and zinc 141, and the etching time is controlled to realize that a residual gold and zinc block is formed between each block of the silicon oxide or silicon nitride layer 15 and the second conductivity type semiconductor layer, and the gold and zinc block is used as The ohmic contact block 14 is used.
  • the horizontal width dimension of the ohmic contact block 14 is lower than the horizontal width dimension of the silicon oxide or silicon nitride layer 15 by at least 2 ⁇ m. Remove the photoresist.
  • the ohmic contact block is subjected to high-temperature fusion processing to form an ohmic contact between the ohmic contact block 14 and the current spreading layer.
  • the photoresist is removed.
  • the block formed by the ohmic contact block 14 and the silicon oxide or silicon nitride layer 15 is combined into a pattern with a wide top and a narrow bottom as a mask, and a fluoride electrical insulating layer is evaporated.
  • the thickness of the fluoride electrical insulating layer is 50-500 ⁇ m , Preferably 50-150 ⁇ m, more preferably about 100 ⁇ m.
  • BOE removes the block of silicon oxide or silicon nitride layer 15, while the surface of the block of silicon oxide or silicon nitride layer 15 and the fluoride electrically insulating layer 7 on the sidewalls will be removed, leaving ohmic
  • the contact block 14 and the fluoride electrically insulating layer 7 cover one side of the second conductive type semiconductor layer.
  • the fluoride electrical insulating layer 7 has a plurality of openings, an ohmic contact block 14 is arranged in the opening, and the sidewall of the opening is inclined.
  • the fluoride electrical insulating layer is formed, a high-temperature treatment is carried out.
  • the conditions of the high-temperature treatment the gas atmosphere is preferably an inert gas, the temperature is 460-500°C, and the time is 10-30 minutes. It should be noted here that by controlling different temperatures and times, the thickness of fluoride ion diffusion can be adjusted.
  • the fluorine ions of the electrical insulating layer 7 are diffused into the current spreading layer 82 of the second conductive semiconductor layer 8.
  • FIG. 21 provides a flow chart of the manufacturing method of the light-emitting element of this embodiment.
  • the obtained single light-emitting element is shown in FIG. 13.
  • the high-temperature fusion step is the same step as the high-temperature treatment step after the formation of the fluoride insulating layer.
  • the semiconductor light emitting sequence includes a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8;
  • the side of the second conductive type semiconductor layer 8 includes an electrical insulating layer, the fluoride electrical insulating layer has multiple openings, and one side of the second conductive type semiconductor layer is set as an electrical contact area and an electrical insulating area.
  • the opening is filled with ohmic contact blocks or ohmic contact layers.
  • the electrical insulating layer is fluoride, specifically at least one of magnesium fluoride and calcium fluoride.
  • the fluorine ions of the fluoride diffuse into the second conductive type semiconductor layer to form a current blocking region.
  • the first electrode is formed on one side of the first conductive type semiconductor layer, and includes a main pad electrode for external wiring and an extended electrode extending horizontally from the periphery of the main pad electrode.
  • the fluorine-containing region is mainly formed under the main pad electrode of the first electrode, that is, vertically below the main pad electrode for the outside of the first electrode and in the second conductivity type semiconductor layer adjacent to the surrounding area by fluorine ion diffusion. In the current blocking area, there is no fluoride ion diffusion in the electrical insulating layer around the extended electrode.
  • the side is as large as possible to circulate, and the current is transmitted through the opening of the electrical insulation layer as much as possible.
  • the electrically insulating layer 7 includes two parts, and the electrically insulating layer 71 of the first part is mainly located vertically below the main pad electrode of the first electrode 11, that is, located on the first electrode 11
  • the main pad electrode is vertically below and adjacent to the surrounding second conductivity type semiconductor layer.
  • the ratio of the area covered by the first portion of the electrically insulating layer 71 to the area of the main pad electrode of the first electrode is 1 to 1.5, and more preferably is less than or equal to 1.2 or less than or equal to 1.1.
  • the ratio of the horizontal width of the covering surface of the first portion of the electrically insulating layer 71 to the horizontal width of the main pad electrode of the first electrode is 1 to 1.25, and more preferably is less than or equal to 1.2, or less than or equal to 1.1.
  • the electrically insulating layer 7 also includes a second part of the electrically insulating layer 72, the second part of the electrically insulating layer 72 is not located under the main pad electrode of the first electrode 11, and the second part of the electrically insulating layer 72 has a through thickness direction There are a plurality of openings, and the openings provide electrical contact areas on one side of the second conductive type semiconductor layer 8.
  • the ohmic contact 6 there is an ohmic contact 6 under the electrically insulating layer 7, and the ohmic contact layer is a transparent conductive layer, such as ITO or IZO.
  • the ohmic contact 6 passes through the opening of the electrically insulating layer 72 covering at least the second part of One side of the conductive type semiconductor layer is in contact.
  • this structure can effectively stabilize the voltage.
  • the present embodiment provides the following manufacturing method, which includes:
  • a semiconductor light emitting sequence is obtained on a growth substrate 101, including a first conductivity type semiconductor layer 10, a light emitting layer 9 and a second conductivity type semiconductor layer 8.
  • the growth substrate is gallium arsenide.
  • the first part of the electrical insulating layer 71 is vapor-deposited and processed at a high temperature, and the fluorine element diffuses into the second conductive type semiconductor layer 8 to form a fluorine-containing region 801.
  • the second part of the electrical insulating layer 72 is evaporated, which covers the remaining surface of the second conductivity type semiconductor layer 8, and a plurality of openings are formed on the second part of the electrical insulating layer 72 , Forming an ohmic contact covering the electrically insulating layer 7 and the opening.
  • the remaining steps are as shown in the manufacturing process flow chart of FIG. 27, and can be manufactured by referring to the corresponding steps in the first to second embodiments to obtain the structure of the light-emitting element as shown in FIG. 22.
  • the main pad electrode of the first electrode is located vertically above the first part of the electrical insulating layer.
  • the semiconductor light emitting elements according to the first to third embodiments can obtain a package structure through a package support such as EMC or ceramic package.
  • Further packaging structures may be arranged on the circuit substrate according to application requirements, and optical members such as light guide plates, prism sheets, diffusion sheets, and fluorescent sheets may be arranged on the path of light emitted from the light emitting element.
  • Further applications can include displays such as TVs or display screens, lighting devices such as indoor lights, outdoor street lights, indicators, etc. according to application requirements.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种半导体发光元件，包括：半导体发光序列，半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层；电绝缘层覆盖第二导电类型半导体层一侧部分区域形成电绝缘区域，第二导电类型半导体层一侧未被覆盖的部分区域为电接触区域，第二导电类型半导体层中包括含氟区域。其中电绝缘层为氟化物，氟化物的氟离子通过高温扩散进入第二导电类型半导体层中形成含氟区域，含氟区域至少形成在第一电极的主焊盘电极下方的第二导电类型半导体层中，能够提高局部方块电阻，改善在第一电极的主焊盘电极下方的第二导电类型半导体层中的电流分散情况，促进电流向远离第一电极的主焊盘电极的周围区域横向扩散，从而提高光均匀分散性。

Description

一种半导体发光元件及发光装置 技术领域
本发明涉及LED发光元件。
背景技术
目前LED发光元件，已经广泛运用于照明、显示、交通信号、数据存储、医疗设备等多个领域的设备上。LED发光元件的光效的影响因素很多，其中除了外延结构的内量子效率，还包括衬底的散热性、出光侧的出光效率等等。
为了改善衬底的散热性，一方面，可置换外延生长衬底成为更高热传导的基板，因为硅或碳化硅或金属基板的热导率较砷化镓高，目前商业化的方法是采用键合工艺，实现衬底转移至硅或碳化硅或金属基板。但经过衬底转移后，N型外延层反转向上，需要在N型GaAs外延层上设计接触层及电极层，这样会造成电极遮光的问题。
另外一方面，为了改善出光效率，可设置金属反射层。其中金属反射层与低折射率的电绝缘层组合使用对于反射效果的改善会更加明显。目前半导体序列的折射率为2.5～3.0左右，在金属反射层与半导体序列之间通常设置一低于半导体序列折射率的透明电绝缘层，自半导体序列辐射的光线会在低折射率的电绝缘层与半导体序列的界面处发生大角度全反射返回至半导体序列，小角度的光线会继续穿过电绝缘层至金属反射层进行反射返回半导体序列，并从半导体序列的出光侧出光。因此，绝缘层的透明度以及折射率值为反射效果的主要影响因素。较佳的，目前使用的电绝缘层的折射率通常为低于2.0，主要使用氮化硅、氧化硅、氟化镁、氟化钙等至少之一种。其中氟化物如氟化钙、氟化镁由于具有更低折射率，低于1.5，并且具有高透光率，因此使用该类氟化物能够更显著地提高出光效率。
发明概述
技术问题
问题的解决方案
技术解决方案
基于本发明的目的，本发明提供如下一种半导体发光元件，包括：
半导体发光序列，半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层；
电绝缘层覆盖第二导电类型半导体层一侧部分区域形成电绝缘区域，第二导电类型半导体层一侧未被覆盖的部分区域为电接触区域，
其特征在于：第二导电类型半导体层中包括含氟区域。
优选的，所述含氟区域位于第二导电类型半导体层和绝缘层之间的界面处，并延伸至第二导电类型半导体层中。
优选的，所述电绝缘层为氟化物。
优选的，所述的含氟区域为电绝缘层的氟元素扩散形成。
优选的，第二导电类型半导体层中含氟区域的厚度为1～1000nm，更优选的，所述的含氟区域的厚度为10～100nm。
优选的，所述的含氟区域的含氟元素浓度介于1E17～1E21/cm 3。
优选的，所述的第二导电类型半导体层包括电流扩展层，含氟区域位于电流扩展层与电绝缘层的界面处，并延伸至第二导电类型半导体层的电流扩展层中。
优选的，所述的电流扩展层为GaP或GaAs或AlGaInP。
优选的，所述含氟区域的厚度不高于电流扩展层的厚度。
优选的，所述含氟区域的厚度高于电流扩展层的厚度。
优选的，所述含氟区域与横向周围区域为同质区。
优选的，所述的第一导电类型半导体层一侧具有第一电极，第一电极包括外部打线用的主焊盘电极，所述的含氟区域至少位于所述主焊盘电极的垂直方向上的第二导电类型半导体层中。
优选的，所述的第一导电类型半导体层一侧具有第一电极，第一电极包括外部打线用的主焊盘电极，所述的含氟区域主要位于所述主焊盘电极的垂直方向上的第二导电类型半导体层中。
优选的，所述的第一导电类型半导体层、发光层和第二导电类型半导体层分别为AlxInyGa1-x-yP(0≤x≤1，0≤y≤1)和或AlzGa1-zAs(0≤z≤1)的材料制成。
优选的，在电绝缘层远离第二导电类型半导体层的一侧具有第二电极。
优选的，电绝缘层具有多个贯穿其厚度的开口，开口内为电接触区域。
优选的，第二电极与第二导电类型半导体层一侧之间通过欧姆接触层形成电接触，欧姆接触层材料为透明导电层，至少覆盖电接触区域。
优选的，第二电极与第二导电类型半导体层一侧之间通过欧姆接触层形成电接触，欧姆接触层材料为至少两种金属的组合。
优选的，所述的第二电极与第二导电类型半导体层一侧之间包括金属反射层。
20.根据权利要求16所述的一种半导体发光元件，其特征在于：所述的电绝缘层的开口的侧壁相对于远离半导体发光序列的一侧面倾斜，倾斜的角度为大于90°，小于等于170°。
本发明同时提供如下一种半导体发光元件的制备方法，其包括：
获得半导体发光序列，包括第一导电类型半导体层、发光层和第二导电类型半导体层；
在第二导电类型半导体层表面侧形成局部覆盖的电绝缘层，电绝缘层为氟化物；
高温扩散处理，氟元素扩散至第二导电类型半导体层中形成含氟区域；
制作第一电极与第一导电类型半导体层电性连接，第二电极与第二导电类型半导体层电性连接。
优选的，高温扩散处理的温度为360～600℃，时间0.01～60min。
优选的，高温扩散处理后，在未被电绝缘层覆盖的第二导电类型半导体层一侧形成欧姆接触。
优选的，欧姆接触为透明导电层或多种金属组合形成的块状。
优选的，第一电极位于第一导电类型半导体层一侧，包括外部打线用的主焊盘电极，所述的高温扩散处理使含氟区域主要形成在第一电极外部打线用的主焊盘电极在垂直方向上的第二导电类型半导体层中。
优选的，高温扩散处理之前，在未被电绝缘层覆盖的第二导电类型半导体层一侧生长欧姆接触的材料，欧姆接触的材料为至少两种金属的组合。
优选的，所述的欧姆接触的材料与第二导电类型半导体层一侧形成的欧姆接触 步骤与高温扩散处理为同一步骤。
优选的，第二电极包括一金属反射层。
本发明同时提供如下一种半导体发光元件的制备方法，其包括：
获得半导体发光序列，包括第一导电类型半导体层、发光层和第二导电类型半导体层；
制作多处的欧姆接触块在第二导电类型半导体层一侧，
在第二导电类型半导体层表面侧形成局部覆盖的电绝缘层，电绝缘层为金属氟化盐；
高温扩散处理，金属氟化盐的氟元素扩散至第二导电类型半导体层中形成含氟区域；
制作第一电极与第一导电类型半导体层电性连接，第二电极与第二导电类型半导体层连接。
优选的，所述的欧姆接触块与第二导电类型半导体层一侧的高温熔合步骤与电绝缘层的高温扩散处理步骤为同一步骤。
优选的，所述的欧姆接触块与第二导电类型半导体层一侧的高温熔合步骤早于电绝缘层的高温扩散处理步骤。
根据本发明的半导体发光元件获得的发光装置，其中所述的发光装置为封装体或照明装置或显示装置。
发明的有益效果
有益效果
(1)含氟区域至少形成在第一电极的主焊盘电极垂直下方的第二导电类型半导体层中，提高了该区域的局部方块电阻，改善了在第一电极的主焊盘电极下方的第二导电类型半导体层中的电流分散情况，促进电流向远离第一电极的主焊盘电极的周围区域横向扩散，从而可以减少第一电极下方的发光，从而减少第一电极对出光的遮挡，提高光均匀分散性。
(2)含氟区域直接来自于电绝缘层，经过高温扩散处理即可形成，工艺简单，且可行性高。
(3)含氟区域至少位于第一电极的主焊盘电极的垂直下方，并且可仅形成在 第二导电类型半导体层所包括的电流扩散层中，对电流扩展层中电流进行有效阻挡。
(4)含氟区域可仅形成在第一电极的主焊盘电极的垂直下方或周围附近。由此避免电流集中在第一电极的主焊盘电极下方，促进电流向第一电极的主焊盘电极的周围区域横向扩散，并且避免电压上升过高。
对附图的简要说明
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1是一种传统的半导体发光元件结构示意图。
图2是传统的半导体发光元件的第一电极的结构示意图。
图3-6是实施例一的半导体发光元件的结构示意图。
图7是实施例一的半导体发光元件SIMS元素分析图。
图8-11是实施例一的半导体发光元件的结构示意图。
图12是实施例一的发光元件的制作方法步骤流程图。
图13-20是实施例二的半导体发光元件的结构示意图。
图21是实施例二的发光元件的制作方法步骤流程图。
图22-26是实施例三的半导体发光元件的结构示意图。
图27是实施例三的发光元件的制作方法步骤流程图。
发明实施例
本发明的实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
如图1所示的是正如背景技术所记载的一种传统的半导体发光元件，包括：
半导体发光序列，半导体发光序列包括第一导电类型半导体层10、发光层9和第二导电类型半导体层8；
第二导电类型半导体层8一侧部分区域被电绝缘层7覆盖形成电接触区域，未被覆盖电绝缘层7的一侧部分区域为电接触区域。电绝缘层通常为氧化硅或氮化硅或氟化钙或氟化镁。电绝缘层上通常形成多个开口，开口内为电接触区域。
第一电极11，包括外部打线用的主焊盘电极(一般为圆形或椭圆形)和延伸的扩展电极条，设置在第一导电类型半导体层10一侧，具体如图2所示。
电接触区域中通常设置有欧姆接触层6或欧姆接触块，并在电绝缘层7一侧和欧姆接触层6或欧姆接触块的同侧设置第二电极1。图1中标识有箭头的线示意电流的传输路径，外部电流自第二电极1流经第二导电类型半导体一侧的欧姆接触区域进入半导体发光序列，并至第一电极11的主焊盘电极并流出。
由于第一电极11主焊盘电极为电流集中区域，为了阻挡电流在第一电极的主焊盘电极下方垂直流经半导体发光序列至第二电极1一侧，第一电极的主焊盘电极竖直下方的电绝缘层上无开口设计，即在第一电极的主焊盘电极下方形成电绝缘阻挡区域。
根据该传统的设计类型，虽然再第一电极主焊盘电极下方有电绝缘层7做阻挡，但是在电流扩展层一侧仍然会发生电流会部分集中在第一电极的主焊盘电极的下方，导致发光区域在主焊盘电极下方或周围较明显的集中。
为此本发明提供如下一种半导体发光元件，其相对于传统的设计，能够进一步改善电流均匀分散性，具体如图3所示，其包括：
半导体发光序列，半导体发光序列包括第一导电类型半导体层10、发光层9和第二导电类型半导体层8；
第二导电类型半导体层8一侧部分区域覆盖电绝缘层7形成电绝缘区域，未被覆盖的部分区域为电接触区域。具体的所述的电绝缘层7为氟化物，电绝缘层7通过多个开口实现部分覆盖第二导电类型半导体层8一侧。
第二导电类型半导体层8中包括含氟区域802。所述的含氟区域为氟化物高温扩散至第二导电类型半导体层8中形成，经过测试，含氟区域可提高第二导电类型 半导体层8的局部方块电阻，形成高阻区域。
第一电极11，包括外部打线用的主焊盘电极，设置在第一导电类型半导体层10一侧，含氟区域802至少位于第一电极的主焊盘电极竖直下方的第二导电类型半导体层8中。
如图3所示标记有箭头的线示意的大致电流路径，由于含氟区域802提高了局部方块电阻，流入第一电极的主焊盘电极下方的第二导电类型半导体层8中的电流被进一步阻挡，由此避免电流集中在第一电极的主焊盘电极下方，促进电流向第一电极的主焊盘电极的周围区域横向扩散，利于电流均匀分布，从而提高光均匀分散性。
下面详细说明本实施例提供的发光元件，如图4所示，其包括一基板2；一导电键合层3形成在基板上；金属反射层5，位于导电键合层3上面，金属反射层5位于阻挡层4的上面，电绝缘层，位于金属反射层5上面；半导体序列，位于电绝缘层上面，第一电极11，位于半导体序列上面；以及背面金属层1，位于基板下侧。半导体层序列具有第一导电类型半导体层10、发光层9和第二导电类型半导体层8。
其中第一导电类型为n型或p型，第二导电类型为p型或n型，其中第一导电类型与第二导电类型不同。
作为可选的一种实施方式，本实施例中第一导电类型为n型，第二导电类型为p型。
半导体序列中第一导电类型半导体层10至少包括n型包覆层、与第一导电型不同的第二导电类型半导体层8至少包括p型包覆层81、夹于p型包覆层和n型包覆层之间并可发出规定波长的光的活性层的发光层9；发光层、n型包覆层和p型包覆层分别由III-V族化合物半导体形成。具体而言，可通过使用GaAs系、GaP系、InP系等化合物半导体，InGaAs系、AlInP系、AlGaAs系等三元系化合物半导体，AlGaInP系等四元系化合物半导体而形成。例如，发光层10(其由未掺杂的AlGaInP、AlInP或AlGaAs系的化合物半导体的本体形成)为n型包覆层和p型包覆层(两者分别是通过含有p型的AlGaInP、AlInP或AlGaAs而形成)夹持，通过发光层的成分调控出发光波长的区域可以介于红、黄、绿等可见光以及红外光等不可 见光。
优选地，所述的半导体序列进一步包括一层电流扩展层82位于第二导电性半导体层的表面侧，如p-GaP层或p-GaAs。掺杂浓度至少为8E17以上，掺杂材料可以为Mg、Zn、C。
所述的基板2可用以支持位于其上的半导体层发光序列与其它层或结构，其材料为导电材料。导电材料包含但不限于金属、金属合金、硅、碳化硅、石墨等。
所述的导电键合层3为金金键合、金锡键合或金铟键合层等常规的键合工艺使用的键合层。
金属反射层5可反射来自半导体序列的光，其材料可为金属材料，包含但不限于铜(Cu)、铝(Al)、锡(Sn)、金(Au)、银(Ag)、铅(Pb)、钛(Ti)、镍(Ni)、铂(Pt)、钨(W)或上述材料的合金等。反射层与基板之间还可以包括阻挡层4，位于反射层的下表面。阻障层4可防止反射层的材料扩散至电极层，破坏反射层的结构，避免反射层的反射率降低。本实施例选择反射层如银，厚度为250～750nm。
电绝缘层7覆盖第二导电类型半导体层8一侧部分区域，形成电绝缘区域。
电绝缘层7为折射率低的材料，更优选的1.2～1.5，这类材料具体为氟化物，如氟化镁(MgF2)、氟化钙(GaF2)。其可以由电子束蒸镀或高温蒸镀方法获得。其中不同的蒸镀工艺，如蒸镀温度，获得的折射率会略有差异。氟化物通常比氧化物或氮化物如氧化硅或氮化硅的折射率更低，半导体发光序列所发的光射向透光性电绝缘层时，在半导体序列与电绝缘层之间的界面形成全反射的比例增加。在半导体序列与电绝缘层之间的界面未形成全反射的光穿过电绝缘层到达金属反射层5侧，在金属反射层5上经过反射回半导体序列，从半导体序列的出光侧或从侧壁出光，因而提升发光元件的出光效率。电绝缘层的厚度为0.1～500nm，更优选的为10～100nm。
为了在第二导电类型半导体层8一侧形成电接触区域与电绝缘区域，电绝缘层7包含多个贯穿孔贯穿厚度方向，多个贯穿孔独立地、均匀地或非均匀地分布在电绝缘层7上；贯穿孔的开口暴露的第二导电类型半导体层一侧的区域即电接触区域，电绝缘层7覆盖的区域即电绝缘区域。优选的，贯穿孔的在半导体序列一 侧开口尺寸小于或等于远离半导体序列一侧的相反面上的开口尺寸。更优选的，贯穿孔的在半导体序列一侧开口尺寸小于远离半导体序列一侧的相反面上的开口尺寸，具体的，如图3所示，所述的贯穿孔在半导体序列一侧的面上具有一个第一开口尺寸D1，在远离半导体序列一侧的相反面上有第二开口尺寸D2、该第一开口尺寸D1和第二开口尺寸D2分别定义开口在纵向截面的直径或宽度。第一开口尺寸D1小于第二开口尺寸D2，第一开口的尺寸D1为1～20μm。由此，所述的电绝缘层7的多个贯穿孔的侧壁为垂直的或者侧壁为相对倾斜的平面或相对倾斜的曲面，所述的电绝缘层7与金属反射层5临近的一表面与孔侧壁的面之间的夹角大于90°，更优选的，大于90℃小于等于170°。
欧姆接触层6可以为透明导电层，如悉知的无机金属氧化物，ITO或IZO等，其厚度为0.0001μm-0.6μm，0.0001μm-0.5μm，0.0001μm-0.4μm，0.0001μm-0.3μm，0.0001μm-0.2μm，0.2μm-0.5μm，0.3μm-0.5μm，0.4μm-0.5μm，0.2μm-0.4μm，或者0.2μm-0.3μm。
如图4所示，电绝缘层7的孔的侧壁以及靠近反射层的正面都被透明导电层覆盖，透明导电层可以作为粘附层，保证金属反射层与电绝缘层之间的粘附性。
第一电极11形成在半导体序列之上与第一导电类型半导体层10接触并电连接，第一电极11包括外部打线用的主焊盘电极以及自主焊盘电极延伸的扩展电极1103。外部打线用的主焊盘电极采用多层金属，其中至少包括与第一导电类型半导体层10形成欧姆接触的欧姆接触层1101，该层为金锗、金铍、金锗镍、金锌等至少一种形成，还包括外部打线并提供金属熔合的打线层1102，打线层1102为金、铝、铜等至少一种形成，所述的扩展电极优选金锗镍、金锗、等组合形成。打线层1102与欧姆接触层1101之间还可以包括其它的层，如扩散阻挡层，防止欧姆接触层中的元素扩散至打线层中。
基板2的背面金属层1可定义为第二电极，用于外部电连接，第一电极和第二电极提供不同的电极极性，分别形成电流输入和输出端。
根据本实施例，电绝缘层7的孔不位于外部打线用的主焊盘电极的垂直下方。
根据本实施例。电绝缘层7不仅覆盖在第一电极的主焊盘电极垂直下方的第二导电类型半导体层一侧的区域，而且还覆盖在第二导电类型半导体层一侧的其 它位置，以提供多处开口形成多处的电接触区域，因此含氟区域821不仅形成在第一电极的主焊盘电极的垂直下方，也可形成在整面的电绝缘层7与第二导电类型半导体层8的界面处，并自界面处延伸至第二导电类型半导体层8中一定的厚度。具体的，电绝缘层7的氟元素扩散至第二导电类型半导体层8中形成含氟区域821。含氟区域821可通过高温处理工艺使电绝缘层7在第二导电类型半导体层9中形成。高温处理工艺的温度300℃以上，更佳的为360～600℃，时间为0.01～60min，更佳的温度为420℃以上，更佳的为460～500℃，时间1min～30min。
通过上述处理，可使氟元素扩散至第二导电性半导体层中，导致第二导电类型半导体层的材料的方块电阻提升，形成自电绝缘层7覆盖的界面处深入第二导电类型半导体层中一定厚度的高阻区域，会阻挡电流的横向以及纵向扩散，尤其是第一电极的主焊盘电极垂直下方形成阻挡作用，可提升阻挡电流向第一电极的主焊盘电极下方的电流扩散的效果，促进电流向电绝缘层的开口处分散，提升光均匀分散性。
根据本实施例，自电绝缘层7一侧形成的含氟区域821至少位于第二导电类型半导体层8的电流扩展层82中。当然也不排除氟元素会扩散至属于第二导电类型半导体层8的其它层中，如到达过度层铝镓铟磷或进一步地到达p型覆盖层。本实施例优选的，含氟区域821厚度不超过电流扩展层82或者含氟区域821的厚度低于电流扩展层82的厚度。优选的，所述的电流扩展层为p-GaP。其中电流扩展层p-GaP的厚度为5nm～2μm。含氟区域中的氟浓度不低于1E17/cm 3，更优选的，含氟区域的氟浓度介于1E17～1E21/cm 3。
下面提供获得本实施例发光元件的制备方法，如图5-11所示，为各个步骤对应的结构示意图。其包括以下步骤：
1.在生长衬底上获得半导体发光序列，包括第一导电类型半导体层、发光层和第二导电类型半导体层。
如图5所示，在生长衬底101上通过MOCVD外延生长方法获得半导体发光序列，生长衬底101在本实施例中为砷化镓，需要说明的是，衬底不限于砷化镓，也可以是其它的可实施生长半导体发光序列的衬底也可替代使用。砷化镓衬底上的半导体序列包括依次生长堆叠的第一导电类型半导体层10、发光层9和第二导 电类型半导体层8。第一导电类型半导体层10包括n型覆盖层，第二导电类型半导体层包括p型覆盖层，n型覆盖层具和p型覆盖层具体可以是铝铟磷，发光层为铝镓铟磷。为了后续方便去除生长衬底或保证外延生长质量的需要，可以选择性地在生长衬底与半导体序列之间还可以包括缓冲层、过度层以及蚀刻截止层等。更优选的，第一导电类型半导体层中还可包括n型砷化镓作为欧姆接触层，用于后续第一电极的欧姆接触。更优选地，第二导电类型半导体层8包括p型电流扩展层82，由于第二导电类型半导体层一侧的电流扩展以及欧姆接触，本实施例中电流扩展层82为p型磷化镓。
关于各层的功能及参数可参照下表一。
Figure PCTCN2019087486-appb-000001
2.蒸镀电绝缘层，并在氟化物电绝缘层形成开口。
在第二导电类型半导体层8一侧蒸镀电绝缘层，所述的电绝缘层7优选为氟化镁或氟化钙。电绝缘层7的厚度范围为10～500nm。所述蒸镀的温度至少为20℃，或优选200℃。温度越高，蒸镀的氟化物致密性越高。
所述的电绝缘层形成贯穿厚度的开口，开口优选为多个，开口不会形成在第一 电极的主焊盘电极的垂直下方。为了形成开口，在蒸镀电绝缘层7之前，可以在第二导电类型半导体层一侧先形成多个掩膜图形，掩膜图形为块状，或优选的为上宽下窄型，掩膜图形可以是金属或绝缘层或两者的组合。在掩膜图形表面蒸镀电绝缘层后，去除掩膜图形即形成开口。当采用掩膜图形为上宽下窄型时，可以获得开口的侧壁为倾斜状，以利于后续的欧姆接触层和反射层能够尽量平整、均匀的覆盖在绝缘层表面，尤其是贯穿孔的开口的侧壁与绝缘层表面的夹角处尽量平整。
图6提供从电绝缘层7一侧俯视的示意图。其中开口的形状为圆形或椭圆形或方形或者多边形。
3.高温处理，氟元素扩散至第二导电类型半导体层中。
形成电绝缘层后，进行高温处理，高温处理的条件：气体氛围优选惰性气体，温度为460～500℃，时间为10～30min。如图7所示的示意图，高温处理实现电绝缘层7的氟离子扩散至第二导电性半导体层8的电流扩展层82中。在此需要说明的是，控制不同的温度和时间，可以调整氟离子扩散的厚度不同。
图8提供了图7所示结构的局部厚度方向的SIMS元素分析，包括Ga、P、F、C和Mg元素的浓度分析，其中横坐标为厚度，左侧纵坐标为元素的浓度。图中3条纵向直线示意不同的厚度位置，第一条直线所示的位置为电绝缘层氟化物与GaP的界面处，第二条直线示意的位置是对应氟扩散的深度位置，第三条直线所示意的位置对应高掺GaP接触层与非高掺GaP的界面为GaP的另一界面处。图中可以看出GaP的厚度不低于500nm，F元素扩散进入GaP中不高于40nm。
同时经过CILM测试，发现半导体发光序列表面侧的氟化物经过高温处理后导致半导体发光序列的方块电阻增加。由此可见，F元素的扩散导致GaP层的局部方块电阻增加，改善光均匀分散性。
4.在电绝缘层表面制作欧姆接触层。
如图9所示，制作欧姆接触层6如ITO或IZO，优选如溅镀或蒸镀的方式。欧姆接触层6覆盖至电绝缘层7的开口内与第二导电类型半导体层接触，并覆盖至电绝缘层7的表面侧，欧姆接触层的厚度为1～500nm。
5.金属反射层、阻挡层和键合层。
如图9所示，蒸镀或电镀反射层5，反射层5的材料为银。蒸镀阻挡层4以阻挡金属银扩散至键合层中，阻挡层4的材料优选为钛、铂、铬等至少一种。
蒸镀形成键合层3，键合层3可以是金、铟或锡等材料组成。
6.键合基板，去除生长衬底。
如图10所示，选择一支撑基板2，将生长衬底101上的半导体发光序列上的键合层3与支撑基板2相键合，键合采用高温高压的方式。本实施例中支撑基板2为硅基板。
将生长衬底101移除；生长衬底101可采用研磨、湿法蚀刻移除。
7.制作第一电极和基板的背面电极。
正面形成第一电极11，支撑基板2形成背面金属层1作为第二电极。其中第一电极11包括主焊盘电极，主焊盘电极包括欧姆接触层1101和焊线层1102，包括自主焊盘电极周围延伸出去的延伸电极1103。第一电极11的延伸电极1103下方优选的保留有第一导电类型半导体层10的欧姆接触层1101砷化镓，其余的欧姆接触层101被蚀刻去除。背面金属层1通常为金或铂等材料制成。
半导体发光序列表面和后侧壁可以进一步进行蚀刻以形成粗化面或图案，以利于出光。
8.分离形成单一的发光元件。
通过分离工艺将半导体发光序列分离成多个单元区域，在半导体发光序列的侧壁和表面覆盖绝缘保护层。进一步分离反射层、阻挡层和键合层以及基板以形成多个单一的发光元件。
图12提供了本实施例的发光元件的制作方法步骤流程图。
实施例二
如图13所示，在本实施例中，提供替代性的实施方案，具体的提供如下一种半导体发光元件，其包括半导体发光序列，半导体发光序列包括第一导电类型半导体层10、发光层9和第二导电类型半导体层8；
其中第二导电类型半导体层8侧的电绝缘层7具有多处开口，将第二导电类型半导体层一侧设置成电接触区域与电绝缘区域。
开口内填充的是欧姆接触块14，欧姆接触块14为多处，但不形成在第一电极外 部注入电流用的主焊盘电极下方。欧姆接触块14的形状为块状，金属材质为金锗、金锗镍、金锌、金铍等至少之一种。每一个欧姆接触块14的水平宽度为1～10μm，欧姆接触块14的厚度为1～500nm。
金属反射层5覆盖欧姆接触块14以及电绝缘层7的一侧。
电绝缘层7为氟化物，具体的为氟化镁、氟化钙。
其中电绝缘层7经过高温处理后促使氟离子扩散至第二导电类型半导体层8中形成含氟区域，该含氟区域具有电流阻挡作用。优选的，氟离子至多扩散至第二导电类型半导层中所包括的电流扩展层82p-GaP的整个厚度方向。
下面结合生长方法说明本实施例的结构，其包括以下步骤：
1.在生长衬底上获得半导体发光序列，该步骤与实施例一相同。
如图14所示，在生长衬底101上通过MOCVD外延生长方法获得包括半导体层序列。半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层。生长衬底101本实施例为砷化镓，砷化镓衬底上的半导体序列包括依次生长堆叠的第一导电类型半导体层10、发光层9和第二导电类型半导体层8。第一导电类型半导体层10包括n型覆盖层，本实施例为铝铟磷，第二导电类型半导体层包括p型覆盖层为铝铟磷，发光层为铝镓铟磷。更优选的，第一导电类型半导体层中还可包括n型砷化镓作为欧姆接触层，用于后续第一电极的欧姆接触。更优选地，本实施例中第二导电类型半导体层8中包括p型电流扩展层，电流扩展层为p型磷化镓，用于第二电极的欧姆接触。
2.制作多处的欧姆接触块。
如图15所示，在第二导电类型半导体层一侧蒸镀一层形成欧姆接触块141的层和CVD制作一层氧化硅或氮化硅层15。然后制作一层光刻胶图形16。
如图16所示，以光刻胶图形16作为掩膜，BOE蚀刻氧化硅或氮化硅层15形成多处的块状。如图17所示，选择蚀刻液蚀刻金锌141，控制蚀刻时间实现每一氧化硅或氮化硅层15的块与第二导电类型半导体层之间形成残留的金锌块，金锌块作为欧姆接触块14使用。欧姆接触块14的水平宽度尺寸低于氧化硅或氮化硅层15的块的水平宽度尺寸至少2μm。去除光刻胶。对欧姆接触块进行高温熔合处理，以欧姆接触块14与电流扩展层之间形成欧姆接触。
3.蒸镀电绝缘层，形成氟化物电绝缘层开口。
如图18所示，去除光刻胶。以欧姆接触块14和氧化硅或氮化硅层15形成的块组合成上宽下窄的图形作为掩膜，蒸镀一层氟化物电绝缘层，氟化物电绝缘层的厚度为50～500μm，较佳的为50～150μm，更佳的为100μm左右。
如图19所示，BOE去除氧化硅或氮化硅层15的块，同时氧化硅或氮化硅层15的块的表面以及侧壁上的氟化物电绝缘层7会被去除，留下欧姆接触块14以及氟化物电绝缘层7覆盖在第二导电类型半导体层一侧。氟化物电绝缘层7具有多处开口，开口内有欧姆接触块14，开口的侧壁为倾斜状。
4.高温处理。
形成氟化物电绝缘层后，进行高温处理，高温处理的条件：气体氛围优选惰性气体，温度为460～500℃，时间为10～30min。在此需要说明的是，控制不同的温度和时间，可以调整氟离子扩散的厚度不同。
如图20所示的示意图，经过高温处理，使电绝缘层7的氟离子扩散至第二导电性半导体层8的电流扩展层82中。
镀金属反射层、阻挡层和键合层；键合基板，去除生长衬底；制作第一电极和基板的背面金属层；分离形成单一的发光元件。这些步骤可参照实施例一的相应步骤进行。图21提供了本实施例的发光元件的制作方法步骤流程图。
获得的单一的发光元件如图13所示。
作为一种替代性的实施方法，其中高温熔合步骤与氟化物绝缘层形成之后的高温处理步骤为同一步骤。
实施例三
如图22所示，在本实施例中，提供另外一种半导体发光元件，半导体发光序列包括第一导电类型半导体层10、发光层9和第二导电类型半导体层8；
其中第二导电类型半导体层8侧包括电绝缘层，氟化物电绝缘层具有多处开口，将第二导电类型半导体层一侧设置成电接触区域与电绝缘区域。
开口内填充的是欧姆接触块或者欧姆接触层。
电绝缘层为氟化物，具体的为氟化镁、氟化钙至少之一种。
氟化物的氟离子扩散至第二导电类型半导体层中形成电流阻挡区域。
第一电极形成在第一导电类型半导体层一侧，包括外部打线用的主焊盘电极和从主焊盘电极周围水平延伸出去的扩展电极。
本实施例中含氟区域主要形成在第一电极的主焊盘电极下方，即第一电极外部用的主焊盘电极竖直下方以及邻近周围的第二导电类型半导体层中通过氟离子扩散形成电流阻挡区域，扩展电极周围的电绝缘层无氟离子扩散。
用于主要改变第一电极外部用的主焊盘电极竖直下方的电流路径，使电流尽量避免在主焊盘电极下方以及周围进行竖直方向的传递，而是在第二导电类型半导体层一侧尽量大面积流通，并且尽量通过电绝缘层的开口处进行电流传递。
具体的，如图22所示，其中电绝缘层7，包括两个部分，其中第一部分的电绝缘层71主要位于第一电极11的主焊盘电极竖直下方，即位于第一电极11的主焊盘电极竖直下方以及邻近周围的第二导电类型半导体层中。其中第一部分的电绝缘层71覆盖面的面积与第一电极的主焊盘电极的面积比为1～1.5，更优选的为小于等于1.2或小于等于1.1。更优选的，第一部分的电绝缘层71覆盖面的水平宽度与第一电极的主焊盘电极的水平宽度比为1～1.25，更优选的为小于等于1.2，或小于等于1.1。
电绝缘层7还包括第二部分的电绝缘层72，第二部分的电绝缘层72不位于第一电极11的主焊盘电极的下方，并且第二部分的电绝缘层72具有贯穿厚度方向的开口，开口为多个，开口提供在第二导电类型半导体层8一侧的电接触区域。
作为一种实施方式，电绝缘层7下方具有欧姆接触6，欧姆接触层为透明导电层，如ITO或IZO等，欧姆接触6通过至少覆盖第二部分的电绝缘层72的开口内与第二导电类型半导体层一侧接触。
该结构相对于实施一和二可以有效稳定电压。
为了获得上述的发光元件，本实施例提供如下制作方法，其包括：
1.如图23所示，在生长衬底101上获得半导体发光序列，包括第一导电类型半导体层10、发光层9和第二导电类型半导体层8。生长衬底为砷化镓。
2.如图24-25所示，蒸镀第一部分电绝缘层71，并高温处理，氟元素扩散至第二导电类型半导体层8中形成含氟区域801。
3.如图25-26所示，蒸镀第二部分电绝缘层72，其覆盖在第二导电类型半导体层 8的其余面上，并在第二部分电绝缘层72上形成多处的开口，形成欧姆接触覆盖电绝缘层7及开口内。
4.其余的步骤如图27所示的制作工艺流程图，并可参照实施例一至二的相应步骤制作，获得如图22所示的发光元件的结构。其中第一电极的主焊盘电极位于第一部分电绝缘层的垂直上方。
根据本实施例一至三的半导体发光元件可以通过封装支架如EMC或陶瓷封装获得封装结构。进一步的封装结构可以根据运用需求排列在线路基板上，并且诸如导光板、棱镜片、扩散片以及荧光片的光学构件可以被布置在从发光元件发射的光的路径上。进一步的根据运用需求被运用于可以包括显示器如电视或显示屏、照明装置如室内灯、室外街灯、指示器等等。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (32)

  1. 一种半导体发光元件，包括：
    半导体发光序列，半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层；
    电绝缘层覆盖第二导电类型半导体层一侧部分区域形成电绝缘区域，第二导电类型半导体层一侧未被覆盖的部分区域为电接触区域，
    其特征在于：第二导电类型半导体层中包括含氟区域。
  2. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述含氟区域位于第二导电类型半导体层和绝缘层之间的界面处，并延伸至第二导电类型半导体层中。
  3. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述电绝缘层为氟化物。
  4. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的含氟区域为电绝缘层的氟元素扩散形成。
  5. 根据权利要求4所述的一种半导体发光元件，其特征在于：第二导电类型半导体层中含氟区域的厚度为1～1000nm，更优选的，所述的含氟区域的厚度为10～100nm。
  6. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的含氟区域的含氟元素浓度介于1E17～1E21/cm 3。
  7. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的第二导电类型半导体层包括电流扩展层，含氟区域位于电流扩展层与电绝缘层的界面处，并延伸至第二导电类型半导体层的电流扩展层中。
  8. 根据权利要求7所述的一种半导体发光元件，其特征在于：所述的电流扩展层为GaP或GaAs或AlGaInP。
  9. 根据权利要求7所述的一种半导体发光元件，其特征在于：所述含氟区域的厚度不高于电流扩展层的厚度。
  10. 根据权利要求7所述的一种半导体发光元件，其特征在于：所述含氟区域的厚度高于电流扩展层的厚度。
  11. 根据权利要求7所述的一种半导体发光元件，其特征在于：所述含氟区域与横向周围区域为同质区。
  12. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的第一导电类型半导体层一侧具有第一电极，第一电极包括外部打线用的主焊盘电极，所述的含氟区域至少位于所述主焊盘电极的垂直方向上的第二导电类型半导体层中。
  13. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的第一导电类型半导体层一侧具有第一电极，第一电极包括外部打线用的主焊盘电极，所述的含氟区域主要位于所述主焊盘电极的垂直方向上的第二导电类型半导体层中。
  14. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的第一导电类型半导体层、发光层和第二导电类型半导体层分别为AlxInyGa1-x-yP(0≤x≤1，0≤y≤1)和或AlzGa1-zAs(0≤z≤1)的材料制成。
  15. 根据权利要求1所述的一种半导体发光元件，其特征在于：在电绝缘层远离第二导电类型半导体层的一侧具有第二电极。
  16. 根据权利要求1所述的一种半导体发光元件，其特征在于：电绝缘层具有多个贯穿其厚度的开口，开口内为电接触区域。
  17. 根据权利要求15所述的一种半导体发光元件，其特征在于：第二电极与第二导电类型半导体层一侧之间通过欧姆接触层形成电接触，欧姆接触层材料为透明导电层，至少覆盖电接触区域。
  18. 根据权利要求15所述的一种半导体发光元件，其特征在于：第二电极与第二导电类型半导体层一侧之间通过欧姆接触层形成电接触，欧姆接触层材料为至少两种金属的组合。
  19. 根据权利要求15所述的一种半导体发光元件，其特征在于：所述的第二电极与第二导电类型半导体层一侧之间包括金属反射层。
  20. 根据权利要求16所述的一种半导体发光元件，其特征在于：所述的电绝缘层的开口的侧壁相对于远离半导体发光序列的一侧面倾斜，倾斜的角度为大于90°，小于等于170°。
  21. 一种半导体发光元件的制备方法，其包括：
    获得半导体发光序列，包括第一导电类型半导体层、发光层和第二导电类型半导体层；
    在第二导电类型半导体层表面侧形成局部覆盖的电绝缘层，电绝缘层为氟化物；
    高温扩散处理，氟元素扩散至第二导电类型半导体层中形成含氟区域；
    制作第一电极与第一导电类型半导体层电性连接，第二电极与第二导电类型半导体层电性连接。
  22. 根据权利要求21所述的半导体发光元件的制作方法，其特征在于：高温扩散处理的温度为360～600℃，时间0.01～60min。
  23. 根据权利要求21所述的半导体发光元件的制作方法，其特征在于：高温扩散处理后，在未被电绝缘层覆盖的第二导电类型半导体层一侧形成欧姆接触。
  24. 根据权利要求23所述的半导体发光元件的制作方法，其特征在于：欧姆接触为透明导电层或多种金属组合形成的块状。
  25. 根据权利要求21所述的一种半导体发光元件的制备方法，其特征在于：第一电极位于第一导电类型半导体层一侧，包括外部打线用的主焊盘电极，所述的高温扩散处理使含氟区域主要形成在第一电极外部打线用的主焊盘电极在垂直方向上的第二导电类型半导体层中。
  26. 根据权利要求21所述的半导体发光元件的制作方法，其特征在于：高温扩散处理之前，在未被电绝缘层覆盖的第二导电类型半导体层一侧生长欧姆接触的材料，欧姆接触的材料为至少两种金属的组合。
  27. 根据权利要求21所述的半导体发光元件的制作方法，其特征在于：所述的欧姆接触的材料与第二导电类型半导体层一侧形成的欧姆接触步骤与高温扩散处理为同一步骤。
  28. 根据权利要求21所述的半导体发光元件的制作方法，其特征在于：第二电极包括一金属反射层。
  29. 一种半导体发光元件的制备方法，其包括：
    获得半导体发光序列，包括第一导电类型半导体层、发光层和第二导电类型半导体层；
    制作多处的欧姆接触块在第二导电类型半导体层一侧，
    在第二导电类型半导体层表面侧形成局部覆盖的电绝缘层，电绝缘层为金属氟化盐；
    高温扩散处理，金属氟化盐的氟元素扩散至第二导电类型半导体层中形成含氟区域；
    制作第一电极与第一导电类型半导体层电性连接，第二电极与第二导电类型半导体层连接。
  30. 根据权利要求29所述的一种半导体发光元件的制备方法，其特征在于：所述的欧姆接触块与第二导电类型半导体层一侧的高温熔合步骤与电绝缘层的高温扩散处理步骤为同一步骤。
  31. 根据权利要求29所述的一种半导体发光元件的制备方法，其特征在于：所述的欧姆接触块与第二导电类型半导体层一侧的高温熔合步骤早于电绝缘层的高温扩散处理步骤。
  32. 根据权利要求1～20中任一项的半导体发光元件获得的发光装置。
PCT/CN2019/087486 2019-05-17 2019-05-17 一种半导体发光元件及发光装置 WO2020232586A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2019/087486 WO2020232586A1 (zh) 2019-05-17 2019-05-17 一种半导体发光元件及发光装置
CN201980004732.9A CN111164767B (zh) 2019-05-17 2019-05-17 一种半导体发光元件及发光装置
TW108145797A TWI728595B (zh) 2019-05-17 2019-12-13 半導體發光元件及其製作方法，及發光裝置
US17/527,033 US20220077370A1 (en) 2019-05-17 2021-11-15 Light-emitting component and method for making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/087486 WO2020232586A1 (zh) 2019-05-17 2019-05-17 一种半导体发光元件及发光装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/087487 Continuation-In-Part WO2020232587A1 (zh) 2019-05-17 2019-05-17 一种制作半导体发光元件的方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/527,033 Continuation-In-Part US20220077370A1 (en) 2019-05-17 2021-11-15 Light-emitting component and method for making the same

Publications (1)

Publication Number Publication Date
WO2020232586A1 true WO2020232586A1 (zh) 2020-11-26

Family

ID=70562372

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/087486 WO2020232586A1 (zh) 2019-05-17 2019-05-17 一种半导体发光元件及发光装置

Country Status (3)

Country Link
CN (1) CN111164767B (zh)
TW (1) TWI728595B (zh)
WO (1) WO2020232586A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626057A (zh) * 2009-07-31 2010-01-13 晶能光电（江西）有限公司 发光半导体的互补电极结构及其制造方法
CN102522472A (zh) * 2011-12-30 2012-06-27 厦门市三安光电科技有限公司 具有电流阻挡层的发光二极管及其制作方法
US20160133796A1 (en) * 2014-11-07 2016-05-12 Epistar Corporation Light-emitting device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI672837B (zh) * 2014-07-11 2019-09-21 晶元光電股份有限公司 半導體發光元件
KR101761835B1 (ko) * 2015-05-22 2017-07-26 서울바이오시스 주식회사 고효율 발광 다이오드

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626057A (zh) * 2009-07-31 2010-01-13 晶能光电（江西）有限公司 发光半导体的互补电极结构及其制造方法
CN102522472A (zh) * 2011-12-30 2012-06-27 厦门市三安光电科技有限公司 具有电流阻挡层的发光二极管及其制作方法
US20160133796A1 (en) * 2014-11-07 2016-05-12 Epistar Corporation Light-emitting device and manufacturing method thereof

Also Published As

Publication number Publication date
CN111164767A (zh) 2020-05-15
TWI728595B (zh) 2021-05-21
TW202044620A (zh) 2020-12-01
CN111164767B (zh) 2023-02-17

Similar Documents

Publication Publication Date Title
WO2016019860A1 (zh) 垂直型led芯片结构及其制备方法
CN108365065A (zh) 发光元件
JP2009004625A (ja) 半導体発光装置
JP2008218878A (ja) ＧａＮ系ＬＥＤ素子および発光装置
WO2008082097A1 (en) Light emitting device and fabrication method thereof
TWI719759B (zh) 半導體發光元件的製作方法、半導體發光元件，及發光裝置
TWI636582B (zh) 發光裝置
TW201724559A (zh) 發光元件
TWI718182B (zh) 一種重複使用於製造發光元件的基板之方法
TW201603319A (zh) 光電元件及其製造方法
WO2021119906A1 (zh) 一种发光二极管
TWI740307B (zh) 半導體發光元件
TW201407760A (zh) 發光二極體陣列
CN103811608B (zh) 一种发光二极管的制造方法
WO2017084409A1 (zh) 发光二极管芯片及其制作方法
WO2020232586A1 (zh) 一种半导体发光元件及发光装置
WO2020061750A1 (zh) 一种发光二极管元件
KR101805301B1 (ko) 광추출효율 향상을 위한 p-형 오믹 접합 전극 패턴을 구비한 자외선 발광 다이오드 소자
JP2008226866A (ja) ＧａＮ系ＬＥＤ素子および発光装置
CN103594589B (zh) 一种发光二极管
CN104037279A (zh) 一种具有电流阻挡层的发光二极管的制作方法
US20220077370A1 (en) Light-emitting component and method for making the same
CN103606604B (zh) 一种发光二极管的制造方法
TWI833576B (zh) 發光元件、包含其之發光裝置及發光裝置之製造方法
JP2012104730A (ja) 半導体発光素子

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19929810

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19929810

Country of ref document: EP

Kind code of ref document: A1