WO2020220794A1 - 阵列基板、显示面板、显示装置及阵列基板的制造方法 - Google Patents

阵列基板、显示面板、显示装置及阵列基板的制造方法 Download PDF

Info

Publication number
WO2020220794A1
WO2020220794A1 PCT/CN2020/075527 CN2020075527W WO2020220794A1 WO 2020220794 A1 WO2020220794 A1 WO 2020220794A1 CN 2020075527 W CN2020075527 W CN 2020075527W WO 2020220794 A1 WO2020220794 A1 WO 2020220794A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
signal line
electric field
layer
field shielding
Prior art date
Application number
PCT/CN2020/075527
Other languages
English (en)
French (fr)
Inventor
王金良
朴相镇
王文超
胡波
方鑫
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020220794A1 publication Critical patent/WO2020220794A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present disclosure relates to the field of display technology, and more specifically to an array substrate, a display panel, a display device, and a manufacturing method of the array substrate.
  • LCD liquid crystal display
  • liquid crystal is a substance between solid and liquid. It is liquid under normal conditions, but its molecular arrangement is very regular like solid crystals. If an electric field is applied to it, its molecular arrangement can be changed.
  • this feature can achieve screen display. For example, for a certain pixel of LCD, if the corresponding thin film transistor (TFT) switch is controlled to make a different potential difference between the pixel electrode and the common electrode, the liquid crystal sandwiched between the two electrodes The molecules can be deflected to different degrees, so that the polarized light becomes non-passing, partial passing or passing, thereby realizing the switching of single-point pixels and/or different grayscale display.
  • TFT thin film transistor
  • some embodiments of the present disclosure provide an array substrate.
  • the array substrate includes: a substrate; a plurality of clock signal lines including at least a first clock signal line and a second clock signal line are located on the substrate, the first clock signal line has a first part, the The first part is located on a first area of the substrate, the second clock signal line has a second part, and the second part is located on a second area of the substrate that is different from the first area;
  • the electric field shielding layers above the first part and the second part, the electric field shielding layer and the first clock signal line are electrically insulated from each other, and the electric field shielding layer and the second clock signal line are electrically insulated from each other. insulation.
  • the array substrate further includes: an insulating layer located between the first part and the electric field shielding layer and between the second part and the electric field shielding layer, so that the electric field The shielding layer and the first clock signal line are electrically insulated from each other and the electric field shielding layer and the second clock signal line are electrically insulated from each other.
  • the electric field shielding layer includes a first electric field shielding sublayer and a second electric field shielding sublayer, and the orthographic projection of the first electric field shielding sublayer on the substrate covers the The orthographic projection on the substrate, and the orthographic projection of the second electric field shielding sublayer on the substrate covers the orthographic projection of the second part on the substrate.
  • the first electric field shielding sublayer in a width direction perpendicular to the extending direction of the clock signal line, has the same width as the first clock signal line, and the second electric field shielding sublayer has the same width as the first clock signal line.
  • the second clock signal lines have the same width.
  • the array substrate further includes:
  • An active layer located on the gate insulating layer
  • Source and drain on the gate insulating layer and the active layer Source and drain on the gate insulating layer and the active layer
  • a passivation layer located on the active layer, the source electrode, the drain electrode and the gate insulating layer,
  • the insulating layer is located in the same layer as at least one of the gate insulating layer and the passivation layer.
  • the array substrate further includes: a pixel electrode or a common electrode on the passivation layer, wherein the electric field shielding layer and the pixel electrode or the common electrode are on the same layer.
  • an embodiment of the present disclosure further provides a display panel, wherein the display panel includes the above-mentioned array substrate.
  • the display panel further includes a sealant on the array substrate,
  • the sealant covers the first area, and the sealant covers the first part of the first clock signal line.
  • the display panel further includes a liquid crystal layer on the array substrate,
  • the liquid crystal layer covers the second area, and the liquid crystal layer covers the second part of the second clock signal line.
  • the plurality of clock signal lines further include a third clock signal line, the third clock signal line is located between the first clock signal line and the second clock signal line, and so A part of the third clock signal line is covered by the sealant, and another part of the third clock signal line is covered by the liquid crystal layer.
  • the electric field shielding layer includes a third electric field shielding sublayer located on at least a part of the third clock signal line, and the orthographic projection of the third electric field shielding sublayer on the substrate covers An orthographic projection of at least a part of the third clock signal line on the substrate.
  • the sealant covers an electric field shielding layer located above the first portion of the first clock signal line.
  • the liquid crystal layer covers an electric field shielding layer located above the second portion of the second clock signal line.
  • the sealant covers a part of the third electric field shielding sublayer, and the liquid crystal layer covers another part of the third electric field shielding sublayer.
  • the display panel further includes a display driving circuit electrically connected to the array substrate, wherein the electric field shielding layer is electrically connected to the display driving circuit, and the display driving circuit provides a separate electric signal.
  • some embodiments of the present disclosure provide a display device.
  • the display device includes the aforementioned display panel.
  • some embodiments of the present disclosure provide a method of manufacturing an array substrate.
  • the method includes: forming a plurality of clock signal lines including at least a first clock signal line and a second clock signal line on a substrate, the first clock signal line has a first part, and the first part is formed on the On the first area of the substrate, the second clock signal line has a second portion, and the second portion is formed on a second area of the substrate that is different from the first area; and An electric field shielding layer is formed above the first part and above the second part so that the electric field shielding layer and the first clock signal line are electrically insulated from each other, and the electric field shielding layer and the second clock signal line are electrically insulated from each other .
  • the step of forming an electric field shielding layer over the first part and over the second part includes: in the first part of the first clock signal line and the second part of the second clock signal line An insulating layer is formed on each of them; and an electric field shielding layer is formed on the insulating layer.
  • the method further includes: forming a gate on the substrate; forming a gate insulating layer on the gate; forming an active layer on the gate insulating layer; Forming a source electrode and a drain electrode on the gate insulating layer and the active layer; forming a passivation layer on the active layer, the source electrode, the drain electrode and the gate insulating layer; A through hole is formed on the passivation layer to expose a part of the source electrode or the drain electrode; and a pixel electrode or a common electrode is formed on the passivation layer so that the pixel electrode or the common electrode passes through the The through hole is electrically connected to the source electrode or the drain electrode.
  • the step of forming a plurality of clock signal lines is performed simultaneously with the step of forming the gate.
  • the step of forming the insulating layer is performed simultaneously with the step of forming the gate insulating layer and/or the step of forming the passivation layer.
  • the step of forming the electric field shielding layer is performed simultaneously with the step of forming the pixel electrode or the common electrode.
  • FIG. 1 is a top view showing an example display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a plan view and a side view showing a partial configuration of the display panel shown in FIG. 1 according to an embodiment of the present disclosure.
  • FIG. 3 is a side view showing a further partial configuration example of a partial configuration of the display panel shown in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 4 is a side view showing a further partial configuration of another partial configuration example of the display panel shown in FIG. 2 according to an embodiment of the present disclosure.
  • 5A to 5G are schematic diagrams showing various stages of a product manufactured using an example method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart showing an example method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram schematically showing the electrical connection between the electric field shielding layer and the display driving circuit in the display panel according to an embodiment of the present disclosure.
  • the terms “including” and “containing” and their derivatives mean including but not limiting; the term “or” is inclusive, meaning and/or.
  • the orientation terms used such as “upper”, “lower”, “left”, “right”, etc., are used to indicate relative positional relationships to assist those skilled in the art to understand the present disclosure. Embodiments, and therefore those skilled in the art should understand: “up”/"down” in one direction can be changed to “down”/"up” in the opposite direction, and in the other direction, it may become other Position relationship, such as “left”/"right”, etc.
  • on can mean that one layer is directly formed or disposed on another layer, or can mean a A layer is formed indirectly or arranged on another layer, that is, there are other layers between the two layers.
  • first the terms “first”, “second”, etc. may be used herein to describe various components, components, elements, regions, layers and/or parts, these components, components, elements, regions, and layers And/or part should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and/or section from another.
  • first part, the first member, the first element, the first region, the first layer and/or the first part discussed below may be referred to as the second part, the second member, the second element, the second region , The second layer and/or the second part without departing from the teachings of the present disclosure.
  • the term "located on the same layer” used means that two layers, parts, components, elements or parts can be formed by the same patterning process, and the two layers, parts, components, The elements or parts are generally formed of the same material.
  • the embodiments of the present disclosure are applied to an array substrate of a liquid crystal display device as an example for detailed description.
  • the application field of the present disclosure is not limited to this.
  • the technical solutions according to the embodiments of the present disclosure can be applied to other scenarios where a consistent clock signal or other signals need to be provided.
  • the transistor is described as an example in which the transistor is a bottom-gate thin film transistor (TFT) in the following description, the present disclosure is not limited thereto.
  • the technical solutions of the present application can also be implemented for top-gate transistors or other types of transistors, and only the corresponding layers provided for clock signal lines (or other signal lines) need to be adjusted. can.
  • FIG. 1 is a top view showing an example display panel 10 according to an embodiment of the present disclosure.
  • the display panel 10 may include an effective display area (AA) 100 and a bezel area 110.
  • AA 100 includes a pixel array composed of multiple pixels, which can be used to display a desired image according to a driving signal provided by a display driving circuit.
  • the bezel area 110 may be used to prevent light from leaking from the edge of the display panel 10.
  • the bezel area 110 may be used to prevent light from leaking from the edge of the display panel 10.
  • the edge of the display panel 10 if there is no obstruction by the frame area 110, light emitted through the light guide plate of the backlight module will cause light leakage at the edge of the display panel 10. It will also cause obvious light spots.
  • the bezel area 110 is also provided with various signals (including but not limited to: clock signals, gate drive signals, data drive signals, high-level signals, low-level signals). Signal, ground, etc.).
  • various signals including but not limited to: clock signals, gate drive signals, data drive signals, high-level signals, low-level signals). Signal, ground, etc.
  • FIG. 2 is a top view and a side view showing a partial configuration 120 of the display panel 10 shown in FIG. 1 according to an embodiment of the present disclosure.
  • the upper half of FIG. 2 shows a top view of the portion 120 of the display panel 10 shown in FIG. 1
  • the lower half of FIG. 2 shows that the portion 120 of the display panel 10 shown in FIG. Sectional view or side view of section line AA' in the top view of the part.
  • FIG. 2 only shows the parts related to the embodiment of the present disclosure, and does not show the parts well-known to those skilled in the art.
  • some details in Fig. 2 will be further shown in conjunction with Figs. 3 to 5 when necessary.
  • the partial structure 120 of the display panel 10 can be provided with multiple lines, including (but not limited to): multiple clock signal lines CLK1 130-1 to CLK 8 130-8, Start Vertical Signal line or frame initial signal line STV1, pre-frame reset signal STV2, high-level signal lines VDD1, VDD2, low-level signal lines LVSS, VSS, ground signal line GND, common electrode signal line Vcom, and maintenance during production RP signal line and feedback signal line FEED for debugging.
  • this is only a possible embodiment of the partial structure 120 of the bezel area 110 of the display panel 10 according to the embodiment of the present disclosure, and the present disclosure is not limited thereto.
  • the partial structure 120 of the bezel area 110 of the display panel 10 may include more or fewer lines, or include different lines.
  • clock signal lines CLK1 130-1 to CLK8 130-8 are shown, which can be used to provide a gate driver on the display panel 10 (Gate driver on Array or GOA for short) 160
  • Each shift register in provides a clock signal, so that each shift register can output a gate driving signal for driving a corresponding pixel row.
  • the first clock signal line CLK1 130-1 may be electrically connected to the shift register at the bottom of the GOA 160 to provide it with the clock signal required when scanning the corresponding pixel row.
  • the second clock signal line CLK2 130-2, the third clock signal line CLK3 130-3, and the fourth clock signal line CLK4 130-4 can be electrically connected to the corresponding shift registers in the GOA 160 to provide them with The clock signal required for the corresponding pixel row scan.
  • each adjacent clock signal line is shown in FIG. 2 as if it is electrically connected to an adjacent shift register and then to an adjacent pixel row signal, in fact the adjacent clock signal line It can be electrically connected to non-adjacent shift registers, and the adjacent shift registers can provide gate drive signals to non-adjacent pixel rows.
  • GOA is provided in the left and right side frames of the display panel 10 shown in FIG.
  • the GOA on the left side of the panel (for example, the GOA 160 electrically connected to the clock signal lines shown in FIG. 2) can Provides gate drive signals for odd rows of pixels, and the GOA on the right side of the panel can provide gate drive signals for even rows of pixels.
  • the electrical connection relationship between each clock signal line and the GOA 160 may not be connected in sequence from left to right according to the clock signal line as shown in FIG. 2, but may be electrically connected in other order.
  • the first clock signal line CLK1 130-1 can be electrically connected to the bottom shift register
  • the third clock signal line CLK3 130-3 can be electrically connected to the shift register of the upper row
  • the fifth clock signal line CLK5 130-5 can be electrically connected. Connect the shift register of the previous row, and so on.
  • each clock signal line CLK1 130-1 to CLK8 130-8 (in the top view of the upper half of FIG. 2, the direction perpendicular to the extending direction of the clock signal line is taken as the width The direction) may be approximately 120 micrometers ( ⁇ m).
  • signal lines may be respectively, for example, 80 ⁇ m (for example, VDD1 151, VDD2 153, VSS 159, STV2 157, etc.), 100 ⁇ m (for example, LVSS 155, RP 147, FEED 145, STV1 141, etc.), 150 ⁇ m (for example, GND 149, etc.) and/or 340 ⁇ m (for example, Vcom 143, etc.).
  • the width of these signal lines may depend on design requirements and is not limited to the embodiment shown in FIG. 2.
  • the common electrode signal line Vcom 143 usually needs to be connected to each pixel to provide an electrical signal to the common electrode in each pixel, in order to ensure that the electrical signal of the common electrode of the pixel at each position in the display panel 10 is as large as possible Uniformity, the Vcom 143 shown in FIG. 2 is usually designed to go around the frame area 110 of the display panel 10 to provide electrical signals required by the common electrode to pixels at different positions from various directions.
  • the length of the common electrode line Vcom143 designed in this way is much longer than other signal lines.
  • the width can be widened to form the widest signal line as shown in FIG. 2, for example.
  • other signal lines can also adjust their corresponding widths according to actual needs, and are not limited to the specific design shown in FIG. 2.
  • multiple signal lines including multiple clock signal lines CLK 1 130-1 to CLK8 130-8 may be disposed on the array substrate 220.
  • the black matrix 215 may be used, for example, to make each signal line invisible to the outside, and to avoid possible light leakage at the edge of the display panel 10.
  • the array substrate 220 and the color filter substrate 210 are only used here for illustrative purposes. Therefore, only the elements directly related to the embodiments of the present disclosure are depicted, and therefore, there may be many problems on them. Other elements shown (for example, layers, materials, devices, etc.).
  • the color filter substrate 210 and the array substrate 220 can be connected by a sealant 230 and the liquid crystal layer 240 can be sealed inside the display panel 10.
  • the process of connecting the color filter substrate 210 and the array substrate 220 is generally referred to as a "box-pairing” or "box-forming" process.
  • the sealant 230 may be formed on the outer side of the liquid crystal layer 240 (ie, the left side in the figure) to keep the liquid crystal layer 240 inside the display panel 10.
  • the width of the sealant 230 may be about 1.1 mm (that is, the distance from the boundary line 231 to the boundary line 233 in the lower half of FIG. 2), and the boundary line 233 of the sealant 230 is black
  • the distance from the boundary line of the matrix 215 may be about 0.3 mm
  • the distance from the left (outer) boundary line of the ground signal line 149 to the boundary line of the black matrix 215 may be about 0.1 mm
  • the distance of the boundary line of the substrate 210 is about 0.2 mm. In this way, it can be ensured that the width of the frame area 110 of the display panel 10 is generally about 3 mm and less than 5 mm.
  • the embodiments of the present disclosure are not limited thereto.
  • sealants of different materials can be used, the width of the sealant 230 can be reduced.
  • different signal line layout designs can be used (for example, a 4-clock signal line design, etc.), the overall width of all signal lines can be changed, thereby further reducing the frame.
  • FIG. 3 is a side view showing a further partial configuration 250 of the partial configuration example 120 of the display panel 10 shown in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 3 shows the part enclosed by the dashed frame 250 in FIG. 2 and related structures around it.
  • Three clock signal lines are shown in FIG. 3, namely: a third clock signal line 130-3, a fourth clock signal line 130-4, and a fifth clock signal line 130-5.
  • One or more insulating layers are respectively formed above each clock signal line.
  • the steps of forming each clock signal line and/or these insulating layers may be an original part of the process of manufacturing the TFT array on the array substrate 220, so as not to add any new The process saves manufacturing time and reduces costs.
  • the third clock signal line 130-3, the fourth clock signal line 130-4, and the fifth clock signal line 130-5 may be simultaneously formed in the step for forming the gate of the TFT (for example, , See Figure 5A).
  • the gate mask pattern at a position corresponding to each clock signal line on a mask plate (or photomask) for forming the gate of the TFT.
  • the clock signal lines are also formed at the same time in the same process of forming the gate.
  • the insulating layers 131-3, 131-4, and 131-5 may be simultaneously formed in a step for forming a gate insulating layer (Gate Insulation or GI for short) of a TFT (for example, see FIG.
  • the insulating layers 132-3, 132-4, and 132-5 may be simultaneously formed in a step for forming a passivation layer (Passivation or PVX for short) of the TFT (for example, see FIG. 5E).
  • Passivation passivation or PVX for short
  • FIG. 3 is only used to illustrate the structure, and therefore, the simplified schematic diagram is given, which does not mean that the actual product must be the structure shown in FIG. 3.
  • the structure of the upper and lower layers with the same width as shown in FIG. 3 is usually not formed, but a structure that wraps and covers the clock signal line is formed as shown on the left side of FIG. 5F.
  • FIG. 3 shows that each clock signal line is provided with two insulating layers
  • the present disclosure is not limited to this, but any number of insulating layers may be provided.
  • the main reason for the two insulating layers in FIG. 3 is to simplify the production process, and to not significantly change the original production process and increase the production cost.
  • the insulating layer provided can also be one of the gate insulating layer and the passivation layer, rather than both. For example, by adding a mask to shield the position corresponding to the clock signal line when forming one of the gate insulating layer or the passivation layer of the TFT, thereby avoiding the formation of the corresponding insulating layer.
  • a new process can also be added to specifically form a separate insulating layer on the clock signal line instead of using the above steps in the TFT manufacturing process.
  • part of the clock signal lines on the array substrate (for example, the fifth clock signal line shown in FIG. 2 CLK5 130-5 to the eighth clock signal line CLK8 130-8) are covered by the liquid crystal layer 240, and part of the clock signal lines (for example, the first clock signal line CLK1 130-1 to the third clock signal line CLK3 shown in FIG. 130-3) is covered by the sealant 230, and a part of the clock signal line (for example, the fourth clock signal line CLK4 130-4 shown in FIG. 2) is partially covered by the sealant 230 and partially covered by the liquid crystal layer 240, As shown in Figure 2 and Figure 3.
  • FIG. 4 is a side view showing a further partial configuration 250 of another partial configuration example 120 of the display panel 10 shown in FIG. 2 according to an embodiment of the present disclosure. Similar to FIG. 3, FIG. 4 shows the part encircled by the dashed frame 250 in FIG. 2 and related structures around it. Similarly, FIG. 4 also shows three clock signal lines, namely: a third clock signal line 130-3, a fourth clock signal line 130-4, and a fifth clock signal line 130-5. Also similar to FIG. 3, one or more insulating layers (for example, 131-3, 131-4, 131-5, 132-3, 132-4, and 132-5) are respectively formed above each clock signal line, No detailed description here.
  • a conductive layer or an electric field shielding layer may be formed above the insulating layer. Shielding layers 133-3, 133-4 and 133-5).
  • the direction of the electric field caused by each clock signal line (for example, the third clock signal line 130-3, the fourth clock signal line 130-4, or the fifth clock signal line 130-5) can be made They all point to the electric field shielding layer instead of the sealant 230 and the liquid crystal layer 240 with different dielectric constants, so that the coupling effects of the clock signal lines are roughly the same, and the difference between the clock signals output by it is significantly reduced. This avoids the undesirable effects of horizontal stripes on the display screen eventually caused.
  • the electric field shielding layers 133-3, 133-4, and 133-5 can all be electrically connected to a separate circuit of the display driving circuit (Chip on Film or COF) of the display panel 10, such as Vcom2 (as shown in Figure 7). (Shown), and isolated from the Vcom 143 that provides the common electrode driving signal to the common electrode in each pixel, so as to avoid affecting the normal display of the pixel.
  • a separate circuit of the display driving circuit (Chip on Film or COF) of the display panel 10 such as Vcom2 (as shown in Figure 7). (Shown), and isolated from the Vcom 143 that provides the common electrode driving signal to the common electrode in each pixel, so as to avoid affecting the normal display of the pixel.
  • the electric field shielding layer located on each clock signal line may be referred to as the electric field shielding sublayer.
  • the electric field shielding layer is located on the third clock signal line 130. -3.
  • the electric field shielding layers on the fifth clock signal line 130-5 and the fourth clock signal line 130-4 are respectively called the first electric field shielding sublayer, the second electric field shielding sublayer and the third electric field shielding sublayer, and They are denoted by reference numerals 133-3, 133-5, and 133-4, respectively. It should be understood that such an expression is mainly for the convenience of description.
  • these electric field shielding sublayers are all located on the same layer, thereby constituting the electric field shielding sublayer.
  • FIGS. 5A to 5G are diagrams showing examples of methods for manufacturing an array substrate according to an embodiment of the present disclosure (for example, the array substrate 220 including each signal line and its auxiliary structure shown in FIGS. 3 and 4) is manufactured Schematic diagram of each stage of the product. It should be noted that the method of FIGS. 5A to 5G is implemented as a part of the process of manufacturing TFTs on the array substrate, and therefore the right side of each of FIGS. 5A to 5G shows that the corresponding TFT Schematic diagram of each stage of TFT in the process.
  • a clock signal line 530 (for example, each of the clock signal lines in FIG. 2, FIG. 3, or FIG. 4) may be formed on the substrate 510 first.
  • the gate 520 of the TFT structure (and the corresponding gate (or scanning) signal line, etc.) can be formed on the substrate 510.
  • the clock signal line 530 and the gate 520 may be simultaneously formed in the same step. However, in other embodiments, they may be formed sequentially at different times.
  • a gate insulating layer 531 covering the clock signal line 530 may be formed on the clock signal line 530.
  • a gate insulating layer 531 of a TFT structure may be formed on the gate 520.
  • the gate insulating layer 531 on the clock signal line 530 and the gate insulating layer 531 on the gate 520 may be formed simultaneously in the same step. However, in other embodiments, they may be formed sequentially at different times.
  • an active layer 532 may be formed on the gate insulating layer 531. Since the active layer 532 may be formed through a mask, the pattern on the mask may be designed so that the active layer 532 is not formed on the gate insulating layer 531 on the clock signal line 530. In other words, there is no need to form the active layer 532 for the clock signal line 530.
  • a source electrode 533 and a drain electrode 534 may be formed on the gate insulating layer 531 and/or the active layer 532.
  • the source electrode 533 and the drain electrode 534 can be formed by a mask, the pattern on the mask can be designed so that the source electrode 533 is not formed on the gate insulating layer 531 on the clock signal line 530 And drain 534. In other words, there is no need to form the source electrode 533 and the drain electrode 534 for the clock signal line 530.
  • a passivation layer 535 may be formed on the gate insulating layer 531 on the clock signal line 530.
  • a passivation layer 535 of a TFT structure may be formed on the active layer 532, the source electrode 533, the drain electrode 534, and the gate insulating layer 531.
  • the passivation layer 535 above the clock signal line 530 and the passivation layer 535 above the gate 520 may be simultaneously formed in the same step. However, in other embodiments, they may be formed sequentially at different times.
  • a through hole may be formed on the passivation layer 535, so that a part of the drain electrode 534 covered by it is exposed to facilitate subsequent electrical connection with the pixel electrode. Since the through hole may be formed through a mask, the pattern on the mask may be designed so that the through hole is not formed on the passivation layer 535 above the clock signal line 530. In other words, there is no need to form a via hole for the passivation layer 535 of the clock signal line 530.
  • an electric field shielding layer (or pixel electrode) 536 may be formed on the passivation layer 535 above the clock signal line 530.
  • a pixel electrode 536 electrically connected to the drain electrode 534 may be formed at a through hole at a designated position on the passivation layer 535 above the gate electrode 520 on the right side of FIG. 5G.
  • the electric field shielding layer 536 above the clock signal line 530 and the pixel electrode 536 above the gate 520 may be simultaneously formed in the same step. However, in other embodiments, they may be formed sequentially at different times.
  • the pixel electrode 536 and/or the electric field shielding layer 536 may be made of a transparent conductive material, such as indium tin oxide (ITO).
  • the clock signal line related structure shown in FIG. 4 can be formed, and the effect of avoiding or reducing the horizontal stripes is achieved.
  • FIGS. 5A to 5G only show a solution for manufacturing the clock signal line 530 with the corresponding electric field shielding layer 536 using, for example, a 5-masks process, but the present disclosure is not limited thereto.
  • the common electrode in the case of other array substrate manufacturing processes, for example, in the case where the common electrode is formed after the passivation layer 535 instead of the pixel electrode, the common electrode can also be formed over the clock signal line 530 while manufacturing the common electrode.
  • Electric field shielding layer 536 This can also avoid or reduce different coupling effects caused by different covering materials (for example, the sealant 230 and the liquid crystal layer 240).
  • FIG. 6 is a flowchart illustrating an example method 600 for manufacturing an array substrate according to an embodiment of the present disclosure.
  • the method 600 may start in step S610.
  • step S610 at least a first clock signal line (for example, the third clock signal line CLK3 130-3 in FIG. 4) and a second clock signal line (for example, the fifth clock signal line in FIG. 4) may be formed on the substrate.
  • Multiple clock signal lines including the clock signal line CLK5 130-5) for example, the first clock signal line CLK1 130-1 to the eighth clock signal line CLK8 130-8 in FIG. 2).
  • the first clock signal line may have a first part formed on a first area (for example, an area corresponding to the sealant 230) of the substrate (for example, the substrate 220), and the second clock signal line may There is a second part formed on a second area of the substrate (for example, an area corresponding to the liquid crystal layer 240).
  • an electric field shielding layer (for example, the multiple electric field shielding layers 133-3, 133-4, 133-5 shown in FIG. 4) may be formed above the first part and the second part, so that the electric field The shielding layer and the first clock signal line are electrically insulated from each other, and the electric field shielding layer and the second clock signal line are electrically insulated from each other.
  • step S620 may include: forming an insulating layer on each of the first part of the first clock signal line and the second part of the second clock signal line (for example, FIG. 4 A plurality of insulating layers 131-3, 131-4, 131-5, 132-3, 132-4, and 132-5 are shown); and an electric field shielding layer is formed on the insulating layer.
  • the method 600 may further include: forming a gate (for example, the gate 520) on a substrate (for example, the substrate 510); and forming a gate insulating layer (for example, a gate insulating layer) on the gate.
  • an active layer for example, active layer 532 is formed on the gate insulating layer; a source (for example, source 533) and a drain (for example, drain) are formed on the gate insulating layer and the active layer 534); forming a passivation layer (for example, passivation layer 535) on the active layer, source, drain, and gate insulating layer; forming a through hole on the passivation layer to expose part of the source or drain And forming a pixel electrode or a common electrode (for example, a pixel electrode 536) on the passivation layer, so that the pixel electrode or the common electrode is electrically connected to the source or drain via the through hole.
  • a passivation layer for example, passivation layer 535
  • the step of forming a plurality of clock signal lines may be performed simultaneously with the step of forming the gate (for example, see FIG. 5A).
  • the step of forming the insulating layer may be performed simultaneously with the step of forming the gate insulating layer and/or the step of forming the passivation layer (for example, see FIG. 5B or FIG. 5E).
  • the step of forming the electric field shielding layer may be performed simultaneously with the step of forming the pixel electrode layer or the step of forming the common electrode layer (for example, see FIG. 5G).
  • the step of forming a corresponding electric field shielding layer on the insulating layer includes: forming an electric field shielding layer on the insulating layer having the same width as the clock signal line below it.
  • a display panel is also provided, which may include any one or more of the array substrates described above and a display driving circuit electrically connected to the array substrate.
  • the electric field shielding layer in the array substrate may be electrically connected to the display driving circuit, and the display driving circuit provides a separate electrical signal (for example, Vcom2 independent of Vcom, as shown in FIG. 7) .
  • a display device is also provided, which may include the display panel as described above.
  • each pixel in the display device emit light at the same gray scale as uniformly as possible, and avoid or at least reduce the poor display of the display.
  • Phenomenon such as horizontal stripes, light spots, etc., thereby improving the yield of the display and the user experience.
  • functions described in this document as being implemented by pure hardware, pure software and/or firmware can also be implemented by means of special hardware, a combination of general hardware and software, etc.
  • functions described as being implemented by dedicated hardware e.g., field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.
  • general-purpose hardware e.g., central processing unit (CPU), digital signal processing It can be realized by a combination of DSP and software, and vice versa.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种阵列基板（220），包括：衬底（220）；位于衬底（220）上的至少包括第一时钟信号线（130-3）和第二时钟信号线（130-5）在内的多条时钟信号线（130-3~ 130-5），第一时钟信号线（130-3）具有第一部分，第一部分位于衬底（220）的第一区域上，第二时钟信号线（130-5）具有第二部分，第二部分位于衬底（220）的不同于第一区域的第二区域上；位于第一部分上方和第二部分上方的电场屏蔽层（133-3~133-5），电场屏蔽层（133-3）与第一时钟信号线（130-3）彼此电绝缘，以及电场屏蔽层（133-5）与第二时钟信号线（130-5）彼此电绝缘。还提供了阵列基板（220）、显示面板（10）、显示装置及阵列基板（220）的制造方法。

Description

阵列基板、显示面板、显示装置及阵列基板的制造方法
相关申请的交叉引用
本申请要求于2019年4月30日递交中国专利局的、申请号为201910365770.9的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，且更具体地涉及阵列基板、显示面板、显示装置及阵列基板的制造方法。
背景技术
随着液晶显示技术的普及，液晶显示器(LCD)已经成为了人们日常生产、生活中必不可少的工具。LCD作为一种显示装置，其通过使用液晶分子的特性来实现画面显示。
具体地，液晶是一种介于固体和液体之间的物质，其在常态下呈液态，然而其分子排列却和固体晶体一样非常规则。如果对其施加一个电场，则可以改变其分子排列。通过配合偏光片，这种特性可以实现画面显示。例如，对于LCD的某个特定像素来说，如果通过控制其相应的薄膜晶体管(TFT)开关来使得其像素电极和公共电极之间形成不同的电势差，则夹在这两个电极之间的液晶分子可以发生不同程度的偏转，从而使得偏振光相应变为不通过、部分通过或通过，从而实现了单点像素的开关和/或不同灰阶显示。
然而，随着显示器的分辨率日益增大，其可能具有几十万、几百万、甚至上千万个像素。因此，随着显示器上的电路长度、工艺复杂度的增加，如何保证海量的像素在相同的灰阶下能够均匀地发光，就成了必须要解决的技术难题。
发明内容
在一个方面，本公开的一些实施例提供了一种阵列基板。该阵列基板包括：衬底；位于所述衬底上的至少包括第一时钟信号线和第二时钟信号线在内的多条时钟信号 线，所述第一时钟信号线具有第一部分，所述第一部分位于所述衬底的第一区域上，所述第二时钟信号线具有第二部分，所述第二部分位于所述衬底的不同于所述第一区域的第二区域上；位于所述第一部分上方和所述第二部分上方的电场屏蔽层，所述电场屏蔽层与所述第一时钟信号线彼此电绝缘，以及所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
在一些实施例中，所述阵列基板还包括：绝缘层，位于所述第一部分和所述电场屏蔽层之间以及位于所述第二部分和所述电场屏蔽层之间，以使得所述电场屏蔽层与所述第一时钟信号线彼此电绝缘并使得所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
在一些实施例中，所述电场屏蔽层包括第一电场屏蔽子层和第二电场屏蔽子层，所述第一电场屏蔽子层在所述衬底上的正投影覆盖所述第一部分在所述衬底上的正投影，并且所述第二电场屏蔽子层在所述衬底上的正投影覆盖所述第二部分在所述衬底上的正投影。
在一些实施例中，在与时钟信号线的延伸方向垂直的宽度方向上，所述第一电场屏蔽子层与所述第一时钟信号线具有相同的宽度，所述第二电场屏蔽子层与所述第二时钟信号线具有相同的宽度。
在一些实施例中，所述阵列基板还包括：
位于所述衬底上的栅极；
位于所述栅极上的栅极绝缘层；
位于所述栅极绝缘层的有源层；
位于所述栅极绝缘层和所述有源层上的源极和漏极；和
位于所述有源层、所述源极、所述漏极和所述栅极绝缘层上的钝化层，
其中，所述绝缘层与所述栅极绝缘层和所述钝化层中的至少一个位于同一层。
在一些实施例中，所述阵列基板还包括：位于所述钝化层上的像素电极或公共电极，其中，所述电场屏蔽层与所述像素电极或所述公共电极位于同一层。
在另一方面，本公开的实施例还提供一种显示面板，其中，所述显示面板包括上述的阵列基板。
在一些实施例中，所述显示面板还包括位于所述阵列基板上的密封胶，
其中，所述密封胶覆盖所述第一区域，并且所述密封胶覆盖所述第一时钟信号线的所述第一部分。
在一些实施例中，所述显示面板还包括位于所述阵列基板上的液晶层，
其中，所述液晶层覆盖所述第二区域，并且所述液晶层覆盖所述第二时钟信号线的所述第二部分。
在一些实施例中，所述多条时钟信号线还包括第三时钟信号线，所述第三时钟信号线位于所述第一时钟信号线与所述第二时钟信号线之间，并且，所述第三时钟信号线的一部分被所述密封胶覆盖，所述第三时钟信号线的另一部分被所述液晶层覆盖。
在一些实施例中，所述电场屏蔽层包括位于所述第三时钟信号线的至少一部分上的第三电场屏蔽子层，所述第三电场屏蔽子层在所述衬底上的正投影覆盖所述第三时钟信号线的至少一部分在所述衬底上的正投影。
在一些实施例中，所述密封胶覆盖位于所述第一时钟信号线的所述第一部分上方的电场屏蔽层。
在一些实施例中，所述液晶层覆盖位于所述第二时钟信号线的所述第二部分上方的电场屏蔽层。
在一些实施例中，所述密封胶覆盖所述第三电场屏蔽子层的一部分，所述液晶层覆盖所述第三电场屏蔽子层的另一部分。
在一些实施例中，所述显示面板还包括与所述阵列基板电连接的显示驱动电路，其中，所述电场屏蔽层与所述显示驱动电路电连接，并由所述显示驱动电路提供单独的电信号。
在又一方面，本公开的一些实施例提供了一种显示装置。该显示装置包括前述的显示面板。
在再一方面，本公开的一些实施例提供了一种制造阵列基板的方法。该方法包括：在衬底上形成至少包括第一时钟信号线和第二时钟信号线在内的多条时钟信号线，所述第一时钟信号线具有第一部分，所述第一部分形成于所述衬底的第一区域上，所述第二时钟信号线具有第二部分，以及所述第二部分形成于所述衬底的不同于所述第一区域的第二区域上；以及在所述第一部分上方和所述第二部分上方形成电场屏蔽层，使得所述电场屏蔽层与所述第一时钟信号线彼此电绝缘，以及所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
在一些实施例中，在所述第一部分上方和所述第二部分上方形成电场屏蔽层的步骤包括：在所述第一时钟信号线的第一部分和所述第二时钟信号线的第二部分中的每一个上形成绝缘层；以及在所述绝缘层上形成电场屏蔽层。
在一些实施例中，所述方法还包括：在所述衬底上形成栅极；在所述栅极上形成栅极绝缘层；在所述栅极绝缘层上形成有源层；在所述栅极绝缘层和所述有源层上形成源极和漏极；在所述有源层、所述源极、所述漏极和所述栅极绝缘层上形成钝化层；在所述钝化层上形成通孔，以暴露所述源极或所述漏极的一部分；以及在所述钝化层上形成像素电极或公共电极，使得所述像素电极或所述公共电极经由所述通孔与所述源极或所述漏极电连接。
在一些实施例中，形成多条时钟信号线的步骤是与形成栅极的步骤同时进行的。
在一些实施例中，形成绝缘层的步骤是与形成所述栅极绝缘层的步骤和/或形成所述钝化层的步骤同时进行的。
在一些实施例中，形成电场屏蔽层的步骤是与形成所述像素电极或所述公共电极的步骤同时进行的。
附图说明
通过下面结合附图说明本公开的优选实施例，将使本公开的上述及其它目的、特征和优点更加清楚，其中：
图1是示出了根据本公开实施例的示例显示面板的俯视图。
图2是示出了根据本公开实施例的图1所示的显示面板的局部构造的俯视图和侧视图。
图3是示出了根据本公开实施例的图2所示的显示面板的局部构造示例的进一步局部构造的侧视图。
图4是示出了根据本公开实施例的图2所示的显示面板的另一局部构造示例的进一步局部构造的侧视图。
图5A～图5G是示出了使用根据本公开实施例的制造阵列基板的示例方法所制造的产品的各阶段示意图。
图6是示出了根据本公开实施例的用于制造阵列基板的示例方法的流程图。
图7是示意性示出了根据本公开实施例的显示面板中的电场屏蔽层与显示驱动电路电连接的示意图。
具体实施方式
下面参照附图对本公开的部分实施例进行详细说明，在描述过程中省略了对于本公开来说是不必要的细节和功能，以防止对本公开的理解造成混淆。在本说明书中，下述用于描述本公开原理的各种实施例只是说明，不应该以任何方式解释为限制公开的范围。参照附图的下述描述用于帮助全面理解由权利要求及其等同物限定的本公开的示例性实施例。下述描述包括多种具体细节来帮助理解，但这些细节应认为仅仅是示例性的。因此，本领域普通技术人员应认识到，在不脱离本公开的范围和精神的情况下，可以对本文中描述的实施例进行多种改变和修改。此外，为了清楚和简洁起见，省略了公知功能和结构的描述。此外，贯穿附图，相同的附图标记用于相同或相似的功能、器件和/或操作。此外，在附图中，各部分并不一定按比例来绘制。换言之，附图中的各部分的相对大小、长度等并不一定与实际比例相对应。
在本公开中，术语“包括”和“含有”及其派生词意为包括而非限制；术语“或”是包含性的，意为和/或。此外，在本公开的以下描述中，所使用的方位术语，例如“上”、“下”、“左”、“右”等均用于指示相对位置关系，以辅助本领域技术人员理解本公开实施例，且因此本领域技术人员应当理解：在一个方向上的“上”/“下”，在相反方向上可变为“下”/“上”，且在另一方向上，可能变为其它位置关系，例如“左”/“右”等。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
在本文中，除非另有说明，所采用的术语“位于同一层”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
以下，以本公开实施例应用于液晶显示装置的阵列基板为例来详细说明。然而本领域技术人员应当理解本公开的应用领域不限于此。事实上，根据本公开实施例的技术方案可以应用于其它需要提供一致的时钟信号或其它信号的场景中。此外，尽管在以下描述中以晶体管为底栅型薄膜晶体管(TFT)为例进行了描述，然而本公开不限于此。事实上，如本领域技术人员所能够理解的：对于顶栅型晶体管或其它类型晶体管同样可以实现本申请的技术方案，只需调整针对时钟信号线(或其它信号线)所设置的相应层即可。
图1是示出了根据本公开实施例的示例显示面板10的俯视图。如图1所示，显示面板10可包括有效显示区域(AA)100和边框区域110。AA 100中包括由多个像素组成的像素阵列，其可用于根据显示驱动电路提供的驱动信号来显示所需的画面。
在一些实施例中，边框区域110可以用于防止光线从显示面板10的边缘漏出。例如，在采用液晶显示技术的情况下，在显示面板10的边缘处，如果没有边框区域110的阻挡，则穿过背光模块的导光板出射的光线将造成显示面板10边缘的漏光现象，严重的还会导致出现明显的光斑。
此外，除了防止显示面板10边缘漏光之外，边框区域110中还设置有用于提供各种信号(包括但不限于：时钟信号、栅极驱动信号、数据驱动信号、高电平信号、低电平信号、接地等)的各条线路。接下来，将结合图2来详细描述边框区域110的局部构造120中的具体细节。
图2是示出了根据本公开实施例的图1所示的显示面板10的局部构造120的俯视图和侧视图。具体地，图2的上半部示出了图1所示的显示面板10的局部120的俯视图，且图2的下半部示出了图1所示的显示面板10的局部120沿上半部俯视图中的剖线A-A’的截面图或侧视图。需要注意的是：图2中仅示出了与本公开实施例有关的部分，而并未示出本领域技术人员所熟知的部分。此外，图2中的部分细节在需要时将结合图3～图5来进一步展示。
如图2所示，显示面板10的局部构造120中可设置有多条线路，包括(但不限于)：多条时钟信号线CLK1 130-1～CLK 8 130-8、垂直开始(Start Vertical)信号线或 帧初始信号线STV1、帧前复位信号STV2、高电平信号线VDD1、VDD2、低电平信号线LVSS、VSS、接地信号线GND、公共电极信号线Vcom、以及用于生产时维修调试的RP信号线和反馈信号线FEED等。然而需要注意的是：这仅仅是根据本公开实施例的显示面板10的边框区域110的局部构造120中的一种可能实施例，而本公开不限于此。在另一些实施例中，显示面板10的边框区域110的局部构造120完全可以包括更多或更少的线路，或者包括不同的线路。
在图2所示实施例中，示出了8条时钟信号线CLK1 130-1～CLK8 130-8，它们可用于向显示面板10的栅极驱动电路(Gate driver on Array或简称为GOA)160中的各个移位寄存器提供时钟信号，以使得各个移位寄存器能够输出用于驱动相应像素行的栅极驱动信号。例如，如图2所示，第一时钟信号线CLK1 130-1可电连接到GOA 160中最下边的移位寄存器，以向其提供在相应像素行扫描时所需要的时钟信号。类似地，第二时钟信号线CLK2 130-2、第三时钟信号线CLK3 130-3、第四时钟信号线CLK4 130-4可分别电连接到GOA 160中的对应移位寄存器，以向其提供相应像素行扫描时所需要的时钟信号。需要注意的是：尽管在图2中将各条相邻时钟信号线示出为好像与相邻的移位寄存器电连接并进而与相邻的像素行信号连接，但实际上相邻时钟信号线可以与非相邻的移位寄存器电连接，且相邻的移位寄存器可以向非相邻的像素行提供栅极驱动信号。例如，在图1所示的显示面板10的左右侧边框中都设置了GOA的实施例中，面板左侧GOA(例如，与图2所示的各条时钟信号线电连接的GOA 160)可以提供奇数行像素的栅极驱动信号，而面板右侧GOA可以提供偶数行像素的栅极驱动信号。又例如，在一些实施例中，各条时钟信号线与GOA 160中的电连接关系可以不是如图2所示的按时钟信号线从左至右依次连接，而是可以按其它顺序电连接。例如第一时钟信号线CLK1 130-1可以电连接最下方的移位寄存器，第三时钟信号线CLK3 130-3可以电连接上一行的移位寄存器，第五时钟信号线CLK5 130-5可以电连接再上一行的移位寄存器，依此类推。
此外，在图2所示实施例中，各条时钟信号线CLK1 130-1～CLK8 130-8的宽度(在图2的上半部的俯视图中以与时钟信号线延伸方向垂直的方向作为宽度方向)可以约为120微米(μm)。此外，其它信号线可以分别为例如80μm(例如，VDD1 151、VDD2 153、VSS 159、STV2 157等)、100μm(例如，LVSS 155、RP 147、FEED 145、STV1 141等)、150μm(例如，GND 149等)和/或340μm(例如，Vcom 143等)。然而这些信 号线的宽度可以取决于设计需要，而不限于图2所示实施例。例如，由于公共电极信号线Vcom 143通常需要连接到每个像素中以向每个像素中的公共电极提供电信号，因此为了保证显示面板10中的各个位置处的像素的公共电极的电信号尽量均匀一致，通常会将图2所示的Vcom 143设计为绕显示面板10的边框区域110一周，以从各个方向向不同位置处的像素提供公共电极所需的电信号。然而，这样设计的公共电极线Vcom143的长度比其它信号线要长许多，为了降低电阻，则可以将其宽度加宽，从而形成例如图2中所示的最宽的信号线。类似地，其它信号线也可以根据实际需要来调整其相应宽度，而不限于图2所示的具体设计。
参见图2所示的下半部的局部构造120的侧视图，其示出了沿图2的上半部中的线A-A’剖开的截面图或侧视图。如图2下半部所示，包括多条时钟信号线CLK 1 130-1～CLK8 130-8在内的多条信号线可设置在阵列基板220上。与阵列基板220相对设置的是具有黑矩阵215的彩膜基板210。黑矩阵215可以用于例如使得各信号线对于外部不可见，并避免可能在显示面板10的边缘处发生漏光现象。然而，需要注意的是：阵列基板220和彩膜基板210在这里仅用作说明示意之用，因此只描绘出了与本公开实施例直接相关的要素，且因此实际上其上可以存在很多未示出的其它要素(例如，膜层、材料、器件等)。
如图2的下半部所示，在彩膜基板210和阵列基板220之间可通过密封胶230来连接并将液晶层240密封在显示面板10的内部。连接彩膜基板210和阵列基板220的工艺通常被称为“对盒”或“成盒”工艺。在对盒工艺中，通常在彩膜基板210和阵列基板220之一的指定位置处预先形成一圈密封胶，然后取决于液晶灌注工艺的不同，可以要么将这两个基板直接对盒然后利用毛细作用来灌注液晶材料到对盒后的由密封胶所密闭的空间中，要么在形成密封胶的基板上由密封胶圈出的范围内滴灌液晶，然后再将彩膜基板210和阵列基板220对盒。不管哪种方式，通常都会采用紫外线照射或加热方式来激活密封胶230，从而使得彩膜基板210和阵列基板220相对固定。回到图2所示实施例，密封胶230可形成在液晶层240的外侧(即，图中的左侧)，以将液晶层240保持在显示面板10内部。
在图2所示实施例中，密封胶230的宽度可约为1.1毫米(即，从图2下半部中的边界线231到边界线233的距离)，密封胶230的边界线233到黑矩阵215的边界线的距离可约为0.3毫米，接地信号线149的左侧(外侧)边界线到黑矩阵215的边界 线的距离可约为0.1毫米，而黑矩阵215的边界线到彩膜基板210的边界线的距离约为0.2毫米。这样，可以保证显示面板10的边框区域110的宽度总体上在3毫米左右，且小于5毫米。然而本公开实施例不限于此。在其它实施例中，由于例如可以采用不同材料的密封胶，因此密封胶230的宽度可以变小。此外，在另一些实施例中，由于可以采用不同的信号线布局设计(例如，采用4时钟信号线设计等)，因此可以改变所有信号线的整体宽度，从而使得边框进一步降低。
接下来，将结合图3和图4来详细描述根据本公开实施例的时钟信号线的相关设计。
图3是示出了根据本公开实施例的图2所示的显示面板10的局部构造示例120的进一步局部构造250的侧视图。具体地，图3示出了图2中的由虚线框250所圈出的部分以及周围的相关结构。图3中示出了三条时钟信号线，即：第三时钟信号线130-3、第四时钟信号线130-4和第五时钟信号线130-5。每条时钟信号线上方分别形成有一个或多个绝缘层(例如，131-3、131-4、131-5、132-3、132-4和132-5)。如下面将结合图5A～图5G所要描述的，形成各时钟信号线和/或这些绝缘层的步骤可以是在制造阵列基板220上的TFT阵列的工艺中的原有一部分，从而不增加任何新的工序，节省了制造时间、降低了成本。
在一些实施例中，第三时钟信号线130-3、第四时钟信号线130-4和第五时钟信号线130-5可以是在用于形成TFT的栅极的步骤中同时形成的(例如，参见图5A)。例如，通过在用于形成TFT的栅极的掩模板(或光罩)上与各时钟信号线相对应的位置处设置栅极掩模图案来实现。这样，在形成栅极的同一道工序中也同时形成了各时钟信号线。类似地，绝缘层131-3、131-4和131-5可以是在用于形成TFT的栅极绝缘层(Gate Insulation或简称为GI)的步骤中同时形成的(例如，参见图5B)，而绝缘层132-3、132-4和132-5可以是在用于形成TFT的钝化层(Passivation或简称为PVX)的步骤中同时形成的(例如，参见图5E)。然而，需要注意的是：图3中仅作为示意说明结构之用，且因此给出的是简化的示意图，并不代表实际产品一定是图3所示的构造。例如，在形成各绝缘层时，通常不会如图3所示形成上下层宽度完全一致的结构，而是如图5F的左侧所示形成包裹覆盖时钟信号线的结构。例如，在常见的采用五个掩模板(5masks)的阵列基板制造工艺中，对于栅极绝缘层和钝化层的形成来 说通常是没有掩模板的，且因此无法形成图3中所示出的规整的上下分层结构，而多半是类似于图5F中左侧所示的覆盖结构。
此外，尽管图3中示出了每条时钟信号线上设置有两个绝缘层，但本公开不限于此，而是可以设置有任何数量的绝缘层。图3中设置两个绝缘层的主要原因在于简化生产工序，以不显著改变原有生产工艺、不提高生产成本为目的。然而需要注意的是：所设置的绝缘层也可以是栅极绝缘层和钝化层之一，而不是二者都有。例如，通过增加一个掩模板以在形成TFT的栅极绝缘层或钝化层之一时将与时钟信号线相对应的位置处遮蔽，从而避免形成相应的绝缘层。此外，也可以增加新的工序来专门在时钟信号线上形成单独的绝缘层，而不是采用TFT制造工艺中的上述步骤。
然而，在目前的窄边框LCD显示面板中，由于边框较窄，导致阵列基板和彩膜基板在对盒之后，阵列基板上的部分时钟信号线(例如，图2所示的第五时钟信号线CLK5 130-5～第八时钟信号线CLK8 130-8)被液晶层240所覆盖，一部分时钟信号线(例如，图2所示的第一时钟信号线CLK1 130-1～第三时钟信号线CLK3 130-3)被密封胶230所覆盖，且一部分时钟信号线(例如，图2所示的第四时钟信号线CLK4 130-4)部分被密封胶230所覆盖且部分被液晶层240所覆盖，如图2和图3所示。
在这种情况下，在各条时钟信号线中传导时钟信号时，其中的电流会产生如图3所示的电场，从而与覆盖其的相应层(例如，密封胶230或液晶层240)发生耦合作用。然而，由于密封胶230的介电常数(例如，2.5～6)与液晶层240的介电常数(例如，液晶分子排列方向垂直时为2.6，平行时为5.2)不同，因此导致处于不同区域的时钟信号线(例如，图3所示的第三时钟信号线CLK3 130-3和第五时钟信号线CLK5 130-5)受到的耦合作用不同，并进而导致在同一灰阶条件(即，预期各行像素的充电时间要相同)下，这些时钟信号线中的时钟信号向相应移位寄存器输出的电平不同，并最终导致各行像素的栅极打开时间和像素充电时间不同，从而可能造成显示画面中的横纹不良现象。
因此，为了进一步改进本公开的方案，下面将结合图4来详细描述根据本公开另一实施例的时钟信号线的相关设计。
图4是示出了根据本公开实施例的图2所示的显示面板10的另一局部构造示例120的进一步局部构造250的侧视图。与图3类似地，图4示出了图2中的由虚线框250所圈出的部分以及周围的相关结构。同样地，图4中也示出了三条时钟信号线， 即：第三时钟信号线130-3、第四时钟信号线130-4和第五时钟信号线130-5。同样与图3类似地，每条时钟信号线上方分别形成有一个或多个绝缘层(例如，131-3、131-4、131-5、132-3、132-4和132-5)，这里不再详细描述。
与图3所示实施例相比，为了消除或减轻各时钟信号线与其覆盖物之间的耦合作用，在绝缘层上方还可形成有导电层或电场屏蔽层(例如，图4所示的电场屏蔽层133-3、133-4和133-5)。从而，如图4所示，可以使得由各时钟信号线(例如，第三时钟信号线130-3、第四时钟信号线130-4或第五时钟信号线130-5)引起的电场的方向均指向电场屏蔽层，而非具有不同介电常数的密封胶230和液晶层240，从而使得各时钟信号线受到的耦合作用大体一致，进而使得其输出的各时钟信号之间的差异显著降低，从而避免了最终引起的显示画面的横纹不良效果。
在一些实施例中，电场屏蔽层133-3、133-4和133-5均可以电连接到显示面板10的显示驱动电路(Chip on Film或COF)的单独线路上，例如Vcom2(如图7所示)，并与向各个像素中的公共电极提供公共电极驱动信号的Vcom 143相隔离，从而避免影响像素的正常显示。
需要说明的是，在本文中，为了描述方便，可以将位于各条时钟信号线上的电场屏蔽层分别称为电场屏蔽子层，例如，如图4所示，将位于第三时钟信号线130-3、第五时钟信号线130-5和第四时钟信号线130-4上的电场屏蔽层分别称为第一电场屏蔽子层、第二电场屏蔽子层和第三电场屏蔽子层，并且分别使用附图标记133-3、133-5和133-4表示。应该理解，这样的表述主要是出于方便描述的目的，在本公开的实施例中，这些电场屏蔽子层都位于同一层，从而构成所述电场屏蔽子层。
接下来，将结合图5A～图5G来详细描述制造图4所示的时钟信号线相关结构的方法。
图5A～图5G是示出了使用根据本公开实施例的制造阵列基板(例如，图3和图4所示的包括各信号线及其附属结构在内的阵列基板220)的示例方法所制造的产品的各阶段示意图。需要注意的是，图5A～图5G的方法是作为制造阵列基板上的TFT的工艺的一部分来实现的，且因此在图5A～图5G中的每幅图的右侧示出了在相应TFT工序中TFT的各阶段示意图。
该示例方法可从图5A开始。如图5A所示，可以首先在衬底510上形成时钟信号线530(例如，图2、图3或图4中的各条时钟信号线)。与此同时，在衬底510上可 以形成TFT结构的栅极520(以及相应的栅极(或扫描)信号线等)。换言之，时钟信号线530和栅极520可以是在同一步骤中同时形成的。然而，在另一些实施例中，它们也可以是在不同时机处先后形成的。
接下来，如图5B所示，可以在时钟信号线530上形成覆盖时钟信号线530的栅极绝缘层531。与此同时，在栅极520上可以形成TFT结构的栅极绝缘层531。换言之，时钟信号线530上的栅极绝缘层531和栅极520上的栅极绝缘层531可以是在同一步骤中同时形成的。然而，在另一些实施例中，它们也可以是在不同时机处先后形成的。
接下来，如图5C右侧所示，可以在栅极绝缘层531上形成有源层532。由于有源层532可以是通过掩模板来形成的，因此可以通过设计掩模板上的图案，来使得在时钟信号线530上的栅极绝缘层531上不形成有源层532。换言之，无需针对时钟信号线530来形成有源层532。
接下来，如图5D右侧所示，可以在栅极绝缘层531和/或有源层532上形成源极533和漏极534。同样地，由于源极533和漏极534可以是通过掩模板来形成的，因此可以通过设计掩模板上的图案，来使得在时钟信号线530上的栅极绝缘层531上不形成源极533和漏极534。换言之，无需针对时钟信号线530来形成源极533和漏极534。
接下来，如图5E所示，可以在时钟信号线530上的栅极绝缘层531上形成钝化层535。与此同时，在有源层532、源极533、漏极534和栅极绝缘层531上可以形成TFT结构的钝化层535。换言之，时钟信号线530上方的钝化层535和栅极520上方的钝化层535可以是在同一步骤中同时形成的。然而，在另一些实施例中，它们也可以是在不同时机处先后形成的。
接下来，如图5F右侧所示，可以在钝化层535上形成通孔，使得被其覆盖的漏极534的一部分暴露，以方便后续与像素电极电连接。由于该通孔可以是通过掩模板来形成的，因此可以通过设计掩模板上的图案，来使得在时钟信号线530上方的钝化层535上不形成通孔。换言之，无需针对时钟信号线530的钝化层535来形成通孔。
最后，如图5G所示，可以在时钟信号线530上方的钝化层535上形成电场屏蔽层(或像素电极)536。与此同时，在图5G右侧的栅极520上方的钝化层535上的指定位置的通孔处可以形成与漏极534电连接的像素电极536。换言之，时钟信号线530上方的电场屏蔽层536和栅极520上方的像素电极536可以是在同一步骤中同时形成的。然而，在另一些实施例中，它们也可以是在不同时机处先后形成的。在一些实施 例中，像素电极536和/或电场屏蔽层536可以是由透明导电材料制成的，例如氧化铟锡(ITO)。
通过使用上面结合图5A～图5G来描述的方法，可以形成图4所示的时钟信号线相关结构，并实现避免或减轻横纹不良的效果。
需要注意的是：图5A～图5G仅示出了在采用例如5-masks工艺来制造具有相应电场屏蔽层536的时钟信号线530的方案，然而本公开不限于此。例如，在采用其它阵列基板制造工艺的情况下，例如在钝化层535之后形成的是公共电极，而非像素电极的情况下，也可以在制造公共电极的同时在时钟信号线530的上方形成电场屏蔽层536。这同样可以实现避免或降低不同覆盖材料(例如，密封胶230和液晶层240)所导致的不同耦合作用。
图6是示出了根据本公开实施例的用于制造阵列基板的示例方法600的流程图。方法600可以开始于步骤S610。在步骤S610中，可以在衬底上形成至少包括第一时钟信号线(例如，图4中的第三时钟信号线CLK3 130-3)和第二时钟信号线(例如，图4中的第五时钟信号线CLK5 130-5)在内的多条时钟信号线(例如，图2中的第一时钟信号线CLK1 130-1～第八时钟信号线CLK8 130-8)。该第一时钟信号线可以具有第一部分，该第一部分形成于衬底(例如，衬底220)的第一区域(例如，与密封胶230相对应的区域)上，以及第二时钟信号线可以具有第二部分，该第二部分形成于衬底的第二区域(例如，与液晶层240相对应的区域)上。
接下来，在步骤S620中，可以在第一部分上方和第二部分上方形成电场屏蔽层(例如，图4所示的多个电场屏蔽层133-3、133-4、133-5)，使得电场屏蔽层与第一时钟信号线彼此电绝缘，以及电场屏蔽层与第二时钟信号线彼此电绝缘。
如前所述，在一些实施例中，步骤S620可以包括：在第一时钟信号线的第一部分和第二时钟信号线的第二部分中的每一个部分上分别形成绝缘层(例如，图4所示的多个绝缘层131-3、131-4、131-5、132-3、132-4和132-5)；以及在绝缘层上形成电场屏蔽层。在一些实施例中，方法600还可以包括：在衬底(例如，衬底510)上形成栅极(例如，栅极520)；在栅极上形成栅极绝缘层(例如，栅极绝缘层531)；在栅极绝缘层上形成有源层(例如，有源层532)；在栅极绝缘层和有源层上形成源极(例如，源极533)和漏极(例如，漏极534)；在有源层、源极、漏极和栅极绝缘层上形成钝化层(例如，钝化层535)；在钝化层上形成通孔，以暴露源极或漏极的一部分； 以及在钝化层上形成像素电极或公共电极(例如，像素电极536)，使得像素电极或公共电极经由通孔与源极或漏极电连接。在一些实施例中，形成多条时钟信号线的步骤可以是与形成栅极的步骤同时进行的(例如，参见图5A)。在一些实施例中，形成绝缘层的步骤可以是与形成栅极绝缘层的步骤和/或形成钝化层的步骤同时进行的(例如，参见图5B或图5E)。在一些实施例中，形成电场屏蔽层的步骤可以是与形成像素电极层的步骤或形成公共电极层的步骤同时进行的(例如，参见图5G)。在一些实施例中，在绝缘层上形成相应电场屏蔽层的步骤包括：在绝缘层上形成具有与其下方的时钟信号线相同宽度的电场屏蔽层。
此外，根据本公开的一些实施例，还提供了显示面板，其可以包括如上所述的任一种或多种阵列基板以及与阵列基板电连接的显示驱动电路。在一些实施例中，该阵列基板中的电场屏蔽层可以与显示驱动电路电连接，并由该显示驱动电路来提供单独的电信号(例如，与Vcom相独立的Vcom2，如图7所示)。此外，根据本公开的一些实施例，还提供了显示装置，其可以包括如上所述的显示面板。
通过使用根据本公开实施例的阵列基板、显示面板、显示装置及阵列基板的制造方法，可以使得显示装置中的各个像素在相同灰阶下发光尽量趋于一致，避免或至少减轻显示器的不良显示现象，例如横纹、光斑等现象，从而提升了显示器的良率和用户的体验。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开的范围不局限于上述特定实施例，而应由所附权利要求所限定。
此外，在本文中被描述为通过纯硬件、纯软件和/或固件来实现的功能，也可以通过专用硬件、通用硬件与软件的结合等方式来实现。例如，被描述为通过专用硬件(例如，现场可编程门阵列(FPGA)、专用集成电路(ASIC)等)来实现的功能，可以由通用硬件(例如，中央处理单元(CPU)、数字信号处理器(DSP))与软件的结合的方式来实现，反之亦然。

Claims (22)

  1. 一种阵列基板，包括：
    衬底；
    位于所述衬底上的至少包括第一时钟信号线和第二时钟信号线在内的多条时钟信号线，所述第一时钟信号线具有第一部分，所述第一部分位于所述衬底的第一区域上，所述第二时钟信号线具有第二部分，所述第二部分位于所述衬底的不同于所述第一区域的第二区域上；和
    位于所述第一部分上方和所述第二部分上方的电场屏蔽层，所述电场屏蔽层与所述第一时钟信号线彼此电绝缘，以及所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
  2. 根据权利要求1所述的阵列基板，还包括：
    绝缘层，位于所述第一部分和所述电场屏蔽层之间以及位于所述第二部分和所述电场屏蔽层之间，以使得所述电场屏蔽层与所述第一时钟信号线彼此电绝缘并使得所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
  3. 根据权利要求1所述的阵列基板，其中，所述电场屏蔽层包括第一电场屏蔽子层和第二电场屏蔽子层，所述第一电场屏蔽子层在所述衬底上的正投影覆盖所述第一部分在所述衬底上的正投影，并且所述第二电场屏蔽子层在所述衬底上的正投影覆盖所述第二部分在所述衬底上的正投影。
  4. 根据权利要求3所述的阵列基板，其中，在与时钟信号线的延伸方向垂直的宽度方向上，所述第一电场屏蔽子层与所述第一时钟信号线具有相同的宽度，所述第二电场屏蔽子层与所述第二时钟信号线具有相同的宽度。
  5. 根据权利要求1～4中任一项所述的阵列基板，还包括：
    位于所述衬底上的栅极；
    位于所述栅极上的栅极绝缘层；
    位于所述栅极绝缘层的有源层；
    位于所述栅极绝缘层和所述有源层上的源极和漏极；和
    位于所述有源层、所述源极、所述漏极和所述栅极绝缘层上的钝化层，
    其中，所述绝缘层与所述栅极绝缘层和所述钝化层中的至少一个位于同一层。
  6. 根据权利要求5所述的阵列基板，还包括：位于所述钝化层上的像素电极或公共电极，
    其中，所述电场屏蔽层与所述像素电极或所述公共电极位于同一层。
  7. 一种显示面板，其中，所述显示面板包括根据权利要求1～6中任一项所述的阵列基板。
  8. 根据权利要求7所述的显示面板，还包括位于所述阵列基板上的密封胶，
    其中，所述密封胶覆盖所述第一区域，并且所述密封胶覆盖所述第一时钟信号线的所述第一部分。
  9. 根据权利要求8所述的显示面板，还包括位于所述阵列基板上的液晶层，
    其中，所述液晶层覆盖所述第二区域，并且所述液晶层覆盖所述第二时钟信号线的所述第二部分。
  10. 根据权利要求9所述的显示面板，其中，所述多条时钟信号线还包括第三时钟信号线，所述第三时钟信号线位于所述第一时钟信号线与所述第二时钟信号线之间，并且，所述第三时钟信号线的一部分被所述密封胶覆盖，所述第三时钟信号线的另一部分被所述液晶层覆盖。
  11. 根据权利要求10所述的显示面板，其中，所述电场屏蔽层包括位于所述第三时钟信号线的至少一部分上的第三电场屏蔽子层，所述第三电场屏蔽子层在所述衬底上的正投影覆盖所述第三时钟信号线的至少一部分在所述衬底上的正投影。
  12. 根据权利要求8～11中任一项所述的显示面板，其中，所述密封胶覆盖位于所述第一时钟信号线的所述第一部分上方的电场屏蔽层。
  13. 根据权利要求9～11中任一项所述的显示面板，其中，所述液晶层覆盖位于所述第二时钟信号线的所述第二部分上方的电场屏蔽层。
  14. 根据权利要求11所述的显示面板，其中，所述密封胶覆盖所述第三电场屏蔽子层的一部分，所述液晶层覆盖所述第三电场屏蔽子层的另一部分。
  15. 根据权利要求7～14中任一项所述的显示面板，还包括与所述阵列基板电连接的显示驱动电路，
    其中，所述电场屏蔽层与所述显示驱动电路电连接，并由所述显示驱动电路提供单独的电信号。
  16. 一种显示装置，其中，所述显示装置包括根据权利要求7～15中任一项所述的显示面板。
  17. 一种制造阵列基板的方法，包括：
    在衬底上形成至少包括第一时钟信号线和第二时钟信号线在内的多条时钟信号线，所述第一时钟信号线具有第一部分，所述第一部分形成于所述衬底的第一区域上，所述第二时钟信号线具有第二部分，以及所述第二部分形成于所述衬底的不同于所述第一区域的第二区域上；以及
    在所述第一部分上方和所述第二部分上方形成电场屏蔽层，使得所述电场屏蔽层与所述第一时钟信号线彼此电绝缘，以及所述电场屏蔽层与所述第二时钟信号线彼此电绝缘。
  18. 根据权利要求17所述的方法，其中，在所述第一部分上方和所述第二部分上方形成电场屏蔽层的步骤包括：
    在所述第一时钟信号线的第一部分和所述第二时钟信号线的第二部分中的每一个上形成绝缘层；以及
    在所述绝缘层上形成电场屏蔽层。
  19. 根据权利要求18所述的方法，还包括：
    在所述衬底上形成栅极；
    在所述栅极上形成栅极绝缘层；
    在所述栅极绝缘层上形成有源层；
    在所述栅极绝缘层和所述有源层上形成源极和漏极；
    在所述有源层、所述源极、所述漏极和所述栅极绝缘层上形成钝化层；
    在所述钝化层上形成通孔，以暴露所述源极或所述漏极的一部分；以及
    在所述钝化层上形成像素电极或公共电极，使得所述像素电极或所述公共电极经由所述通孔与所述源极或所述漏极电连接。
  20. 根据权利要求19所述的方法，其中，形成多条时钟信号线的步骤是与形成栅极的步骤同时进行的。
  21. 根据权利要求19或20所述的方法，其中，形成绝缘层的步骤是与形成所述栅极绝缘层的步骤和/或形成所述钝化层的步骤同时进行的。
  22. 根据权利要求19～21中任一项所述的方法，其中，形成电场屏蔽层的步骤是与形成所述像素电极或所述公共电极的步骤同时进行的。
PCT/CN2020/075527 2019-04-30 2020-02-17 阵列基板、显示面板、显示装置及阵列基板的制造方法 WO2020220794A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910365770.9A CN110058469B (zh) 2019-04-30 2019-04-30 阵列基板、显示面板、显示装置及阵列基板的制造方法
CN201910365770.9 2019-04-30

Publications (1)

Publication Number Publication Date
WO2020220794A1 true WO2020220794A1 (zh) 2020-11-05

Family

ID=67322093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/075527 WO2020220794A1 (zh) 2019-04-30 2020-02-17 阵列基板、显示面板、显示装置及阵列基板的制造方法

Country Status (2)

Country Link
CN (1) CN110058469B (zh)
WO (1) WO2020220794A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110058469B (zh) * 2019-04-30 2020-11-27 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及阵列基板的制造方法
KR20220007802A (ko) 2020-07-10 2022-01-19 삼성디스플레이 주식회사 표시장치
CN114815421B (zh) * 2022-04-21 2024-04-19 南京京东方显示技术有限公司 阵列基板、显示面板及显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6982779B2 (en) * 2002-12-31 2006-01-03 Lg.Philips Lcd Co., Ltd. Liquid crystal display panel and fabricating method thereof
CN107134264A (zh) * 2016-02-26 2017-09-05 瀚宇彩晶股份有限公司 驱动电路和显示装置
CN107293556A (zh) * 2017-06-20 2017-10-24 惠科股份有限公司 一种显示面板及显示装置
CN107819009A (zh) * 2016-09-13 2018-03-20 三星显示有限公司 显示装置
CN108254979A (zh) * 2016-12-29 2018-07-06 南京瀚宇彩欣科技有限责任公司 显示面板及其制作方法
CN110058469A (zh) * 2019-04-30 2019-07-26 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及阵列基板的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101192792B1 (ko) * 2006-06-29 2012-10-26 엘지디스플레이 주식회사 Ｇｉｐ 구조의 액정표시장치
KR101896377B1 (ko) * 2012-10-12 2018-09-07 엘지디스플레이 주식회사 베젤이 최소화된 액정표시소자
CN103926732B (zh) * 2014-04-09 2017-05-17 厦门天马微电子有限公司 一种tft阵列基板、显示面板和显示装置
CN109976056B (zh) * 2019-04-08 2023-04-14 京东方科技集团股份有限公司 阵列基板、其制作方法、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6982779B2 (en) * 2002-12-31 2006-01-03 Lg.Philips Lcd Co., Ltd. Liquid crystal display panel and fabricating method thereof
CN107134264A (zh) * 2016-02-26 2017-09-05 瀚宇彩晶股份有限公司 驱动电路和显示装置
CN107819009A (zh) * 2016-09-13 2018-03-20 三星显示有限公司 显示装置
CN108254979A (zh) * 2016-12-29 2018-07-06 南京瀚宇彩欣科技有限责任公司 显示面板及其制作方法
CN107293556A (zh) * 2017-06-20 2017-10-24 惠科股份有限公司 一种显示面板及显示装置
CN110058469A (zh) * 2019-04-30 2019-07-26 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及阵列基板的制造方法

Also Published As

Publication number Publication date
CN110058469B (zh) 2020-11-27
CN110058469A (zh) 2019-07-26

Similar Documents

Publication Publication Date Title
JP6542986B2 (ja) Ｖａ型ｃｏａ液晶表示パネル
WO2019095764A1 (zh) 阵列基板、显示面板及显示装置
JP5770796B2 (ja) 液晶ディスプレイ装置
JP5351498B2 (ja) 液晶表示装置、及びその駆動方法
WO2020220794A1 (zh) 阵列基板、显示面板、显示装置及阵列基板的制造方法
JP5024110B2 (ja) 電気光学装置及び電子機器
WO2016179972A1 (zh) 阵列基板、液晶显示面板及显示装置
TWI753527B (zh) 顯示裝置
US9971212B2 (en) Array substrate, liquid crystal display panel, and liquid crystal display
EP3279721B1 (en) Array substrate and manufacturing method therefor, and display device
WO2016110032A1 (zh) 显示装置
US9685124B2 (en) Electro-optical device including a plurality of scanning lines
US9488887B2 (en) Display device
WO2018054098A1 (zh) 阵列基板及其制造方法、显示面板和显示设备
WO2017024708A1 (zh) 显示基板及其制作方法、显示器件
JP2008076800A (ja) 液晶装置及び電子機器
WO2016090750A1 (zh) 显示基板及其制造方法
US20110304791A1 (en) Display device
US7173681B2 (en) Two pixel electrodes interposing the signal line extending into without extending beyond the recess on the protection film caused by the contact hole
US20160320647A1 (en) Thin film transistor substrate
US9494838B2 (en) Liquid crystal display device
US10718982B2 (en) Liquid crystal display devices
US10558073B2 (en) Display substrate, liquid crystal display panel and fabricating method thereof, and liquid crystal display apparatus
KR102043862B1 (ko) 액정표시장치 및 그 제조방법
US20220123027A1 (en) Display panel and display apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20798613

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20798613

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20798613

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09/06/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20798613

Country of ref document: EP

Kind code of ref document: A1