WO2020220529A1 - Tft 阵列基板及其制作方法 - Google Patents

Tft 阵列基板及其制作方法 Download PDF

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Publication number
WO2020220529A1
WO2020220529A1 PCT/CN2019/102181 CN2019102181W WO2020220529A1 WO 2020220529 A1 WO2020220529 A1 WO 2020220529A1 CN 2019102181 W CN2019102181 W CN 2019102181W WO 2020220529 A1 WO2020220529 A1 WO 2020220529A1
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Prior art keywords
gate
layer
thickness
drain
tft array
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French (fr)
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田新斌
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate and a manufacturing method thereof.
  • LCD Liquid Crystal Display
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules between two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The liquid crystal molecules are controlled to change direction by powering on or not, and the light of the backlight module Refraction produces a picture.
  • the liquid crystal display panel consists of a color filter (CF, Color Filter) substrate, a thin film transistor array (Thin Film Transistor Array, TFT Array) substrate, and liquid crystal (LC) and sealant sandwiched between the color filter substrate and the thin film transistor substrate.
  • Sealant its molding process generally includes: front-end array process (film, yellow light, etching and peeling), middle-end cell process (TFT array substrate and CF substrate bonding) and back-end module assembly Manufacturing process (drive chip and printed circuit board pressing).
  • the front Array process is mainly to form a TFT array substrate to control the movement of liquid crystal molecules
  • the middle Cell process is mainly to add liquid crystal between the TFT array substrate and the CF substrate
  • the latter module assembly process is mainly to drive the chip pressing and bonding.
  • the integration of the printed circuit board drives the rotation of the liquid crystal molecules to display images.
  • FIG. 1 is a schematic structural diagram of a conventional TFT array substrate.
  • the TFT array substrate includes a substrate 100, a gate 200 disposed on the substrate 100, and a gate 200 disposed on the substrate 100 and the gate 200.
  • the gate 200, the gate insulating layer 300, the active layer 400, the source 500 and the drain 600 constitute a TFT device.
  • the TFT device is equivalent to a switch.
  • the voltage applied to the gate 200 is used to control the source 500 and Current between drains 600.
  • the switching characteristics of TFT devices directly affect the performance of liquid crystal display panels. How to improve the switching characteristics of TFT devices, especially the on-state current characteristics of TFT devices, has become a research focus in the panel field.
  • the purpose of the present invention is to provide a TFT array substrate with better switching characteristics and high product quality.
  • Another object of the present invention is to provide a method for manufacturing a TFT array substrate, which can improve the switching characteristics of TFT devices in the TFT array substrate and improve the quality of the product.
  • the present invention first provides a TFT array substrate, including a substrate, a first metal layer provided on the substrate, a gate insulating layer provided on the substrate and the first metal layer, and a gate insulation layer provided on the gate.
  • the first metal layer includes a gate; the active layer is located above the gate; the second metal layer includes a source and a drain spaced apart, and the source and the drain are respectively connected to two ends of the active layer contact;
  • the gate insulating layer includes a first part covering the gate and a second part connected to the first part; the thickness of the first part is smaller than the thickness of the second part.
  • the thickness of the first part is 2800 ⁇ -3200 ⁇ , and the thickness of the second part is 4800 ⁇ -5200 ⁇ ⁇ .
  • the thickness of the first part is 3000 ⁇ , and the thickness of the second part is 5000 ⁇ .
  • the first metal layer further includes a scan line connected to the gate and a capacitor plate spaced apart from the gate and the scan line; part of the drain overlaps the capacitor plate.
  • the TFT array substrate further includes a passivation layer provided on the second metal layer, the active layer, and the gate insulating layer, and a pixel electrode provided on the passivation layer; the passivation layer is provided with a Via hole, the pixel electrode is in contact with the drain electrode through the hole.
  • the present invention also provides a method for manufacturing a TFT array substrate, which includes the following steps:
  • Step S1 Provide a substrate, and form and pattern a first metal material film on the substrate to form a gate;
  • Step S2 An insulating material film is formed on the substrate and the gate and patterned to form a gate insulating layer; the gate insulating layer includes a first part covering the gate and a second part connected to the first part; The thickness of one part is smaller than the thickness of the second part;
  • Step S3 an active layer is formed on the gate insulating layer, the active layer is located above the gate; a second metal material film is formed on the gate insulating layer and the active layer and patterned to form spaced source electrodes And a drain, the source and the drain respectively contact both ends of the active layer.
  • the specific process of patterning the insulating material film to form the gate insulating layer is: forming a layer of photoresist film on the insulating material film, and patterning the photoresist film using a photomask; An opening is formed on the photoresist film, the edge of the opening is located outside the edge of the gate; the insulating material film is dry-etched with the photoresist film as a shield to reduce the thickness of the part of the insulating material film that is not blocked by the photoresist film, The gate insulating layer is formed.
  • the thickness of the first part is 2800 ⁇ -3200 ⁇ , and the thickness of the second part is 4800 ⁇ -5200 ⁇ ⁇ .
  • step S1 when the first metal material film is patterned to form the gate, a scan line connected to the gate and a capacitor plate spaced apart from the gate and the scan line are also formed; in the step S2, the line An insulating material film is formed on the bottom, the gate, the scan line and the capacitor plate; the part of the drain overlaps the capacitor plate.
  • the manufacturing method of the TFT array substrate further includes step S4, forming a passivation layer on the source, drain, active layer, and gate insulating layer, and patterning the passivation layer to form a via hole above the drain ; Making a pixel electrode on the passivation layer, the pixel electrode is in contact with the drain through the hole.
  • the TFT array substrate of the present invention includes a substrate, a first metal layer provided on the substrate, a gate insulating layer provided on the substrate and the first metal layer, and a gate insulating layer provided on the gate insulating layer.
  • the gate insulating layer includes a first part covering the gate and a second part connected to the first part. The thickness of the first part is smaller than the thickness of the second part, which can effectively improve the opening of the TFT device. State current and lower the threshold voltage to improve its switching characteristics, thereby enhancing the quality of the product.
  • the manufacturing method of the TFT array substrate of the present invention can improve the switching characteristics of the TFT devices in the TFT array substrate and improve the quality of products.
  • FIG. 1 is a schematic diagram of the structure of a conventional TFT array substrate
  • FIG. 2 is a schematic top view of the TFT array substrate of the present invention.
  • Figure 3 is a schematic cross-sectional view taken along the line A-A' in Figure 2;
  • Figure 4 is a schematic cross-sectional view taken along the line B-B' in Figure 2;
  • FIG. 5 is a flowchart of the manufacturing method of the TFT array substrate of the present invention.
  • step S1 is a schematic diagram of step S1 of the manufacturing method of the TFT array substrate of the present invention.
  • step S2 of the manufacturing method of the TFT array substrate of the present invention are schematic diagrams of step S2 of the manufacturing method of the TFT array substrate of the present invention.
  • FIG. 10 is a schematic diagram of step S3 of the manufacturing method of the TFT array substrate of the present invention.
  • the present invention provides a TFT array substrate, including a substrate 10, a first metal layer 20 provided on the substrate 10, a gate provided on the substrate 10 and the first metal layer 20
  • the first metal layer 20 includes a gate 21.
  • the active layer 40 is located above the gate 21.
  • the second metal layer 50 includes a source 51 and a drain 52 spaced apart, and the source 51 and the drain 52 are in contact with two ends of the active layer 40 respectively.
  • the gate 21, the gate insulating layer 30, the active layer 40, the source 51 and the drain 51 constitute a TFT device.
  • the gate insulating layer 30 includes a first part 31 covering the gate 21 and a second part 32 connected to the first part 31.
  • the thickness of the first portion 31 is smaller than the thickness of the second portion 32.
  • the thickness of the first portion 31 is 2800 ⁇ -3200 ⁇ , and the thickness of the second portion 32 is 4800 ⁇ -5200 ⁇ .
  • the thickness of the first part 31 is 3000 ⁇ , and the thickness of the second part 32 is 5000 ⁇ .
  • the first metal layer 20 further includes a scan line 22 connected to the gate 21 and a capacitor plate 23 spaced apart from the gate 21 and the scan line 22. The portion of the drain 52 overlaps the capacitor plate 23 to form a storage capacitor.
  • the gate insulating layer 30 can be made in the following manner: an insulating material film 39 is formed on the substrate 10, the gate 21, the scan line 22, and the capacitor plate 23, and A photoresist film 90 is formed on the insulating material film 39, and the photoresist film 90 is patterned using a photomask to form an opening 91 on the photoresist film 90, and the edge of the opening 91 is located at the edge of the gate 21 Outside.
  • the insulating material film 39 is dry-etched with the photoresist film 90 as a shield to reduce the thickness of the portion of the insulating material film 39 not shielded by the photoresist film 90 to form the gate insulating layer 30.
  • the second metal layer 50 further includes a data line (not shown) connected to the source electrode 51.
  • the TFT array substrate further includes a passivation layer 60 disposed on the second metal layer 50, the active layer 40, and the gate insulating layer 30 and disposed on the passivation layer 60 ⁇ pixel electrode 70.
  • the passivation layer 60 is provided with a via 61 located above the drain 52, and the pixel electrode 70 is in contact with the drain 52 through the hole 61.
  • the TFT array substrate can be applied to a liquid crystal display panel, and can also be applied to an OLED display panel.
  • the gate insulating layer in the existing TFT array substrate is a film with uniform thickness.
  • the gate insulating layer 30 includes a first portion 31 covering the gate 21 and a first portion 31 connected to the first portion 31. Two parts 32, and make the thickness of the first part 31 smaller than the thickness of the second part 32, that is, the thickness of the gate insulating layer 30 above the gate 21 is reduced, ensuring that the data line and the scan line 23 in the TFT array substrate While having a smaller capacitance, it can effectively improve the characteristic curve of the TFT device, increase the on-state current of the TFT device, reduce the threshold voltage of the TFT device, and improve the switching characteristics of the TFT device, thereby improving the pixel performance of the TFT array substrate.
  • the charging feature improves the display image quality of the display panel using the TFT array substrate, effectively improving the quality of the product.
  • the present invention also provides a manufacturing method of a TFT array substrate, which includes the following steps:
  • Step S1 referring to FIG. 6, a substrate 10 is provided, and a first metal material film is formed on the substrate 10 and patterned to form a gate 21.
  • a scan line 22 connected to the gate 21 and a capacitor plate spaced apart from the gate 21 and the scan line 22 are also formed. twenty three.
  • Step S2 referring to FIGS. 7 and 9, an insulating material film 39 is formed on the substrate 10 and the gate 21 and patterned to form a gate insulating layer 30.
  • the gate insulating layer 30 includes a first part 31 covering the gate 21 and a second part 32 connected to the first part 31.
  • the thickness of the first portion 31 is smaller than the thickness of the second portion 32.
  • the specific process of patterning the insulating material film 39 to form the gate insulating layer 30 is: referring to FIG. 8, a photoresist film 90 is formed on the insulating material film 39, and a light line is used.
  • the photoresist film 90 is patterned by the mask, and an opening 91 is formed on the photoresist film 90.
  • the edge of the opening 91 is located outside the edge of the gate 21, and the insulating material film 39 is shielded by the photoresist film 90. Dry etching reduces the thickness of the part of the insulating material film 39 that is not blocked by the photoresist film 90 to form the gate insulating layer 30.
  • the first part 31 of the gate insulating layer 30 corresponds to the opening 91 of the photoresist film 90, and the second part 32 corresponds to the area other than the opening 91 in the photoresist film 90.
  • the thickness of the first portion 31 is 2800 ⁇ -3200 ⁇ , and the thickness of the second portion 32 is 4800 ⁇ -5200 ⁇ .
  • the thickness of the first part 31 is 3000 ⁇ , and the thickness of the second part 32 is 5000 ⁇ .
  • an insulating material film 39 is formed on the substrate 10, the gate 21, the scan line 22, and the capacitor plate 23.
  • Step S3 referring to FIG. 10, an active layer 40 is formed on the gate insulating layer 30, and the active layer 40 is located above the gate 21.
  • a second metal material film is formed on the gate insulating layer 30 and the active layer 40 and patterned to form a spaced source 51 and a drain 52.
  • the source 51 and the drain 52 are respectively connected to the active layer 40 Contact at both ends.
  • the gate 21, the gate insulating layer 30, the active layer 40, the source 51 and the drain 51 constitute a TFT device.
  • the portion of the drain 52 overlaps the capacitor plate 23, thereby forming a storage capacitor.
  • the second metal material film is patterned to form the source electrode 51 and the drain electrode 52, and a data line (not shown) connected to the source electrode 51 is also formed.
  • Step S4 With reference to FIGS. 2 to 4, a passivation layer 60 is formed on the source 51, the drain 52, the active layer 40 and the gate insulating layer 30, and the passivation layer 60 is patterned to form a 52 via 61 above.
  • a pixel electrode 70 is formed on the passivation layer 60, and the pixel electrode 70 is in contact with the drain electrode 52 through the hole 61.
  • an insulating material film 39 is formed on the gate 21 and the substrate 10 and patterned to form a first part 31 covering the gate 21 and a second part 32 connected to the first part 31.
  • the gate insulating layer 30 is made so that the thickness of the first portion 31 is smaller than the thickness of the second portion 32, that is, the thickness of the gate insulating layer 30 above the gate 21 is reduced, and the data line in the TFT array substrate is guaranteed With a small capacitance between the scanning line 23 and the scan line 23, it can effectively improve the characteristic curve of the TFT device, increase the on-state current of the TFT device, reduce the threshold voltage of the TFT device, and improve the switching characteristics of the TFT device, thereby improving the TFT
  • the charging characteristics of the pixels in the array substrate can improve the display image quality of the display panel using the TFT array substrate, which effectively improves the quality of the product.
  • the TFT array substrate of the present invention includes a substrate, a first metal layer provided on the substrate, a gate insulating layer provided on the substrate and the first metal layer, and a gate insulating layer provided on the gate insulating layer.
  • the gate insulating layer includes a first part covering the gate and a second part connected to the first part. The thickness of the first part is smaller than the thickness of the second part, which can effectively improve the on-state of the TFT device. Current and lower the threshold voltage to improve its switching characteristics, thereby enhancing the quality of the product.
  • the manufacturing method of the TFT array substrate of the present invention can improve the switching characteristics of the TFT devices in the TFT array substrate and improve the quality of products.

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Abstract

一种TFT阵列基板及其制作方法。TFT阵列基板包括衬底（10）、设于衬底（10）上的第一金属层（20）、设于衬底（10）及第一金属层（20）上的栅极绝缘层（30）、设于栅极绝缘层（30）上的有源层（40）及设于栅极绝缘层（30）上的第二金属层（50），第一金属层（20）包括栅极（21），有源层（40）位于栅极（21）上方，第二金属层（50）包括间隔的源极（51）及漏极（52），源极（51）及漏极（52）分别与有源层（40）的两端接触，栅极绝缘层（30）包括覆盖栅极（21）的第一部分（31）及连接第一部分（31）的第二部分（32），第一部分（31）的厚度小于第二部分（32）的厚度，能够有效提升TFT器件的开态电流并降低阈值电压以提升其开关特性，从而提升产品的品质。

Description

TFT阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
 背景技术
随着显示技术的发展，液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组（back light module）。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜（CF，Color Filter）基板、薄膜晶体管阵列（Thin Film Transistor Array，TFT Array）基板、及夹设于彩膜基板与薄膜晶体管基板之间的液晶（LC）及密封胶框（Sealant）组成，其成型工艺一般包括：前段阵列制程（薄膜、黄光、蚀刻及剥膜）、中段成盒（Cell）制程（TFT阵列基板与CF基板贴合）及后段模组组装制程（驱动芯片与印刷电路板压合）。其中，前段Array制程主要是形成TFT阵列基板，以便于控制液晶分子的运动，中段Cell制程主要是在TFT阵列基板与CF基板之间添加液晶，后段模组组装制程主要是驱动芯片压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
请参阅图1，为现有的一种TFT阵列基板的结构示意图，该TFT阵列基板包括衬底100、设于衬底100上的栅极200、设于衬底100及栅极200上的栅极绝缘层300、设于栅极绝缘层300上且位于栅极200上方的有源层400以及设于栅极绝缘层300上且与有源层400两端连接的源极500及漏极600，栅极200、栅极绝缘层300、有源层400、源极500及漏极600构成TFT器件，该TFT器件相当于一个开关，利用施加于栅极200上的电压来控制源极500与漏极600之间的电流。TFT器件的开关特性直接影响到液晶显示面板的性能，如何提升TFT器件的开关特性，尤其是TFT器件的开态电流特性，已经成为面板领域的研究重点。
 技术问题
本发明的目的在于提供一种TFT阵列基板，开关特性较好，产品品质高。
本发明的另一目的在于提供一种TFT阵列基板的制作方法，能够提升TFT阵列基板中TFT器件的开关特性，提升产品的品质。
 技术解决方案
为实现上述目的，本发明首先提供一种TFT阵列基板，包括衬底、设于衬底上的第一金属层、设于衬底及第一金属层上的栅极绝缘层、设于栅极绝缘层上的有源层及设于栅极绝缘层上的第二金属层；
所述第一金属层包括栅极；所述有源层位于栅极上方；所述第二金属层包括间隔的源极及漏极，所述源极及漏极分别与有源层的两端接触；
所述栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分；所述第一部分的厚度小于第二部分的厚度。
所述第一部分的厚度为2800Å -3200Å ，所述第二部分的厚度为4800 Å -5200 Å 。
所述第一部分的厚度为3000Å ，所述第二部分的厚度为5000 Å 。
所述第一金属层还包括与栅极连接的扫描线以及与栅极及扫描线均间隔的电容极板；所述漏极的部分与电容极板重叠。
所述TFT阵列基板还包括设于第二金属层、有源层及栅极绝缘层上的钝化层及设于钝化层上的像素电极；所述钝化层设有位于漏极上方的过孔，所述像素电极经过孔与漏极接触。
本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底，在衬底上形成第一金属材料膜并进行图案化，形成栅极；
步骤S2、在衬底及栅极上形成绝缘材料膜并进行图案化，形成栅极绝缘层；所述栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分；所述第一部分的厚度小于第二部分的厚度；
步骤S3、在栅极绝缘层上制作有源层，所述有源层位于栅极上方；在栅极绝缘层及有源层上形成第二金属材料膜并进行图案化，形成间隔的源极及漏极，所述源极及漏极分别与有源层的两端接触。
所述步骤S2中，对绝缘材料膜进行图案化形成栅极绝缘层的具体过程为：在绝缘材料膜上形成一层光阻膜，利用一道光罩对所述光阻膜进行图案化处理，在光阻膜上形成开口，所述开口的边缘位于栅极边缘的外侧；以光阻膜为遮挡对绝缘材料膜进行干蚀刻，减薄绝缘材料膜未被光阻膜遮挡的部分的厚度，形成栅极绝缘层。
所述第一部分的厚度为2800Å -3200Å ，所述第二部分的厚度为4800 Å -5200 Å 。
所述步骤S1中在对第一金属材料膜进行图案化形成栅极的同时还形成与栅极连接的扫描线以及与栅极及扫描线均间隔的电容极板；所述步骤S2中在衬底、栅极、扫描线及电容极板上形成绝缘材料膜；所述漏极的部分与电容极板重叠。
所述TFT阵列基板的制作方法还包括步骤S4、在源极、漏极、有源层及栅极绝缘层上形成钝化层，对钝化层进行图案化，形成位于漏极上方的过孔；在钝化层上制作像素电极，所述像素电极经过孔与漏极接触。
 有益效果
本发明的有益效果：本发明的TFT阵列基板包括衬底、设于衬底上的第一金属层、设于衬底及第一金属层上的栅极绝缘层、设于栅极绝缘层上的有源层及设于栅极绝缘层上的第二金属层，第一金属层包括栅极，有源层位于栅极上方，第二金属层包括间隔的源极及漏极，源极及漏极分别与有源层的两端接触，栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分，第一部分的厚度小于第二部分的厚度，能够有效提升TFT器件的开态电流并降低阈值电压以提升其开关特性，从而提升产品的品质。本发明的TFT阵列基板的制作方法能够提升TFT阵列基板中TFT器件的开关特性，提升产品的品质。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT阵列基板的结构示意图；
图2为本发明的TFT阵列基板的俯视示意图；
图3为沿图2中的A-A’线的剖视示意图；
图4为沿图2中的B-B’线的剖视示意图；
图5为本发明的TFT阵列基板的制作方法的流程图；
图6为本发明的TFT阵列基板的制作方法的步骤S1的示意图；
图7至图9为本发明的TFT阵列基板的制作方法的步骤S2的示意图；
图10为本发明的TFT阵列基板的制作方法的步骤S3的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2至图4，本发明提供一种TFT阵列基板，包括衬底10、设于衬底10上的第一金属层20、设于衬底10及第一金属层20上的栅极绝缘层30、设于栅极绝缘层30上的有源层40及设于栅极绝缘层30上的第二金属层50。所述第一金属层20包括栅极21。所述有源层40位于栅极21上方。所述第二金属层50包括间隔的源极51及漏极52，所述源极51及漏极52分别与有源层40的两端接触。栅极21、栅极绝缘层30、有源层40、源极51及漏极51构成TFT器件。
需要重点注意的是，所述栅极绝缘层30包括覆盖栅极21的第一部分31及连接第一部分31的第二部分32。所述第一部分31的厚度小于第二部分32的厚度。
具体地，所述第一部分31的厚度为2800Å -3200Å ，所述第二部分32的厚度为4800 Å -5200 Å 。优选地，所述第一部分31的厚度为3000Å ，所述第二部分32的厚度为5000 Å 。
具体地，所述第一金属层20还包括与栅极21连接的扫描线22以及与栅极21及扫描线22均间隔的电容极板23。所述漏极52的部分与电容极板23重叠，以形成存储电容。
具体地，请结合图7至图9，所述栅极绝缘层30可通过如下方式制得：在衬底10、栅极21、扫描线22及电容极板23上形成绝缘材料膜39，在绝缘材料膜39上形成一层光阻膜90，利用一道光罩对所述光阻膜90进行图案化处理，在光阻膜90上形成开口91，所述开口91的边缘位于栅极21边缘的外侧。以光阻膜90为遮挡对绝缘材料膜39进行干蚀刻，减薄绝缘材料膜39未被光阻膜90遮挡的部分的厚度，形成栅极绝缘层30。
具体地，所述第二金属层50还包括与源极51连接的数据线（未图示）。
具体地，请结合图2及图4，所述TFT阵列基板还包括设于第二金属层50、有源层40及栅极绝缘层30上的钝化层60及设于钝化层60上的像素电极70。所述钝化层60设有位于漏极52上方的过孔61，所述像素电极70经过孔61与漏极52接触。
具体地，所述TFT阵列基板可应用于液晶显示面板，也可应用于OLED显示面板。
需要说明的是，现有的TFT阵列基板中的栅极绝缘层是厚度均匀的膜层，本发明中通过使得栅极绝缘层30包括覆盖栅极21的第一部分31及连接第一部分31的第二部分32，并且使得第一部分31的厚度小于第二部分32的厚度，也即栅极21上方的栅极绝缘层30的厚度被减薄，在保证TFT阵列基板中数据线与扫描线23之间具有较小的电容的同时，能够有效地改善TFT器件的特性曲线，加大TFT器件的开态电流，降低TFT器件的阈值电压，提升TFT器件的开关特性，从而提升TFT阵列基板中像素的充电特性，以提升应用该TFT阵列基板的显示面板的显示画质，有效地提升了产品的品质。
请参阅图5，基于同一发明构思，本发明还提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图6，提供衬底10，在衬底10上形成第一金属材料膜并进行图案化，形成栅极21。
具体地，所述步骤S1中在对第一金属材料膜进行图案化形成栅极21的同时还形成与栅极21连接的扫描线22以及与栅极21及扫描线22均间隔的电容极板23。
步骤S2、请参阅图7及图9，在衬底10及栅极21上形成绝缘材料膜39并进行图案化，形成栅极绝缘层30。所述栅极绝缘层30包括覆盖栅极21的第一部分31及连接第一部分31的第二部分32。所述第一部分31的厚度小于第二部分32的厚度。
具体地，所述步骤S2中，对绝缘材料膜39进行图案化形成栅极绝缘层30的具体过程为：请参阅图8，在绝缘材料膜39上形成一层光阻膜90，利用一道光罩对所述光阻膜90进行图案化处理，在光阻膜90上形成开口91，所述开口91的边缘位于栅极21边缘的外侧，以光阻膜90为遮挡对绝缘材料膜39进行干蚀刻，减薄绝缘材料膜39未被光阻膜90遮挡的部分的厚度，形成栅极绝缘层30，栅极绝缘层30的第一部分31与光阻膜90的开口91对应，第二部分32与光阻膜90中开口91以外的区域对应。
具体地，所述第一部分31的厚度为2800Å -3200Å ，所述第二部分32的厚度为4800 Å -5200 Å 。优选地，所述第一部分31的厚度为3000Å ，所述第二部分32的厚度为5000 Å 。
具体地，所述步骤S2中在衬底10、栅极21、扫描线22及电容极板23上形成绝缘材料膜39。
步骤S3、请参阅图10，在栅极绝缘层30上制作有源层40，所述有源层40位于栅极21上方。在栅极绝缘层30及有源层40上形成第二金属材料膜并进行图案化，形成间隔的源极51及漏极52，所述源极51及漏极52分别与有源层40的两端接触。栅极21、栅极绝缘层30、有源层40、源极51及漏极51构成TFT器件。
具体地，所述漏极52的部分与电容极板23重叠，从而形成存储电容。
具体地，所述步骤S3中对第二金属材料膜进行图案化形成源极51及漏极52的同时还形成与源极51连接的数据线（未图示）。
步骤S4、请结合图2至图4，在源极51、漏极52、有源层40及栅极绝缘层30上形成钝化层60，对钝化层60进行图案化，形成位于漏极52上方的过孔61。在钝化层60上制作像素电极70，所述像素电极70经过孔61与漏极52接触。
需要说明的是，本发明中通过在栅极21及衬底10上形成绝缘材料膜39并对其进行图案化形成包括覆盖栅极21的第一部分31及连接第一部分31的第二部分32的栅极绝缘层30，并且使得第一部分31的厚度小于第二部分32的厚度，也即栅极21上方的栅极绝缘层30的厚度被减薄，在保证制得的TFT阵列基板中数据线与扫描线23之间具有较小的电容的同时，能够有效地改善TFT器件的特性曲线，加大TFT器件的开态电流，降低TFT器件的阈值电压，提升TFT器件的开关特性，从而提升TFT阵列基板中像素的充电特性，以提升应用该TFT阵列基板的显示面板的显示画质，有效地提升了产品的品质。
综上所述，本发明的TFT阵列基板包括衬底、设于衬底上的第一金属层、设于衬底及第一金属层上的栅极绝缘层、设于栅极绝缘层上的有源层及设于栅极绝缘层上的第二金属层，第一金属层包括栅极，有源层位于栅极上方，第二金属层包括间隔的源极及漏极，源极及漏极分别与有源层的两端接触，栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分，第一部分的厚度小于第二部分的厚度，能够有效提升TFT器件的开态电流并降低阈值电压以提升其开关特性，从而提升产品的品质。本发明的TFT阵列基板的制作方法能够提升TFT阵列基板中TFT器件的开关特性，提升产品的品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括衬底、设于衬底上的第一金属层、设于衬底及第一金属层上的栅极绝缘层、设于栅极绝缘层上的有源层及设于栅极绝缘层上的第二金属层；
    所述第一金属层包括栅极；所述有源层位于栅极上方；所述第二金属层包括间隔的源极及漏极，所述源极及漏极分别与有源层的两端接触；
    所述栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分；所述第一部分的厚度小于第二部分的厚度。
  2. 如权利要求1所述的TFT阵列基板，其中，所述第一部分的厚度为2800Å -3200Å ，所述第二部分的厚度为4800 Å -5200 Å 。
  3. 如权利要求2所述的TFT阵列基板，其中，所述第一部分的厚度为3000Å ，所述第二部分的厚度为5000 Å 。
  4. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层还包括与栅极连接的扫描线以及与栅极及扫描线均间隔的电容极板；所述漏极的部分与电容极板重叠。
  5. 如权利要求1所述的TFT阵列基板，还包括设于第二金属层、有源层及栅极绝缘层上的钝化层及设于钝化层上的像素电极；所述钝化层设有位于漏极上方的过孔，所述像素电极经过孔与漏极接触。
  6. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底，在衬底上形成第一金属材料膜并进行图案化，形成栅极；
    步骤S2、在衬底及栅极上形成绝缘材料膜并进行图案化，形成栅极绝缘层；所述栅极绝缘层包括覆盖栅极的第一部分及连接第一部分的第二部分；所述第一部分的厚度小于第二部分的厚度；
    步骤S3、在栅极绝缘层上制作有源层，所述有源层位于栅极上方；在栅极绝缘层及有源层上形成第二金属材料膜并进行图案化，形成间隔的源极及漏极，所述源极及漏极分别与有源层的两端接触。
  7. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述步骤S2中，对绝缘材料膜进行图案化形成栅极绝缘层的具体过程为：在绝缘材料膜上形成一层光阻膜，利用一道光罩对所述光阻膜进行图案化处理，在光阻膜上形成开口，所述开口的边缘位于栅极边缘的外侧；以光阻膜为遮挡对绝缘材料膜进行干蚀刻，减薄绝缘材料膜未被光阻膜遮挡的部分的厚度，形成栅极绝缘层。
  8. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述第一部分的厚度为2800Å -3200Å ，所述第二部分的厚度为4800 Å -5200 Å 。
  9. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述步骤S1中在对第一金属材料膜进行图案化形成栅极的同时还形成与栅极连接的扫描线以及与栅极及扫描线均间隔的电容极板；所述步骤S2中在衬底、栅极、扫描线及电容极板上形成绝缘材料膜；所述漏极的部分与电容极板重叠。
  10. 如权利要求6所述的TFT阵列基板的制作方法，还包括步骤S4、在源极、漏极、有源层及栅极绝缘层上形成钝化层，对钝化层进行图案化，形成位于漏极上方的过孔；在钝化层上制作像素电极，所述像素电极经过孔与漏极接触。
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CN114823719A (zh) * 2022-04-06 2022-07-29 广州华星光电半导体显示技术有限公司 阵列基板及其制备方法

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