WO2020220341A1 - 一种半导体器件及电子设备 - Google Patents

一种半导体器件及电子设备 Download PDF

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Publication number
WO2020220341A1
WO2020220341A1 PCT/CN2019/085364 CN2019085364W WO2020220341A1 WO 2020220341 A1 WO2020220341 A1 WO 2020220341A1 CN 2019085364 W CN2019085364 W CN 2019085364W WO 2020220341 A1 WO2020220341 A1 WO 2020220341A1
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Prior art keywords
shielding
inductor
semiconductor device
metal
layer
Prior art date
Application number
PCT/CN2019/085364
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English (en)
French (fr)
Inventor
姚亚玲
伍得阳
朱千明
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980095880.6A priority Critical patent/CN113785494B/zh
Priority to PCT/CN2019/085364 priority patent/WO2020220341A1/zh
Publication of WO2020220341A1 publication Critical patent/WO2020220341A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

  • This application relates to the field of electronic technology, in particular to a semiconductor device and electronic equipment.
  • VCO Voltage-Controlled Oscillator
  • the radiation interference of VCO (Voltage-Controlled Oscillator) inductor has always been a thorny issue for semiconductor devices.
  • the area of semiconductor devices is getting smaller and smaller, coupled with the continuous improvement of VCO performance indicators, the AC current in the VCO inductor is also increasing, resulting in the frequency pulling of the VCO inductor (which may affect other The inductance, the other inductances are biased), leakage (leakage) and other problems become more and more serious.
  • the existing technology uses symmetrical structures such as figure-eight inductors, butterfly inductors or parallel coupled inductors to reduce radiation, because such inductors can cancel out part of the magnetic field.
  • a metal ring of the same layer is added to the outside of the inductor to enhance isolation.
  • the existing VCO inductor layout processing method has no effect on the inductor's interference with the surrounding radiation, and the radiation improvement in the area near the inductor is small.
  • the isolation ring of the same layer is added, the isolation improvement for high frequency is small due to the parasitic resistance and inductance of the isolation ring itself.
  • This application provides a semiconductor device and electronic equipment to reduce electromagnetic interference caused by the inductance of the oscillator in the semiconductor device to other components in the semiconductor device.
  • a semiconductor device in a first aspect, includes a bare core, and an oscillator and a shielding cover provided in the bare core; in specific settings, the oscillator includes a resonant cavity, and the resonant The cavity contains inductance.
  • the inductor may have electromagnetic leakage and affect other components in the bare core. Therefore, a shielding cover is also provided in the provided bare core, and the shielding cover is used to cover the inductance in the above-mentioned resonant cavity. It is also used to shield the inductor to avoid its electromagnetic leakage.
  • the electromagnetic radiation of the inductor is shielded only by the metal layer provided on the same layer.
  • the semiconductor device provided in the present application covers the inductor through a shielding cover and protects the inductor. The electromagnetic radiation is shielded, thereby reducing the electromagnetic interference of the inductor on other components except the oscillator.
  • the resonant cavity of the oscillator not only includes the above-mentioned inductor, but also includes a variable capacitor and a switched capacitor array connected in parallel with the inductor.
  • the shielding cover is also used to cover at least one of the variable capacitor and the switched capacitor array in the oscillation cavity.
  • the shielding cover is used to cover these structures, the electromagnetic radiation of the resonant cavity can also be shielded, the electromagnetic interference effect of the resonant cavity on other components is reduced, and the electromagnetic isolation is strengthened.
  • the oscillator When the oscillator is specifically set up, the oscillator further includes a cross-coupling tube coupled with the resonant cavity; the shielding cover is also used to cover the cross-coupling tube.
  • the semiconductor device when the semiconductor device is specifically arranged, in addition to the above-mentioned bare core structure, it also includes a packaging structure covering the bare core, and the packaging structure is used for packaging the bare core.
  • the provided bare core has a multi-layer structure.
  • it when it is specifically installed, it includes a substrate and a plurality of metal layers stacked on the substrate; and among the plurality of metal layers, at least two first metal layers are respectively A shield ring is provided.
  • a shielding layer is provided on the packaging structure; and the provided shielding layer is electrically connected with at least two shielding rings provided on at least two first metal layers to form the aforementioned shielding cover.
  • the shielding layer and the shielding ring are provided to form a shielding cover covering the inductance.
  • the inductor is provided on at least one second metal layer of the plurality of metal layers; at least one of the at least two first metal layers and the at least one The second metal layer is a different metal layer, and at least one of the at least two first metal layers is located on the at least one second metal layer.
  • the shielding effect of the electromagnetic radiation of the inductor can be improved, thereby reducing the electromagnetic interference of the inductor on other components except the oscillator.
  • the shielding ring provided on each first metal layer is a metal ring.
  • each shielding ring When each shielding ring is specifically set up, the shape and size of each shielding ring may be the same or different. For example, along the thickness direction of the bare core, the size of the shield ring gradually becomes larger, or gradually smaller, or one large and one small are alternately arranged. Of course, it can also be equal. In this case, the vertical projection of each shield ring on the second metal layer surrounds the inductor. This facilitates the electrical connection between the shielding rings and can achieve the effect of covering the inductance.
  • each shielding ring When the shape of each shielding ring is specifically set, the structure of each shielding ring is a symmetric structure, the structure of the inductor is a symmetric structure, and the symmetry axis of the symmetric structure is coaxial with the axis of the inductor.
  • the shielding effect of the electromagnetic radiation of the inductor can be effectively improved.
  • adjacent shielding rings of the at least two shielding rings are electrically connected through vias.
  • vias in order to reduce electromagnetic leakage, the spacing between the vias is relatively dense, for example, the gap between two vias is less than one-tenth of the shielded wavelength.
  • the shielding layer and the uppermost shielding ring of the at least two shielding rings are electrically connected through a plurality of metal posts.
  • the structure of the inductor is a symmetric structure
  • the plurality of metal pillars are arranged symmetrically along the symmetry axis of the inductor.
  • the plurality of metal pillars includes a plurality of first metal pillars and a plurality of second metal pillars, and the first metal pillars and the second metal pillars The diameter of the column is different.
  • the metal pillar can adopt the original structure on the semiconductor device, such as a ball holder, which is used for growing solder balls and used for packaging connection.
  • the shielding layer is connected to the uppermost shielding ring of the at least two shielding rings They are electrically connected by a plurality of metal pillars; the gap between any adjacent metal pillars and the gap between any adjacent via holes are determined according to the frequency of radiation of the inductor and the target attenuation value. Thereby improving the shielding effect of the electromagnetic radiation of the inductor.
  • the adjacent shielding rings of the at least two shielding rings are electrically connected through vias; or, the shielding layer and the shielding ring located on the uppermost layer of the at least two shielding rings pass through multiple channels.
  • the metal pillars are electrically connected; the gap between any adjacent metal pillars and the gap between any adjacent via holes are determined according to the frequency of radiation of the inductor and the target attenuation value.
  • the gap between any adjacent metal pillars and the gap between any adjacent via holes are the first width value, and the first width
  • the value is one-twentieth of the wavelength corresponding to the frequency of the radiation of the inductor; and when the target attenuation value is greater than the first set attenuation value, and the difference between the target attenuation value and the first set attenuation value is the same as the second preset attenuation value
  • the value ratio is N; N is a positive integer; the gap between any adjacent metal pillars and the gap between any adjacent via holes are all of the first width value
  • the gap between any adjacent metal pillars and the gap between any adjacent via holes is less than one tenth of the wavelength corresponding to the frequency of the radiation of the inductor.
  • the ground layer further includes a ground layer disposed in the bare core, and the ground layer is located between the substrate and the at least one second metal layer.
  • the ground layer blocks the electromagnetic radiation of the inductor in the direction of the substrate, and improves the shielding effect of the electromagnetic radiation of the inductor.
  • the inductor includes a first inductor and a second inductor connected in series, and the first inductor and the second inductor have a symmetrical structure.
  • the inductor is disposed on at least one second metal layer among the multiple metal layers in the bare core.
  • the first inductor and the second inductor are disposed on the same second metal layer, or the first inductor and the second Two inductors are arranged on different second metal layers.
  • a semiconductor device which includes a bare core and an oscillator provided in the bare core.
  • the oscillator includes a resonant cavity, and the resonant cavity contains an inductor.
  • the inductor may have electromagnetic radiation which may affect other components provided in the bare core. Therefore, the semiconductor device also includes a shielding structure that includes at least the same layer as the inductor and surrounding the inductor. The first shielding ring and at least one second shielding ring arranged on a different layer from the inductor; and the first shielding ring is electrically connected to the at least one second shielding ring. The electromagnetic radiation of the inductor is shielded by the shielding structure.
  • the shielding structure provided by the present application shields the electromagnetic radiation of the inductor through a multilayer shielding ring , Thereby reducing the electromagnetic interference of the inductance to other components in the semiconductor device except the oscillator.
  • the bare core includes: a substrate and a plurality of metal layers stacked on the substrate; wherein the inductor and the first shielding ring are provided on at least one of the plurality of metal layers.
  • the second shield ring is arranged on at least one first metal layer of the plurality of metal layers.
  • each shielding ring may be the same or different.
  • the size of the shielding ring gradually becomes larger, or gradually smaller, or one large and one small are alternately arranged.
  • the size of the shielding ring can also be equal.
  • the vertical projection of each second shielding ring on the at least one second metal layer surrounds the inductor.
  • each shielding ring When the shape of each shielding ring is specifically set, the structures of the first shielding ring and each second shielding ring are both symmetrical, and the structure of the inductor is symmetrical; and the first shielding ring and each The respective symmetry axis of the second shielding ring is coaxial with the symmetry axis of the inductor.
  • the shielding effect of the electromagnetic radiation of the inductor can be effectively improved.
  • the adjacent shielding rings of the at least two shielding rings are electrically connected through vias.
  • the spacing between the via holes is relatively dense, for example, the gap between two via holes is less than one-tenth of the shielded wavelength.
  • the above-mentioned shielding structure may also include other structures.
  • the semiconductor device further includes: a package structure covering the bare core, and the shielding structure further It includes a shielding layer provided on the packaging structure, and the shielding ring at the uppermost layer of the first shielding ring and the at least one second shielding ring is electrically connected to the shielding layer through a plurality of metal pillars.
  • the shielding layer is electrically connected with the shielding ring to form a cover, and the cover is used to cover the inductor to improve the electromagnetic radiation of the inductor.
  • the structure of the inductor is a symmetric structure
  • the plurality of metal pillars may be arranged symmetrically along the symmetry axis of the inductor.
  • the plurality of metal pillars includes a plurality of first metal pillars and a plurality of second metal pillars, and the first metal pillars and the second metal pillars The diameter of the column is different.
  • the shielding effect is increased by using different metal posts.
  • the metal pillar can adopt the original structure on the semiconductor device, such as a ball holder, which is used for growing solder balls and used for packaging connection.
  • the shielding layer is connected to the uppermost shielding ring of the at least two shielding rings They are electrically connected by a plurality of metal pillars; the gap between any adjacent metal pillars and the gap between any adjacent via holes are determined according to the frequency of radiation of the inductor and the target attenuation value. Thereby improving the shielding effect of the electromagnetic radiation of the inductor.
  • the adjacent shielding rings of the at least two shielding rings are electrically connected through vias; or, the shielding layer and the shielding ring located on the uppermost layer of the at least two shielding rings pass through multiple channels.
  • the metal pillars are electrically connected; the gap between any adjacent metal pillars and the gap between any adjacent via holes are determined according to the frequency of radiation of the inductor and the target attenuation value.
  • the gap between any adjacent metal pillars and the gap between any adjacent via holes are the first width value, and the first width
  • the value is one-twentieth of the wavelength corresponding to the frequency of the radiation of the inductor; and when the target attenuation value is greater than the first set attenuation value, and the difference between the target attenuation value and the first set attenuation value is the same as the second preset attenuation value
  • the value ratio is N; N is a positive integer; the gap between any adjacent metal pillars and the gap between any adjacent via holes are all of the first width value
  • the gap between any adjacent metal pillars and the gap between any adjacent via holes is less than one tenth of the wavelength corresponding to the frequency of the radiation of the inductor. Thereby improving the shielding effect of the electromagnetic radiation of the inductor.
  • the semiconductor device further includes a ground layer disposed in the die, and the ground layer is located between the substrate and the at least one second metal layer.
  • the ground layer blocks the electromagnetic radiation of the inductor in the direction of the substrate, and improves the shielding effect of the electromagnetic radiation of the inductor.
  • an electronic device in a third aspect, includes a substrate and the semiconductor device described in any one of the above, and the semiconductor device is disposed on the substrate.
  • the electromagnetic radiation of the inductor is shielded by the shielding cover.
  • the electromagnetic radiation of the inductor is shielded only by the metal layer provided in the same layer.
  • the semiconductor device provided by the present application covers the inductor and the The electromagnetic radiation of the inductor is shielded to improve the shielding effect.
  • Fig. 1 is a schematic structural diagram of an oscillator provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of the internal structure of a semiconductor device provided by an embodiment of the application.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the application.
  • FIG. 4 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the application.
  • FIG. 5 is a bottom view of a semiconductor device provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a simulation of a semiconductor device provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a simulation of a semiconductor device provided by an embodiment of the application.
  • the semiconductor device can be a semiconductor device with different functions, and can be applied to different electronic devices when in use.
  • an embodiment of the present application provides a semiconductor device. The figure illustrates the semiconductor device in detail.
  • FIG. 1 shows a circuit diagram of the oscillator.
  • the oscillator 100 includes a resonant cavity 102, which is cross-coupled to the resonant cavity 102. Tubes 101a, 101b; among them, the cross-coupled tubes 101a, 101b are used to provide negative resistance compensation for the resonant cavity 102, and the resonant cavity 102 is used to generate an oscillating signal.
  • the oscillator 100 may be a voltage-controlled oscillator VCO, or other types of oscillators 100.
  • the resonant cavity 102 of the oscillator contains inductance. In the resonant cavity 102 shown in FIG.
  • the inductor includes a first inductor and a second inductor connected in series, wherein the first inductor is the resonant inductor L1, the second inductor is the resonant inductor L2, and the first inductor and the second inductor are Symmetrical structure.
  • the resonant cavity 102 may also include a variable capacitor and a switched capacitor array connected in parallel with the inductor; as shown in FIG. 1, the number of variable capacitors is two, in the figure 1 is the voltage control variable capacitor VAR1 and the voltage control variable capacitor VAR2.
  • the switch capacitor array provided includes a capacitor C1, a capacitor C2, and a switch SW connected in series.
  • the above-mentioned capacitors, variable capacitors, and switched capacitor arrays constitute a basic inductance-capacitor parallel resonant network, whose frequency is determined by the inductance value and the capacitance value; and the change of frequency (coarse frequency adjustment) can be controlled through the control voltage switch of SW. Controlling the voltage on the variable capacitor can control the continuous change of the frequency (fine frequency adjustment); due to the parasitic resistance of the actual inductance and capacitive devices, there will be energy consumption during the oscillation process.
  • the complementary cross-connection method of the cross-coupling tube 101 can generate negative impedance and continuously inject energy into the resonant network to maintain its stable oscillation.
  • the number of cross-coupled tubes 101 is two, one of the cross-coupled tubes 101 includes a negative resistance tube M1 and a negative resistance tube M2, and the other cross-coupled tube 101 includes a negative resistance tube M3 and a negative resistance tube. Tube M4.
  • the capacitor in the above-mentioned oscillator 100 periodically stores and releases energy in the form of an electric field, and the inductor periodically stores and releases energy in the form of a magnetic field. Among them, the periodic change of the inductive magnetic field interferes with other components in the semiconductor device and produces The source of radiation.
  • FIG. 1 is only a specific example of the oscillator 100.
  • the oscillator 100 does not include the cross-coupling tube 101 and adopts other structures, or the oscillator 100 provided in the embodiment of the present application may also Other structures of existing known oscillators are adopted.
  • the inductance in the resonant cavity 102 will cause interference to other components of the semiconductor device.
  • a shielding cover is provided in the semiconductor device provided in the embodiment of the present application, and the shielding cover covers the inductor to achieve the effect of shielding the electromagnetic radiation of the inductor. The following describes in detail how the shielding case shields the inductance with reference to the drawings.
  • Figures 2 and 3 show the structure of a semiconductor device.
  • the semiconductor device includes a die, a shield and an oscillator provided on the die (only the inductance of the oscillator is shown in Figure 2).
  • the bare core includes a substrate and a plurality of metal layers 10 stacked on the substrate, and a dielectric layer is spaced between the plurality of metal layers 10, that is, the dielectric layer and the metal layer 10 are alternately stacked to form a bare core. core.
  • the positions of the inductor 20 of the oscillator are shown in FIGS. 3 and 5.
  • the inductor 20 is disposed on a second metal layer 12 in the bare core.
  • the first inductor and the second inductor may be disposed on different second metals.
  • the number of corresponding second metal layers 12 is two.
  • the structure of the shielding cover is the same. Therefore, the inductor 20 is provided on the same metal layer 10 as an example for description.
  • the second metal layer 12 where the inductor 20 is provided can be provided at different positions in the die.
  • the second metal layer 12 is located in the middle of the plurality of metal layers 10.
  • a placement area for placing the inductor 20 is formed by etching on the second metal layer 12 in the bare core, and the inductor 20 is provided in the placement area, and the placed inductor 20 and the second The other parts of the metal on the metal layer 12 are electrically isolated.
  • Different structural shapes can be adopted for the prepared inductor 20.
  • the inductor 20 adopts a symmetrical structure. Different symmetrical structures can be used in specific settings. As shown in FIG.
  • the inductor 20 has a figure-eight-shaped structure, and one end of the figure-eight-shaped inductor is open and connected to the input end and the output end.
  • the inductor 20 may also adopt other symmetrical structures, for example, the inductor 20 is a parallel coupled inductor or a butterfly inductor.
  • the electromagnetic radiation of the inductor in the resonant cavity is relatively large, so although the inductor 20 adopts a symmetrical structure to reduce radiation, it still inevitably generates radiation, which affects other inductors ( Other components 200) generate frequency pulling (caused by the mutual influence between the two inductors), and also cause energy leakage of the inductor 20.
  • a shielding cover is provided in the bare core provided in the embodiment of the present application.
  • the shielding cover covers the above-mentioned inductor 20 and can shield the radiation of the inductor 20, thereby reducing the influence of the inductor 20 on other inductors. At the same time, energy leakage can be reduced.
  • the shielding cover is also carried by the bare core during specific installation, and the metal layer 10 on the bare core is used to form a cavity that covers the inductor 20.
  • the shielding case When the shielding case is specifically set, the shielding case includes shielding rings 40 respectively provided on at least two first metal layers 11 of the plurality of metal layers 10, and each shielding ring 40 is provided on the first metal layer 11.
  • the metal ring, the metal ring can be a circular ring, a square ring or a ring structure of other shapes.
  • the provided at least two layers of shielding rings 40 are stacked along the thickness direction of the bare core and surround the inductor 20. It can be seen from the above description that the inductor 20 is located in the space enclosed by the shielding ring 40 when the inductor 20 is set, but there can be different ways to specifically set it, which will be listed below.
  • the inductor 20 is flush with the shield ring 40 at the bottom, or the inductor 20 is flush with the shield ring 40 at the top, of course, the shield ring 40 with the inductor 20 in the middle can also be flush.
  • the inductor 20 is located in the middle of the space enclosed by at least two layers of shielding rings 40. At this time, above and below the inductor 20 (the direction in which the metal layers 10 are stacked is used as the reference direction) There is a shielding ring 40.
  • the vertical distance between the uppermost shielding ring 40 and the inductor 20 is h1, and the lowermost shielding ring 40 is away from the inductor 20.
  • the vertical distance of the inductor 20 is h2. Therefore, when the inductor 20 radiates, the electromagnetic radiation of the inductor 20 can be shielded by the shielding ring 40 in the horizontal, diagonally upward, and diagonally downward directions. Compared with the prior art, the electromagnetic radiation of the inductor 20 can be shielded.
  • the isolation improvement for high frequency is small.
  • the at least two-layer shielding ring 40 provided in the embodiment of the present application has a certain shielding effect on the electromagnetic radiation of the inductor 20 in the horizontal and oblique directions of the inductor 20, and the at least two-layer shielding ring 40 provided by the embodiment of the present application It has a certain width and height, so it can effectively reduce the grounding resistance and further improve the shielding effect.
  • the shielding ring 40 can be prepared by using the first metal layer 11 in the bare core.
  • a shield ring 40 may be provided on part of the metal layer 10 or all the metal layer 10 in the bare core.
  • the bare core shown in FIG. 3 has six metal layers, and the six metal layers are provided with a shielding ring 40. Therefore, the six metal layers illustrated in FIG. 3 are all the first metal layers. 11.
  • one metal layer is provided with the inductor 20. At this time, the metal layer where the inductor 20 is located belongs to the first metal layer 11 and the second metal layer 12 at the same time.
  • At least one of the at least two first metal layers 11 and at least one of the second metal layers 12 are different metal layers, and at least one of the at least two first metal layers 11 has a first metal layer 11a. It is located on at least one second metal layer 12 (take the placement direction of the bare core shown in FIG. 2 as the reference direction).
  • the number of shield rings 40 formed is at least two.
  • the part of the metal layer 10 includes a second metal layer 12 provided with an inductor 20 and several metal layers adjacent to the second metal layer 12.
  • the shield ring 40 When each shield ring 40 is specifically arranged, the shield ring 40 is a closed ring structure. During specific preparation, a metal ring is etched on the first metal layer 11, and the metal ring is the shield ring 40.
  • the shape and structure of the shielding ring 40 of different layers may be the same or different.
  • the size of the shielding ring 40 gradually becomes larger along the thickness direction of the bare core. Or gradually become smaller, or alternately arrange one big and one small.
  • the sizes of the shielding rings 40 can also be the same. As shown in FIG. 3, the sizes of the shielding layers shown in FIG.
  • each shielding ring 40 is in the second metal layer.
  • the vertical projection of 12 surrounds the inductor 20.
  • the several different setting methods of the shielding ring 40 listed above can all be applied in the embodiments of the present application. And when the shielding ring 40 is specifically set, no matter which setting method is adopted, the structure of each shielding ring 40 is a symmetrical structure, and the symmetry axis of the symmetrical structure is coaxial with the axis of the inductor 20, so as to improve The shielding effect of the electromagnetic radiation of the inductor 20.
  • the shielding rings 40 prepared on the plurality of metal layers 10 are laminated, and any adjacent shielding rings 40 are electrically connected, so that the laminated shielding rings 40 are superimposed to form a ring shape with a certain thickness. structure.
  • any adjacent shielding rings 40 are electrically connected through a via 30.
  • a plurality of vias 30 are electrically connected between any two adjacent shielding rings 40.
  • the vias 30 are used to connect the shielding ring 40, in order to reduce electromagnetic leakage, the vias 30 are arranged in a denser arrangement between the vias 30 in the same layer, and the vias 30 should be ensured between two adjacent vias 30.
  • the gap is smaller than the screen.
  • the gap between any adjacent vias 30 is determined according to the radiation frequency of the inductor 20 and the target attenuation value. For example, in specific settings, when the target attenuation value is less than the first set attenuation value, the first preset attenuation value corresponds to the first attenuation rate, and the gap between any adjacent vias 30 is the first width value , The first width value is one twentieth of the wavelength corresponding to the frequency of the radiation of the inductor 20; and when the target attenuation value is greater than the first set attenuation value, and the difference between the target attenuation value and the first set attenuation value is The ratio of the second preset attenuation value (corresponding to the second attenuation rate) is N; N is a positive integer; the gap between any adjacent vias 30 is the value of the first width
  • the electromagnetic wave radiated by the inductor starts to be 20dB/10 times (1/10 cutoff frequency) or 6dB/8 times (1/2 cutoff frequency) ), where the rate of 20dB/10 times the frequency is the above-mentioned first attenuation rate, and the rate of 6dB/8 times the frequency is the above-mentioned second attenuation rate.
  • the higher the emission frequency of the inductor the more serious the attenuation, because its wavelength is shorter.
  • the maximum allowable gap and the trench (including the gap between the vias 30) of the shield can be calculated. For example, if the radiation of 1GHz (wavelength is 300mm) needs to be attenuated by 26dB, a gap of 150mm will begin to attenuate, so when there is a gap of less than 150mm, the 1GHz radiation will be attenuated.
  • the gap between the vias 30 is specifically set, the gap between any adjacent vias 30 is less than one-tenth of the wavelength corresponding to the frequency of the radiation of the inductor 20, so as to avoid excessive Electromagnetic leakage occurs between the holes 30.
  • the diameter of the via hole 30 is not limited in the embodiment of the present application, but the via hole 30 provided should be able to maintain the electrical connection effect between the two shielding rings 40.
  • other methods can also be used, such as a long strip hole (long waist hole), which is used to connect two adjacent shielding rings. 40.
  • each side of the shielding ring 40 is connected to a long waist hole. Since the inner wall of the long waist hole can be laid with a continuous metal layer, the long waist hole is used. At the same time, the gap between the two shielding rings 40 can be reduced, and the connection area of the two shielding rings 40 can be increased, which improves the electrical connection effect of the two adjacent shielding rings 40, thereby increasing the electromagnetic radiation to the inductor 20. The shielding effect.
  • the shielding cover in addition to the shielding ring 40 in the bare core, other structures are also included.
  • semiconductor devices need to be packaged with bare cores during preparation. Therefore, a package structure 80 covering the bare core is also provided on the bare core of the semiconductor device.
  • the shielding case at this time also includes a shielding layer 50 provided on the packaging structure 80, and the shielding layer 50 is located on the side of the packaging structure 80 away from the bare core.
  • the shielding layer 50 is electrically connected to the at least two shielding rings 40 provided on the at least two first metal layers 11, and more specifically, the shielding layer 50 and the at least two shielding rings 40 are located in the uppermost layer.
  • the shield ring 40 is electrically connected to each other, wherein the uppermost shield ring 40 is the shield ring closest to the packaging structure 80.
  • a metal layer such as a copper metal layer or an iron metal layer, can be formed on the surface of the package structure 80 by spraying or coating.
  • a plurality of metal pillars 70 are provided in the packaging structure 80, and the plurality of metal pillars 70 are connected to the shielding ring 40 and the shielding layer 50, respectively. Electrically connected and arranged in a ring shape.
  • the gap between any adjacent metal pillars 70 is determined according to the frequency of radiation of the inductor 20 and the target attenuation value. Therefore, the shielding effect of the electromagnetic radiation of the inductor 20 is improved. In the specific setting, the gap between any adjacent metal pillars 70 is determined according to the radiation frequency of the inductor 20 and the target attenuation value.
  • the first preset attenuation value corresponds to the first attenuation rate
  • the gap between any adjacent metal pillars 70 is the first width value
  • the first width value is one-twentieth of the wavelength corresponding to the frequency of the radiation of the inductor 20; and when the target attenuation value is greater than the first set attenuation value, and the difference between the target attenuation value and the first set attenuation value is equal to the first
  • the ratio of the second preset attenuation value (corresponding to the second attenuation rate) is N; N is a positive integer; the gap between any adjacent metal pillars and the gap between any adjacent via holes 30 are both the first width value of
  • N is a positive integer
  • the gap between any adjacent metal pillars and the gap between any adjacent via holes 30 are both the first width value of
  • the distance between adjacent metal pillars 70 is less than one-tenth of the shielded wavelength (wavelength of electromagnetic radiation of the inductor), thereby reducing leakage.
  • the plurality of metal pillars 70 are arranged in a symmetrical manner. As shown in FIG. 5, the structure of the inductor 20 is a symmetrical structure, and the plurality of metal pillars 70 They are arranged symmetrically along the symmetry axis of the inductor 20 to improve the shielding effect of the electromagnetic radiation of the inductor 20.
  • the plurality of metal pillars 70 includes a plurality of first metal pillars 71 and a plurality of second metal pillars 72, and the first metal pillars 71 and the second metal pillars The diameters of the two metal pillars 72 are different. As shown in FIGS. 4 and 5, FIGS.
  • first metal pillar 71 and the second metal pillar 72 show the structure of the first metal pillar 71 and the second metal pillar 72, wherein the diameter of the first metal pillar 71 is larger than the diameter of the second metal pillar 72, and
  • the first metal pillar 71 and the second metal pillar 72 respectively adopt a symmetrical structure, that is, the first metal pillar 71 is symmetrical, and the second metal pillar 72 is also symmetrical.
  • the existing structure on the semiconductor device can be used for arrangement.
  • the first metal pillar 71 uses a metal pad used for packaging connection in the original semiconductor device
  • the second metal pillar 72 uses a ball holder (used for growing solder balls and used for packaging connection). Therefore, the shielding structure can be formed using the structure on the original semiconductor device.
  • a metal layer can be directly encapsulated in the packaging structure 80 as a connection structure between the shielding ring 40 and the shielding layer 50.
  • the shielding cover when the shielding cover includes the metal pillar 70 in the packaging structure 80, the shielding cover includes a shielding ring 40 located in the bare core and a shielding layer 50 located on the packaging structure 80. At this time, the shielding cover is partially located at Inside the die, part of it is located in the package structure 80.
  • the shielding cover shown in FIG. 3 only covers the inductor, but it should be understood that when the resonant cavity provided in the embodiment of the present application includes a variable capacitor connected in parallel with the inductor 20 and a switched capacitor array, the shielding cover may also be provided. At least one of the variable capacitor and the switched capacitor array is covered.
  • a shielding cover can also cover the cross-coupling tube. It can be seen from the above description that when the shielding cover is set, only the inductor 20 can be covered or other components in the oscillator can be covered.
  • the bare core is also provided with a ground layer 60, and the ground layer 60 is located between the substrate and the at least one second metal layer 12, and the ground layer 60 and the shielding layer 50 are arranged separately Both sides of the inductor 20, so that the ground layer 60 can shield the leakage of the inductor 20 along the substrate direction.
  • the ground layer 60 and the shielding cover together form a shielding cavity to shield the electromagnetic radiation of the inductor 20 in the horizontal and vertical directions, thereby avoiding other components in the semiconductor device and other components other than the semiconductor device. Other components cause electromagnetic interference.
  • the ground layer 60 is provided on the third metal layer 13 of the plurality of metal layers 10, and the third metal layer 13 is located on the side of the second metal layer 12 away from the shielding layer 50.
  • the ground layer 60 may be disposed on the third metal layer 13 adjacent to the second metal layer 12, or may be disposed on the second metal layer. 12 separated metal layers.
  • the ground layer 60 is formed by etching the third metal layer 13.
  • the ground layer 60 may be directly electrically connected to the shield ring 40 provided, or there may be a certain gap.
  • a shield ring 40 may also be provided on the metal layer where the ground layer 60 is provided.
  • the metal layer belongs to both the first metal layer 11 and the third metal layer 13.
  • FIG. 6 it can be seen from FIG. 6 that at the first harmonic, the energy of the inductor 20 in the semiconductor device provided by the embodiment of the present application is significantly reduced. From -52db at M3: 10.9GHz, optimized to -79db at M5: 10.1GHz. As shown in FIG. 7, FIG. 7 shows the improvement effect of the leakage amount. Compared with the semiconductor device in the prior art, the electromagnetic radiation leakage amount of the inductor 20 in the semiconductor device provided by the embodiment of the present application is reduced from 49.17 dBm to 43.49 dBm.
  • the semiconductor device uses the metal layer in the bare core 10 times, and combines the packaging substrate, the metal ball structure of the packaging (for packaging connection) and other levels to place the inductor 20 on In a three-dimensional shielded cavity, a completely symmetrical design layout of the window structure of each layer of metal around the inductor 20 and the top metal of the bare die, and the metal ball structure of the package, etc., can significantly reduce the inductor 20's peripheral wiring and other components
  • the radiation interference problem of 200 can also significantly reduce the stray problem caused by direct radiation of the inductor, effectively suppress the frequency pulling, and can significantly reduce the interference problem of the first harmonic of the inductor 20.
  • the shielding structure includes at least a first shielding ring arranged on the same layer as the inductor 20 and surrounding the inductor 20, and at least one second shielding ring arranged on a different layer from the inductor 20; wherein, the first shielding ring is at least A second shielding ring is electrically connected.
  • the inductor 20 and the first shielding ring are provided on at least one second metal layer 12 of the plurality of metal layers; and at least one of the plurality of metal layers is provided with The second shield ring.
  • the shielding ring and the inductor 20 are carried on different metal layers, and the shielding structure is formed by electrically connecting the shielding rings 40 of different layers to shield the electromagnetic radiation of the inductor 20.
  • the shielding structure is formed by electrically connecting the shielding rings 40 of different layers to shield the electromagnetic radiation of the inductor 20.
  • the shield ring on the same layer as the inductor 40 is the aforementioned first shield ring
  • the shield ring on a different layer from the inductor 40 is the aforementioned second shield ring.
  • the shielding structure at this time can be regarded as a partial shielding cover structure.
  • the shielding structure can also adopt the same structure as the shielding cover.
  • the shielding structure includes a shielding ring 40 and a shielding layer.
  • part of the structure of the shield can be used to shield the electromagnetic radiation of the inductor 20, or the entire shield can be used to shield the electromagnetic radiation of the inductor 20.
  • An embodiment of the present application also provides an electronic device, which includes a substrate, and the semiconductor device described in any one of the foregoing disposed on the substrate.
  • the inductor 20 is placed in a three-dimensional shielding cavity by using the metal layer 10 in the bare core and the shielding layer on the package structure.
  • the completely symmetrical design layout of the pillars can significantly reduce the radiation interference problem of the inductor 20 on the surrounding wiring and other components 200, and can also significantly reduce the stray problem caused by the direct radiation of the inductor, effectively suppress the frequency pulling, and can obviously Reduce the interference problem of the inductance 20 first harmonic.

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Abstract

本申请提供了一种半导体器件及电子设备，该半导体器件包括一个裸芯，以及设置在所述裸芯中的振荡器和屏蔽罩；其中，所述振荡器包括谐振腔，所述谐振腔包括电感；所述屏蔽罩用于罩住所述电感。本申请提供的半导体器件通过屏蔽罩罩住电感，从而在振荡器工作时，可以对该电感的电磁辐射进行屏蔽。

Description

一种半导体器件及电子设备 技术领域
本申请涉及到电子技术领域，尤其涉及到一种半导体器件及电子设备。
背景技术
VCO(Voltage-Controlled Oscillator，电压控制振荡器)电感的辐射干扰一直是半导体器件的棘手问题。随着工艺的演进，半导体器件面积越来越小，再加上VCO性能指标的不断的提高，使得VCO电感内的交流电流也越来越大，导致VCO电感的频率牵引(可能会影响到其他的电感，把其他电感带偏)、leakage(泄漏)等问题越趋严重。
为了减少VCO电感的辐射，现有的技术会采用8字形电感、蝴蝶型电感或者并联耦合电感等对称结构来降低辐射，因为这样的电感可以相互抵消部分磁场。此外，在采用上述VCO电感类型的同时，会在电感外面加同层金属环用来加强隔离，现有的VCO电感版图处理方式，对于电感干扰周边辐射无效果，而且电感附近区域的辐射改善小。虽然加了同层的隔离环，但是由于隔离环本身的寄生电阻和电感的存在，对高频的隔离改善较小。
发明内容
本申请提供了一种半导体器件及电子设备，用以降低半导体器件中的振荡器的电感对半导体器件中的其他元件造成的电磁干扰。
第一方面，提供了一种半导体器件，该半导体器件包括一个裸芯，以及设置在该裸芯中的振荡器和屏蔽罩；在具体设置时，该振荡器包括谐振腔，在设置的该谐振腔中包含电感。在使用时，该电感可能出现电磁泄漏从而影响到裸芯中设置的其他元件，因此在设置的裸芯中还设置了一个屏蔽罩，该屏蔽罩用于罩住上述的谐振腔中的电感，并用于屏蔽该电感，避免其电磁泄漏，相比与现有技术中只通过同层设置的金属层对电感的电磁辐射进行屏蔽，本申请提供的半导体器件通过屏蔽罩罩住电感并对电感的电磁辐射进行屏蔽，从而降低了电感对于除振荡器之外的其他元件的电磁干扰。
在设置振荡器时，该振荡器的谐振腔除了包含上述的电感外，还包括分别与电感并联的可变电容以及开关电容阵列。在设置屏蔽罩时，该屏蔽罩还用于罩住振荡腔中的可变电容以及开关电容阵列中的至少一个。在采用屏蔽罩罩住这些结构时，同样可以达到屏蔽谐振腔的电磁辐射，降低了谐振腔对其他部件的电磁干扰的效果，强化了电磁隔离。
在具体设置振荡器时，所述振荡器还包括与所述谐振腔耦合的交叉耦合管；所述屏蔽罩还用于罩住所述交叉耦合管。
在具体设置半导体器件时，除了上述的裸芯结构外，还包括覆盖在裸芯的封装结构，该封装结构用于封装裸芯。其中，设置的裸芯为多层结构，在具体设置时，其包括一个基底以及层叠设置在该基底上的多个金属层；并且在多个金属层中，至少两个第一金属层上分别设置有屏蔽环。同时在封装结构上设置了屏蔽层；并且设置的屏蔽层与至少两个第一金属层上设置的至少两个屏蔽环电连接形成了上述的屏蔽罩。通过设置的屏蔽层与屏蔽环形成罩住电感的屏蔽罩。
在设置屏蔽环时，在所述多个金属层中的至少一个第二金属层上设置有所述电感；所述至少两个第一金属层中至少有一个第一金属层与所述至少一个第二金属层为不同的金 属层，且所述至少两个第一金属层中至少有一个第一金属层位于所述至少一个第二金属层之上。可以提高对该电感的电磁辐射的屏蔽效果，从而降低了电感对于除振荡器之外的其他元件的电磁干扰。
在具体设置屏蔽环时，每个第一金属层上设置的屏蔽环为金属环。
在具体设置每个屏蔽环时，每个屏蔽环的形状大小可以相同也可以不同。如沿裸芯的厚度方向，屏蔽环的尺寸逐渐变大，或者逐渐变小，或者一大一小的交替排列。当然也可以相等，此时，每个屏蔽环在所述第二金属层上的垂直投影环绕所述电感。从而方便屏蔽环之间的电连接，并且可以达到罩住电感的效果。
在具体设置每个屏蔽环的形状时，每个屏蔽环的结构为对称结构，所述电感的结构为对称结构，且所述对称结构的对称轴线与所述电感的轴线共轴线。通过采用对称结构可以有效的提高对电感的电磁辐射的屏蔽效果。
在实现屏蔽环之间的电连接时可以采用不同的方式，如在一个具体的实施方案中，所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接。在采用过孔时，为了降低电磁泄漏，设置的过孔之间的间距比较密集，如两个过孔之间的间隙小于被屏蔽波长的十分之一。当然除了上述过孔的连接方式外，还可以采用设置一个长条形的孔，如长腰孔，通过该长腰孔使得相邻的两个屏蔽环电连接，以增加两个屏蔽环的连接面积，降低电磁泄漏。
在具体连接屏蔽环与屏蔽层时，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接。
在具体设置多个金属柱，且所述电感的结构为对称结构时，所述多个金属柱沿所述电感的对称轴线对称排列。通过采用对称的方式设置，有效的提高了对电感的电磁辐射的屏蔽效果。
在具体设置多个金属柱时，可以采用不同的金属柱结构，如多个金属柱包括多个第一金属柱及多个第二金属柱，且所述第一金属柱与所述第二金属柱的直径不同。该金属柱可以采用半导体器件上原有的结构，如采用球托，该球托用于生长锡球，用于封装连接。
为了提高屏蔽的效果，在所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙根据所述电感的辐射的频率以及目标衰减值确定。从而改善对电感的电磁辐射的屏蔽效果。
在具体设置时，至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均根据所述电感的辐射的频率以及目标衰减值确定。如在具体设置时，在目标衰减值小于第一设定衰减值时，任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均为第一宽度值，第一宽度值为电感的辐射的频率对应的波长的二十分之一；而在目标衰减值大于第一设定衰减值时，且目标衰减值与第一设定衰减值的差与第二预设衰减值的比值为N；N为正整数；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均为第一宽度值的
Figure PCTCN2019085364-appb-000001
任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙小于所述电感的辐射的频率对应的波长的十分之一。
此外，还包括设置在所述裸芯中的接地层，且所述接地层位于所述基底与所述至少一 个第二金属层之间。通过接地层阻挡电感向基底方向上的电磁辐射，提高对电感的电磁辐射的屏蔽效果。
在具体设置上述的电感时，该电感包括串联的第一电感及第二电感，且所述第一电感及所述第二电感呈对称结构。在具体设置时，该电感设置在裸芯中多个金属层中的至少一个第二金属层上，如第一电感及第二电感设置在同一个第二金属层上，或者第一电感与第二电感设置了不同的第二金属层上。
第二方面，提供了一种半导体器件，该半导体器件包括一个裸芯，以及设置在所述裸芯中的振荡器。该振荡器包括谐振腔，该谐振腔中包含电感。在振荡器工作时，该电感可能出现电磁辐射从而影响到裸芯中设置的其他元件，因此该半导体器件还包括一个屏蔽结构，该屏蔽结构至少包括与所述电感同层设置且环绕所述电感的第一屏蔽环，以及与所述电感不同层设置的至少一个第二屏蔽环；并且第一屏蔽环与至少一个第二屏蔽环之间电连接。通过屏蔽结构屏蔽电感的电磁辐射，相比于现有技术中只通过同层设置的金属层对电感的电磁辐射进行屏蔽，本申请提供的屏蔽结构通过多层屏蔽环对电感的电磁辐射进行屏蔽，从而降低了电感对于半导体器件中除振荡器之外的其他元件的电磁干扰。
在裸芯设计中，可以通过不同的金属层来承载屏蔽环以及电感。具体地，所述裸芯包括：基底以及层叠设置在所述基底上的多个金属层；其中，所述电感及所述第一屏蔽环设置在所述多个金属层中的至少一个第二金属层上；所述第二屏蔽环设置在所述多个金属层中至少一个第一金属层上。
在具体设置第一屏蔽环和第二屏蔽环时，其中每个屏蔽环的形状大小可以相同也可以不同。如沿裸芯的厚度方向，屏蔽环的尺寸逐渐变大，或者逐渐变小，或者一大一小的交替排列，当然屏蔽环的尺寸也可以相等。此时，每个第二屏蔽环在所述至少一个第二金属层上的垂直投影环绕所述电感。采用上述设置方案，方便了屏蔽环之间的电连接，并且可以达到罩住电感的效果。
在具体设置每个屏蔽环的形状时，所述第一屏蔽环及每个第二屏蔽环的结构均为对称结构，所述电感的结构为对称结构；且所述第一屏蔽环及每个第二屏蔽环各自的对称轴线与所述电感的对称轴线共轴。通过采用对称结构可以有效的提高对电感的电磁辐射的屏蔽效果。
在实现屏蔽环之间的电连接时，可以采用不同的方式，如在一个具体的实施方案中，所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接。在采用过孔时，为了降低电磁辐射，设置的过孔之间的间距比较密集，如两个过孔之间的间隙小于被屏蔽波长的十分之一。当然除了上述过孔的连接方式外，还可以采用设置一个长条形的孔，如长腰孔，通过该长腰孔使得相邻的两个屏蔽环电连接，以增加两个屏蔽环的连接面积，降低电磁辐射。
上述的屏蔽结构除了设置的多层屏蔽环外，还可以包括其它结构，如在一个具体的可实施方案中，所述半导体器件还包括：覆盖所述裸芯的封装结构，所述屏蔽结构还包括在所述封装结构上设置的屏蔽层，且所述第一屏蔽环及所述至少一个第二屏蔽环中位于最上层的屏蔽环与所述屏蔽层通过多个金属柱电连接。通过屏蔽层与屏蔽环电连接形成一个罩体，通过该罩体罩住电感来改善电感的电磁辐射情况。
在具体设置多个金属柱时，若所述电感的结构为对称结构，则所述多个金属柱可以沿所述电感的对称轴线对称排列。通过采用对称的方式设置，有效的提高了对电感的电磁辐射的屏蔽效果。
在具体设置多个金属柱时，可以采用不同的金属柱结构，如多个金属柱包括多个第一金属柱及多个第二金属柱，且所述第一金属柱与所述第二金属柱的直径不同。通过采用不同的金属柱来增加屏蔽效果。该金属柱可以采用半导体器件上原有的结构，如采用球托，该球托用于生长锡球，用于封装连接。
为了提高屏蔽的效果，在所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙根据所述电感的辐射的频率以及目标衰减值确定。从而改善对电感的电磁辐射的屏蔽效果。
在具体设置时，至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均根据所述电感的辐射的频率以及目标衰减值确定。如在具体设置时，在目标衰减值小于第一设定衰减值时，任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均为第一宽度值，第一宽度值为电感的辐射的频率对应的波长的二十分之一；而在目标衰减值大于第一设定衰减值时，且目标衰减值与第一设定衰减值的差与第二预设衰减值的比值为N；N为正整数；任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均为第一宽度值的
Figure PCTCN2019085364-appb-000002
任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙小于所述电感的辐射的频率对应的波长的十分之一。从而改善对电感的电磁辐射的屏蔽效果。
此外，该半导体器件还包括设置在所述裸芯中的接地层，且所述接地层位于所述基底与所述至少一个第二金属层之间。通过接地层阻挡电感向基底方向上的电磁辐射，提高对电感的电磁辐射的屏蔽效果。
第三方面，提供了一种电子设备，该电子设备包括基板，以及上述任一项所述的半导体器件，且所述半导体器件设置于所述基板之上。通过该屏蔽罩对电感的电磁辐射进行屏蔽，相比与现有技术中只通过同层设置的金属层对电感的电磁辐射进行屏蔽，本申请提供的半导体器件通过屏蔽罩罩住电感并对该电感的电磁辐射进行屏蔽，提高了屏蔽效果。
附图说明
图1为本申请实施例提供的振荡器的结构示意图；
图2为本申请实施例提供的半导体器件的内部结构示意图；
图3为本申请实施例提供的半导体器件的截面示意图；
图4为本申请实施例提供的另一半导体器件的截面示意图；
图5为本申请实施例提供的半导体器件的仰视图；
图6为本申请实施例提供的半导体器件的仿真示意图；
图7为本申请实施例提供的半导体器件的仿真示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
为了方便理解本申请实施例提供的半导体器件，下面首先说明一下其应用场景。该半 导体器件可以为不同功能的半导体器件，在使用时可以应用到不同的电子设备上。在半导体器件应用时，由于设置在半导体器件里的振荡器中的电感会产生电磁辐射，影响到半导体器件上的其他元件的工作，因此，本申请实施例提供了一种半导体器件，下面结合附图对该半导体器件进行详细的说明。
为方便理解，首先说明一下本申请实施例提供的半导体器件中包含的振荡器，图1中示出了振荡器的电路图，该振荡器100包括谐振腔102，分别与谐振腔102耦合的交叉耦合管101a、101b；其中，交叉耦合管101a、101b用于为谐振腔102提供负阻补偿，谐振腔102用于产生振荡信号。在图1所示的振荡器100中，两个交叉耦合管101分别在谐振腔102的两端相耦合，其中交叉耦合管101a耦合接电源电压VDD，交叉耦合管101b耦合接地Vss。本申请，振荡器100可以为压控振荡器VCO，或者为其他类型的振荡器100。但是无论采用哪种振荡器，该振荡器的谐振腔102均包含电感。在图1中所示的谐振腔102中，电感包括串联的第一电感及第二电感，其中第一电感为谐振电感L1，第二电感为谐振电感L2，且第一电感及第二电感呈对称结构。在具体设置该谐振腔102时，除了上述的电感外，还可以包括与电感并联的可变电容以及开关电容阵列；如图1中所示，其中可变电容的个数为两个，在图1中分别为电压控制可变电容VAR1和电压控制可变电容VAR2。而设置的开关电容阵列包含串联的电容C1、电容C2以及开关SW。上述电容、可变电容及开关电容阵列构成了基本的电感电容并联谐振网络，其频率由电感值以及电容值共同决定；并且通过SW的控制电压开关可以控制频率的改变(频率粗调)，通过控制可变电容上的电压可以控制频率的连续改变(频率细调)；由于实际的电感、电容器件存在寄生电阻，因此其振荡过程中会有能量消耗，为了维持谐振网络的稳定振荡，通过设置的交叉耦合管101的互补交叉接法，可以产生负阻抗，持续为谐振网络注入能量维持其稳定振荡。如图1中所示交叉耦合管101的个数为两个，其中的一个交叉耦合管101包括负阻管M1及负阻管M2，而另一个交叉耦合管101包括负阻管M3及负阻管M4。上述振荡器100中的电容以电场的形式周期性地储存和释放能量，电感以磁场的形式周期性地储存和释放能量，其中，电感磁场的周期性变化是干扰半导体器件中的其他元件以及产生辐射的源头。当然，应当理解的是图1仅仅是对振荡器100的一个具体示例，还可以振荡器100中不包含交叉耦合管101而采用其他的结构，或者在本申请实施例提供的振荡器100还可以采用现有的已知振荡器的其他结构。但是无论采用哪种振荡器100，其谐振腔102中的电感都会对半导体器件的其他元件造成干扰。为了降低该振荡器100的干扰，在本申请实施例提供的半导体器件中设置了屏蔽罩，该屏蔽罩罩住电感以达到屏蔽电感的电磁辐射的效果。下面结合附图详细说明一下屏蔽罩如何屏蔽电感。
图2及图3中所示为半导体器件的结构，该半导体器件包括一个裸芯(die)以及设置在裸芯的屏蔽罩及振荡器(图2中仅示出了振荡器的电感)。在具体设置时，该裸芯包括基底以及层叠设置在该基底上的多个金属层10，并且在多个金属层10之间间隔了介质层，即介质层与金属层10交替层叠设置形成裸芯。
一并参考图3及图5，在图3及图5中示出了振荡器的电感20所处的位置。在具体设置时，该电感20设置在了裸芯中的一个第二金属层12上，当然在具体设置该电感20时，也可以将第一电感及第二电感分别设置在不同的第二金属层12上，此时，对应的第二金属层12的个数为两个。但是无论采用哪种方式设置的屏蔽罩的结构都相同，因此以电感20设置在同一金属层10上为例进行说明。在设置电感20时，设置电感20的第二金属层 12可以设置在裸芯中不同的位置，如在一个具体的实施方案中，该第二金属层12位于多个金属层10的中间位置。在具体形成该电感20时，通过在该裸芯中的第二金属层12上刻蚀形出放置该电感20的放置区，在该放置区内设置电感20，并且设置的电感20与第二金属层12上其他部分的金属电隔离。对于制备的电感20可以采用不同的结构形状，如在一个具体的可实施方案中，该电感20采用对称的结构。在具体设置时可以采用不同的对称结构，如图2中所示的电感20采用8字形的结构，并且该8字形的电感的一端开口并连接了输入端及输出端。在采用对称结构时，由于电感的对称结构可以相互抵消部分磁场，因此，可通过电感20的自身结构降低电磁辐射。当然应当理解的是，该电感20还可以采用其他的对称结构，如该电感20为并联耦合电感或者蝴蝶型电感。
继续参考图2，由于振荡器的工作频段比较高，谐振腔中的电感的电磁辐射比较大，因此虽然电感20采用对称结构降低了辐射，但是仍不可避免的会产生辐射，对其他的电感(其他元件200)产生频率牵引(两个电感之间的相互影响造成)，同时也会造成电感20的能量泄漏。为了改善这种情况，在本申请实施例提供的裸芯中设置了一个屏蔽罩，该屏蔽罩罩住了上述电感20，并可屏蔽电感20的辐射，从而降低电感20对其他电感的影响，同时也可以降低其能量泄漏。该屏蔽罩在具体设置时也是通过裸芯承载，并且利用了裸芯上的金属层10形成罩住电感20的腔室。
在具体设置屏蔽罩时，该屏蔽罩包括在多个金属层10中的至少两个第一金属层11上分别设置的屏蔽环40，每个屏蔽环40为设置在第一金属层11上的金属环，该金属环可以为圆形环、方形环或者其他形状的环形结构。如图3所示，设置的至少两层屏蔽环40沿裸芯的厚度方向层叠，并且环绕电感20。由上述描述可以看出，在设置电感20时其位于屏蔽环40围住的空间内，但是在具体设置时可以有不同的方式，下面一一列举说明。如电感20与位于最下方的屏蔽环40齐平，或者电感20与位于最上方的屏蔽环40齐平，当然还可以电感20位于中间的屏蔽环40齐平。在如图3所示的结构中，该电感20位于至少两层屏蔽环40围成的空间的中间位置，此时，在电感20的上方以及下方(以金属层10层叠的方向作为参考方向)均有屏蔽环40，由于在垂直方向上与电感20存在一定的高度差，如图3中所示，最上层的屏蔽环40距离电感20的垂直距离为h1，最下层的屏蔽环40距离电感20的垂直距离为h2，因此在电感20辐射时，在水平方向上、斜向上、斜向下方向上可以通过屏蔽环40屏蔽电感20的电磁辐射，相比与现有技术中采用与电感20同层设置金属环的结构来说，由于金属环本身的寄生电阻和电感的存在，对高频的隔离改善较小。而在本申请实施例提供的至少两层屏蔽环40在电感20的水平方向、斜向方向上对电感20的电磁辐射具有一定的屏蔽效果，并且本申请实施例提供的至少两层屏蔽环40具有一定的宽度以及高度，因此可以有效的降低接地电阻，更进一步的提高屏蔽效果。
由上述描述可以看出，在具体形成上述屏蔽环40时，屏蔽环40可以利用裸芯中的第一金属层11来制备。在具体制备时，可以在裸芯内的部分金属层10或者全部金属层10上设置屏蔽环40。如图3中所示，图3中示出的裸芯具有六层金属层，而六层金属层均设置了屏蔽环40，因此，图3中示例的六层金属层均为第一金属层11。当然在设置的六层金属层中，有一层金属层设置了电感20，此时电感20所在金属层同时属于第一金属层11及第二金属层12。但是至少两个第一金属层11中至少有一个第一金属层11a与至少一个第二金属层12为不同的金属层，并且至少两个第一金属层11中至少有一个第一金属层11a位于至少一个第二金属层12之上(以图2中所示的裸芯的放置方向为参考方向)。以使得 形成的屏蔽环40的个数为至少两个。
当然也可以采用仅部分金属层10设置屏蔽环40。此外，在采用部分金属层10制备金属环时，该部分金属层10包括设置有电感20的第二金属层12以及与该第二金属层12相邻的几层金属层。
在具体设置每个屏蔽环40时，该屏蔽环40为封闭的环形结构。具体制备时，在第一金属层11上刻蚀出一个金属环，该金属环即为屏蔽环40。在具体形成上述的屏蔽环40时，不同层的屏蔽环40的形状结构可以相同也可以不同，如在一个具体的实施方案中，沿裸芯的厚度方向，屏蔽环40的尺寸逐渐变大，或者逐渐变小，或者一大一小的交替排列。当然除了上述列举的方式外，还可以各个屏蔽环40的尺寸均相同，如图3中所示，在图3所示的屏蔽层的大小均相同，并且每个屏蔽环40在第二金属层12的垂直投影环绕电感20。上述列举的几种不同的屏蔽环40的设置方式均可以应用在本申请的实施例中。并且在具体设置上述屏蔽环40时，无论采用哪种设置方式，每个屏蔽环40的结构均为对称结构，并且该对称结构的对称轴线与电感20的轴线共轴线，以通过对称结构来改善对电感20的电磁辐射的屏蔽效果。
继续参考图3，在多个金属层10上制备的屏蔽环40呈层叠状，并且任意相邻的屏蔽环40之间电连接，从而使得层叠的屏蔽环40叠加形成一个环形且具有一定厚度的结构。在具体实现屏蔽环40之间的电连接时，可以采用不同的方式，如在图3所示的结构中，任意相邻的屏蔽环40之间通过过孔30电连接。并且任意相邻的两个屏蔽环40之间采用多个过孔30电连接。在采用过孔30连接屏蔽环40时，为了降低电磁泄漏，采用同层设置的过孔30之间的设置比较密集的方式来设置过孔30，并且应该保证相邻两个过孔30之间的间隙小于被屏。
在至少两个屏蔽环40中相邻的屏蔽环40之间通过过孔30电连接时，任意相邻的过孔30之间的间隙根据电感20的辐射的频率以及目标衰减值确定。如在具体设置时，在目标衰减值小于第一设定衰减值时，其中第一预设衰减值对应于第一衰减速率，任意相邻的过孔30之间的间隙均为第一宽度值，第一宽度值为电感20的辐射的频率对应的波长的二十分之一；而在目标衰减值大于第一设定衰减值时，且目标衰减值与第一设定衰减值的差与第二预设衰减值(对应第二衰减速率)的比值为N；N为正整数；任意相邻的过孔30之间的间隙均为第一宽度值的
Figure PCTCN2019085364-appb-000003
示例性的，任一频率电磁波的波长为:波长(λ)＝光速(C)/频率(Hz)。当过孔30之间的间隙的长度为波长(截止频率)的一半时，电感辐射的电磁波开始以20dB/10倍频(1/10截止频率)或6dB/8倍频(1/2截止频率)的速率衰减，其中，20dB/10倍频的速率为上述的第一衰减速率，6dB/8倍频的速率为上述的第二衰减速率。通常电感发射频率越高衰减越严重，因为它的波长越短。当涉及到最高频率时，必须要考虑可能会出现的任何谐波，不过实际上只需考虑一次及二次谐波即可。一旦知道了电感20辐射的频率及强度，就可计算出屏蔽罩的最大允许间隙和沟槽(包含过孔30之间的间隙)。例如，如果需要对1GHz(波长为300mm)的辐射衰减26dB，则150mm的间隙将会开始产生衰减，因此当存在小于150mm的间隙时，1GHz辐射就会被衰减。所以对1GHz频率来讲，若需要衰减20dB(目标衰减值)，按照上述的规律计算为：(300mm/2)/10＝300mm/20＝15mm，则间隙应小于15mm(150mm的1/10)，需要衰减26dB(目标衰减值)时，则相当于在20db的 基础上再衰减6db，因此为((300mm/2)/10)/2＝300mm/40＝7.5mm，则间隙应小于7.5mm(15mm的1/2以上)，需要衰减32dB(目标衰减值)时，则为(((300mm/2)/10)/2)2＝300mm/80＝3.75mm，间隙应小于3.75mm(7.5mm的1/2以上)。
通过上述描述可以看出，在具体设置过孔30之间的间隙时，任意相邻的过孔30之间的间隙小于电感20的辐射的频率对应的波长的十分之一，以避免在过孔30之间出现电磁泄漏。此外，对于过孔30的直径在本申请实施例中不做限定，但是设置的过孔30应该能够保持两个屏蔽环40之间的电连接效果。当然除了图3所示的过孔30的连接方式外，还可以采用其他的方式，如采用一个长条形的孔(长腰孔)，该长腰孔用于连接相邻的两个屏蔽环40，在具体连接时，以屏蔽环40为矩形为例，每个屏蔽环40的边对应连接一个长腰孔，由于长腰孔的内壁可以铺设连续的金属层，因此，在采用长腰孔时，可以降低两个屏蔽环40之间的间隙的同时还增加两个屏蔽环40的连接面积，改善了相邻的两个屏蔽环40的电连接效果，进而提高了对电感20的电磁辐射的屏蔽效果。
如图4中所示，在本申请实施例提供的屏蔽罩中，除了包含裸芯内的屏蔽环40外，还包括其他结构。如半导体器件在制备时需要封装裸芯。因此，该半导体器件的裸芯上还设置了覆盖裸芯的封装结构80。此时的屏蔽罩还包括在封装结构80上设置的屏蔽层50，且屏蔽层50位于封装结构80背离裸芯一面。在设置该屏蔽层50时，屏蔽层50与至少两个第一金属层11上设置的至少两个屏蔽环40电连接，更具体的为屏蔽层50与至少两个屏蔽环40中位于最上层的屏蔽环40电连接，其中，所述的最上层的屏蔽环40为最靠近封装结构80的屏蔽环。在具体制备该屏蔽层50时，可采用喷涂或者涂覆的方式在封装结构80的表面形成一层金属层，如铜金属层或者铁金属层。
在具体实现屏蔽层50与屏蔽环40之间电连接时，如图4中所示，在封装结构80内设置多个金属柱70，且多个金属柱70分别与屏蔽环40及屏蔽层50电连接并排列成环形。此外，在设置金属柱70时，任意相邻的金属柱70之间的间隙根据电感20的辐射的频率以及目标衰减值确定。从而改善对电感20的电磁辐射的屏蔽效果。在具体设置时，任意相邻的金属柱70之间的间隙根据电感20的辐射的频率以及目标衰减值确定。如在具体设置时，在目标衰减值小于第一设定衰减值时，其中第一预设衰减值对应于第一衰减速率，任意相邻的金属柱70之间的间隙为第一宽度值，第一宽度值为电感20的辐射的频率对应的波长的二十分之一；而在目标衰减值大于第一设定衰减值时，且目标衰减值与第一设定衰减值的差与第二预设衰减值(对应第二衰减速率)的比值为N；N为正整数；任意相邻的金属柱之间的间隙及任意相邻的过孔30之间的间隙均为第一宽度值的
Figure PCTCN2019085364-appb-000004
具体的示例可以参考关于电感20的过孔之间的间隙的描述，在此不再赘述。如相邻的金属柱70之间的间距小于被屏蔽波长(电感的电磁辐射的波长)的十分之一，从而降低泄漏。同样的，为了改善屏蔽效果，在具体设置多个金属柱70时，多个金属柱70采用对称的方式排列，如图5中所示，电感20的结构为对称结构，且多个金属柱70沿电感20的对称轴线对称排列，以提高对电感20的电磁辐射的屏蔽效果。
此外，在具体设置金属柱70时可以采用不同的金属柱70结构，如多个金属柱70包括多个第一金属柱71及多个第二金属柱72，且该第一金属柱71与第二金属柱72的直径不同。如图4及图5中所示，图4及图5示出了第一金属柱71及第二金属柱72的结构，其中第一金属柱71的直径大于第二金属柱72的直径，并且在排列时，第一金属柱71及 第二金属柱72分别采用对称的结构，即第一金属柱71分别对称，第二金属柱72也分别对称。在具体设置第一金属柱71及第二金属柱72时，可以利用半导体器件上已有的结构进行设置。如第一金属柱71采用原半导体器件中的用于封装连接的金属垫，而第二金属柱72采用球托(用于生长锡球，用于封装连接)。从而可以利用原半导体器件上的结构形成屏蔽结构。
当然上述金属柱70仅仅为一个具体的示例，在本申请实施例提供的屏蔽罩中还可以采用在封装结构80中直接封装金属层作为屏蔽环40与屏蔽层50的连接结构。
通过上述描述可以看出，在屏蔽罩包含封装结构80中的金属柱70时，该屏蔽罩包括位于裸芯内的屏蔽环40以及位于封装结构80上的屏蔽层50，此时屏蔽罩部分位于裸芯内部，部分位于封装结构80中。
在图3所示的屏蔽罩仅仅罩住了电感，但是应当理解的是，在本申请实施例提供的谐振腔包含与电感20并联的可变电容以及开关电容阵列时，设置的屏蔽罩也可以罩住可变电容以及开关电容阵列中的至少一个。此外，在振荡器包括交叉耦合管时，设置的屏蔽罩也可以罩住该交叉耦合管。通过上述描述可以看出，在设置屏蔽罩时，既可以仅罩住电感20也可以将振荡器中的其他部件罩住。
一并参考图4及图5，该裸芯中还设置了接地层60，且接地层60位于基底与至少一个第二金属层12之间，且设置的接地层60及屏蔽层50分列在电感20的两侧，以使得接地层60可以屏蔽电感20的下方沿基底方向的泄漏。也就是说，接地层60与屏蔽罩一起，形成一个屏蔽腔体，对电感20沿水平方向和垂直方向的电磁辐射进行屏蔽，从而避免了对半导体器件中的其他元件，以及半导体器件之外的其他元件造成电磁干扰。
在设置时，接地层60设置在多个金属层10中的第三金属层13，且第三金属层13位于第二金属层12背离屏蔽层50的一侧。如图4中所示的在电感20设置在第二金属层12时，接地层60可以设置在与第二金属层12相邻的第三金属层13上，也可以设置在与第二金属层12相隔的金属层上。在具体设置接地层60时，通过刻蚀第三金属层13形成该接地层60。此外，在具体设置该接地层60时，该接地层60可以与设置的屏蔽环40直接电连接，也可以存在一定的间隙。在接地层60与屏蔽环40之间存在间隙时，屏蔽环40与接地层60分别接地，并且接地层60与屏蔽环40之间的间隙应该保证不会泄露。此外，在设置接地层60的金属层上也可以设置屏蔽环40，此时，该金属层既属于第一金属层11也属于第三金属层13。
为了方便理解本申请实施例提供的半导体器件中对电感20的电磁辐射的屏蔽效果，以采用屏蔽环40以及两个屏蔽层对半导体器件进行屏蔽的结构为例与现有技术中的半导体器件进行仿真对比，其结构如图6及图7所示，首先参考图6，从图6中可以看到，在一次谐波处，本申请实施例提供半导体器件中的电感20能量降低很明显。从M3:10.9GHz处的-52db，优化到了M5：10.1GHz处的-79db。如图7中所示，图7示出了泄漏量的改善效果。本申请实施例提供的半导体器件中的电感20的电磁辐射泄漏量与现有技术中的半导体器件相比从49.17dBm减少到43.49dBm。
通过上述描述可以看出，在本申请实施例提供的半导体器件通过利用裸芯中的金属层10次，并结合封装基板、封装的金属球结构(用于封装连接)等层次将电感20放置在一个立体的屏蔽腔里面，对电感20四周的各层金属和裸die顶层金属的开窗结构、封装的金属球结构等进行完全对称的设计布局，可以明显降低电感20对周边走线及其他元件200 的辐射干扰问题，也可以明显降低电感直接辐射造成的杂散问题，有效的抑制频率牵引，同时可以明显的降低电感20一次谐波的干扰问题。
应当理解的是，本申请实施例提供的半导体器件在实现对电感20屏蔽时，不仅限于上述中描述的屏蔽罩，还可以采用屏蔽结构，下面对该屏蔽结构进行说明。
首先对于半导体器件中裸芯以及谐振器与上述中说明的振荡器及裸芯结构相同，在此不再赘述。在设置屏蔽结构时，该屏蔽结构至少包括与电感20同层设置且环绕电感20的第一屏蔽环，以及与电感20不同层设置的至少一个第二屏蔽环；其中，第一屏蔽环与至少一个第二屏蔽环之间电连接。在具体实现时，在裸芯中，电感20及第一屏蔽环设置在所述多个金属层中的至少一个第二金属层12；且多个金属层至少一个第一金属层11上设置有第二屏蔽环。即通过在不同的金属层来承载屏蔽环以及电感20，并且通过设置的不同层的屏蔽环40之间电连接形成屏蔽结构来屏蔽电感20的电磁辐射。具体的可以参考上述中关于图3中的描述。其中，在图3中所示的结构中，与电感40同层的屏蔽环为上述的第一屏蔽环，与电感40不同层的屏蔽环为上述的第二屏蔽环。此时的屏蔽结构可以看成部分的屏蔽罩结构。
此外，对于屏蔽结构也可以采用与屏蔽罩相同的结构，此时，该屏蔽结构包含屏蔽环40以及屏蔽层，其具体的连接方式可以参考上述中关于图4中的介绍。
通过上述描述可以看出，在本申请实施例提供的半导体器件中，既可以采用屏蔽罩的部分结构来实现屏蔽电感20的电磁辐射，也可以通过整个屏蔽罩来实现屏蔽电感20的电磁辐射。
本申请实施例还提供了一种电子设备，该电子设备包括基板，以及设置在该基板上的上述任一项所述的半导体器件。在本申请实施例提供的半导体器件通过利用裸芯中的金属层10，并结合封装结构上的屏蔽层将电感20放置在一个立体的屏蔽腔里面，对电感20四周的各层金环和金属柱等进行完全对称的设计布局，可以明显降低电感20对周边走线及其他元件200的辐射干扰问题，也可以明显降低电感直接辐射造成的杂散问题，有效的抑制频率牵引，同时可以明显的降低电感20一次谐波的干扰问题。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (28)

  1. 一种半导体器件，其特征在于，包括：
    裸芯，以及设置在所述裸芯中的振荡器和屏蔽罩；其中，所述振荡器包括谐振腔，所述谐振腔包括电感；
    所述屏蔽罩用于罩住所述电感。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述谐振腔还包括：分别与所述电感并联的可变电容以及开关电容阵列；所述屏蔽罩还用于罩住所述可变电容以及所述开关电容阵列中的至少一个。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述振荡器还包括：与所述谐振腔相耦合的交叉耦合管；所述屏蔽罩还用于罩住所述交叉耦合管。
  4. 根据权利要求1～3任一项所述的半导体器件，其特征在于，所述半导体器件还包括：覆盖所述裸芯的封装结构，所述裸芯包括：基底以及层叠设置在所述基底上的多个金属层，其中，在所述多个金属层中的至少两个第一金属层上分别设置有屏蔽环，在所述封装结构上设置有屏蔽层，所述屏蔽层与所述至少两个第一金属层上设置的至少两个屏蔽环电连接，形成所述屏蔽罩。
  5. 根据权利要求4所述的半导体器件，其特征在于，每个第一金属层上设置的屏蔽环为金属环。
  6. 根据权利要求4或5所述的半导体器件，其特征在于，在所述多个金属层中的至少一个第二金属层上设置有所述电感；所述至少两个第一金属层中至少有一个第一金属层与所述至少一个第二金属层为不同的金属层，且所述至少两个第一金属层中至少有一个第一金属层位于所述至少一个第二金属层之上。
  7. 根据权利要求4所述的半导体器件，其特征在于，每个屏蔽环在所述至少一个第二金属层上的垂直投影环绕所述电感。
  8. 根据权利要求4～7任一项所述的半导体器件，其特征在于，每个屏蔽环的结构为对称结构，所述电感的结构为对称结构，且所述对称结构的对称轴线与所述电感的对称轴线共轴。
  9. 根据权利要求4～8任一项所述的半导体器件，其特征在于，所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接。
  10. 根据权利要求4～9任一项所述的半导体器件，其特征在于，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接。
  11. 根据权利要求10所述的半导体器件，其特征在于，所述电感的结构为对称结构，所述多个金属柱沿所述电感的对称轴线对称排列。
  12. 根据权利要求10或11所述的半导体器件，其特征在于，所述多个金属柱包括多个第一金属柱及多个第二金属柱，且所述第一金属柱与所述第二金属柱的直径不同。
  13. 根据权利要求10～12任一项所述的半导体器件，其特征在于，在所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；
    任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均根据所述电感的辐射的频率以及目标衰减值确定。
  14. 根据权利要求13所述的半导体器件，其特征在于，任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙小于所述电感的辐射的频率对应的波长的十分之一。
  15. 根据权利要求4～14任一项所述的半导体器件，其特征在于，还包括：设置在所述裸芯中的接地层，且所述接地层位于所述基底与所述至少一个第二金属层之间。
  16. 根据权利要求1～15任一项所述的半导体器件，其特征在于，所述电感包括：串联的第一电感及第二电感，且所述第一电感及所述第二电感呈对称结构。
  17. 一种半导体器件，其特征在于，包括裸芯，以及设置在所述裸芯中的振荡器以及屏蔽结构；其中，
    所述振荡器包括谐振腔，所述谐振腔包括电感；
    所述屏蔽结构至少包括与所述电感同层设置且环绕所述电感的第一屏蔽环，以及与所述电感不同层设置的至少一个第二屏蔽环；其中，所述第一屏蔽环与所述至少一个第二屏蔽环之间电连接。
  18. 根据权利要求17所述的半导体器件，其特征在于，所述裸芯包括：基底以及层叠设置在所述基底上的多个金属层；其中，所述电感及所述第一屏蔽环设置在所述多个金属层中的至少一个第二金属层上；所述第二屏蔽环设置在所述多个金属层中至少一个第一金属层上。
  19. 根据权利要求18所述的半导体器件，其特征在于，每个第二屏蔽环在所述至少一个第二金属层上的垂直投影环绕所述电感。
  20. 根据权利要求18或19所述的半导体器件，其特征在于，所述第一屏蔽环及每个第二屏蔽环的结构均为对称结构，所述电感的结构为对称结构；
    且所述第一屏蔽环及每个第二屏蔽环各自的对称轴线与所述电感的对称轴线共轴。
  21. 根据权利要求18或19所述的半导体器件，其特征在于，所述第一屏蔽环及所述第二屏蔽环中相邻的屏蔽环之间通过过孔电连接。
  22. 根据权利要求17～21任一项所述的半导体器件，其特征在于，所述半导体器件还包括：覆盖所述裸芯的封装结构，所述屏蔽结构还包括在所述封装结构上设置的屏蔽层，且所述第一屏蔽环及所述至少一个第二屏蔽环中位于最上层的屏蔽环与所述屏蔽层通过多个金属柱电连接。
  23. 根据权利要求22所述的半导体器件，其特征在于，所述电感的结构为对称结构；所述多个金属柱沿所述电感的对称轴线对称排列。
  24. 根据权利要求22或23所述的半导体器件，其特征在于，所述多个金属柱包括多个第一金属柱及多个第二金属柱，且所述第一金属柱与所述第二金属柱的直径不同。
  25. 根据权利要求22～24任一项所述的半导体器件，其特征在于，在所述至少两个屏蔽环中相邻的屏蔽环之间通过过孔电连接时；或，所述屏蔽层与所述至少两个屏蔽环中位于最上层的屏蔽环之间通过多个金属柱电连接；
    任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙均根据所述电感的辐射的频率以及目标衰减值确定。
  26. 根据权利要求25所述的半导体器件，其特征在于，任意相邻的金属柱之间的间隙及任意相邻的过孔之间的间隙小于所述电感的辐射的频率对应的波长的十分之一。
  27. 根据权利要求18～26任一项所述的半导体器件，其特征在于，还包括设置在所述裸芯中的接地层，且所述接地层位于所述基底与所述至少一个第二金属层之间。
  28. 一种电子设备，其特征在于，包括基板，以及如权利要求1～16任一项所述的半导体器件或权利要求17～27任一项所述的半导体器件，所述半导体器件设置于所述基板之上。
PCT/CN2019/085364 2019-04-30 2019-04-30 一种半导体器件及电子设备 WO2020220341A1 (zh)

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