WO2020215928A1 - 超声波指纹识别装置及显示装置 - Google Patents

超声波指纹识别装置及显示装置 Download PDF

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Publication number
WO2020215928A1
WO2020215928A1 PCT/CN2020/079974 CN2020079974W WO2020215928A1 WO 2020215928 A1 WO2020215928 A1 WO 2020215928A1 CN 2020079974 W CN2020079974 W CN 2020079974W WO 2020215928 A1 WO2020215928 A1 WO 2020215928A1
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Prior art keywords
layer
electrode
ultrasonic fingerprint
fingerprint identification
insulating layer
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PCT/CN2020/079974
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English (en)
French (fr)
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邸云萍
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京东方科技集团股份有限公司
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Publication of WO2020215928A1 publication Critical patent/WO2020215928A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing

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  • the present disclosure generally relates to the field of fingerprint identification sensors, and in particular to ultrasonic fingerprint identification devices and display devices.
  • Existing ultrasonic fingerprint identification devices include ultrasonic fingerprint identification devices prepared by a semiconductor process using a silicon wafer as a substrate, and ultrasonic fingerprint recognition devices prepared by a low-temperature polysilicon process using glass as a substrate.
  • the performance of existing ultrasonic fingerprint identification devices needs to be further improved to meet the development requirements of display panels.
  • an ultrasonic fingerprint identification device includes:
  • Circuit layer including thin film transistors
  • a piezoelectric device layer including a driving electrode, a receiving electrode, and a piezoelectric film layer between the driving electrode and the receiving electrode;
  • An organic insulating layer is provided between the circuit layer and the piezoelectric device layer.
  • the first extraction electrode, the first extraction electrode is arranged on the side of the organic insulating layer away from the piezoelectric device layer, and the first extraction electrode passes through the first via hole passing through the source and drain insulating layer of the circuit layer and the circuit layer
  • the source and drain of the thin film transistor in are electrically connected, while the first lead electrode is electrically connected to the receiving electrode.
  • the ultrasonic fingerprint identification device further includes a second extraction electrode, which is located on the side of the piezoelectric film layer opposite to the driving electrode and passes through the piezoelectric film layer.
  • the second via hole or the extended portion of the driving electrode is electrically connected to the driving electrode.
  • the ultrasonic fingerprint identification device further includes a first insulating layer disposed between the organic insulating layer and the piezoelectric film layer, and the receiving electrode and the second extraction electrode are disposed on the first insulating layer.
  • An insulating layer is away from the side of the piezoelectric film layer.
  • the ultrasonic fingerprint identification device further includes an inorganic insulating layer disposed between the organic insulating layer and the receiving electrode.
  • the ultrasonic fingerprint identification device further includes a backing layer disposed on the side of the driving electrode away from the piezoelectric film layer to form the backing layer The density of the material is greater than that of the driving electrode.
  • the ultrasonic fingerprint identification device further includes a protective layer disposed on the side of the backing layer away from the driving electrode.
  • the receiving electrode and the second extraction electrode are in the same layer and spaced apart from each other.
  • the ultrasonic fingerprint identification device further includes a flexible substrate.
  • the circuit layer includes an active layer, and a third via is provided between the active layer and the source and drain to achieve electrical connection through the third via,
  • the third via hole and the first via hole are aligned in a direction perpendicular to the active layer; or, the first via hole and the third via hole are not aligned in a direction perpendicular to the active layer, the first The via hole is electrically connected to the source and drain.
  • the first extraction electrode is symmetrically arranged with the first via hole as the center.
  • the circuit layer includes a source and drain insulating layer, and the source and drain are formed on a side of the source and drain insulating layer away from the first extraction electrode so as to pass through the source and drain insulating layer and the first Lead out electrodes to separate;
  • the thickness of the organic insulating layer is configured to be greater than the thickness of the source and drain insulating layer, and the capacitance between the receiving electrode and the source and drain can be reduced below a desired value.
  • the circuit layer includes:
  • the first thin film transistor, the active layer of the first thin film transistor sequentially includes an N-type heavily doped region, an N-type lightly doped region, a polysilicon region, an N-type lightly doped region, and an N-type heavily doped region; and/ or
  • the second thin film transistor, the active layer of the second thin film transistor includes a P-type heavily doped region, a polysilicon region, and a P-type heavily doped region in sequence.
  • the backing layer is a metal layer.
  • a display device which includes the ultrasonic fingerprint identification device provided by each embodiment of the present disclosure and a display panel attached thereto.
  • the display panel has a flexible base substrate.
  • a third aspect of the present disclosure provides a method of manufacturing the above-mentioned display ultrasonic fingerprint identification device, the method including:
  • circuit layer including a thin film transistor, an organic insulating layer and a piezoelectric device layer one by one on the flexible substrate;
  • the piezoelectric device includes: a driving electrode, a receiving electrode, and a piezoelectric film layer between the driving electrode and the receiving electrode;
  • the ultrasonic fingerprint identification device also includes:
  • the first extraction electrode which is arranged on the side of the organic insulating layer away from the piezoelectric device layer, is electrically connected to the receiving electrode through a first via hole, and is electrically connected to the source and drain of the circuit layer .
  • the method further includes: when the receiving electrode is formed, a second extraction electrode is simultaneously formed by patterning, and the second extraction electrode is on the side of the piezoelectric film layer opposite to the driving electrode and passes through the second pass.
  • the hole is electrically connected to the driving electrode.
  • the method further includes: forming a backing layer on the piezoelectric device layer.
  • the method further includes: peeling off the supporting substrate.
  • the wiring density of the peripheral circuit caused by the large size can be reduced.
  • the thickness of the entire fingerprint identification device can also be reduced, and an ultra-thin and bendable effect can be obtained.
  • Fig. 1 shows an exemplary structural block diagram of an NMOS-based ultrasonic fingerprint identification device according to an embodiment of the present disclosure
  • Fig. 2 shows an exemplary structural block diagram of a PMOS-based ultrasonic fingerprint recognition device according to another embodiment of the present disclosure
  • Fig. 3 shows an exemplary flow chart of a manufacturing method of an NMOS-based ultrasonic fingerprint identification device according to an embodiment of the present disclosure
  • FIG. 4 shows an exemplary flowchart of a manufacturing method of a PMOS-based ultrasonic fingerprint identification device according to another embodiment of the present disclosure.
  • FIG. 5 shows an exemplary process diagram of forming a receiving electrode and an extraction electrode according to an embodiment of the present disclosure.
  • FIG. 6 shows an exemplary process diagram of forming a receiving electrode and an extraction electrode according to an embodiment of the present disclosure.
  • the substrate thinning process loses the yield and results in the ultrasonic fingerprint identification device and the display cover
  • the glass takes up a lot of space, which makes the product thickness larger; the use of rigid substrate is not suitable for bonding with ultra-thin flexible display screens, and the product is not suitable for generating large-size panels.
  • An embodiment of the present disclosure provides an ultrasonic fingerprint identification device including: a circuit layer including a thin film transistor; a piezoelectric device layer; and an organic insulating layer 12 disposed between the two.
  • the piezoelectric device includes: a driving electrode 18 and a receiving electrode 14 for providing a driving voltage, and a piezoelectric film layer 17 between the two.
  • the piezoelectric film layer 17 functions as an electrical signal provided by the driving electrode 18 Under the action of sound waves, it can produce ultrasonic waves, and can produce electric signals that reflect the strength of sound waves under the action of sound waves.
  • the ultrasonic fingerprint identification device further includes: a first extraction electrode 11, the first extraction electrode 11 is disposed on the side of the organic insulating layer 12 away from the piezoelectric device layer 17, and passes through the circuit layer
  • the first via 21 of the source-drain insulating layer 10 is electrically connected to the source and drain 9 of the thin film transistor in the circuit layer.
  • the ultrasonic fingerprint identification device may further include a second extraction electrode 15 on the side of the piezoelectric film layer 17 opposite to the driving electrode 18 and passing through the piezoelectric film layer.
  • the second via 22 is electrically connected to the driving electrode 18.
  • the second extraction electrode 15 is electrically connected to the driving electrode through the extended portion of the driving electrode.
  • the receiving electrode 14 and the second extraction electrode 15 are formed by patterning the conductive layer, and then, the piezoelectric material used for the piezoelectric thin film layer 17 is covered (the first insulating layer 16 and) The piezoelectric material layer is patterned to form the pattern of the piezoelectric film layer 17.
  • the pattern of the piezoelectric film layer 17 includes the piezoelectric film layer 17 and the second via 22 exposing the receiving electrode 15 and the second extraction electrode 16, Then, a conductive material layer for the driving electrode 18 is formed on the pattern of the piezoelectric thin film layer 17. In this process, the conductive material for the driving electrode 18 fills the second via 22, thereby forming a layer on the piezoelectric thin film layer.
  • the driving electrode 18 is electrically connected to the second via 22 exposing the driving electrode 17 and the second extraction electrode 15 in the piezoelectric film layer pattern.
  • the difference from the embodiment in FIG. 5 is that the pattern of the piezoelectric film layer 17 is directly formed on the receiving electrode 14 and the second extraction electrode 15. It includes a piezoelectric film layer 17 and an opening that exposes the receiving electrode and the second extraction electrode.
  • the piezoelectric film layer covers the receiving electrode 14 (the receiving electrode 14 may be covered with the first insulating layer 16); and then the piezoelectric film layer 17 A conductive material layer for the driving electrode 18 is formed on the pattern to form a driving electrode on the piezoelectric thin film layer, and the conductive material for the driving electrode 18 fills the exposed driving electrode in the pattern of the piezoelectric thin film layer 17 in the process And the opening portion of the second extraction electrode thereby forming an extension portion of the driving electrode.
  • the second extraction electrode 15 may be electrically connected to the extended portion of the driving electrode.
  • the receiving electrode 14 and the second extraction electrode 15 can be formed at one time by forming a conductive film and a patterning process, and then a patterned piezoelectric film layer is formed, that is, the pattern of the piezoelectric film layer has a reserved portion exposed.
  • the piezoelectric device is formed by the driving electrode 18, the receiving electrode 14, and the piezoelectric thin film layer 17 (made of piezoelectric material) between the two.
  • the driving electrode 18 can be electrically connected to a power source to provide an alternating electrical signal, so that the piezoelectric material generates sound waves due to the inverse piezoelectric effect.
  • the piezoelectric film layer 17 can also generate electrical signals under the action of sound waves.
  • the electrical signals of the piezoelectric film layer 17 are received by the receiving electrode 14 and transmitted to the source and drain 9 of the circuit layer.
  • the final circuit layer can be based on the electrical signal of the receiving electrode 14.
  • the signal constructs the shape of the sound wave response, such as the fingerprint of a finger.
  • the first extraction electrode 11 is provided so that a part of the leads used for signal transmission can be located on the layer where the first extraction electrode 11 (such as organic insulating Therefore, enough space is obtained for arranging these leads, which can solve the problem of insufficient space for the lead arrangement of the ultrasonic fingerprint identification device in large-area display panels or equipment applications.
  • the strength of the entire ultrasonic fingerprint identification device can also be increased, thus making the ultrasonic fingerprint identification device of this embodiment suitable for application to large-area panels; in addition, Since the thickness of the organic insulating layer is large, the depth of the via hole is large, resulting in insufficient reliability of the electrical connection through the via hole.
  • the first lead electrode 11 of this embodiment improves the reliability of the electrical connection in the via hole;
  • the increase in the thickness of the insulating layer can reduce the parasitic capacitance between the receiving electrode and the first extraction electrode and the source and drain electrodes.
  • the driving electrode 19 of the piezoelectric device layer has a large thickness, which is not suitable for making leads in practical applications. Therefore, the second extraction electrode 15 is provided as the lead of the driving electrode 19.
  • the piezoelectric device may further include a first insulating layer 16 disposed between the organic insulating layer 12 and the piezoelectric thin film layer 17, and the receiving electrode 14 and the second extraction electrode 15 are disposed on the first insulating layer 16. The side away from the piezoelectric film layer.
  • an inorganic insulating layer 12 can also be provided, which can prevent the material of the organic insulating layer 12 from interfering with the material properties of the receiving electrode 14.
  • Fig. 1 shows the structure of a specific embodiment. However, it should be understood that not all components in Fig. 1 are necessary.
  • An ultrasonic fingerprint identification device comprising a gate insulating layer 4, a gate 5, a flat layer 8, a source drain 9, a source drain insulating layer 10, an organic insulating layer 12, a receiving electrode 14, and a first insulating layer arranged in sequence 16.
  • the first extraction electrode 11 is disposed on the organic insulating layer 12 and is electrically connected to the source and drain 9 through the first via 21;
  • the second extraction electrode 15 is provided on the first insulating layer 16 and is electrically connected to the driving electrode 18 through the second via 22.
  • the source drain 9 and the driving electrode 18 are provided with a first extraction electrode 11 and a second extraction electrode 15, respectively, and the source and drain 9 and the first extraction electrode 11 are on different layers (ie, the source and drain 9 are located in the source and drain).
  • the first lead electrode 11 is located on the side of the source and drain insulating layer 10 facing the organic insulating layer 12; in other words, the source and drain electrodes 9 are formed on the source and drain insulating layer 10
  • the side of the layer 10 away from the first extraction electrode 11 is separated from the first extraction electrode 11 by the source and drain insulating layer 10), the driving electrode 18 and the second extraction electrode 15 are arranged on different layers (that is, the driving electrode 18 is arranged On the piezoelectric film layer 17, the second lead electrode 15 is arranged on the side of the first insulating layer 16 away from the piezoelectric film layer).
  • each source and drain 9 and the driving electrode 18 can be provided with its lead electrode, or part of the source and drain 9 and the drive electrode 18 can be provided with lead electrodes.
  • a backing layer 19 is provided on the side of the driving electrode 18 facing away from the piezoelectric film layer 17.
  • a backing layer 19 is provided on the side of the driving electrode 18 away from the piezoelectric film layer 17.
  • the density of the material forming the backing layer is greater than that of the driving electrode, making the vibration Most of the ultrasonic waves generated by the piezoelectric film 17 can be reflected toward the flat layer 8 through the backing layer 19, which improves the accuracy of fingerprint recognition.
  • the backing layer 19 is formed of metal.
  • the density of the metal forming the backing layer 19 is higher than the density of the material forming the driving electrode 18.
  • the high-density metal may be metals such as silver and copper.
  • the backing layer 19 can increase the strength of the entire ultrasonic fingerprint identification device, thereby allowing application to the display panel without using a too thick supporting substrate.
  • the receiving electrode 14 and the second extraction electrode 15 are spaced apart from each other, and both are disposed on the first insulating layer 16 in the same layer. Such an arrangement method can save space and the thickness of the fingerprint identification device compared to the manner in which the receiving electrode 14 and the second extraction electrode 15 are respectively arranged on different layers. It should be noted that the first extraction electrode 11 is connected to the receiving electrode 14 through a fourth via 24 for collecting the voltage signal of the receiving electrode 14 to form a fingerprint image.
  • an inorganic insulating layer 13 is provided between the organic insulating layer 12 and the first insulating layer 16. In this way, it is prevented that when the receiving electrode 14 and the organic insulating layer 12 are arranged in close proximity, the organic insulating layer 12 itself adsorbs impurities or absorbs water to cause adverse effects on the metal electrode.
  • the ultrasonic fingerprint identification device further includes a substrate 1, and the substrate 1 is a flexible substrate.
  • the flexible substrate is thinner than the traditional glass substrate, so it is ultra-thin without increasing the process such as the thinning process of the glass substrate.
  • the ultrasonic fingerprint recognition device may be an ultrasonic fingerprint recognition panel.
  • the circuit layer of the ultrasonic fingerprint identification device may include a plurality of thin film transistors, which receive electrical signals in order to construct the information of the electrical signal response; the circuit layer may also control the circuit layer and the like for controlling the ultrasonic fingerprint identification device operating.
  • the circuit layer may be a CMOS circuit layer, an NMOS circuit layer, or a PMOS circuit layer.
  • the circuit layer may include an active layer 29, which may be composed of low-temperature polysilicon, and the active layer 29 is disposed on the side of the gate insulating layer 4 away from the gate 5, and A third via hole 23 is provided between the source layer 29 and the source and drain electrodes 9.
  • the third via hole 23 and the first via hole 21 are in a direction substantially perpendicular to the active layer 29 (or substantially perpendicular to the substrate 1). It is advantageous to align the third via 23 and the first via 21 in a straight line, which can save space.
  • the third via 23 and the first via 21 may not be aligned, which is particularly advantageous when the thickness of the insulating layer is large, because the alignment increases the complexity of the process and reduces The reliability of the device; at this time, the first via 21 can be aligned with the source and drain to achieve electrical connection. This configuration reduces the process complexity and improves the reliability of the electrical connection. It is easy to realize the close arrangement of the switching transistors, and more switching transistors can be arranged in the same space.
  • a buffer layer 2 is provided between the substrate 1 and the active layer 29.
  • a protective layer 20 is provided on the side of the backing layer 19 facing away from the driving electrode 18.
  • the first extraction electrode 11 is symmetrically arranged with the first via hole 21 as the center.
  • the symmetrical arrangement can simplify the positioning process of the patterned lead electrode.
  • the thickness of the organic insulating layer 12 is greater than the thickness of the source-drain insulating layer 10.
  • Increasing the thickness of the organic insulating layer 12 can increase the distance between the receiving electrode 14 and the source drain 9 and reduce the capacitance value of the parallel plate capacitor formed between the receiving electrode 14 and the source drain 9.
  • the capacitance value of the parallel plate capacitor is proportional to the dielectric constant and inversely proportional to the distance. Therefore, using the organic insulating layer 12 with a smaller dielectric constant and increasing its thickness will reduce the capacitance value of the parallel plate capacitor.
  • the capacitance value of the parallel plate capacitance formed between the receiving electrode 14 and the source and drain 9 can be reduced to below a desired value, without affecting the ultrasonic fingerprint identification device to sense fingerprints.
  • the circuit layer includes a first thin film transistor, and the active layer 29 of the first thin film transistor is sequentially arranged with N in the direction parallel to the substrate (in the direction parallel to the substrate).
  • Type heavily doped area 6 N type lightly doped area 7, polysilicon area 3, N type lightly doped area 7, and N type heavily doped area 6.
  • the difference between the PMOS-based ultrasonic fingerprint identification device and the NMOS-based ultrasonic fingerprint identification device shown in FIG. 2 lies in the active layer 30.
  • the circuit layer of the PMOS ultrasonic fingerprint identification device includes a second thin film transistor.
  • the active layer 30 of the second thin film transistor (in the direction parallel to the substrate) is sequentially provided with a P-type heavily doped region 26, a polysilicon region 25, and a P-type heavy Doped region 26.
  • the circuit layer includes a first thin film transistor and a second thin film transistor, wherein the active layer 29 of the first thin film transistor is sequentially arranged with N-type transistors in a direction parallel to the substrate (in the direction parallel to the substrate).
  • a P-type heavily doped region 26, a polysilicon region 25, and a P-type heavily doped region 26 are sequentially arranged.
  • the present disclosure also discloses a display device, which includes the ultrasonic fingerprint identification device provided by each embodiment of the present disclosure and a display panel attached to the ultrasonic fingerprint identification device.
  • the display panel has a flexible base substrate.
  • the display panel and the laminated ultrasonic fingerprint identification device both use flexible substrates, an ultra-thin and bendable effect can be obtained.
  • the driving electrode 18 applies a driving voltage, so that the piezoelectric film layer 17 generates ultrasonic waves under the inverse piezoelectric effect.
  • the finger touches or approaches the substrate 1 the ultrasonic wave propagates to the finger and is reflected by the finger.
  • the ridges and valleys of the fingerprint of the finger reflect the sound wave energy differently, so when the sound waves reflected by the fingerprint ridges and valleys respectively propagate to the piezoelectric film layer 17, different electrical signals are generated due to the piezoelectric effect, and these electrical signals are Receive and recognize fingerprints.
  • the present disclosure also discloses a manufacturing method of the ultrasonic fingerprint identification device.
  • the manufacturing method of an NMOS-based ultrasonic fingerprint identification device includes the following steps:
  • Step S1 forming a flexible substrate 1 on a glass substrate.
  • Step S2 The buffer layer 2 is formed, which can be formed by coating, chemical vapor deposition (CVD, Chemical Vapor Deposition), and plasma chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition).
  • CVD chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • Step S3 forming an active layer 29, which is a polysilicon film
  • Step S4 Perform ion implantation of TFT Vth to adjust the threshold voltage Vth;
  • Step S5 forming the gate insulating layer 4, which can be formed by coating, chemical vapor deposition (CVD, Chemical Vapor Deposition), and plasma chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition);
  • CVD chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • Step S6 the gate 5 is patterned and formed, and the gate 5 can be formed by a physical vapor deposition method, and then the required pattern is formed through a process of exposure and wet etching;
  • Step S7 Perform N-type heavily doped ion implantation to form an N-type heavily doped region 6 in the active layer;
  • Step S8 Perform N-type lightly doped ion implantation to form an N-type lightly doped region 7 in the active layer;
  • Step S9 forming a flat layer and a via connected to the N-type heavily doped region 6 so as to be electrically connected to the source and drain 9;
  • Step S10 the source and drain electrodes 9 are patterned, and the gate electrode 5 can be formed by physical vapor deposition, and then the required pattern is formed through a process of exposure and wet etching;
  • Step S11 forming a source-drain insulating layer 10 and a via hole connected to the source and drain electrode 9 so as to be connected to the first lead electrode 11 through the via hole;
  • Step S12 patterning to form the first extraction electrode 11, a physical vapor deposition method may be used to form a gate, and then a desired pattern is formed through a process of exposure and wet etching;
  • Step S13 forming an organic insulating layer 12 and a via hole connected to the first lead electrode 11, through which the source and drain electrodes 9 are electrically connected to the receiving electrode; it can be understood that not every source and drain 9 All the lead electrodes 11 need to be electrically connected to the receiving electrode 14, but a connection via is formed at the position of the organic insulating layer that needs to be electrically connected to the receiving electrode 14 so that the receiving electrode 14 and the first lead electrode 11 are electrically connected;
  • Step S14 forming an inorganic insulating layer and the extended via hole of the via hole connected to the first lead electrode 11 in step S13, so that the source and drain electrodes 9 are electrically connected to the receiving electrode 14;
  • Step S15 the simultaneous receiving electrode 14 and the second lead electrode 15 are formed by patterning, the electrode layer can be formed by physical vapor deposition, and then the required pattern is formed through the process of exposure and wet etching;
  • Step S16 forming a first insulating layer 16 and a via hole electrically connected to the second extraction electrode 15, and the second extraction electrode 15 is connected to the driving electrode 18 through the via hole;
  • Step S17 patterning to form the piezoelectric film layer 17;
  • Step S18 patterning to form the driving electrode 18, specifically, a physical vapor deposition method may be used to form the driving electrode layer, and then the desired pattern is formed through a process of exposure and wet etching;
  • Step S19 patterning to form a backing layer 19;
  • Step S20 forming a protective layer 20, and peeling off the glass substrate.
  • steps S7 and S8 are different, and the corresponding steps of the manufacturing method of the PMOS-based ultrasonic fingerprint recognition device P-type heavily doped ion implantation is performed for step S27 to form a P-type heavily doped region 26 in the active layer.

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Abstract

本申请公开了一种超声波指纹识别装置及显示装置。超声波指纹识别装置，包括电路层、压电器件层以及设置在两者之间的有机绝缘层。压电器件包括：用于提供驱动电压的驱动电极和接收电极以及两者之间的压电薄膜层，压电薄膜层在驱动电极提供的电信号作用下能够产生超声波，并能够在声波作用下产生反应声波强弱的电信号。超声波指纹识别装置还包括：第一引出电极，第一引出电极设置于有机绝缘层，通过第一过孔与源漏极电连接。

Description

超声波指纹识别装置及显示装置
相关申请的交叉引用
本申请要求于2019年4月24日提交的、名称为“超声波指纹识别面板及显示装置”的中国专利申请No.201910337453.6的优先权，该专利申请的公开内容通过引用方式整体并入本文。
技术领域
本公开一般涉及指纹识别传感器领域，尤其涉及超声波指纹识别装置及显示装置。
背景技术
现有的超声波指纹识别器件有以硅晶圆为衬底的半导体工艺制备的超声波指纹识别器件，还有以玻璃为衬底的低温多晶硅工艺制备的超声波指纹识别器件。然而现有的超声波指纹识别器件性能需要进一步改善以便满足显示面板的发展要求。
发明内容
期望提供一种性能改善的超声波指纹识别装置及显示装置。
一方面，一种超声波指纹识别装置，包括：
包括薄膜晶体管的电路层；
压电器件层，压电器件层包括驱动电极、接收电极以及所述驱动电极和所述接收电极之间的压电薄膜层；以及
有机绝缘层，设置在所述电路层和所述压电器件层之间；以及
第一引出电极，所述第一引出电极设置于所述有机绝缘层的远离压电器件层一侧，第一引出电极通过穿过电路层的源漏极绝缘层的第一过孔与电路层中的薄膜晶体管的源漏极电连接，同时第一引出电极与所述接收电极电连接。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括第二引出电极，所述第二引出电极在压电薄膜层的与驱动电极相对的一侧并通过穿过压电薄膜层的第二过孔或驱动电极的延伸部分与所述驱动 电极电连接。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括第一绝缘层，设置于有机绝缘层和压电薄膜层之间，所述接收电极和所述第二引出电极设置于第一绝缘层远离压电薄膜层的一侧。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括无机绝缘层，设置在有机绝缘层和接收电极之间。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括背衬层，所述背衬层设置在所述驱动电极的背离所述压电薄膜层的一侧，形成背衬层的材料的密度比驱动电极的材料密度大。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括保护层，设置在背衬层的背离驱动电极的一侧。
在本公开的一个或多个实施例中，所述接收电极与所述第二引出电极同层且相互间隔开。
在本公开的一个或多个实施例中，超声波指纹识别装置还包括柔性基板。
在本公开的一个或多个实施例中，电路层包括有源层，所述有源层与所述源漏极之间设置有第三过孔以通过第三过孔实现电连接，
其中所述第三过孔与所述第一过孔在垂直于有源层的方向上对准；或，第一过孔与第三过孔在垂直有源层的方向上不对准，第一过孔与源漏极实现电连接。
在本公开的一个或多个实施例中，所述第一引出电极以所述第一过孔为中心对称设置。
在本公开的一个或多个实施例中，电路层包括源漏极绝缘层，源漏极形成在源漏极绝缘层的远离第一引出电极的一侧以便通过源漏极绝缘层与第一引出电极隔开；
其中，所述有机绝缘层的厚度配置成大于所述源漏极绝缘层的厚度，并且能够将接收电极与源漏极之间的电容减小至期望值以下。
在本公开的一个或多个实施例中，电路层包括：
第一薄膜晶体管，所述第一薄膜晶体管的有源层依次包括N型重掺杂区、N型轻掺杂区、多晶硅区、N型轻掺杂区、N型重掺杂区；和 /或
第二薄膜晶体管，所述第二薄膜晶体管的有源层依次包括P型重掺杂区、多晶硅区、P型重掺杂区。
在本公开的一个或多个实施例中，背衬层是金属层。
本公开的第二方面，提供一种显示装置，包括本公开各实施例所提供的超声波指纹识别装置和与其贴合的显示面板。
在本公开的一个或多个实施例中，显示面板具有柔性衬底基板。
本公开的第三方面，提供一种制造上述的显示超声波指纹识别装置的方法，所述方法包括：
提供支撑基板，在支撑基板上形成柔性基板；
在柔性基板上逐一地形成包括薄膜晶体管的电路层、有机绝缘层以及压电器件层；
其中，压电器件包括：驱动电极、接收电极以及所述驱动电极和所述接收电极之间的压电薄膜层；和
其中，超声波指纹识别装置还包括：
第一引出电极，所述第一引出电极设置于所述有机绝缘层的远离压电器件层一侧，通过第一过孔与所述接收电极电连接，并且与电路层的源漏极电连接。
在一个实施例中，方法还包括：在形成接收电极时，通过图案化同时形成第二引出电极，所述第二引出电极在压电薄膜层的与驱动电极相对的一侧并通过第二过孔与所述驱动电极电连接。
在一个实施例中，方法还包括：在压电器件层上形成背衬层。
在一个实施例中，方法还包括：剥离支撑基板。
根据本公开实施例提供的技术方案，通过在不同层分别设置多个引出电极，能够降低大尺寸引起的周边电路的走线密集度。进一步的，根据本公开的某些实施例，通过采用柔性基板，还能减少整个指纹识别装置的厚度，获得超薄和可弯曲的效果。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描 述，本公开的其它特征、目的和优点将会变得更明显：
图1示出了根据本公开实施例的基于NMOS的超声波指纹识别装置的示例性结构框图；
图2示出了根据本公开另一实施例的基于PMOS的超声波指纹识别装置的示例性结构框图；
图3示出了根据本公开实施例的基于NMOS的超声波指纹识别装置制造方法的示例性流程图；
图4示出了根据本公开另一实施例的基于PMOS的超声波指纹识别装置制造方法的示例性流程图。
[根据细则26改正10.04.2020]　
图5示出了根据本公开实施例的形成接收电极和引出电极的示例性过程图。
[根据细则26改正10.04.2020]　
图6示出了根据本公开实施例的形成接收电极和引出电极的示例性过程图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
由于相关领域的超声波指纹识别器件的衬底厚(即使玻璃衬底通过减薄工艺厚度在0.1mm左右)，因而衬底减薄工艺损失了良率，并且导致超声波指纹识别器件与显示屏盖板玻璃贴合时占用的空间大，使得产品厚度变大；使用刚性衬底，不适合与超薄柔性的显示屏进行贴合，产品不适用于生成大尺寸面板。
本公开的实施例提供一种超声波指纹识别装置，包括：包括薄膜晶体管的电路层；压电器件层；以及设置在两者之间的有机绝缘层12。
在本实施例中，压电器件包括：用于提供驱动电压的驱动电极18和接收电极14以及两者之间的压电薄膜层17，压电薄膜层17在驱动电极18提供的电信号作用下能够产生超声波，并能够在声波作用下产生反应声波强弱的电信号。在本实施例中，超声波指纹识别装置还包括：第一引出电极11，所述第一引出电极11设置于所述有机绝缘层12 的远离压电器件层17一侧，通过穿过电路层的源漏极绝缘层10的第一过孔21与电路层中的薄膜晶体管的源漏极9电连接。
在一个实施例中，超声波指纹识别装置还可以包括第二引出电极15，所述第二引出电极15在压电薄膜层17的与驱动电极18相对的一侧并通过穿过压电薄膜层的第二过孔22与所述驱动电极18电连接。在零一实施例中，第二引出电极15通过驱动电极的延伸部分与所述驱动电极电连接。
在一个实施例中，例如图5所示，通过图案化导电层形成接收电极14和第二引出电极15，随后，覆盖(第一绝缘层16和)用于压电薄膜层17的压电材料层，对压电材料层图案化处理形成压电薄膜层17的图案，压电薄膜层17的图案包括压电薄膜层17和露出接收电极15和第二引出电极16的第二过孔22，再在压电薄膜层17的图案上形成用于驱动电极18的导电材料层，在此过程中用于驱动电极18的导电材料填充第二过孔22中，由此在压电薄膜层上形成驱动电极18，并且在压电薄膜层图案中的露出驱动电极17和第二引出电极15的第二过孔22中形成电连接。
在一个实施例中，例如图6所示，与图5的实施例不同的是，在接收电极14和第二引出电极15上直接形成压电薄膜层17的图案，压电薄膜层17的图案包括压电薄膜层17和露出接收电极和第二引出电极的开口部分，压电薄膜层覆盖接收电极14(接收电极14上可以覆盖了第一绝缘层16)；再在压电薄膜层17的图案上形成用于驱动电极18的导电材料层，以便在压电薄膜层上形成驱动电极，并且在此过程中用于驱动电极18的导电材料填充压电薄膜层17的图案中的露出驱动电极和第二引出电极的开口部分从而形成驱动电极延伸部分。
在一个实施例中，第二引出电极15可以驱动电极的延伸部分电连接。根据本实施例，可以通过形成导电膜和图案化工艺一次形成接收电极14和第二引出电极15，随后形成具有图案的压电薄膜层，也即压电薄膜层的图案具有预留的部分暴露第二引出电极15，在随后形成驱动电极18时，形成驱动电极18的导电材料同时形成驱动电极18和驱动电极的延伸部分，类似图1和图2中示出的穿过第二过孔的部分。这是有利的，可以 不用在压电薄膜层上刻蚀第二过孔。
在本实施例中，压电器件由驱动电极18、接收电极14以及两者之间的(压电材料形成的)压电薄膜层17形成。驱动电极18可以电连接电源，提供交变电信号，从而使得压电材料由于逆压电效应而产生声波。压电薄膜层17还能够在声波作用下产生电信号，压电薄膜层17的电信号通过接收电极14接收，并传递给电路层的源漏极9，最终电路层可以基于接收电极14的电信号构建声波反应的形状，例如手指的指纹。
在大面积的面板中，与源漏电极9电连接的引线较多，并且这些引线可能需要避开像素电极对应的位置以避免影响开口率，因而用于布置这些引线的空间受到限制，导致在一层上布置这些引线(例如信号线)在空间上非常拥挤或不足，本实施例设置第一引出电极11，使得用于信号传输的一部分引线可以在第一引出电极11所在层(例如有机绝缘层12)上布置，因而获得足够的空间用于布置这些引线，因而可以解决大面积显示面板或设备应用中的用于超声波指纹识别装置的引线布置的空间不足的问题。在本实施例中，由于有机绝缘层12厚度增大，还可以使得整个超声波指纹识别装置的强度得以增大，因而使得本实施例的超声波指纹识别装置适于应用于大面积的面板；此外，由于有机绝缘层的厚度较大，因而过孔的深度较大，导致经由过孔的电连接可靠性不足，本实施例的第一引出电极11使得过孔中的电连接的可靠性提高；有机绝缘层的厚度增大可以减小接收电极和第一引出电极、源漏极之间的寄生电容。
在本实施例中，压电器件层的驱动电极19厚度大，本身在实际应用中不适于制作引线，因而设置第二引出电极15作为驱动电极19的引线。
在压电器件中，还可以包括第一绝缘层16，设置于有机绝缘层12和压电薄膜层17之间，所述接收电极14和所述第二引出电极15设置于第一绝缘层16的远离压电薄膜层一侧。
在有机绝缘层12和第一绝缘层16之间，还可以设置无机绝缘层12，可以阻挡有机绝缘层12的材料对接收电极14的材料性质的干扰。
图1示出一种具体实施例的结构，然而，应该理解图1中的部件并非全部都是必须的。一种超声波指纹识别装置，包括依次设置的栅极绝缘层4、栅极5、平坦层8、源漏极9、源漏极绝缘层10、有机绝缘层12、接收电极14、第一绝缘层16、压电薄膜层17、驱动电极18，还包括：
第一引出电极11，第一引出电极11设置于有机绝缘层12，通过第一过孔21与源漏极9电连接；
第二引出电极15，第二引出电极15设置于第一绝缘层16，通过第二过孔22与驱动电极18电连接。
通过给源漏极9和驱动电极18分别设置第一引出电极11和第二引出电极15，且源漏极9和第一引出电极11分别在不同的层(即，源漏极9位于源漏极绝缘层10的远离有机绝缘层12的一侧，第一引出电极11位于源漏极绝缘层10的朝向有机绝缘层12的一侧；换句话说，源漏极9形成在源漏极绝缘层10的远离第一引出电极11的一侧以便通过源漏极绝缘层10与第一引出电极11隔开)，驱动电极18和第二引出电极15设置在不同的层(即驱动电极18设置于压电薄膜层17上，第二引出电极15设置于第一绝缘层16的远离压电薄膜层的一侧)。这样的设置能够实现在周边电路上形成多层布设的数据走线，有利于形成大尺寸的指纹识别装置。
可以理解的是，根据实际应用场景给每个源漏极9和驱动电极18都可以设置其引出电极，或者给部分源漏极9和驱动电极18设置引出电极。
在一些实施例中，驱动电极18背离压电薄膜层17的一侧设置有背衬层19。在声波领域，两种介质的声阻差越大，其介质的质量差越大，同时声速变化越大。声阻抗差越大，声子的惯性越大，惯性越大给超声波反射创造了能量条件，所以，两种介质的声阻抗差越大，超声波反射能力越大。其中，声阻抗为：
声阻抗＝密度×介质中的声速
显然，声阻抗与密度成正比，因此在驱动电极18的背离压电薄膜层17的一侧设置有背衬层19，形成背衬层的材料的密度比驱动电极 的材料密度大，使得振动中的压电薄膜17产生的超声波能够通过背衬层19大部分反射至朝向平坦层8的方向，提高了指纹识别的精度。背衬层19由金属形成，例如形成背衬层19的金属的密度比形成驱动电极18的材料的密度高。高密度金属可以是例如银、铜等金属。背衬层19可以提高整个超声波指纹识别装置的强度，从而允许在不使用太厚的支撑衬底的情况下应用至显示面板。
在一些实施例中，接收电极14与第二引出电极15相互间隔开，两者并同层设置于第一绝缘层16。这样的设置方式，相对接收电极14与第二引出电极15分别设置于不同层的方式而言，能够节省空间和指纹识别装置的厚度。需要说明的是，第一引出电极11与该接收电极14通过第四过孔24连接，用于采集接收电极14的电压信号，以形成指纹图像。
在一些实施例中，有机绝缘层12与第一绝缘层16之间设置有无机绝缘层13。这样，防止了接收电极14与有机绝缘层12紧邻设置时，有机绝缘层12自身吸附杂质或吸水性所带来的对金属电极的不良影响。
在一些实施例中，超声波指纹识别装置还包括基板1，基板1为柔性基板。柔性基板相对传统的玻璃基板而言较薄，因此在不增加工艺例如玻璃基板的减薄工艺的基础上实现了超薄。在此实施例中，超声波指纹识别装置可以是超声波指纹识别面板。
在一些实施例中，超声波指纹识别装置的电路层可以包括多个薄膜晶体管，这些薄膜晶体管接收电信号以便构建电信号反应的信息；电路层还可以控制电路层等用于控制超声波指纹识别装置的操作。电路层可以是CMOS电路层、NMOS电路层或PMOS电路层。在如图1所示的具体实施例中，电路层可以包括有源层29，有源层可以由低温多晶硅构成，有源层29设置于栅极绝缘层4背离栅极5的一侧，有源层29与源漏极9之间设置有第三过孔23，第三过孔23和第一过孔21在大体垂直于有源层29的方向(或者说，与基板1大体垂直)上对准成一条线上，这是有利的，因而第三过孔23和第一过孔21对准在一条直线方向上可以节省空间。然而，根据本公开的零一实施例，第三 过孔23和第一过过孔21可以不对准，这在绝缘层厚度大的情况下尤其有利，因为对准增加工艺的复杂性，降低了器件的可靠性；此时，第一过孔21可以对准源漏极实现电连接即可，这样的配置降低了工艺复杂度，提高了电连接的可靠性。使得易于实现开关晶体管的紧密设置，在相同的空间能够设置更多的开关晶体管。
在一些实施例中，为了增加缓冲效果，在基板1与有源层29之间设置有缓冲层2。在一些实施例中，在背衬层19背离驱动电极18的一侧设置保护层20。
在一些实施例中，第一引出电极11以第一过孔21为中心对称设置。对称设置的方式能够简化图案化引出电极的定位工序。
在一些实施例中，有机绝缘层12的厚度大于源漏极绝缘层10的厚度。增加有机绝缘层12厚度，能够增加接收电极14与源漏极9之间的距离，减少了接收电极14与源漏极9之间形成的平行板电容的电容值。具体地，平行板电容的电容值与介电常数成正比，与距离成反比。因此，采用介电常数较小的有机绝缘层12，并增加其厚度，将减小该平行板电容的电容值。例如，可以将接收电极14与源漏极9之间形成的平行板电容的电容值减小至期望值以下，不影响超声波指纹识别装置感测指纹。
在图1示出的NMOS的超声波指纹识别装置中，其中电路层包括第一薄膜晶体管，第一薄膜晶体管的有源层29在平行于基板的方向(在平行于基板方向)上依次设置有N型重掺杂区6、N型轻掺杂区7、多晶硅区3、N型轻掺杂区7、N型重掺杂区6。
如图2所示的基于PMOS的超声波指纹识别装置与基于NMOS的超声波指纹识别装置区别在于有源层30。PMOS的超声波指纹识别装置的电路层包括第二薄膜晶体管，第二薄膜晶体管的有源层30(在平行于基板方向上)依次设置有P型重掺杂区26、多晶硅区25、P型重掺杂区26。
本公开的一个实施例中，电路层包括第一薄膜晶体管和第二薄膜晶体管，其中第一薄膜晶体管的有源层29在平行于基板的方向(在平行于基板方向)上依次设置有N型重掺杂区6、N型轻掺杂区7、多晶 硅区3、N型轻掺杂区7、N型重掺杂区6；第二薄膜晶体管的有源层30(在平行于基板方向上)依次设置有P型重掺杂区26、多晶硅区25、P型重掺杂区26。
本公开还公开一种显示装置，该显示装置包括本公开各实施例所提供的的超声波指纹识别装置和与其贴合的显示面板。
在一些实施例中，显示面板具有柔性衬底基板。当显示面板和贴合的超声波指纹识别装置均采用柔性基板时，能够获得超薄可弯曲的效果。
在使用过程中，驱动电极18施加驱动电压，使得压电薄膜层17在逆压电效应下产生超声波，当手指触摸或靠近基底1时，超声波传播至手指，并被手指反射。手指的指纹的脊和谷对声波能量的反射不同，因而分别被指纹的脊和谷反射的声波传播至压电薄膜层17时，由于压电效应会产生不同的电信号，这些电信号被电路接收而辨识指纹。
本公开还公开了一种超声波指纹识别装置的制造方法。如图3所示，基于NMOS的超声波指纹识别装置的制造方法包括如下步骤：
步骤S1：在玻璃基底上，形成柔性基板1。
步骤S2：形成缓冲层2，可采用涂布、化学气相沉积(CVD，Chemical Vapor Deposition)、等离子体化学气相沉积(PECVD，Plasma Enhanced Chemical Vapor Deposition)方式形成。
步骤S3：形成有源层29，该有源层29为多晶硅薄膜；
步骤S4：进行TFT Vth的离子注入，以调整阈值电压Vth；
步骤S5：形成栅极绝缘层4，可采用涂布、化学气相沉积(CVD，Chemical Vapor Deposition)、等离子体化学气相沉积(PECVD，Plasma Enhanced Chemical Vapor Deposition)方式形成；
步骤S6：图案化形成栅极5，可采用物理气相沉积法形成栅极5，再经过曝光显示湿刻的工艺形成所需图案；
步骤S7：进行N型重掺杂离子注入，以在有源层形成N型重掺杂区6；
步骤S8：进行N型轻掺杂离子注入，以在有源层形成N型轻掺杂区7；
步骤S9：形成平坦层以及与N型重掺杂区6相连的过孔，以便与源漏极9电连接；
步骤S10：图案化形成源漏极9，可采用物理气相沉积法形成栅极5，再经过曝光显示湿刻的工艺形成所需图案；
步骤S11：形成源漏极绝缘层10及与源漏极9相连的过孔，以便通过该过孔与第一引出电极11连接；
步骤S12：图案化形成第一引出电极11，可采用物理气相沉积法形成栅极，再经过曝光显示湿刻的工艺形成所需图案；
步骤S13：形成有机绝缘层12及与第一引出电极11连接的过孔，通过该过孔源漏极9与接收电极电连接；可以理解的是，并不是每个源漏极9的第一引出电极11都需要与接收电极14电连接，而是在该有机绝缘层的需要与接收电极14电连接的位置形成连接过孔以便接收电极14与第一引出电极11形成电连接；
步骤S14：形成无机绝缘层及步骤S13中与第一引出电极11连接的过孔的延长过孔，使得源漏极9与接收电极14电连接；
步骤S15：图案化形成同时接收电极14及第二引出电极15，可采用物理气相沉积法形成电极层，再经过曝光显示湿刻的工艺形成所需图案；
步骤S16：形成第一绝缘层16及与第二引出电极15电连接的过孔，通过该过孔第二引出电极15与驱动电极18连接；
步骤S17：图案化形成压电薄膜层17；
步骤S18：图案化形成驱动电极18，具体地可采用物理气相沉积法形成驱动电极层，再经过曝光显示湿刻的工艺形成所需图案；
步骤S19：图案化形成背衬层19；
步骤S20：形成保护层20，剥离玻璃基板。
如图4所示的基于PMOS的超声波指纹识别装置的制造方法与基于NMOS的超声波指纹识别装置的制造方法区别在于，步骤S7和步骤S8不同，基于PMOS的超声波指纹识别装置的制造方法的对应步骤为步骤S27进行P型重掺杂离子注入，在有源层形成P型重掺杂区26。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说 明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (14)

  1. 一种超声波指纹识别装置，包括：
    电路层，包括薄膜晶体管；
    压电器件层，压电器件层包括驱动电极、接收电极以及所述驱动电极和所述接收电极之间的压电薄膜层；
    有机绝缘层，设置在所述电路层和所述压电器件层之间；和
    第一引出电极，所述第一引出电极设置于所述有机绝缘层的远离压电器件层一侧，第一引出电极通过穿过电路层的源漏极绝缘层的第一过孔与电路层中的薄膜晶体管的源漏极电连接，同时第一引出电极与所述接收电极电连接。
  2. 根据权利要求1所述的超声波指纹识别装置，还包括：第二引出电极，所述第二引出电极在压电薄膜层的与驱动电极相对的一侧并通过穿过压电薄膜层的第二过孔或驱动电极的延伸部分与所述驱动电极电连接。
  3. 根据权利要求1所述的超声波指纹识别装置，还包括：第一绝缘层，设置于有机绝缘层和压电薄膜层之间，所述接收电极和所述第二引出电极设置于第一绝缘层地远离压电薄膜层的一侧。
  4. 根据权利要求1所述的超声波指纹识别装置，还包括：无机绝缘层，设置在有机绝缘层和接收电极之间。
  5. 根据权利要求1所述的超声波指纹识别装置，其中，超声波指纹识别装置还包括背衬层，所述背衬层设置在所述驱动电极的背离所述压电薄膜层的一侧，形成背衬层的材料的密度比驱动电极的材料密度大。
  6. 根据权利要求5所述的超声波指纹识别装置，还包括保护层，设置在背衬层的背离驱动电极的一侧。
  7. 根据权利要求2所述的超声波指纹识别装置，其中，所述接收电极与所述第二引出电极同层且相互间隔开。
  8. 根据权利要求1所述的超声波指纹识别装置，其中，还包括柔性基板。
  9. 根据权利要求1所述的超声波指纹识别装置，其中，电路层包 括有源层，所述有源层与所述源漏极之间设置有第三过孔以实现电连接，
    其中所述第三过孔与所述第一过孔在垂直于有源层的方向上对准；或，第一过孔与第三过孔在垂直有源层的方向上不对准，第一过孔与源漏极实现电连接。
  10. 根据权利要求1所述的超声波指纹识别装置，其中，电路层包括源漏极绝缘层，源漏极形成在源漏极绝缘层的远离第一引出电极的一侧以便通过源漏极绝缘层与第一引出电极隔开；
    其中，所述有机绝缘层的厚度配置成大于所述源漏极绝缘层的厚度，并且能够将接收电极与源漏极之间的电容减小至期望值以下。
  11. 根据权利要求1所述的超声波指纹识别装置，其中电路层包括：
    第一薄膜晶体管，所述第一薄膜晶体管的有源层依次包括N型重掺杂区、N型轻掺杂区、多晶硅区、N型轻掺杂区、N型重掺杂区；和/或
    第二薄膜晶体管，所述第二薄膜晶体管的有源层依次包括P型重掺杂区、多晶硅区、P型重掺杂区。
  12. 根据权利要求5所述的超声波指纹识别装置，其中，背衬层是金属层。
  13. 一种显示装置，其中，包括权利要求1-12任一所述的超声波指纹识别装置和与其贴合的显示面板。
  14. 根据权利要求13所述的显示装置，其中，所述显示面板具有柔性衬底基板。
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