WO2020211604A1 - 数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置 - Google Patents

数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置 Download PDF

Info

Publication number
WO2020211604A1
WO2020211604A1 PCT/CN2020/080909 CN2020080909W WO2020211604A1 WO 2020211604 A1 WO2020211604 A1 WO 2020211604A1 CN 2020080909 W CN2020080909 W CN 2020080909W WO 2020211604 A1 WO2020211604 A1 WO 2020211604A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
signal
circuit
sub
terminal
Prior art date
Application number
PCT/CN2020/080909
Other languages
English (en)
French (fr)
Inventor
张舜航
廖峰
张慧
贾玉娥
刘立伟
侯凯
王洪润
袁丽君
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020211604A1 publication Critical patent/WO2020211604A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a data latch circuit and driving method, a data latch and driving method, and a display device.
  • display devices such as desktop display products, electronic equipment, and wearable display devices have been widely used, and the power consumption of display devices has always been concerned by consumers.
  • the MIP circuit mainly uses SPI (Serial Peripheral Interface) technology to reduce power consumption.
  • SPI Serial Peripheral Interface
  • the Source IC (source driver circuit) part is built on the array substrate (Array). All data signals are transmitted by one data signal terminal. In this way, the cost of IC (Integrated Circuit, integrated circuit) can be reduced, and power consumption can be reduced.
  • a data latch circuit in one aspect, includes a selection sub-circuit, a first control sub-circuit, a latch sub-circuit and a second control sub-circuit.
  • the selection sub-circuit is coupled to a first data signal terminal, a second data signal terminal and a clock pulse signal terminal; the selection sub-circuit is configured to be controlled by a signal received at the clock pulse signal terminal under different In the time period, the data signal received at the first data signal terminal and the data signal received at the second data signal terminal are transmitted.
  • the first control sub-circuit is coupled to the selection sub-circuit and the first control signal terminal; the first control sub-circuit is configured to transmit data from the first control signal terminal under the control of the signal received at the first control signal terminal The data signal of the selection sub-circuit.
  • the latch sub-circuit is coupled to the first control sub-circuit and the first voltage terminal; the latch sub-circuit is configured to receive a data signal from the first control sub-circuit, and the first control sub-circuit The data signal is latched under the action of the voltage at the voltage terminal.
  • the second control sub-circuit is coupled to the latch sub-circuit, the second control signal terminal and the signal output terminal; the second control sub-circuit is configured to be the signal received at the second control signal terminal Under control, the data signal latched in the latch sub-circuit is transmitted to the signal output terminal.
  • the selection sub-circuit includes a multiplexer.
  • the channel selection signal end of the multiplexer is coupled to the clock pulse signal end, the first input end of the multiplexer is coupled to the first data signal end, and the multiplexer
  • the second input terminal is coupled to the second data signal terminal, and the output terminal of the multiplexer is coupled to the first control sub-circuit.
  • the first control sub-circuit includes a first transmission gate sub-circuit.
  • the control terminal of the first transmission gate sub-circuit is coupled to the first control signal terminal, the input terminal of the first transmission gate sub-circuit is coupled to the selector sub-circuit, and the output terminal of the first transmission gate sub-circuit is Coupled with the latch sub-circuit.
  • the latch sub-circuit includes a NAND gate and an inverter.
  • the first input terminal of the NAND gate is coupled to the first control sub-circuit, the second input terminal of the NAND gate is coupled to the first voltage terminal, and the output terminal of the NAND gate is coupled to The circuit of the second control sub-circuit is coupled; the input end of the inverter is coupled to the output end of the NAND gate and the second control sub-circuit, and the output end of the inverter is coupled to the The first input terminal of the NAND gate is coupled.
  • the second control sub-circuit includes a second transmission gate sub-circuit.
  • the control terminal of the second transmission gate sub-circuit is coupled to the second control signal terminal, the input terminal of the second transmission gate sub-circuit is coupled to the latch sub-circuit, and the output of the second transmission gate sub-circuit is The terminal is coupled to the signal output terminal.
  • the data latch circuit further includes an amplifier.
  • the amplifier is coupled to the second control sub-circuit and the signal output terminal; the amplifier is configured to amplify the signal from the second control sub-circuit and transmit the amplified signal to all The signal output terminal.
  • the data latch includes: N data latch circuits as described in any of the foregoing embodiments; wherein, N is an even number greater than 2.
  • the different data latch circuits are coupled to different clock pulse signal terminals and are coupled to different first control signal terminals.
  • the N data latch circuits are coupled to the same first data signal terminal.
  • the N data latch circuits are coupled to the same second data signal terminal.
  • the N data latch circuits are coupled to the same second control signal terminal.
  • N is 6 or 8.
  • a display device in another aspect, includes: the data latch as described in any of the foregoing embodiments.
  • the display device further includes a plurality of data lines.
  • the multiple data lines are divided into multiple groups, each group includes N data lines, and the N data lines included in each group are respectively coupled to the signal output terminals of the N data latch circuits included in the data latch. Pick up.
  • the data latch includes at least 6 data latch circuits.
  • the display device also includes a plurality of pixels arranged in an array, and each column of pixels includes a first color subpixel, a second color subpixel, and a third color subpixel; the first color subpixel and the second color subpixel in the odd-numbered columns are The color sub-pixels and the third color sub-pixels are respectively coupled to the signal output terminals of the three data latch circuits in the data latch through three data lines; The two-color sub-pixel and the third-color sub-pixel are respectively coupled to the signal output ends of the other three data latch circuits in the data latch through three data lines.
  • the data latch includes 8 data latch circuits.
  • Each column of pixels also includes a fourth color sub-pixel; the first-color sub-pixel, the second-color sub-pixel, the third-color sub-pixel, and the fourth-color sub-pixel in the odd-numbered columns pass through 4 data lines to communicate with the data respectively.
  • the signal output ends of the four data latch circuits in the latch are coupled; the first color subpixel, the second color subpixel, the third color subpixel, and the fourth color subpixel in the even-numbered column of pixels pass through four data
  • the lines are respectively coupled to the signal output terminals of the other four data latch circuits in the data latch.
  • a method for driving a data latch circuit as described in any of the above embodiments which includes: under the control of the first signal received at the clock pulse signal end of the selection sub-circuit, the first data signal
  • the data signal received at the terminal is transmitted to the first control sub-circuit, or, under the control of the second signal received at the clock pulse signal terminal, the selection sub-circuit transmits the data signal received at the second data signal terminal to the first Control sub-circuit;
  • the first control sub-circuit transmits the data signal to the latch sub-circuit under the control of the turn-on signal received at the first control signal terminal;
  • the latch sub-circuit is at the first voltage terminal
  • the data signal is latched under the action of the received fixed voltage signal;
  • the second control sub-circuit is latched in all the internal parts of the latch sub-circuit under the control of the open signal received at the second control signal terminal.
  • the data signal is transmitted to the signal output terminal.
  • a method for driving a data latch as described in any of the above embodiments, and the N data latch circuits are divided into two groups.
  • the driving method of the data latch includes: N/2 data latch circuits in the first group sequentially latch the data signal received at the first data signal terminal; in the same time period, N/2 data in the second group The two data latch circuits sequentially latch the data signal received at the second data signal terminal; the N data latch circuits transmit the data signals latched in each to the signal output terminal.
  • the N data latch circuits transmit the data signals latched in each to the signal output terminal, including: the second control signal terminals of the N data latch circuits simultaneously receive the enable signal, and The data signals stored in the respective internals are simultaneously transmitted to the signal output terminal.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • Fig. 2 is a structural diagram of a display panel according to some embodiments.
  • Fig. 3 is a structural diagram of a display device according to the related art
  • FIG. 4 is a driving timing diagram of the data latch in the display device shown in FIG. 3;
  • FIG. 5 is a structural diagram of a data latch circuit according to some embodiments.
  • 6a is a structural diagram of each sub-circuit in the data latch circuit shown in FIG. 5;
  • Fig. 6b is another structural diagram of a data latch circuit according to some embodiments.
  • FIG. 7 is a driving timing diagram of the data latch circuit shown in FIG. 5;
  • FIG. 8 is another structural diagram of a display device according to some embodiments.
  • FIG. 9 is a driving timing diagram of the data latch in the display device shown in FIG. 8;
  • 10 to 14 are diagrams of a driving process of a data latch in a display device according to some embodiments.
  • FIG. 15 is another structural diagram of a display device provided according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • the display device 200' in the related art includes a display panel 10', and the display panel 10' adopts SPI technology.
  • the display panel includes P data lines DL
  • signals are respectively transmitted to the P data lines DL through one data signal terminal SI, and the data signal terminal SI is connected to a plurality of data lines DL through the data latch 30'.
  • the data latch 30' includes 8 data latch circuits LAT (respectively numbered LAT1 to LAT8), the data latch circuit LAT is coupled to the clock pulse signal terminal CP, the clock signal terminal CLK, the data signal terminal SI and the data line DL .
  • the eight data latch circuits LAT are coupled to the same data signal terminal SI and the clock signal terminal CLK, and the eight data latch circuits LAT are respectively coupled to different clock pulse signal terminals CP and data lines DL.
  • the P data lines DL are divided into P/8 groups, and the 8 data lines DL included in each group are respectively coupled to 8 data latch circuits LAT.
  • the data signal terminal SI sequentially outputs the signals on all the data lines DL, the first pulse (a pulse may be, for example, the width of a CLK), the first clock pulse signal terminal CP1 is turned on , The first data latch circuit LAT1 receives the signal of R1 and latches the R1 signal in the first data latch circuit LAT1, and then the first clock pulse signal terminal CP1 is closed.
  • the first pulse a pulse may be, for example, the width of a CLK
  • the first clock pulse signal terminal CP1 is turned on
  • the first data latch circuit LAT1 receives the signal of R1 and latches the R1 signal in the first data latch circuit LAT1, and then the first clock pulse signal terminal CP1 is closed.
  • the second clock pulse signal terminal CP2 is turned on, the second data latch circuit LAT2 receives the G1 signal, and the G1 signal is latched in the second data latch circuit LAT2, and then the second clock pulse signal terminal CP2 is turned off .
  • the third clock pulse signal terminal CP3 is turned on, the third data latch circuit LAT3 receives the signal of B1 and latches the B1 signal in the third data latch circuit LAT3, and then the third clock pulse signal terminal CP3 is turned off .
  • the fourth clock pulse signal terminal CP4 is turned on, the fourth data latch circuit LAT4 receives the signal of D1 and latches the D1 signal in the fourth data latch circuit LAT4, and then the fourth clock pulse signal terminal CP4 is turned off .
  • the fifth clock pulse signal terminal CP5 is turned on, the fifth data latch circuit LAT5 receives the signal of R2, and the R2 signal is latched in the fifth data latch circuit LAT5, and then the fifth clock pulse signal terminal CP5 is turned off .
  • the sixth clock pulse signal terminal CP6 is turned on, the sixth data latch circuit LAT6 receives the G2 signal, and the G2 signal is latched in the sixth data latch circuit LAT6, and then the sixth clock pulse signal terminal CP6 is turned off .
  • the seventh clock pulse signal terminal CP7 is turned on, the seventh data latch circuit LAT7 receives the B2 signal, and the B2 signal is latched in the seventh data latch circuit LAT7, and then the seventh clock pulse signal terminal CP7 is turned off .
  • the eighth clock pulse signal terminal CP8 is turned on, the eighth data latch circuit LAT8 receives the signal of D2, and locks the D2 signal in the eighth data latch circuit LAT8, and then the eighth clock pulse signal terminal CP8 is turned off .
  • the clock signal terminal CLK receives the clock signal at the same time, and simultaneously transmits the data signal latched in the eight data latch circuits LAT to the data line DL coupled to each data latch circuit LAT.
  • one data latch circuit LAT is coupled to a plurality of data lines DL, and each data line DL is coupled to a control unit, and when a certain data line DL receives a data signal, it is coupled to the data line DL The control unit will be turned on. After the control unit is turned on, the data line DL can receive the data signal. Therefore, although one data latch circuit LAT is coupled to a plurality of data lines DL, the data latch circuit LAT transmits a data signal to one of the data lines DL coupled to the data latch circuit LAT.
  • the eight data latch circuits LAT can transmit the data signal to the data line DL after receiving the data signal in sequence. In this way, 8 pulses need to be passed, otherwise the data will be lost and disordered, which results in a lower refresh frequency of the display panel using the SPI technology.
  • the refresh frequency of products using SPI technology is mainly determined by the amount of data transmitted by the data signal terminal. Although a data signal terminal transmits all data signals, although the power consumption can be reduced, the refresh frequency is low, and generally can only reach About 2MHZ, it is difficult to meet user needs.
  • Some embodiments of the present disclosure provide a data latch circuit LAT, as shown in FIG. 5, including: a selection sub-circuit 60, a first control sub-circuit 70, a latch sub-circuit 80, and a second control sub-circuit 90.
  • the selection sub-circuit 60 is coupled to the first data signal terminal SI1, the second data signal terminal SI2 and the clock pulse signal terminal CP.
  • the first control sub-circuit 70 is coupled to the selection sub-circuit 60 and the first control signal terminal CT1.
  • the latch sub-circuit 80 is coupled to the first control sub-circuit 70 and the first voltage terminal V1.
  • the second control sub-circuit 90 is coupled to the latch sub-circuit 80, the second control signal terminal CT2 and the signal output terminal OUT.
  • the selection sub-circuit 60 is configured to transmit the data signal received at the first data signal terminal SI1 and the data signal received at the second data signal terminal SI2 in different time periods under the control of the signal received at the clock pulse signal terminal CP. Data signal.
  • the first control sub-circuit 70 is configured to transmit the data signal from the selection sub-circuit 60 under the control of the signal received at the first control signal terminal CT1.
  • the latch sub-circuit 80 is configured to receive the data signal from the first control sub-circuit 70 and latch the data signal under the action of the voltage of the first voltage terminal V1.
  • the second control sub-circuit 90 is configured to transmit the data signal latched in the latch sub-circuit 80 to the signal output terminal OUT under the control of the signal received at the second control signal terminal CT2.
  • the selection sub-circuit 60 transmits the data signal received at the data signal of the first data signal terminal SI1. In the case that the signal received at the clock pulse signal terminal CP is the second signal, the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2.
  • the selection sub-circuit 60 transmits the data signal to the first control sub-circuit 70.
  • the selection sub-circuit 60 selects and transmits the data signal received at one of the first data signal terminal SI1 and the second data signal terminal SI2, that is, the selection sub-circuit 60 transmits the data signal received at the first data signal terminal SI1.
  • the data signal received at the second data signal terminal SI2 is transmitted.
  • the signal received at the clock pulse signal terminal CP is a high-level signal, that is, when the first signal is a high-level signal, the selection sub-circuit 60 transmits the data received at the first data signal terminal SI1
  • the signal, the signal received at the clock pulse signal terminal CP is a low-level signal, that is, when the second signal is a low-level signal, the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2.
  • the signal received at the clock pulse signal terminal CP is a low-level signal, that is, when the first signal is a low-level signal
  • the selection sub-circuit 60 transmits the data signal received at the first data signal terminal SI1
  • the signal received at the clock pulse signal terminal CP is a high-level signal, that is, when the second signal is a high-level signal
  • the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2.
  • the first control sub-circuit 70 transmits the data signal from the selection sub-circuit 60.
  • the first control sub-circuit 70 stops transmitting the data signal from the selection sub-circuit 60.
  • the first control sub-circuit 70 transmits the data signal from the selection sub-circuit 60 to the latch under the control of the signal received at the first control signal terminal CT1. Sub-circuit 80. In this way, although the selection sub-circuit 60 transmits the data signal to the first control sub-circuit 70, the first control sub-circuit 70 is opened under the control of the signal received at the first control signal terminal CT1, and therefore, the latch sub-circuit 80 It is not always possible to receive the data signal.
  • the first control sub-circuit 70 can be used as a switch to control whether the selection sub-circuit 60 and the latch sub-circuit 80 are connected.
  • the latch sub-circuit 80 receives the data signal from the first control sub-circuit 70, and when the voltage of the first voltage terminal V1 is a fixed voltage, the latch sub-circuit 80 latches the data signal inside the latch sub-circuit 80 .
  • the signal output terminal OUT of the data latch circuit LAT is coupled to the data line DL in the display panel.
  • the second control sub-circuit 90 transmits the data signal latched in the latch sub-circuit 80 to the signal output terminal OUT.
  • the second control sub-circuit 90 stops transmitting the data signal latched in the latch sub-circuit 80 to the signal output terminal OUT.
  • the second control sub-circuit 90 can be used as a switch to control whether the latch sub-circuit 80 and the signal output terminal OUT are connected.
  • the data latch circuit LAT provided by the embodiment of the present disclosure is respectively coupled to the first data signal terminal SI1 and the second data signal terminal SI2.
  • One data latch circuit LAT can be connected to the first data signal terminal SI1 in different time periods.
  • the received data signal is transmitted to the signal output terminal OUT, and the data signal received at the second data signal terminal SI2 is transmitted to the signal output terminal OUT.
  • the data latch circuit LAT when the display panel includes a plurality of data latch circuits LAT, at the same time period, a part of the data latch circuit LAT receives the data signal from the first data signal terminal SI1, and the other part of the data latch circuit LAT Receive the data signal from the second data signal terminal SI2.
  • the data latch circuit LAT in the related art requires 8 pulses to transmit 8 data signals to the data line DL, but in the present disclosure
  • the data latch circuit LAT requires 4 pulses to transmit 8 data signals to the data line DL. Therefore, the data latch circuit LAT in the present disclosure can shorten the transmission time of the data signal to the data line DL and improve the data signal The transmission speed, thereby increasing the refresh frequency of the display device.
  • the selection sub-circuit 60 includes a multiplexer 61.
  • the channel selection signal terminal of the multiplexer 61 is coupled with the clock pulse signal terminal CP, the first input terminal of the multiplexer 61 is coupled with the first data signal terminal SI1, and the second input terminal of the multiplexer 61 is coupled with The second data signal terminal SI2 is coupled, and the output terminal of the multiplexer 61 is coupled to the first control sub-circuit 70.
  • the multiplexer 61 selects to transmit the data signal received at the first data signal terminal SI1 to the first control sub-circuit 70. In the case that the signal received at the clock pulse signal terminal CP is the second signal, the multiplexer 61 selects to transmit the data signal received at the second data signal terminal SI2 to the first control sub-circuit 70.
  • the first control sub-circuit 70 includes a first transmission gate sub-circuit 71.
  • the control terminal of the first transmission gate sub-circuit 71 is coupled to the first control signal terminal CT1, the input terminal of the first transmission gate sub-circuit 71 is coupled to the selector sub-circuit 60, and the output terminal of the first transmission gate sub-circuit 71 is coupled to the latch sub-circuit 80 coupling.
  • the first transmission gate sub-circuit 71 When the signal received at the first control signal terminal CT1 is the first signal, the first transmission gate sub-circuit 71 is turned on, so that the selection sub-circuit 60 and the latch sub-circuit 80 are connected. When the signal received at the first control signal terminal CT1 is the second signal, the first transmission gate sub-circuit 71 is closed, so that the selection sub-circuit 60 and the latch sub-circuit 80 are disconnected.
  • the selection sub-circuit 60 includes the multiplexer 61
  • the input end of the first transmission gate sub-circuit 71 is coupled to the output end of the multiplexer 61.
  • the latch sub-circuit 80 includes a NAND gate 81 and an inverter 82.
  • the first input terminal of the NAND gate 81 is coupled to the first control sub-circuit 70, the second input terminal of the NAND gate 81 is coupled to the first voltage terminal V1, and the output terminal of the NAND gate 81 is coupled to the second control sub-circuit 90 Coupled.
  • the input terminal of the inverter 82 is coupled with the output terminal of the NAND gate 81, and the output terminal of the inverter 82 is coupled with the first input terminal of the NAND gate 81.
  • the signal received at the first voltage terminal V1 is a fixed voltage signal, for example, a DC voltage signal.
  • the data signal is transmitted in the loop formed by the NAND gate 81 and the inverter 82, so that the data signal is latched.
  • the first control sub-circuit 70 includes the transmission gate sub-circuit 71
  • the first input terminal of the NAND gate 81 is coupled to the output terminal of the transmission gate sub-circuit 71.
  • the second control sub-circuit 90 includes a second transmission gate sub-circuit 91.
  • the control terminal of the second transmission gate sub-circuit 91 is coupled to the second control signal terminal CT2, the input terminal of the second transmission gate sub-circuit 91 is coupled to the latch sub-circuit 80, and the output terminal of the second transmission gate sub-circuit 91 is coupled to the signal output terminal OUT coupling.
  • the latch sub-circuit 80 when the latch sub-circuit 80 includes a NAND gate 81 and an inverter 82, the input terminal of the second transmission gate sub-circuit 91 is connected to the output terminal of the NAND gate 81.
  • the data latch circuit LAT further includes an amplifier 50.
  • One end of the amplifier 50 is coupled to the second control sub-circuit 90, and the other end is coupled to the signal output terminal OUT.
  • the amplifier 50 is configured to amplify the signal from the second control sub-circuit 90 and transmit the amplified signal to the signal output terminal OUT.
  • the specific implementation manners of the selection sub-circuit 60, the first control sub-circuit 70, the latch sub-circuit 80, and the second control sub-circuit 90 are not limited to those described above.
  • the above examples do not limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • an embodiment of the present disclosure also provides a driving method of the data latch circuit LAT. As shown in FIG. 7, the driving method includes:
  • the selection sub-circuit 60 transmits the data signal received at the first data signal terminal SI1 to the first control sub-circuit 70 under the control of the first signal received at the clock pulse signal terminal CP (L stage in FIG. 7) .
  • the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2 to the first control sub-circuit 70 under the control of the second signal received at the clock pulse signal terminal CP (as shown in M in FIG. 7 stage).
  • the signal received at the clock pulse signal terminal CP is a high-level signal, that is, when the first signal is a high-level signal
  • the selection sub-circuit 60 transmits the data signal received at the first data signal terminal SI1 To the first control sub-circuit 70.
  • the signal received at the clock pulse signal terminal CP is a low-level signal, that is, when the second signal is a low-level signal
  • the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2 to the first A control sub-circuit 70.
  • the high-level signal is a high level relative to the low-level signal, and the high-level signal may be a negative value, for example.
  • the signal received at the clock pulse signal terminal CP is either the first signal or the second signal.
  • the selection sub-circuit 60 transmits the data signal received at the first data signal terminal SI1 to the first control under the control of the clock pulse signal terminal CP.
  • Sub-circuit 70 In the case where the signal received at the clock pulse signal terminal CP is the second signal, the selection sub-circuit 60 transmits the data signal received at the second data signal terminal SI2 to the first control under the control of the clock pulse signal terminal CP. Sub-circuit 70.
  • the selection sub-circuit 60 continues to transmit the data signal to the first control sub-circuit 70, but whether the data signal can be transmitted to the latch sub-circuit 80 depends on whether the first control sub-circuit 70 is turned on.
  • the first control sub-circuit 70 transmits the data signal to the latch sub-circuit 80 under the control of the turn-on signal received at the first control signal terminal CT1.
  • the first control sub-circuit 70 is turned on under the control of the turn-on signal received at the first control signal terminal CT1, and transmits the data signal from the selection sub-circuit 60 to the latch sub-circuit 80.
  • the first control sub-circuit 70 is turned off under the control of the cut-off signal received at the first control signal terminal CT1, so that the data signal from the selection sub-circuit 60 cannot be transmitted to the latch sub-circuit 80.
  • the data signal from the selection sub-circuit 60 may be a data signal received at the first data signal terminal SI1, or may also be a data signal received at the second data signal terminal SI2. And, the data signal is related to the signal of the clock pulse signal terminal CP.
  • the signal received at the clock pulse signal terminal CP is a high-level signal
  • the selection sub-circuit 60 transmits the R1 signal received at the first data signal terminal SI1 to the first control sub-circuit 70.
  • the first control sub-circuit 70 is turned on under the control of the turn-on signal received at the first control signal terminal CT1, and transmits the R1 signal from the selection sub-circuit 60 to the latch sub-circuit 80.
  • the signal received at the clock pulse signal terminal CP is a low-level signal
  • the selection sub-circuit 60 transmits the R4 signal received at the second data signal terminal SI2 to the first control sub-circuit 70
  • the first control sub-circuit The circuit 70 is turned on under the control of the turn-on signal received at the first control signal terminal CT1, and transmits the R4 signal from the selection sub-circuit 60 to the latch sub-circuit 80.
  • the latch sub-circuit 80 latches the data signal under the action of the fixed voltage signal received at the first voltage terminal V1.
  • the fixed voltage signal may be, for example, a low-level DC signal or a high-level DC signal.
  • the fixed voltage signal is related to the specific structure of the NAND gate 81.
  • the second control sub-circuit 90 transmits the data signal latched in the latch sub-circuit 80 to the signal output terminal OUT under the control of the opening signal received at the second control signal terminal CT2.
  • the first control sub-circuit 70 When the first control sub-circuit 70 is turned on, the data signal from the selection sub-circuit 60 is transmitted to the latch sub-circuit 80, and the latch sub-circuit 80 latches the data signal.
  • the signal received at the second control signal terminal CT2 is a cut-off signal, the data signal is always latched in the latch sub-circuit 80.
  • the second control sub-circuit 90 transmits the data signal latched in the latch sub-circuit 80 to the signal output terminal OUT. The data signal is transmitted to the data line DL through the signal output terminal OUT.
  • the moment when the second control signal terminal CT2 receives the turn-on signal may be the same as or different from the moment when the first control signal terminal CT1 receives the turn-on signal, and it can be set reasonably according to needs.
  • the data latch circuit LAT is respectively coupled to the first data signal terminal SI1 and the second data signal terminal SI2, and one data latch circuit LAT can be used in different time periods.
  • the data signal received at the first data signal terminal SI1 is transmitted to the signal output terminal OUT
  • the data signal received at the second data signal terminal SI2 is transmitted to the signal output terminal OUT.
  • a part of the data latch circuit LAT receives the data signal transmitted by the first data signal terminal SI1
  • the other part of the data latch circuit LAT Receive the data signal transmitted by the second data signal terminal SI2.
  • the data latch circuit LAT in the related art requires 8 pulses to transmit 8 data signals to the data line DL.
  • the data latch circuit LAT needs 4 pulses to transmit 8 data signals to the data line DL. Therefore, the data latch circuit LAT in the present disclosure can shorten the transmission time of the data signal to the data line DL and improve the data signal. The transmission speed, thereby increasing the refresh frequency of the display device.
  • Some embodiments of the present disclosure also provide a data latch 30, as shown in FIG. 8, including N data latch circuits LAT as in any of the above-mentioned embodiments (in FIG. 8, the data latch 30 includes 8 A data latch circuit LAT is taken as an example for illustration), where N is an even number greater than 2.
  • Different data latch circuits are coupled to different clock pulse signal terminals CP, and are coupled to different first control signal terminals CT1.
  • N can be 4, 6, or 8, etc.
  • N 8 as an example to illustrate a working process of the above-mentioned data latch 30, in which the first to fourth data latch circuits LAT are divided into the first group, and the fifth to eighth levels
  • the data latch circuit LAT is divided into the second group.
  • FIG 9 when the data latch 30 is in the L phase:
  • the first-level data latch circuit LAT1 in the first-level data latch circuit LAT1, the first signal is received at the clock pulse signal terminal CP1, the first control signal terminal CT1-1 receives the turn-on signal, and the first voltage terminal V1 receives the fixed signal. Voltage signal, the first-level data latch circuit LAT1 latches the R1 signal received at the first data signal terminal SI1.
  • the first-level data latch circuit LAT1 receives the data signal from the first data signal terminal SI1
  • the other three-level data latch circuits that is, the second-level data latch circuit LAT2 and the second The level 3 data latch circuit LAT3 and the level 4 data latch circuit LAT4 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the fifth-level data latch circuit LAT5 latches the R2 signal received at the second data signal terminal SI2.
  • the fifth-level data latch circuit LAT5 receives the data signal from the second data signal terminal SI2
  • the other three-level data latch circuits that is, the sixth-level data latch circuit LAT6, the first The 7-level data latch circuit LAT7 and the 8-level data latch circuit LAT8 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the first level data latch circuit LAT1 receives the data signal from the second data signal terminal SI2, but because the signal received at the first control signal terminal CT1-1 is an off signal, the first level The data latch circuit LAT1 does not latch the data signal from the second data signal terminal SI2.
  • the first signal is received at the clock pulse signal terminal CP5, the cut-off signal is received at the first control signal terminal CT1-5, and the fixed voltage signal is received at the first voltage terminal V1.
  • the fifth-level data latch circuit LAT5 will be in the second
  • the R2 signal received at the data signal terminal SI2 is latched in the fifth-level data latch circuit LAT5.
  • the fifth-level data latch circuit LAT5 receives the data signal from the first data signal terminal SI1, since the signal received at the first control signal terminal CT1-5 is an off signal, the fifth-level data The latch circuit LAT5 does not latch the data signal from the first data signal terminal SI1.
  • the second-level data latch circuit LAT2 latches the G1 signal received at the first data signal terminal SI1.
  • the second-level data latch circuit LAT2 receives the data signal from the first data signal terminal SI1
  • the other three-level data latch circuits that is, the first-level data latch circuit LAT1, the second The level 3 data latch circuit LAT3 and the level 4 data latch circuit LAT4 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the second signal is received at the clock pulse signal terminal CP6, the start signal is received at the first control signal terminal CT1-6, and the fixed voltage signal is received at the first voltage terminal V1.
  • the level data latch circuit LAT6 latches the G2 signal received at the second data signal terminal SI2.
  • the sixth-level data latch circuit LAT6 receives the data signal of the second data signal terminal SI2, and the other three-level data latch circuits (that is, the fifth-level data latch circuit LAT5, the seventh The level data latch circuit LAT7 and the eighth level data latch circuit LAT8) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the clock pulse signal terminal CP2 of the second level data latch circuit LAT2 receives the second signal, the cutoff signal is received at the first control signal terminal CT1-2, and the fixed voltage signal is received at the first voltage terminal V1.
  • the second level data lock The storage circuit LAT2 latches the G1 signal received at the first data signal terminal SI1 in the second-level data latch circuit LAT2.
  • the clock pulse signal terminal CP6 of the sixth level data latch circuit LAT6 receives the first signal, the cut-off signal is received at the first control signal terminal CT1-6, and the fixed voltage signal is received at the first voltage terminal V1.
  • the sixth level data lock The storage circuit LAT6 latches the G2 signal received at the second data signal terminal SI2 in the sixth-level data latch circuit LAT6.
  • the level 3 data latch circuit LAT3 latches the B1 signal received at the first data signal terminal SI1.
  • the third-level data latch circuit LAT3 receives the data signal from the first data signal terminal SI1, and the other three-level data latch circuits (that is, the first-level data latch circuit LAT1, the first The 2-level data latch circuit LAT2 and the fourth-level data latch circuit LAT4) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the seventh level data latch circuit LAT7 the second signal is received at the clock pulse signal terminal CP7, the turn-on signal is received at the first control signal terminal CT1-7, and the fixed voltage signal is received at the first voltage terminal V1.
  • the level data latch circuit LAT7 latches the B2 signal received at the second data signal terminal SI2.
  • the seventh-level data latch circuit LAT7 receives the data signal from the second data signal terminal SI2, and the other three-level data latch circuits (that is, the fifth-level data latch circuit LAT5, the first The 6-level data latch circuit LAT6 and the 8-level data latch circuit LAT8) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the clock pulse signal terminal CP3 of the third level data latch circuit LAT3 receives the second signal, receives the cut-off signal at the first control signal terminal CT1-3, and receives the fixed voltage signal at the first voltage terminal V1.
  • the third level data lock The storage circuit LAT3 latches the B1 signal received at the first data signal terminal SI1 in the third-level data latch circuit LAT3.
  • the clock pulse signal terminal CP7 of the seventh level data latch circuit LAT7 receives the first signal, the cut-off signal is received at the first control signal terminal CT1-7, and the fixed voltage signal is received at the first voltage terminal V1.
  • the seventh level data lock The storage circuit LAT7 latches the B2 signal received at the second data signal terminal SI2 in the seventh-level data latch circuit LAT7.
  • the fourth level data latch circuit LAT4 latches the D1 signal received at the first data signal terminal SI1.
  • the fourth-level data latch circuit LAT4 receives the data signal from the first data signal terminal SI1, and the other three-level data latch circuits (that is, the first-level data latch circuit LAT1, the first The level 2 data latch circuit LAT2 and the level 3 data latch circuit LAT3) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the eighth level data latch circuit LAT8 the second signal is received at the clock pulse signal terminal CP8, the start signal is received at the first control signal terminal CT1-8, and the fixed voltage signal is received at the first voltage terminal V1.
  • the level data latch circuit LAT8 latches the D2 signal received at the second data signal terminal SI2.
  • the eighth-level data latch circuit LAT8 receives the data signal from the second data signal terminal SI2, and the other three-level data latch circuits (that is, the fifth-level data latch circuit LAT5, the first The six-level data latch circuit LAT6 and the seventh-level data latch circuit LAT7) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the data signals in the storage circuit LAT8 are simultaneously transmitted to the eight data lines DL coupled to the signal output terminals OUT.
  • the second signal received at the clock pulse signal terminal CP1 remains unchanged, the turn-on signal is received at the first control signal terminal CT11, and the fixed voltage signal is received at the first voltage terminal V1.
  • the level 1 data latch circuit LAT1 latches the R4 signal received at the second data signal terminal SI2.
  • the first-level data latch circuit LAT1 receives the data signal from the second data signal terminal SI2, and the other three-level data latch circuits (ie, the second-level data latch circuit LAT2, the second The level 3 data latch circuit LAT3 and the level 4 data latch circuit LAT4) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the fifth-level data latch circuit LAT5 latches the R3 signal received at the first data signal terminal SI1.
  • the fifth-level data latch circuit LAT5 receives the data signal of the first data signal terminal SI1
  • the other three-level data latch circuits that is, the sixth-level data latch circuit LAT6, the seventh The level data latch circuit LAT7 and the eighth level data latch circuit LAT8 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the first control signal terminal CT1-1 of the first level data latch circuit LAT1 receives the cut-off signal, and the fixed voltage signal is received at the first voltage terminal V1, and the first level data latch circuit LAT1 will be at the second data signal terminal SI2
  • the received R4 signal is latched in the first-level data latch circuit LAT1.
  • the first control signal terminal CT1-5 of the fifth level data latch circuit LAT5 receives the cut-off signal, the fixed voltage signal is received at the first voltage terminal V1, and the R3 signal received at the first data signal terminal SI1 is latched in the fifth level Data latch circuit LAT5.
  • the second-level data latch circuit LAT2 receives the data signal from the second data signal terminal SI2
  • the other three-level data latch circuits that is, the first-level data latch circuit LAT1, the first The level 3 data latch circuit LAT3 and the level 4 data latch circuit LAT4 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the sixth-level data latch circuit LAT6 latches the G3 signal received at the first data signal terminal SI1.
  • the sixth-level data latch circuit LAT6 receives the data signal from the first data signal terminal SI1, and the other three-level data latch circuits (that is, the fifth-level data latch circuit LAT5, the first The 7-level data latch circuit LAT7 and the 8-level data latch circuit LAT8) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the first control signal terminal CT1-6 of the level 6 data latch circuit LAT6 receives the cut-off signal, and the fixed voltage signal is received at the first voltage terminal V1, and the level 6 data latch circuit LAT6 will be at the first data signal terminal SI1
  • the received G3 signal is latched in the sixth-level data latch circuit LAT6.
  • the third-level data latch circuit LAT3 receives the data signal from the second data signal terminal SI2, and the other three-level data latch circuits (ie, the second-level data latch circuit LAT2, the second The level 3 data latch circuit LAT3 and the level 4 data latch circuit LAT4) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the seventh-level data latch circuit LAT7 the first signal received at the clock pulse signal terminal CP7 remains unchanged, the turn-on signal is received at the first control signal terminal CT1-7, and the fixed voltage signal is received at the first voltage terminal V1 ,
  • the seventh-level data latch circuit LAT7 latches the B3 signal received at the first data signal terminal SI1.
  • the seventh-level data latch circuit LAT7 receives the data signal from the first data signal terminal SI1
  • the other three-level data latch circuits that is, the fifth-level data latch circuit LAT5, the first The 6-level data latch circuit LAT6 and the 8-level data latch circuit LAT8 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the first control signal terminal CT1-7 of the seventh-level data latch circuit LAT7 receives the cut-off signal, and the fixed voltage signal is received at the first voltage terminal V1, and the seventh-level data latch circuit LAT7 will be at the first data signal terminal SI1.
  • the received B3 signal is latched in the seventh-level data latch circuit LAT7.
  • the fourth-level data latch circuit LAT4 latches the D4 signal received at the second data signal terminal SI2.
  • the fourth-level data latch circuit LAT4 receives the data signal from the second data signal terminal SI2, and the other three-level data latch circuits (that is, the first-level data latch circuit LAT1, the first The level 2 data latch circuit LAT2 and the level 3 data latch circuit LAT3) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the eighth level data latch circuit LAT8 latches the D3 signal received at the first data signal terminal SI1.
  • the 8-level data latch circuit LAT8 receives the data signal from the first data signal terminal SI1, and the other three-level data latch circuits (that is, the fifth-level data latch circuit LAT5, The six-level data latch circuit LAT6 and the seventh-level data latch circuit LAT7) neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the data signals of are simultaneously transmitted to the eight data lines DL coupled to the signal output terminals OUT.
  • each level of data latch circuit is coupled to the first data signal terminal SI1 and the second data signal terminal SI2, and each level of data latch circuit can be used in different time periods.
  • the data signal received at the first data signal terminal SI1 is transmitted to the signal output terminal OUT
  • the data signal received at the second data signal terminal SI2 can be transmitted to the signal output terminal OUT.
  • a part of the data latch circuit LAT in the data latch 30 receives the data signal from the first data signal terminal SI1
  • another part of the data latch circuit LAT receives the data signal from the first data signal terminal SI1. 2.
  • the data latch 30 in the related art requires 8 pulses to transmit 8 data signals to the data line DL, but in the present disclosure It takes 4 pulses for the data latch 30 to transmit 8 data signals to the data line DL. Therefore, the data latch circuit LAT in the present disclosure can shorten the time for transmitting the data signal to the data line DL and improve the data The transmission speed of the signal, thereby increasing the refresh frequency of the display device.
  • the display device in the related art transmits a set of The data signal requires 4 pulses. Therefore, the refresh frequency of the display device in the related art can only reach 2 MHz, while the refresh frequency of the display device in the present disclosure can reach 3.7 MHz, which improves the refresh frequency.
  • N data latch circuits LAT are coupled to the same first data signal terminal SI1.
  • the wiring arrangement of the display device is simplified.
  • N data latch circuits LAT are coupled to the same second data signal terminal SI2. In this case, the wiring arrangement of the display device is simplified.
  • the N data latch circuits LAT are coupled to the same second control signal terminal CT2. In this case, the wiring arrangement of the display device is simplified.
  • N data latch circuits LAT are coupled to the same first voltage terminal V1. In this case, the wiring arrangement of the display device is simplified.
  • the embodiment of the present disclosure provides a method for driving the data latch 30. Based on the data latch 30 in any of the above embodiments, the N data latch circuits LAT included in the data latch 30 are equally divided into two
  • the driving method of the data latch 30 includes:
  • i can be 1, 2, 3, or 4.
  • the data latch circuit LAT1-i of the i-th stage in the first group receives the data signal from the first data signal terminal SI1
  • the other data latch circuits in the first group neither receive the first data
  • the data signal from the signal terminal SI1 also does not receive the data signal from the second data signal terminal SI2.
  • the first group and the second group respectively include 4 data latch circuits LAT as an example.
  • the first-level data latch circuit LAT1-1 in the first group receives the data signal from the first data signal terminal SI1
  • the second-level data latch circuit LAT1-2 and the first group in the first group Both the level 3 data latch circuit LAT1-3 and the level 4 data latch circuit LAT1-4 neither receive the data signal from the first data signal terminal SI1 nor the data signal from the second data signal terminal SI2.
  • the arrangement order of the data latch circuit LAT on the display panel can be set reasonably according to needs.
  • the arrangement of the data latch circuit LAT in FIG. 15 is only based on the driving order, not the arrangement order.
  • the other data latch circuits in the second group are A data signal terminal SI1 and a second data signal terminal SI2 are disconnected; wherein, 1 ⁇ i ⁇ N/2, and i is a positive integer.
  • the i-th data latch circuit LAT2-i in the second group receives the data signal from the second data signal terminal SI2
  • the other data latch circuits LAT in the second group neither receive the first data
  • the data signal from the signal terminal SI1 also does not receive the data signal from the second data signal terminal SI2.
  • the N data latch circuits LAT transmit the data signals latched in each to the signal output terminal OUT.
  • the second control signal terminals CT2 of the N data latch circuits LAT in the data latch 30 simultaneously receive the enable signal, and the N data latch circuits LAT simultaneously transmit the data signals latched in their respective internals to the signal output ⁇ OUT.
  • some embodiments of the present disclosure provide a display device 200.
  • the display device 200 may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, etc., for example, a watch.
  • PDA personal digital assistant
  • the display device may be a display panel, or a device including a display panel and a frame. The following takes the display device as an example that includes a frame and other structures.
  • the display device 200 includes a display panel 10 as shown in FIG. 1.
  • the display panel 10 has an effective display area (Active Area, AA) 100 and a peripheral area 101 located around the effective display area 100.
  • the effective display area 100 includes a plurality of sub pixels 20.
  • the multiple sub-pixels 20 are arranged in a matrix as an example.
  • the sub-pixels 20 arranged in a row along the horizontal direction X are called sub-pixels in the same row
  • the sub-pixels 20 arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • the sub-pixels in the same row can be connected to a gate line.
  • GL connection the same column of sub-pixels can be connected to a data line DL.
  • the sub-pixel 20 is provided with a pixel circuit 201 for controlling the sub-pixel 20 to display, and the pixel circuit 201 is provided on the base substrate of the display panel 10.
  • the display panel 10 may also be a light emitting diode display panel, such as an organic light emitting diode (OLED) display panel.
  • OLED organic light emitting diode
  • the pixel circuit 201 includes a transistor M and a liquid crystal capacitor C.
  • the two plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode.
  • the gate of the transistor M is connected to the gate line GL
  • the first electrode is connected to the data line DL
  • the second electrode is connected to the liquid crystal capacitor C for transmitting the data signal on the data line DL to the liquid crystal capacitor C.
  • each data line DL receives a data signal.
  • the display panel 10 including P columns of sub-pixels 20 as an example, there are P data lines DL that need to receive data signals.
  • the display device 200 adopts the SPI technology, and each data line DL is coupled to a data latch circuit LAT, and the data signal is transmitted to the data line DL through the data latch circuit LAT.
  • the multiple data lines DL included in the display device 200 may be divided into multiple groups, and each group includes N data lines DL.
  • the N data lines DL included in each group are respectively coupled to the signal output terminals OUT of the N data latch circuits LAT included in the data latch 30.
  • a plurality of pixels in the display device 200 are arranged in an array.
  • Each column of pixels includes a first color sub pixel, a second color sub pixel, and a third color sub pixel.
  • the first color, the second color and the third color are three primary colors, for example, red, blue and green.
  • the data latch 30 includes at least 6 data latch circuits LAT.
  • the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel in the odd-numbered column of pixels pass through three data lines, and respectively communicate with the signal output terminals of the three data latch circuits LAT in the data latch 30.
  • OUT coupling; the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel in the even-numbered column of pixels are connected to the other three data latch circuits LAT in the data latch 30 through three data lines
  • the signal output terminal OUT is coupled.
  • each column of pixels further includes a fourth color sub-pixel, for example, the fourth color may be white.
  • the data latch 30 includes 8 data latch circuits LAT. Among them, the first-color sub-pixel, the second-color sub-pixel, the third-color sub-pixel, and the fourth-color sub-pixel in the odd-numbered column of pixels pass through four data lines and are respectively latched with four data in the data latch 30 The signal output terminal OUT of the circuit LAT is coupled; the first-color sub-pixel, the second-color sub-pixel, the third-color sub-pixel, and the fourth-color sub-pixel in the even-numbered column of pixels are connected to the data latch through 4 data lines, respectively The signal output terminals OUT of the other four data latch circuits LAT in 30 are coupled.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种数据锁存电路，包括选择子电路(60)、第一控制子电路(70)、锁存子电路(80)和第二控制子电路(90)。选择子电路(60)在时钟脉冲信号端处接收的信号的控制下，在不同时间段内，传输在第一数据信号端处接收的数据信号和在第二数据信号端处接收的数据信号；第一控制子电路(70)在第一控制信号端处接收的信号的控制下，传输来自选择子电路(60)的数据信号；锁存子电路(80)接收来自第一控制子电路(70)的数据信号，并在第一电压端的电压的作用下锁存该数据信号；第二控制子电路(90)在第二控制信号端处接收的信号的控制下，将锁存在锁存子电路(80)内部的数据信号传输至信号输出端。

Description

数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置
本申请要求于2019年04月16日提交的、申请号为201910303629.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置。
背景技术
随着显示技术的发展，台式显示产品、电子设备、可穿戴显示设备等显示装置得到了广泛的应用，而显示装置的功耗问题，一直倍受消费者的关注。
以目前可穿戴产品中的手表为例，手表的功耗问题一直是本领域技术人员较为关注的技术问题。目前采用MIP(Memory In Pixel，存储在像素中)电路的手表产品，因其具有低功耗的特性，而广泛的应用在目前的市场中。
MIP电路主要是通过采用的SPI(Serial Peripheral Interface，串行外设接口)技术来减少功耗的，在SPI技术中，将Source IC(源极驱动电路)部分做在阵列基板(Array)上，由一个数据信号端传输所有的数据信号。这样一来，可以降低IC(Integrated Circuit，集成电路)的成本，又可以减少功耗。
发明内容
一方面，提供一种数据锁存电路。所述数据锁存电路包括选择子电路、第一控制子电路、锁存子电路和第二控制子电路。所述选择子电路与第一数据信号端、第二数据信号端和时钟脉冲信号端耦接；所述选择子电路被配置为在所述时钟脉冲信号端处接收的信号的控制下，在不同时间段内，传输在所述第一数据信号端处接收的数据信号和在所述第二数据信号端处接收的数据信号。所述第一控制子电路与所述选择子电路和第一控制信号端耦接；所述第一控制子电路被配置为在所述第一控制信号端处接收的信号的控制下，传输来自所述选择子电路的数据信号。所述锁存子电路与所述第一控制子电路和第一电压端耦接；所述锁存子电路被配置为接收来自所述第一控制子电路的数据信号，并在所述第一电压端的电压的作用下锁存该数据信号。所述第二控制子电路与所述锁存子电路、第二控制信号端和信号输出端耦接；所述第二控制子电路被配置为在所述第二控制信号端处接收的信号的控制下，将锁存在所述锁存子电路内部的数据信号传输至所述信号输出端。
在一些实施例中，所述选择子电路包括多路选择器。所述多路选择器 的通道选择信号端与所述时钟脉冲信号端耦接，所述多路选择器的第一输入端与所述第一数据信号端耦接，所述多路选择器的第二输入端与所述第二数据信号端耦接，所述多路选择器的输出端与所述第一控制子电路耦接。
在一些实施例中，所述第一控制子电路包括第一传输门子电路。所述第一传输门子电路的控制端与所述第一控制信号端耦接，所述第一传输门子电路的输入端与所述选择子电路耦接，所述第一传输门子电路的输出端与所述锁存子电路耦接。
在一些实施例中，所述锁存子电路包括与非门和反向器。所述与非门的第一输入端与所述第一控制子电路耦接，所述与非门的第二输入端与所述第一电压端耦接，所述与非门的输出端与所述第二控制子的电路耦接；所述反向器的输入端与所述与非门的输出端和所述第二控制子电路耦接，所述反向器的输出端与所述与非门的第一输入端耦接。
在一些实施例中，所述第二控制子电路包括第二传输门子电路。所述第二传输门子电路的控制端与所述第二控制信号端耦接，所述第二传输门子电路的输入端与所述锁存子电路耦接，所述第二传输门子电路的输出端与所述信号输出端耦接。
在一些实施例中，所述数据锁存电路还包括放大器。所述放大器与所述第二控制子电路和所述信号输出端耦接；所述放大器被配置为，对来自所述第二控制子电路的信号进行放大，并将放大后的信号传输至所述信号输出端。
另一方面，提供一种数据锁存器。所述数据锁存器包括：N个如上述任一实施例所述的数据锁存电路；其中，N为大于2的偶数。不同所述数据锁存电路与不同的时钟脉冲信号端耦接，且与不同的第一控制信号端耦接。
在一些实施例中，N个所述数据锁存电路与同一第一数据信号端耦接。
在一些实施例中，N个所述数据锁存电路与同一第二数据信号端耦接。
在一些实施例中，N个所述数据锁存电路与同一第二控制信号端耦接。
在一些实施例中，N为6或者8。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的数据锁存器。
在一些实施例中，所述显示装置还包括多根数据线。所述多根数据线分为多组，每组包括N根数据线，每组所包括的N根数据线分别与所述数 据锁存器所包括的N个数据锁存电路的信号输出端耦接。
在一些实施例中，所述数据锁存器包括至少6个数据锁存电路。所述显示装置还包括阵列式排布的多个像素，每列像素包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素；奇数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与所述数据锁存器中的3个数据锁存电路的信号输出端耦接；偶数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与所述数据锁存器中的另外3个数据锁存电路的信号输出端耦接。
在一些实施例中，所述数据锁存器包括8个数据锁存电路。每列像素还包括第四颜色亚像素；奇数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素通过4根数据线，分别与所述数据锁存器中的4个数据锁存电路的信号输出端耦接；偶数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素通过4根数据线，分别与所述数据锁存器中的另外4个数据锁存电路的信号输出端耦接。
再一方面，提供一种如上述任一实施例所述的数据锁存电路的驱动方法，包括：选择子电路在时钟脉冲信号端处接收的第一信号的控制下，将在第一数据信号端处接收的数据信号传输至第一控制子电路，或者，选择子电路在时钟脉冲信号端处接收的第二信号的控制下，将在第二数据信号端处接收的数据信号传输至第一控制子电路；所述第一控制子电路在第一控制信号端处接收的开启信号的控制下，将所述数据信号传输至锁存子电路；所述锁存子电路在第一电压端处接收的固定电压信号的作用下，对所述数据信号进行锁存；第二控制子电路在第二控制信号端处接收的开启信号的控制下，将锁存在所述锁存子电路内部的所述数据信号传输至信号输出端。
又一方面，提供一种如上述任一实施例所述的数据锁存器的驱动方法，N个数据锁存电路均分为两组。所述数据锁存器的驱动方法包括：第一组中的N/2个数据锁存电路依次锁存第一数据信号端处接收的数据信号；在同一时段内，第二组中的N/2个数据锁存电路依次锁存第二数据信号端处接收的数据信号；所述N个数据锁存电路将锁存在各自内部的数据信号传输至信号输出端。
在一些实施例中，所述N个数据锁存电路将锁存在各自内部的数据信号传输至信号输出端，包括：所述N个数据锁存电路的第二控制信号端同时接收开启信号，将存储在各自内部的数据信号同时传输至信号输出端。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的显示面板的一种结构图；
图3为根据相关技术的显示装置的结构图；
图4为图3所示的显示装置中的数据锁存器的驱动时序图；
图5为根据一些实施例的数据锁存电路的一种结构图；
图6a为图5所示的数据锁存电路中各子电路的结构图；
图6b为根据一些实施例的数据锁存电路的另一种结构图；
图7为图5所示的数据锁存电路的驱动时序图；
图8为根据一些实施例的显示装置的另一种结构图；
图9为图8所示的显示装置中的数据锁存器的驱动时序图；
图10～图14为根据一些实施例的显示装置中的数据锁存器驱动过程图；
图15为根据一些实施例提供的显示装置的又一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术 语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如图3所示，相关技术中的显示装置200'包括显示面板10'，该显示面板10'采用SPI技术。在显示面板包括P根数据线DL的情况下，通过一个数据信号端SI向P根数据线DL分别传输信号，数据信号端SI通过数据锁存器30'与多根数据线DL连接。
数据锁存器30'包括8个数据锁存电路LAT(分别编号为LAT1～LAT8)，数据锁存电路LAT与时钟脉冲信号端CP、时钟信号端CLK、数据信号端SI和数据线DL耦接。8个数据锁存电路LAT与同一数据信号端SI和时钟信号端CLK耦接，8个数据锁存电路LAT分别与不同的时钟脉冲信号端CP和数据线DL耦接。
P根数据线DL分为P/8组，每组中所包括的8根数据线DL分别与8个数据锁存电路LAT耦接。
如图4所示，在数据传输过程中，数据信号端SI依次输出所有数据线DL上的信号，第一个脉冲(一个脉冲例如可以是一个CLK的宽度)，第一时钟脉冲信号端CP1打开，第一数据锁存电路LAT1接收R1的信号，并将R1信号锁存在第一数据锁存电路LAT1内，然后第一时钟脉冲信号端CP1关闭。
第二个脉冲，第二时钟脉冲信号端CP2打开，第二数据锁存电路LAT2接收G1的信号，并将G1信号锁存在第二数据锁存电路LAT2内，然后第二时钟脉冲信号端CP2关闭。
第三个脉冲，第三时钟脉冲信号端CP3打开，第三数据锁存电路LAT3 接收B1的信号，并将B1信号锁存在第三数据锁存电路LAT3内，然后第三时钟脉冲信号端CP3关闭。
第四个脉冲，第四时钟脉冲信号端CP4打开，第四数据锁存电路LAT4接收D1的信号，并将D1信号锁存在第四数据锁存电路LAT4内，然后第四时钟脉冲信号端CP4关闭。
第五个脉冲，第五时钟脉冲信号端CP5打开，第五数据锁存电路LAT5接收R2的信号，并将R2信号锁存在第五数据锁存电路LAT5内，然后第五时钟脉冲信号端CP5关闭。
第六个脉冲，第六时钟脉冲信号端CP6打开，第六数据锁存电路LAT6接收G2的信号，并将G2信号锁存在第六数据锁存电路LAT6内，然后第六时钟脉冲信号端CP6关闭。
第七个脉冲，第七时钟脉冲信号端CP7打开，第七数据锁存电路LAT7接收B2的信号，并将B2信号锁存在第七数据锁存电路LAT7内，然后第七时钟脉冲信号端CP7关闭。
第八个脉冲，第八时钟脉冲信号端CP8打开，第八数据锁存电路LAT8接收D2的信号，并将D2信号锁存在第八数据锁存电路LAT8内，然后第八时钟脉冲信号端CP8关闭。
在第八个脉冲，时钟信号端CLK同时接收时钟信号，将锁存在8个数据锁存电路LAT中的数据信号同时传输至与各数据锁存电路LAT耦接的数据线DL中。
可以理解的是，一个数据锁存电路LAT与多根数据线DL耦接，每根数据线DL耦接有控制单元，在轮到某根数据线DL接收数据信号时，与数据线DL耦接的控制单元才会开启。控制单元开启后，数据线DL才能接收到数据信号。因此，虽然一个数据锁存电路LAT耦接多根数据线DL，但是数据锁存电路LAT将数据信号传输至与该数据锁存电路LAT耦接的数据线DL中的一根数据线DL。
然后从第9个至第16个数据信号开始，重复上述过程，直至所有数据信号传输完毕。
通过上述传输过程，可以看出8个数据锁存电路LAT依次接收完数据信号后，才能把数据信号传输给数据线DL。这样一来，需要经过8个脉冲，否则数据会发生丢失和错乱，而这就导致采用SPI技术的显示面板的刷新频率较低。并且，采用SPI技术的产品的刷新频率主要由数据信号端传输数据信号的数据量决定，一个数据信号端传输所有的数据信号的方案虽然可以降低 功耗，但刷新频率较低，一般只能达到2MHZ左右，很难满足用户需求。
本公开的一些实施例提供一种数据锁存电路LAT，如图5所示，包括：选择子电路60、第一控制子电路70、锁存子电路80和第二控制子电路90。
如图5所示，选择子电路60与第一数据信号端SI1、第二数据信号端SI2和时钟脉冲信号端CP耦接。
第一控制子电路70与选择子电路60和第一控制信号端CT1耦接。
锁存子电路80与第一控制子电路70和第一电压端V1耦接。
第二控制子电路90与锁存子电路80、第二控制信号端CT2和信号输出端OUT耦接。
选择子电路60被配置为在时钟脉冲信号端CP处接收的信号的控制下，在不同时间段内，传输在第一数据信号端SI1处接收的数据信号和在第二数据信号端SI2处接收的数据信号。
第一控制子电路70被配置为在第一控制信号端CT1处接收的信号的控制下，传输来自选择子电路60的数据信号。
锁存子电路80被配置为接收来自第一控制子电路70的数据信号，并在第一电压端V1的电压的作用下锁存该数据信号。
第二控制子电路90被配置为在第二控制信号端CT2处接收的信号的控制下，将锁存在锁存子电路80内部的数据信号传输至信号输出端OUT。
其中，在时钟脉冲信号端CP处接收的信号为第一信号的情况下，选择子电路60传输在第一数据信号端SI1的数据信号处接收的数据信号。在时钟脉冲信号端CP处接收的信号为第二信号的情况下，选择子电路60传输在第二数据信号端SI2处接收的数据信号。
在数据锁存电路LAT包括第一控制子电路70的情况下，选择子电路60将数据信号传输至第一控制子电路70。
可以理解的是，选择子电路60选择传输在第一数据信号端SI1和第二数据信号端SI2中的一个信号端处接收的数据信号，即，选择子电路60传输在第一数据信号端SI1处接收的数据信号，或者传输在第二数据信号端SI2处接收的数据信号。
示例性地，在时钟脉冲信号端CP处接收的信号为高电平信号，即，第一信号为高电平信号的情况下，选择子电路60传输在第一数据信号端SI1处接收的数据信号，在时钟脉冲信号端CP处接收的信号为低电平信号，即，第二信号为低电平信号的情况下，选择子电路60传输在第二数据信号端SI2处接收的数据信号。或者，在时钟脉冲信号端CP处接收的信号为低电平信号，即， 第一信号为低电平信号的情况下，选择子电路60传输在第一数据信号端SI1处接收的数据信号，在时钟脉冲信号端CP处接收的信号为高电平信号，即，第二信号为高电平信号的情况下，选择子电路60传输在第二数据信号端SI2处接收的数据信号。
在第一控制信号端CT1处接收的信号为第一信号的情况下，第一控制子电路70传输来自选择子电路60的数据信号。在第一控制信号端CT1处接收的信号为第二信号的情况下，第一控制子电路70停止传输来自选择子电路60的数据信号。
在数据锁存电路LAT包括锁存子电路80的情况下，第一控制子电路70在第一控制信号端CT1处接收的信号的控制下，将来自选择子电路60的数据信号传输至锁存子电路80。这样一来，虽然选择子电路60向第一控制子电路70传输数据信号，但第一控制子电路70在第一控制信号端CT1处接收的信号的控制下打开，因此，锁存子电路80并不一定能够接收到数据信号。
可以理解的是，第一控制子电路70可以作为一个开关，以控制选择子电路60和锁存子电路80是否连通。
锁存子电路80接收来自第一控制子电路70的数据信号，并且在第一电压端V1的电压为固定电压的情况下，锁存子电路80将该数据信号锁存在锁存子电路80内部。
其中，数据锁存电路LAT的信号输出端OUT与显示面板中的数据线DL耦接。
在第二控制信号端CT2处接收的信号为第一信号的情况下，第二控制子电路90将锁存在锁存子电路80中的数据信号传输至信号输出端OUT。在第二控制信号端CT2处接收的信号为第二信号的情况下，第二控制子电路90停止将锁存在锁存子电路80中的数据信号传输至信号输出端OUT。
可以理解的是，第二控制子电路90可以作为一个开关，以控制锁存子电路80和信号输出端OUT是否连通。
本公开实施例提供的数据锁存电路LAT分别与第一数据信号端SI1和第二数据信号端SI2耦接，一个数据锁存电路LAT可以在不同时间段分别将在第一数据信号端SI1处接收的数据信号传输至信号输出端OUT，将在第二数据信号端SI2处接收的数据信号传输至信号输出端OUT。
这样一来，在显示面板包括多个数据锁存电路LAT的情况下，在同一时间段，一部分数据锁存电路LAT接收来自第一数据信号端SI1的数据信号，另一部分的数据锁存电路LAT接收来自第二数据信号端SI2的数据信号。在 此情况下，以显示面板包括8个数据锁存电路LAT为例，相关技术中的数据锁存电路LAT将8个数据信号传输至数据线DL需要的时间为8个脉冲，而本公开中的数据锁存电路LAT将8个数据信号传输至数据线DL需要的时间为4个脉冲，因此，本公开中的数据锁存电路LAT可以缩短数据信号传输至数据线DL的时间，提高数据信号的传输速度，从而提高显示装置的刷新频率。
示例性地，如图6a所示，选择子电路60包括多路选择器61。
多路选择器61的通道选择信号端与时钟脉冲信号端CP耦接，多路选择器61的第一输入端与第一数据信号端SI1耦接，多路选择器61的第二输入端与第二数据信号端SI2耦接，多路选择器61的输出端与第一控制子电路70耦接。
在时钟脉冲信号端CP处接收的信号为第一信号的情况下，多路选择器61选择将在第一数据信号端SI1处接收的数据信号传输至第一控制子电路70。在时钟脉冲信号端CP处接收的信号为第二信号的情况下，多路选择器61选择将在第二数据信号端SI2处接收的数据信号传输至第一控制子电路70。
示例性地，如图6a所示，第一控制子电路70包括第一传输门子电路71。
第一传输门子电路71的控制端与第一控制信号端CT1耦接，第一传输门子电路71的输入端与选择子电路60耦接，第一传输门子电路71的输出端与锁存子电路80耦接。
在第一控制信号端CT1处接收的信号为第一信号的情况下，第一传输门子电路71开启，使得选择子电路60和锁存子电路80连通。在第一控制信号端CT1处接收的信号为第二信号的情况下，第一传输门子电路71关闭，使得选择子电路60和锁存子电路80断开。
在一些实施例中，在选择子电路60包括多路选择器61的情况下，第一传输门子电路71的输入端耦接多路选择器61的输出端。
示例性地，如图6a所示，锁存子电路80包括与非门81和反向器82。
与非门81的第一输入端与第一控制子电路70耦接，与非门81的第二输入端与第一电压端V1耦接，与非门81的输出端与第二控制子电路90耦接。
反向器82的输入端与与非门81的输出端耦接，反向器82的输出端与与非门81的第一输入端耦接。
需要说明的是，在第一电压端V1处接收的信号为固定电压信号，例如，直流电压信号。
在此基础上，数据信号在与非门81和反向器82形成的回路中传输，从而实现对数据信号的锁存。
在一些实施例中，在第一控制子电路70包括传输门子电路71的情况下，与非门81的第一输入端耦接传输门子电路71的输出端。
示例性地，如图6a所示，第二控制子电路90包括第二传输门子电路91。
第二传输门子电路91的控制端与第二控制信号端CT2耦接，第二传输门子电路91的输入端与锁存子电路80耦接，第二传输门子电路91的输出端与信号输出端OUT耦接。
在一些实施例中，在锁存子电路80包括与非门81和反向器82的情况下，第二传输门子电路91的输入端连接与非门81的输出端。
在一些实施例中，如图6b所示，数据锁存电路LAT还包括放大器50。
放大器50的一端与第二控制子电路90耦接，另一端与信号输出端OUT耦接。放大器50被配置为对来自第二控制子电路90的信号进行放大，并将放大后的信号传输至信号输出端OUT。
需要说明的是，在本公开的实施例提供的电路中，选择子电路60、第一控制子电路70、锁存子电路80和第二控制子电路90的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
基于上述数据锁存电路LAT，本公开实施例还提供一种数据锁存电路LAT的驱动方法，如图7所示，驱动方法包括：
选择子电路60在时钟脉冲信号端CP处接收的第一信号的控制下，将在第一数据信号端SI1处接收的数据信号传输至第一控制子电路70(如图7中的L阶段)。
或者，选择子电路60在时钟脉冲信号端CP处接收的第二信号的控制下，将在第二数据信号端SI2处接收的数据信号传输至第一控制子电路70(如图7中的M阶段)。
例如，在时钟脉冲信号端CP处接收的信号为高电平信号，即，第一信号为高电平信号的情况下，选择子电路60将在第一数据信号端SI1处接收的数据信号传输至第一控制子电路70。在时钟脉冲信号端CP处接收的信号为低电平信号，即，第二信号为低电平信号的情况下，选择子电路60将在第二数据信号端SI2处接收的数据信号传输至第一控制子电路70。
其中，上述高电平信号是相对上述低电平信号而言为高电平，高电平信 号例如可以为负值。
需要说明的是，在时钟脉冲信号端CP处接收的信号要么为第一信号，要么为第二信号。
在时钟脉冲信号端CP处接收的信号为第一信号的情况下，选择子电路60在时钟脉冲信号端CP的控制下，将在第一数据信号端SI1处接收的数据信号传输至第一控制子电路70。在时钟脉冲信号端CP处接收的信号为第二信号的情况下，选择子电路60在时钟脉冲信号端CP的控制下，将在第二数据信号端SI2处接收的数据信号传输至第一控制子电路70。
因此，选择子电路60持续向第一控制子电路70传输数据信号，但数据信号能否传输至锁存子电路80，与第一控制子电路70是否开启有关。
第一控制子电路70在第一控制信号端CT1处接收的开启信号的控制下，将数据信号传输至锁存子电路80。
第一控制子电路70在第一控制信号端CT1处接收的开启信号的控制下导通，将来自选择子电路60的数据信号传输至锁存子电路80。第一控制子电路70在第一控制信号端CT1处接收的截止信号的控制下断开，使得来自选择子电路60的数据信号无法传输至锁存子电路80。
需要说明的是，来自选择子电路60的数据信号，可以是在第一数据信号端SI1处接收的数据信号，也可也是在第二数据信号端SI2处接收的数据信号。并且，该数据信号与时钟脉冲信号端CP的信号有关。
以图7为例，在L阶段，在时钟脉冲信号端CP处接收的信号为高电平信号，选择子电路60将在第一数据信号端SI1处接收的R1信号传输至第一控制子电路70，第一控制子电路70在第一控制信号端CT1处接收的开启信号的控制下导通，将来自选择子电路60的R1信号传输至锁存子电路80。
在M阶段，在时钟脉冲信号端CP处接收的信号为低电平信号，选择子电路60将在第二数据信号端SI2处接收的R4信号传输至第一控制子电路70，第一控制子电路70在第一控制信号端CT1处接收的开启信号的控制下导通，将来自选择子电路60的R4信号传输至锁存子电路80。
锁存子电路80在第一电压端V1处接收的固定电压信号的作用下，对数据信号进行锁存。
需要说明的是，固定电压信号例如可以是直流低电平信号，也可以是直流高电平信号。在锁存子电路80包括与非门81的情况下，固定电压信号与与非门81具体的结构有关。
第二控制子电路90在第二控制信号端CT2处接收的开启信号的控制下， 将锁存在锁存子电路80内部的数据信号传输至信号输出端OUT。
在第一控制子电路70导通的情况下，来自选择子电路60的数据信号传输至锁存子电路80，锁存子电路80对该数据信号进行锁存。在第二控制信号端CT2处接收的信号为截止信号的情况下，数据信号一直锁存在锁存子电路80中。在第二控制信号端CT2处接收的信号为开启信号的情况下，第二控制子电路90将锁存在锁存子电路80内部的数据信号传输至信号输出端OUT。数据信号经信号输出端OUT传输至数据线DL。
需要说明的是，第二控制信号端CT2处接收开启信号的时刻，可以与第一控制信号端CT1处接收开启信号的时刻相同，也可以不同，根据需要合理设置即可。
本公开实施例提供的数据锁存电路LAT的驱动方法，数据锁存电路LAT分别与第一数据信号端SI1和第二数据信号端SI2耦接，一个数据锁存电路LAT可以在不同时间段分别将在第一数据信号端SI1处接收的数据信号传输至信号输出端OUT，将在第二数据信号端SI2处接收的数据信号传输至信号输出端OUT。这样一来，在显示面板包括多个数据锁存电路LAT的情况下，在同一时间段，一部分数据锁存电路LAT接收第一数据信号端SI1传输的数据信号，另一部分的数据锁存电路LAT接收第二数据信号端SI2传输的数据信号。
在此情况下，以显示面板包括8个数据锁存电路LAT为例，相关技术中数据锁存电路LAT将8个数据信号传输至数据线DL需要的时间为8个脉冲，而本公开中的数据锁存电路LAT将8个数据信号传输至数据线DL需要的时间为4个脉冲，因此，本公开中的数据锁存电路LAT可以缩短将数据信号传输至数据线DL的时间，提高数据信号的传输速度，从而提高显示装置的刷新频率。
本公开的一些实施例还提供一种数据锁存器30，如图8所示，包括N个如上述任一实施例中的数据锁存电路LAT(图8中以数据锁存器30包括8个数据锁存电路LAT为例进行示意)，其中，N为大于2的偶数。
不同数据锁存电路与不同的时钟脉冲信号端CP耦接，且与不同的第一控制信号端CT1耦接。
例如，N可以为4、6或8等。
以下以N等于8为例，示例一种上述数据锁存器30的工作过程，其中，将第1级至第4级数据锁存电路LAT划分为第一组，将第5级至第8级数据锁存电路LAT划分为第二组。如图9所示，数据锁存器30在L阶段时：
S10、CP1＝1，CT1-1＝1，CT2＝0。如图10所示，第一级数据锁存电路LAT1中，在时钟脉冲信号端CP1处接收第一信号，第一控制信号端CT1-1处接收开启信号，在第一电压端V1处接收固定电压信号，第一级数据锁存电路LAT1将在第一数据信号端SI1处接收的R1信号锁存。
在此阶段，在第一组中，只有第1级数据锁存电路LAT1接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第2级数据锁存电路LAT2、第3级数据锁存电路LAT3和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
与此同时，CP5＝0，CT1-5＝1，CT2＝0。如图10所示，第5级数据锁存电路LAT5中，在时钟脉冲信号端CP5处接收第二信号，在第一控制信号端CT1-5处接收开启信号，在第一电压端V1处接收固定电压信号，第5级数据锁存电路LAT5将在第二数据信号端SI2处接收的R2信号锁存。
在此阶段，在第二组中，只有第5级数据锁存电路LAT5接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第6级数据锁存电路LAT6、第7级数据锁存电路LAT7和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S20、CP1＝0，CT1-1＝0，CT2＝0。在时钟脉冲信号端CP1处接收第二信号，在第一控制信号端CT1-1处接收截止信号，在第一电压端V1处接收固定电压信号，第1级数据锁存电路LAT1将在第一数据信号端SI1处接收的R1信号锁存在第1级数据锁存电路LAT1中。
在此阶段中，虽然第1级数据锁存电路LAT1接收的来自第二数据信号端SI2的数据信号，但是由于在第一控制信号端CT1-1处接收的信号是截止信号，所以第1级数据锁存电路LAT1并未对来自第二数据信号端SI2的数据信号进行锁存。
CP5＝1，CT1-5＝0，CT2＝0。在时钟脉冲信号端CP5处接收第一信号，在第一控制信号端CT1-5处接收截止信号，在第一电压端V1处接收固定电压信号，第5级数据锁存电路LAT5将在第二数据信号端SI2处接收的R2信号锁存在第5级数据锁存电路LAT5中。
在此阶段中，虽然第5级数据锁存电路LAT5接收来自第一数据信号端SI1的数据信号，但是由于在第一控制信号端CT1-5处接收的信号是截止信号，所以第5级数据锁存电路LAT5并未对来自第一数据信号端SI1上的数据信号 进行锁存。
与此同时，CP2＝1，CLK2-1＝1，CT2＝0。如图11所示，第2级数据锁存电路LAT2中，在时钟脉冲信号端CP2处接收第一信号，在第一控制信号端CT1-2处接收开启信号，在第一电压端V1处接收固定电压信号，第2级数据锁存电路LAT2将在第一数据信号端SI1处接收的G1信号锁存。
在此阶段，在第一组中，只有第2级数据锁存电路LAT2接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第1级数据锁存电路LAT1、第3级数据锁存电路LAT3和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
如图11所示，CP6＝0，CT1-6＝1，CT2＝0。第6级数据锁存电路LAT6中，在时钟脉冲信号端CP6处接收第二信号，在第一控制信号端CT1-6处接收开启信号，在第一电压端V1处接收固定电压信号，第6级数据锁存电路LAT6将在第二数据信号端SI2处接收的G2信号锁存。
在此阶段，在第二组中，只有第6级数据锁存电路LAT6接收第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第7级数据锁存电路LAT7和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S30、CP2＝0，CT1-2＝0，CT2＝0。第2级数据锁存电路LAT2的时钟脉冲信号端CP2接收第二信号，在第一控制信号端CT1-2处接收截止信号，在第一电压端V1处接收固定电压信号，第2级数据锁存电路LAT2将在第一数据信号端SI1处接收的G1信号锁存在第2级数据锁存电路LAT2中。
CP6＝1，CT1-6＝0，CT2＝0。第6级数据锁存电路LAT6的时钟脉冲信号端CP6接收第一信号，在第一控制信号端CT1-6处接收截止信号，在第一电压端V1处接收固定电压信号，第6级数据锁存电路LAT6将在第2数据信号端SI2处接收的G2信号锁存在第6级数据锁存电路LAT6中。
与此同时，CP3＝1，CT1-3＝1，CT2＝0。如图12所示，第3级数据锁存电路LAT3中，在时钟脉冲信号端CP3处接收第一信号，在第一控制信号端CT1-3处接收开启信号，在第一电压端V1处接收固定电压信号，第3级数据锁存电路LAT3将在第一数据信号端SI1处接收的B1信号锁存。
在此阶段，在第一组中，只有第3级数据锁存电路LAT3接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第1级数据锁存电路 LAT1、第2级数据锁存电路LAT2和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
如图12所示，CP7＝0，CT1-7＝1，CT2＝0。第7级数据锁存电路LAT7中，在时钟脉冲信号端CP7处接收第二信号，在第一控制信号端CT1-7处接收开启信号，在第一电压端V1处接收固定电压信号，第7级数据锁存电路LAT7将在第二数据信号端SI2处接收的B2信号锁存。
在此阶段，在第二组中，只有第7级数据锁存电路LAT7接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第6级数据锁存电路LAT6和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S40、CP3＝0，CT1-3＝0，CT2＝1。第3级数据锁存电路LAT3的时钟脉冲信号端CP3接收第二信号，在第一控制信号端CT1-3处接收截止信号，在第一电压端V1处接收固定电压信号，第3级数据锁存电路LAT3将在第一数据信号端SI1处接收的B1信号锁存在第3级数据锁存电路LAT3中。
CP7＝1，CT1-7＝0，CT2＝1。第7级数据锁存电路LAT7的时钟脉冲信号端CP7接收第一信号，在第一控制信号端CT1-7处接收截止信号，在第一电压端V1处接收固定电压信号，第7级数据锁存电路LAT7将在第二数据信号端SI2处接收的B2信号锁存在第7级数据锁存电路LAT7中。
与此同时，CP4＝1，CT1-4＝1，CT2＝1。如图13所示，第4级数据锁存电路LAT4中，在时钟脉冲信号端CP4处接收第一信号，在第一控制信号端CT1-4处接收开启信号，在第一电压端V1处接收固定电压信号，第4级数据锁存电路LAT4将在第一数据信号端SI1处接收的D1信号锁存。
在此阶段，在第一组中，只有第4级数据锁存电路LAT4接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第1级数据锁存电路LAT1、第2级数据锁存电路LAT2和第3级数据锁存电路LAT3)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
如图13所示，CP8＝0，CT1-8＝1，CT2＝1。第8级数据锁存电路LAT8中，在时钟脉冲信号端CP8处接收第二信号，在第一控制信号端CT1-8处接收开启信号，在第一电压端V1处接收固定电压信号，第8级数据锁存电路LAT8将在第二数据信号端SI2处接收的D2信号锁存。
在此阶段，在第二组中，只有第8级数据锁存电路LAT8接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第6级数据锁存电路LAT6和第7级数据锁存电路LAT7)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
与此同时，如图13所示，CT2＝1，在第二控制信号端CT2处接收的开启信号的控制下，锁存在第一级数据锁存电路LAT1、第二级数据锁存电路LAT2、第三级数据锁存电路LAT3、第四级数据锁存电路LAT4、第五级数据锁存电路LAT5、第六级数据锁存电路LAT6、第七级数据锁存电路LAT7、第八级数据锁存电路LAT8中的数据信号同时传输至与各信号输出端OUT耦接的8根数据线DL。
在M阶段：
S100、CP1＝0，CT1-1＝1，CT2＝0。第一级数据锁存电路LAT1中，在时钟脉冲信号端CP1处接收的第二信号不变，在第一控制信号端CT11处接收开启信号，在第一电压端V1处接收固定电压信号，第1级数据锁存电路LAT1将在第二数据信号端SI2处接收的R4信号锁存。
在此阶段，在第一组中，只有第1级数据锁存电路LAT1接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第2级数据锁存电路LAT2、第3级数据锁存电路LAT3和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
与此同时，CP5＝1，CT1-5＝1，CT2＝0。第5级数据锁存电路LAT5中，在时钟脉冲信号端CP5处接收的第一信号不变，在第一控制信号端CT15处接收开启信号，在第一电压端V1处接收固定电压信号，第5级数据锁存电路LAT5将在第一数据信号端SI1处接收的R3信号锁存。
在此阶段，在第二组中，只有第5级数据锁存电路LAT5接收第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第6级数据锁存电路LAT6、第7级数据锁存电路LAT7和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S200、CP1＝1，CT1-1＝0，CT2＝0。第1级数据锁存电路LAT1的第一控制信号端CT1-1接收截止信号，在第一电压端V1处接收固定电压信号，第1级数据锁存电路LAT1将在第二数据信号端SI2处接收的R4信号锁存在 第1级数据锁存电路LAT1中。
CP5＝1，CT1-5＝0，CT2＝0。第5级数据锁存电路LAT5的第一控制信号端CT1-5接收截止信号，在第一电压端V1处接收固定电压信号，在第一数据信号端SI1处接收的R3信号锁存在第5级数据锁存电路LAT5中。
与此同时，CP2＝0，CLK2-1＝1，CT2＝0。第2级数据锁存电路LAT2中，在时钟脉冲信号端CP2处接收的第二信号不变，在第一控制信号端CT1-2处接收开启信号，在第一电压端V1处接收固定电压信号，第2级数据锁存电路LAT2将在第二数据信号端SI2处接收的G4信号锁存。
在此阶段，在第一组中，只有第2级数据锁存电路LAT2接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第1级数据锁存电路LAT1、第3级数据锁存电路LAT3和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
CP6＝1，CT1-6＝1，CT2＝0。第6级数据锁存电路LAT6中，在时钟脉冲信号端CP6处接收的第一信号不变，在第一控制信号端CT1-6处接收开启信号，在第一电压端V1处接收固定电压信号，第6级数据锁存电路LAT6将在第一数据信号端SI1处接收的G3信号锁存。
在此阶段，在第二组中，只有第6级数据锁存电路LAT6接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第7级数据锁存电路LAT7和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S300、CP2＝1，CT1-2＝0，CT2＝0。第2级数据锁存电路LAT2的第一控制信号端CT1-2接收截止信号，在第一电压端V1处接收固定电压信号，第2级数据锁存电路LAT2将在第二数据信号端SI2处接收的G4信号锁存在第2级数据锁存电路LAT2中。
CP6＝0，CT1-6＝0，CT2＝0。第6级数据锁存电路LAT6的第一控制信号端CT1-6接收截止信号，在第一电压端V1处接收固定电压信号，第6级数据锁存电路LAT6将在第一数据信号端SI1处接收的G3信号锁存在第6级数据锁存电路LAT6中。
与此同时，CP3＝0，CT1-3＝1，CT2＝0。第3级数据锁存电路LAT3中，在时钟脉冲信号端CP3处接收的第二信号不变，在第一控制信号端CT1-3处接收开启信号，在第一电压端V1处接收固定电压信号，第3级数据锁存电路 LAT3将在第二数据信号端SI2处接收的B4信号锁存。
在此阶段，在第一组中，只有第3级数据锁存电路LAT3接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第2级数据锁存电路LAT2、第3级数据锁存电路LAT3和第4级数据锁存电路LAT4)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
CP7＝1，CT1-7＝1，CT2＝0。第7级数据锁存电路LAT7中，在时钟脉冲信号端CP7处接收的第一信号不变，在第一控制信号端CT1-7处接收开启信号，在第一电压端V1处接收固定电压信号，第7级数据锁存电路LAT7将在第一数据信号端SI1处接收的B3信号锁存。
在此阶段，在第二组中，只有第7级数据锁存电路LAT7接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第6级数据锁存电路LAT6和第8级数据锁存电路LAT8)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
然后，S400、CP3＝1，CT1-3＝0，CT2＝1。第3级数据锁存电路LAT3的第一控制信号端CT1-3接收截止信号，在第一电压端V1处接收固定电压信号，第3级数据锁存电路LAT3将在第二数据信号端SI2处接收的B4信号锁存在第3级数据锁存电路LAT3中。
CP7＝0，CT1-7＝0，CT2＝1。第7级数据锁存电路LAT7的第一控制信号端CT1-7接收截止信号，在第一电压端V1处接收固定电压信号，第7级数据锁存电路LAT7将在第一数据信号端SI1处接收的B3信号锁存在第7级数据锁存电路LAT7中。
与此同时，CP4＝0，CT1-4＝1，CT2＝1。第四级数据锁存电路LAT4中，在时钟脉冲信号端CP4处接收的第二信号不变，在第一控制信号端CT1-4处接收开启信号，在第一电压端V1处接收固定电压信号，第4级数据锁存电路LAT4将在第二数据信号端SI2处接收的D4信号锁存。
在此阶段，在第一组中，只有第4级数据锁存电路LAT4接收来自第二数据信号端SI2的数据信号，其他三级数据锁存电路(即第1级数据锁存电路LAT1、第2级数据锁存电路LAT2和第3级数据锁存电路LAT3)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
CP8＝1，CT1-8＝1，CT2＝1。第8级数据锁存电路LAT8中，在时钟脉冲 信号端CP8处接收的第一信号不变，在第一控制信号端CT1-8处接收开启信号，在第一电压端V1处接收固定电压信号，第8级数据锁存电路LAT8将在第一数据信号端SI1处接收的D3信号锁存。
在此阶段，在第二组中，只有第8级数据锁存电路LAT8接收来自第一数据信号端SI1的数据信号，其他三级数据锁存电路(即第5级数据锁存电路LAT5、第6级数据锁存电路LAT6和第7级数据锁存电路LAT7)既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
与此同时，CT2＝1，如图14所示，在第二控制信号端CT2处接收开启信号，锁存在第一级数据锁存电路LAT1、第二级数据锁存电路LAT2、第三级数据锁存电路LAT3、第四级数据锁存电路LAT4、第五级数据锁存电路LAT5、第六级数据锁存电路LAT6、第七级数据锁存电路LAT7、第八级数据锁存电路LAT8中的数据信号同时传输至与各信号输出端OUT耦接的8根数据线DL。
重复上述L阶段和M阶段，直至所有的数据线DL上均传输信号。
本公开实施例提供的数据锁存器30，每一级数据锁存电路均与第一数据信号端SI1和第二数据信号端SI2耦接，每一级数据锁存电路在不同时间段既可以将在第一数据信号端SI1处接收的数据信号传输至信号输出端OUT，又可以将在第二数据信号端SI2处接收的数据信号传输至信号输出端OUT。这样一来，在数据传输的过程中，数据锁存器30中的一部分数据锁存电路LAT接收来自第一数据信号端SI1的数据信号，与此同时，另一部分数据锁存电路LAT接收来自第二数据信号端SI2的数据信号。
在此情况下，以显示面板包括8个数据锁存电路LAT为例，相关技术中的数据锁存器30将8个数据信号传输至数据线DL需要的时间为8个脉冲，而本公开中的数据锁存器30将8个数据信号传输至数据线DL需要的时间为4个脉冲，因此，本公开中的数据锁存电路LAT可以缩短将数据信号传输至数据线DL的时间，提高数据信号的传输速度，从而提高显示装置的刷新频率。
由表1所示，在显示装置中需要传输的数据量固定的情况下，相关技术中，在显示装置的刷新频率为2MHZ的情况下，每个脉冲的持续时间能达到0.85ns。而本公开中，在显示装置的刷新频率为2MHZ的情况下，每个脉冲的持续时间能达到1.6ns，所以，在相同刷新率情况下，本公开中每个脉冲的时间增加接近两倍，冗余量大大增加，可延长信号的持续时间，保证充电时间充足。
而在相关技术中和本公开中每个脉冲的持续时间均为0.85ns的情况下，由于相关技术中的显示装置传输一组数据信号需要8个脉冲，而本公开中的显示装置传输一组数据信号需4个脉冲，因此，相关技术中的显示装置的刷新频率只能达到2MHZ，而本公开中的显示装置的刷新频率可达到3.7MHZ，提高了刷新频率。
表1本公开和相关技术中的显示装置的参数对比
Figure PCTCN2020080909-appb-000001
在一些实施例中，如图8所示，N个数据锁存电路LAT与同一第一数据信号端SI1耦接。在此情况下，显示装置的线路排布得到简化。
在一些实施例中，如图8所示，N个数据锁存电路LAT与同一第二数据信号端SI2耦接。在此情况下，显示装置的线路排布得到简化。
在一些实施例中，如图8所示，N个数据锁存电路LAT与同一第二控制信号端CT2耦接。在此情况下，显示装置的线路排布得到简化。
在一些实施例中，如图8所示，N个数据锁存电路LAT与同一第一电压端V1耦接。在此情况下，显示装置的线路排布得到简化。
本公开的实施例提供一种数据锁存器30的驱动方法，基于上述任一实施例中的数据锁存器30，将数据锁存器30包括的N个数据锁存电路LAT均分为两组，数据锁存器30的驱动方法包括：
依次控制第一组中的N/2个数据锁存电路LAT锁存第一数据信号端SI1处接收的数据信号；在同一时段内，依次控制第二组中的N/2个数据锁存电路LAT锁存第二数据信号端SI2处接收的数据信号。
可以理解的是，控制第一组中的第i级数据锁存电路LAT1-i锁存第一数据信号端SI1的数据信号时，在同一时段内，控制第一组中的其他数据锁存电路LAT与第一数据信号端SI1和第二数据信号端SI2断开。其中，1≤i≤N/2，且i为正整数。
例如，在N＝8的情况下，i可以为1、2、3或者4。
也就是说，当第一组中的第i级数据锁存电路LAT1-i接收来自第一数据 信号端SI1的数据信号时，第一组中的其他数据锁存电路既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
如图15所示，以N等于8，第一组和第二组分别包括4个数据锁存电路LAT为例。
在驱动过程中，第一组中的第1级数据锁存电路LAT1-1接收来自第一数据信号端SI1的数据信号时，第一组中的第2级数据锁存电路LAT1-2、第3级数据锁存电路LAT1-3和第4级数据锁存电路LAT1-4均既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
需要说明的是，数据锁存电路LAT在显示面板上的排布顺序，可以根据需要合理设置，图15中的数据锁存电路LAT的排序仅是以驱动顺序为例，并不是排布顺序。
同理，当第二组中的第i级数据锁存电路LAT2-i锁存来自第二数据信号端SI2的数据信号时，在同一时段内，第二组中的其他数据锁存电路与第一数据信号端SI1和第二数据信号端SI2断开；其中，1≤i≤N/2，且i为正整数。
也就是说，第二组中的第i级数据锁存电路LAT2-i接收来自第二数据信号端SI2的数据信号时，第二组中的其他数据锁存电路LAT既不接收来自第一数据信号端SI1的数据信号，也不接收来自第二数据信号端SI2的数据信号。
在第二控制信号端CT2处接收的信号的控制下，N个数据锁存电路LAT将锁存在各自内部的数据信号传输至信号输出端OUT。
示例性地，数据锁存器30中的N个数据锁存电路LAT的第二控制信号端CT2同时接收开启信号，N个数据锁存电路LAT将锁存在各自内部的数据信号同时传输至信号输出端OUT。
如图1所示，本公开的一些实施例提供一种显示装置200。
显示装置200例如可以是手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑、可穿戴显示设备等，例如可以为手表。本公开实施例对上述显示装置的具体形式不做特殊限制。其中，显示装置可以是显示面板，也可以是包含显示面板和边框等结构的装置。以下以显示装置为包括边框等结构的装置为例进行示意。
显示装置200包括如图1所示的显示面板10。该显示面板10具有有效显示区(Active Area，AA)100和位于该有效显示区100周边的周边区101。有效显示区100包括多个亚像素(sub pixel)20。
为了方便说明，本公开的实施例中上述多个亚像素20是以矩阵形式排列为例进行的说明。此时，沿水平方向X排列成一排的亚像素20称为同一行亚 像素，沿竖直方向Y排列成一排的亚像素20称为同一列亚像素，同一行亚像素可以与一根栅线GL连接，同一列亚像素可以与一根数据线DL连接。亚像素20内设置有用于控制亚像素20进行显示的像素电路201，像素电路201设置在显示面板10的衬底基板上。
以下以显示面板10为液晶显示面板为例，对亚像素20中的像素电路201进行举例说明。当然，显示面板10也可以是发光二极管显示面板，如有机发光二极管(organic light emitting diode，OLED)显示面板。
示例性的，如图2所示，像素电路201包括晶体管M和液晶电容C。该液晶电容C的两个极板分别由像素电极和公共电极构成。晶体管M的栅极连接栅线GL，第一极连接数据线DL，第二极连接液晶电容C，用于将数据线DL上的数据信号传输至液晶电容C。
如图2所示，每根数据线DL上接收数据信号，以显示面板10包括P列亚像素20为例，有P根数据线DL需要接收数据信号。
其中，显示装置200采用SPI技术，每根数据线DL与一个数据锁存电路LAT耦接，通过数据锁存电路LAT向数据线DL传输数据信号。
在一些实施例中，当将本公开提供的数据锁存器应用于上述显示装置200时，显示装置200中包括的多根数据线DL可划分为多组，每组包括N根数据线DL。
在此情况下，如图15所示，每组所包括的N根数据线DL分别与数据锁存器30所包括的N个数据锁存电路LAT的信号输出端OUT耦接。
示例性地，显示装置200中的多个像素呈阵列式排布。每列像素包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素。
其中，第一颜色、第二颜色和第三颜色为三基色，例如，红色、蓝色和绿色。
在此情况下，数据锁存器30包括至少6个数据锁存电路LAT。其中，奇数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与数据锁存器30中的3个数据锁存电路LAT的信号输出端OUT耦接；偶数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与数据锁存器30中的另外3个数据锁存电路LAT的信号输出端OUT耦接。
此外，每列像素还包括第四颜色亚像素，例如，第四颜色可以为白色。在此情况下，数据锁存器30包括8个数据锁存电路LAT。其中，奇数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素 通过4根数据线，分别与数据锁存器30中的4个数据锁存电路LAT的信号输出端OUT耦接；偶数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素通过4根数据线，分别与数据锁存器30中的另外4个数据锁存电路LAT的信号输出端OUT耦接。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种数据锁存电路，包括：
    选择子电路，与第一数据信号端、第二数据信号端和时钟脉冲信号端耦接；所述选择子电路被配置为，在所述时钟脉冲信号端处接收的信号的控制下，在不同时间段内，传输在所述第一数据信号端处接收的数据信号和在所述第二数据信号端处接收的数据信号；
    第一控制子电路，与所述选择子电路和第一控制信号端耦接；所述第一控制子电路被配置为，在所述第一控制信号端处接收的信号的控制下，传输来自所述选择子电路的数据信号；
    锁存子电路，与所述第一控制子电路和第一电压端耦接；所述锁存子电路被配置为，接收来自所述第一控制子电路的数据信号，并在所述第一电压端的电压的作用下锁存该数据信号；
    第二控制子电路，与所述锁存子电路、第二控制信号端和信号输出端耦接；所述第二控制子电路被配置为，在所述第二控制信号端处接收的信号的控制下，将锁存在所述锁存子电路内部的数据信号传输至所述信号输出端。
  2. 根据权利要求1所述的数据锁存电路，其中，所述选择子电路包括：
    多路选择器；所述多路选择器的通道选择信号端与所述时钟脉冲信号端耦接，所述多路选择器的第一输入端与所述第一数据信号端耦接，所述多路选择器的第二输入端与所述第二数据信号端耦接，所述多路选择器的输出端与所述第一控制子电路耦接。
  3. 根据权利要求1或2所述的数据锁存电路，其中，所述第一控制子电路包括：
    第一传输门子电路；所述第一传输门子电路的控制端与所述第一控制信号端耦接，所述第一传输门子电路的输入端与所述选择子电路耦接，所述第一传输门子电路的输出端与所述锁存子电路耦接。
  4. 根据权利要求1～3中任一项所述的数据锁存电路，其中，所述锁存子电路包括：
    与非门，所述与非门的第一输入端与所述第一控制子电路耦接，所述与非门的第二输入端与所述第一电压端耦接，所述与非门的输出端与所述第二控制子的电路耦接；
    反向器，所述反向器的输入端与所述与非门的输出端和所述第二控制子电路耦接，所述反向器的输出端与所述与非门的第一输入端耦接。
  5. 根据权利要求1～4中任一项所述的数据锁存电路，其中，所述第二控制子电路包括：
    第二传输门子电路；所述第二传输门子电路的控制端与所述第二控制信号端耦接，所述第二传输门子电路的输入端与所述锁存子电路耦接，所述第二传输门子电路的输出端与所述信号输出端耦接。
  6. 根据权利要求1～5中任一项所述的数据锁存电路，还包括：
    放大器；所述放大器与所述第二控制子电路和所述信号输出端耦接；所述放大器被配置为，对来自所述第二控制子电路的信号进行放大，并将放大后的信号传输至所述信号输出端。
  7. 一种数据锁存器，包括：
    N个如权利要求1～6中任一项所述的数据锁存电路；其中，N为大于2的偶数；
    不同所述数据锁存电路与不同的时钟脉冲信号端耦接，且与不同的第一控制信号端耦接。
  8. 根据权利要求7所述的数据锁存器，其中，N个所述数据锁存电路与同一第一数据信号端耦接。
  9. 根据权利要求7或8所述的数据锁存器，其中，N个所述数据锁存电路与同一第二数据信号端耦接。
  10. 根据权利要求7～9中任一项所述的数据锁存器，其中，N个所述数据锁存电路与同一第二控制信号端耦接。
  11. 根据权利要求7～10中任一项所述的数据锁存器，其中，N为6或者8。
  12. 一种显示装置，包括：
    如权利要求7～11中任一项所述的数据锁存器。
  13. 根据权利要求12所述的显示装置，还包括：
    多根数据线，所述多根数据线分为多组，每组包括N根数据线，每组所包括的N根数据线分别与所述数据锁存器所包括的N个数据锁存电路的信号输出端耦接。
  14. 根据权利要求13所述的显示装置，其中，所述数据锁存器包括至少6个数据锁存电路；
    所述显示装置还包括：阵列式排布的多个像素，每列像素包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素；
    奇数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与所述数据锁存器中的3个数据锁存电路的信号输出端耦接；
    偶数列像素中的第一颜色亚像素、第二颜色亚像素和第三颜色亚像素通过3根数据线，分别与所述数据锁存器中的另外3个数据锁存电路的信号输出端耦接。
  15. 根据权利要求14所述的显示装置，其中，所述数据锁存器包括8个数据锁存电路；
    每列像素还包括第四颜色亚像素；
    奇数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素通过4根数据线，分别与所述数据锁存器中的4个数据锁存电路的信号输出端耦接；
    偶数列像素中的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素和第四颜色亚像素通过4根数据线，分别与所述数据锁存器中的另外4个数据锁存电路的信号输出端耦接。
  16. 一种如权利要求1～6中任一项所述的数据锁存电路的驱动方法，包括：
    选择子电路在时钟脉冲信号端处接收的第一信号的控制下，将在第一数据信号端处接收的数据信号传输至第一控制子电路；或者，选择子电路在时钟脉冲信号端处接收的第二信号的控制下，将在第二数据信号端处接收的数据信号传输至第一控制子电路；
    所述第一控制子电路在第一控制信号端处接收的开启信号的控制下，将所述数据信号传输至锁存子电路；
    所述锁存子电路在第一电压端处接收的固定电压信号的作用下，对所述数据信号进行锁存；
    第二控制子电路在第二控制信号端处接收的开启信号的控制下，将锁存在所述锁存子电路内部的所述数据信号传输至信号输出端。
  17. 一种如权利要求7～11中任一项所述的数据锁存器的驱动方法，N个数据锁存电路均分为两组；
    所述数据锁存器的驱动方法，包括：
    第一组中的N/2个数据锁存电路依次锁存第一数据信号端处接收的数据信号；在同一时段内，第二组中的N/2个数据锁存电路依次锁存第二数据信号端处接收的数据信号；
    所述N个数据锁存电路将锁存在各自内部的数据信号传输至信号输出端。
  18. 根据权利要求17所述的数据锁存器的驱动方法，其中，所述N个数 据锁存电路将锁存在各自内部的数据信号传输至信号输出端，包括：
    所述N个数据锁存电路的第二控制信号端同时接收开启信号，将存储在各自内部的数据信号同时传输至信号输出端。
PCT/CN2020/080909 2019-04-16 2020-03-24 数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置 WO2020211604A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910303629.6 2019-04-16
CN201910303629.6A CN109920362B (zh) 2019-04-16 2019-04-16 数据锁存单元及驱动方法、数据锁存器及驱动方法、显示装置

Publications (1)

Publication Number Publication Date
WO2020211604A1 true WO2020211604A1 (zh) 2020-10-22

Family

ID=66977397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/080909 WO2020211604A1 (zh) 2019-04-16 2020-03-24 数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置

Country Status (2)

Country Link
CN (1) CN109920362B (zh)
WO (1) WO2020211604A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920362B (zh) * 2019-04-16 2021-04-30 京东方科技集团股份有限公司 数据锁存单元及驱动方法、数据锁存器及驱动方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072452A (en) * 1997-11-14 2000-06-06 Aurora Systems, Inc. System and method for using forced states to improve gray scale performance of a display
WO2009051361A2 (en) * 2007-10-18 2009-04-23 Mc Technology Co., Ltd. Output voltage amplifier and driving device of liquid crystal display using the same
CN105551451A (zh) * 2016-01-04 2016-05-04 友达光电股份有限公司 液晶显示器
CN105575316A (zh) * 2016-02-29 2016-05-11 厦门天马微电子有限公司 多路选择电路、显示面板和显示装置
CN108630166A (zh) * 2018-07-02 2018-10-09 京东方科技集团股份有限公司 像素记忆电路、液晶显示器和可穿戴设备
CN109920362A (zh) * 2019-04-16 2019-06-21 京东方科技集团股份有限公司 数据锁存单元及驱动方法、数据锁存器及驱动方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256633B1 (en) * 2003-05-01 2007-08-14 Ample Communications, Inc. Systems for implementing high speed and high integration chips
CN101404135B (zh) * 2008-11-03 2014-07-30 深圳市中庆光电显示科技开发有限公司 一种提高刷新速率的方法、扫描控制装置及显示系统
US8836399B2 (en) * 2013-02-05 2014-09-16 Texas Instruments Incorporated Positive edge flip-flop with dual-port slave latch
US9496854B2 (en) * 2015-03-10 2016-11-15 International Business Machines Corporation High-speed latch circuits by selective use of large gate pitch
CN105243982B (zh) * 2015-10-12 2018-03-13 深圳天珑无线科技有限公司 一种用于显示器的驱动控制器和驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072452A (en) * 1997-11-14 2000-06-06 Aurora Systems, Inc. System and method for using forced states to improve gray scale performance of a display
WO2009051361A2 (en) * 2007-10-18 2009-04-23 Mc Technology Co., Ltd. Output voltage amplifier and driving device of liquid crystal display using the same
CN105551451A (zh) * 2016-01-04 2016-05-04 友达光电股份有限公司 液晶显示器
CN105575316A (zh) * 2016-02-29 2016-05-11 厦门天马微电子有限公司 多路选择电路、显示面板和显示装置
CN108630166A (zh) * 2018-07-02 2018-10-09 京东方科技集团股份有限公司 像素记忆电路、液晶显示器和可穿戴设备
CN109920362A (zh) * 2019-04-16 2019-06-21 京东方科技集团股份有限公司 数据锁存单元及驱动方法、数据锁存器及驱动方法、显示装置

Also Published As

Publication number Publication date
CN109920362A (zh) 2019-06-21
CN109920362B (zh) 2021-04-30

Similar Documents

Publication Publication Date Title
CN101000414B (zh) 液晶显示器
WO2020173262A1 (zh) 显示面板、显示装置及驱动方法
US6566643B2 (en) Electro-optical device, method of driving the same, and electronic apparatus using the same
CN103915069B (zh) 显示面板的驱动电路及其驱动模块与显示设备和制造方法
US10971104B2 (en) Shift register and method for driving the same, gate driving circuit, and display device
JP2004309669A (ja) アクティブマトリクス型表示装置とその駆動方法
US20220327987A1 (en) Display substrate, display panel, display apparatus and display driving method
CN101930706A (zh) 信号线驱动电路、显示装置和电子装置
CN101303895B (zh) 移位缓存器
CN107452351A (zh) 一种移位寄存器、其驱动方法、驱动控制电路及显示装置
US20230207031A1 (en) Shift register and driving method therefor, gate driver circuit, and display apparatus
WO2020142923A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
JP2021534438A (ja) シフトレジスタユニット、ゲート駆動回路、表示装置及び駆動方法
US11244595B2 (en) Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
KR20050000012A (ko) 액정표시장치의 데이터 구동회로 및 그 구동방법
CN106952625A (zh) 移位寄存器、其驱动方法、栅极驱动电路及显示面板
US20220114938A1 (en) Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
US20210225249A1 (en) Scan shift circuit, touch shift circuit, driving method and related apparatus
JP2005055813A (ja) 液晶表示装置及び液晶表示装置駆動方法
WO2020211604A1 (zh) 数据锁存电路及驱动方法、数据锁存器及驱动方法、显示装置
JP2004004242A (ja) データ処理回路、表示装置および携帯端末
US10297216B2 (en) Gate driving circuit and array substrate using the same
TW591268B (en) Active matrix type display device
WO2021016942A1 (zh) 显示面板、显示装置以及驱动方法
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20791247

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20791247

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20791247

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10.05.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20791247

Country of ref document: EP

Kind code of ref document: A1