WO2020211303A1 - 斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法 - Google Patents

斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法 Download PDF

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Publication number
WO2020211303A1
WO2020211303A1 PCT/CN2019/110218 CN2019110218W WO2020211303A1 WO 2020211303 A1 WO2020211303 A1 WO 2020211303A1 CN 2019110218 W CN2019110218 W CN 2019110218W WO 2020211303 A1 WO2020211303 A1 WO 2020211303A1
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Prior art keywords
switch
generator
integrator
terminal
voltage
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PCT/CN2019/110218
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English (en)
French (fr)
Inventor
雷述宇
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宁波飞芯电子科技有限公司
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Publication of WO2020211303A1 publication Critical patent/WO2020211303A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/52—Input signal integrated with linear return to datum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the field of signal control, in particular to a ramp generator, an analog-digital converter, and a control method for generating ramp signals.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS image sensors have low power consumption, large dynamic range, small size, and low cost. Advantages, widely used in digital cameras, scanners and cameras and other fields.
  • the ADC (English: Analog-to-Digital Converter, Chinese: Analog-to-Digital Converter) in the CMOS image sensor determines the speed and accuracy of processing data.
  • the ADC in the CMOS image sensor usually includes a ramp signal generator.
  • the ramp signal output by the ramp signal generator is usually not adjustable, and the process of the ramp signal generator or the external environment may change , So it will cause the output ramp signal to be unstable, thereby reducing the processing accuracy of the ADC.
  • the purpose of this application is to provide a ramp generator, an analog-digital converter and a control method for generating a ramp signal, so as to solve the problem of unstable ramp signal output by the ramp signal generator in the prior art.
  • a ramp generator includes a current source, a signal generator, and a controller.
  • the output terminal of the current source is connected to the signal
  • the input terminal of the generator is connected, the output terminal of the signal generator is connected with the input terminal of the controller, and the output terminal of the controller is connected with the input terminal of the current source;
  • the signal generator is configured to generate a ramp signal according to the current output by the current source
  • the controller is configured to adjust a feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source;
  • the current source is configured to control the current output by the current source according to the adjusted feedback voltage.
  • the controller includes a differential integrator, the differential integrator includes a differential module and an integrator; the output terminal of the differential module is connected with the input terminal of the integrator, and the output terminal of the integrator is connected with The input terminal of the current source is connected, and the input terminal of the differential module is connected with the output terminal of the signal generator;
  • the differential module is configured to perform differential processing between the output voltage of the signal generator and the first voltage, and input the obtained differential voltage to the integrator, and the output voltage of the signal generator includes the initial voltage being the reset voltage , The voltage value of the ramp signal output through the preset duration;
  • the integrator is configured to perform integration processing on the differential voltage to obtain the feedback voltage.
  • the differential module includes at least any one of the following: a resistor or a capacitor;
  • the integrator includes at least any one of the following:
  • Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
  • the integrator is the single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier, a second capacitor, a fourth capacitor, and a fifth switch ;
  • the first terminal of the second capacitor is used as the input terminal of the controller, the second terminal of the second capacitor is connected to the inverting input terminal of the second operational amplifier, and the non-inverting input of the second operational amplifier is Terminal is connected to the reference voltage, the output terminal of the second operational amplifier is used as the output terminal of the controller, the first terminal of the fifth switch is connected to the first voltage, and the first terminal of the fifth switch is The two ends are connected to the first end of the second capacitor, the first end of the fourth capacitor is connected to the inverting input end of the second operational amplifier, and the second end of the fourth capacitor is connected to the first end of the fourth capacitor. Two output terminals of the operational amplifier are connected.
  • the single-ended first-order active analog integrator further includes: a third capacitor and a tenth switch;
  • the first end of the third capacitor is connected to the second end of the second capacitor, the second end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the tenth switch is set Between the first end of the third capacitor and the reference voltage;
  • the single-ended first-order active analog integrator further includes: a sixth switch, a seventh switch, an eighth switch, a ninth switch, and an eleventh switch;
  • the second end of the eighth switch is connected to the second end of the fourth capacitor, the first end of the eighth switch is connected to the output end of the second operational amplifier, and the seventh switch is arranged on the Between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier, the ninth switch is arranged between the second terminal of the fourth capacitor and the reference voltage; the first The six switch is arranged between the first terminal of the fourth capacitor and the inverting input terminal of the second operational amplifier, and the eleventh switch is arranged between the second terminal of the third capacitor and the fourth capacitor. Between the first end of the capacitor.
  • the signal generator includes at least any one of the following:
  • First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
  • the current source includes at least any one of the following: a field effect transistor, a mirror current source, and a resistor.
  • the signal generator is the first-order active analog generator, and the first-order active analog generator includes: a first operational amplifier, a first capacitor, a connection switch, and a first switch;
  • the output terminal of the current source is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the inverting input terminal of the first operational amplifier.
  • the input terminal is connected to the reference voltage
  • the first terminal of the first capacitor is connected to the inverting input terminal of the first operational amplifier
  • the second terminal of the first capacitor is connected to the output terminal of the first operational amplifier
  • the first terminal of the connection switch is connected to the output terminal of the first operational amplifier
  • the second terminal of the connection switch is used as the output terminal of the signal generator to be connected to the controller, and the first operation
  • the output terminal of the amplifier is used as the output terminal of the ramp generator;
  • the first-order active analog generator further includes: a second switch, a third switch, and a fourth switch;
  • the first end of the fourth switch is connected to the second end of the first capacitor, the second end of the fourth switch is connected to the reset voltage, and the first end of the third switch is connected to the first operation
  • the output terminal of the amplifier is connected, the second terminal of the third switch is connected to the second terminal of the first capacitor, and the second switch is arranged at the inverting input terminal of the first operational amplifier and the first capacitor. Between the output terminals of the operational amplifier.
  • the field effect tube further includes: a twelfth switch;
  • the gate of the field effect tube is used as the input terminal of the current source, the source of the field effect tube is connected to a power source, and the drain of the field effect tube is used as the output terminal of the current source.
  • the two switches are arranged between the drain of the field effect transistor and the reference voltage.
  • an analog-to-digital converter applied to an image sensor.
  • the analog-to-digital converter includes the ramp generator, a comparator, and a latch described in the first aspect of the embodiments of the present application.
  • the output terminal of the ramp generator is connected to the first input terminal of the comparator, the second input terminal of the comparator is configured to receive a pixel signal, and the output terminal of the comparator is connected to the input terminal of the latch.
  • the output of the latch is connected to the first input of the register, the output of the counter is connected to the second input of the register, and the output of the register serves as the analog digital The output of the converter.
  • a control method for generating a ramp signal which is applied to the ramp generator described in the first aspect of the embodiments of the present application, and the method includes:
  • the current source controls the current output by the current source according to the adjusted feedback voltage.
  • the controller includes a differential integrator, the differential integrator includes a differential module and an integrator; the output terminal of the differential module is connected with the input terminal of the integrator, and the output terminal of the integrator is connected with The input terminal of the current source is connected, and the input terminal of the differential module is connected with the output terminal of the signal generator;
  • the adjusting the feedback voltage by the controller according to the ramp signal and applying the adjusted feedback voltage to the current source includes:
  • the output voltage of the signal generator and the first voltage are differentially processed by the differential module, and the obtained differential voltage is input to the integrator.
  • the output voltage of the signal generator includes the initial voltage as the reset voltage, The voltage value of the ramp signal output through the preset duration;
  • the differential voltage is integrated by the integrator to obtain the feedback voltage.
  • the differential module includes at least any one of the following: a resistor or a capacitor;
  • the integrator includes at least any one of the following:
  • Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device
  • the signal generator includes at least any one of the following:
  • First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator;
  • the current source includes at least any one of the following: a field effect tube, a mirror current source and a resistor.
  • the signal generator is the first-order active analog generator, and the first-order active analog generator includes: a first operational amplifier, a first capacitor, a connection switch, and a first switch;
  • the output terminal of the current source is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the inverting input terminal of the first operational amplifier.
  • the input terminal is connected to a reference voltage (Vref)
  • the first terminal of the first capacitor is connected to the inverting input terminal of the first operational amplifier
  • the second terminal of the first capacitor is connected to the first operational amplifier.
  • the output terminal is connected, the first terminal of the connection switch is connected to the output terminal of the first operational amplifier, the second terminal of the connection switch is used as the output terminal of the signal generator to be connected to the controller, the The output terminal of the first operational amplifier is used as the output terminal of the ramp generator;
  • the integrator is the single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier, a second capacitor, a fourth capacitor, and a fifth switch;
  • the first terminal of the second capacitor is used as the input terminal of the controller, the second terminal of the second capacitor is connected to the inverting input terminal of the second operational amplifier, and the non-inverting input of the second operational amplifier is Terminal is connected to the reference voltage, the output terminal of the second operational amplifier is used as the output terminal of the controller, the first terminal of the fifth switch is connected to the first voltage, and the first terminal of the fifth switch is The two ends are connected to the first end of the second capacitor, the first end of the fourth capacitor is connected to the inverting input end of the second operational amplifier, and the second end of the fourth capacitor is connected to the first end of the fourth capacitor. Two output terminals of the operational amplifier are connected;
  • the generating a ramp signal by the signal generator according to the current output by the current source and outputting the ramp signal to the controller includes:
  • the output voltage of the first operational amplifier is the reset voltage
  • the output voltage of the second operational amplifier is the reference
  • the adjusting the feedback voltage by the controller according to the ramp signal and applying the adjusted feedback voltage to the current source includes:
  • connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the controller is connected to the first switch according to the voltage value of the ramp signal.
  • connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the controller is controlled according to the voltage of the ramp signal And the first voltage to control the feedback voltage, including:
  • connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the final state voltage value of the ramp signal of the controller is greater than the When the first voltage is used, the feedback voltage is reduced, and when the final state voltage value of the ramp signal is less than the first voltage, the feedback voltage is increased.
  • the first-order active analog generator further includes: a second switch, a third switch, and a fourth switch;
  • the first end of the fourth switch is connected to the second end of the first capacitor, the second end of the fourth switch is connected to the reset voltage, and the first end of the third switch is connected to the first operation
  • the output terminal of the amplifier is connected, the second terminal of the third switch is connected to the second terminal of the first capacitor, and the second switch is arranged at the inverting input terminal of the first operational amplifier and the first capacitor. Between the output terminals of the operational amplifier;
  • the single-ended first-order active analog integrator further includes: a seventh switch, an eighth switch and a ninth switch;
  • the second end of the eighth switch is connected to the second end of the fourth capacitor, the first end of the eighth switch is connected to the output end of the second operational amplifier, and the seventh switch is arranged on the Between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier, a ninth switch is arranged between the second terminal of the fourth capacitor and the reference voltage;
  • the generating a ramp signal by the signal generator according to the current output by the current source and outputting the ramp signal to the controller includes:
  • the third switch, the fifth switch, and the eighth switch are controlled to close, and the connection switch, the connection switch, and the The first switch, the second switch, the fourth switch, the seventh switch, and the ninth switch are turned off so that the output voltage of the first operational amplifier is the reset voltage, and the The output voltage of the second operational amplifier is the reference voltage;
  • the adjusting the feedback voltage by the controller according to the ramp signal, and applying the adjusted feedback voltage to the current source includes:
  • connection switch, the third switch, and the eighth switch are controlled to close, and the first switch, the second switch, the fourth switch, and the first switch are controlled.
  • the fifth switch, the seventh switch and the ninth switch are turned off, so that the controller controls the feedback voltage according to the voltage value of the ramp signal and the first voltage;
  • control of the connection switch, the second switch, the fourth switch, the seventh switch, and the ninth switch is repeatedly executed until the After the first preset time period, control the connection switch, the third switch, and the eighth switch to close, and control the first switch, the second switch, the fourth switch, and the fifth switch , The step of turning off the seventh switch and the ninth switch until the preset condition is met.
  • the preset condition is that the voltage value of the ramp signal is equal to the first voltage
  • connection switch, the third switch and the eighth switch are closed to control the first switch, the second switch, the fourth switch, the fifth switch, the seventh switch and the The number of steps in which the ninth switch is turned off is equal to the preset value.
  • the field effect tube further includes: a twelfth switch;
  • the gate of the field effect tube is used as the input terminal of the current source, the source of the field effect tube is connected to a power source, and the drain of the field effect tube is used as the output terminal of the current source.
  • the two switches are arranged between the drain of the field effect transistor and the reference voltage;
  • the switch is disconnected from the eighth switch, and further includes:
  • controlling said third switch, said fifth switch and said eighth switch are closed, and controlling said connection switch, said first switch, said second switch, said fourth switch, and said seventh switch Disconnecting from the ninth switch further includes:
  • connection switch, the third switch, and the eighth switch are controlled to be closed, and the first switch, the second switch, the fourth switch, the fifth switch, and the seventh switch are controlled.
  • the switch is disconnected from the ninth switch, and further includes:
  • the single-ended first-order active analog integrator further includes: a third capacitor, a sixth switch, a tenth switch, and an eleventh switch;
  • the first end of the third capacitor is connected to the second end of the second capacitor, the second end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the sixth switch is set Between the first terminal of the fourth capacitor and the inverting input terminal of the second operational amplifier, the tenth switch is arranged between the first terminal of the third capacitor and the reference voltage, so The eleventh switch is arranged between the second end of the third capacitor and the first end of the fourth capacitor;
  • the switch is disconnected from the eighth switch, and further includes:
  • the third switch, the fifth switch, and the eighth switch are controlled to close, and the connection switch, the first switch, and the The turning off of the second switch, the fourth switch, the seventh switch and the ninth switch further includes:
  • connection switch, the third switch, and the eighth switch are controlled to be closed, and the first switch, the second switch, the fourth switch, the fifth switch, and the seventh switch are controlled.
  • the switch is disconnected from the ninth switch, and further includes:
  • the ramp generator provided by the present application includes a current source, a signal generator, and a controller.
  • the output terminal of the current source is connected to the input terminal of the signal generator, and the output terminal of the signal generator is connected to the controller.
  • the input terminal is connected, and the output terminal of the controller is connected to the input terminal of the current source.
  • the signal generator can generate a ramp signal according to the current output by the current source.
  • the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
  • the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.
  • Fig. 1 is a block diagram showing a ramp generator according to an exemplary embodiment
  • Fig. 2a is a circuit diagram of a ramp generator according to an exemplary embodiment
  • Fig. 2b is a schematic diagram of a state of the ramp generator shown in Fig. 2a;
  • Fig. 2c is a schematic diagram of another state of the ramp generator shown in Fig. 2a;
  • Fig. 3 is a circuit diagram showing another ramp generator according to an exemplary embodiment
  • Fig. 4 is a circuit diagram showing another ramp generator according to an exemplary embodiment
  • Fig. 5a is a circuit diagram of another ramp generator according to an exemplary embodiment
  • Fig. 5b is a schematic diagram of a state of the ramp generator shown in Fig. 5a;
  • Fig. 5c is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
  • Fig. 5d is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
  • Fig. 5e is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
  • Fig. 6 is a block diagram showing an analog-to-digital converter according to an exemplary embodiment
  • Fig. 7 is a flowchart showing a control method for generating a ramp signal according to an exemplary embodiment.
  • the third capacitor C3 The fourth capacitor C4
  • the sixth switch S6 The seventh switch S7
  • Fig. 1 is a block diagram showing a ramp generator according to an exemplary embodiment.
  • the ramp generator 100 includes a current source 101, a signal generator 102, and a controller 103, and the output of the current source 101 The terminal is connected with the input terminal of the signal generator 102, the output terminal of the signal generator 102 is connected with the input terminal of the controller 103, and the output terminal of the controller 103 is connected with the input terminal of the current source 101.
  • the signal generator 102 is configured to generate a ramp signal according to the current output by the current source 101.
  • the controller 103 is configured to adjust the feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source 101.
  • the current source 101 is configured to control the current output by the current source 101 according to the adjusted feedback voltage.
  • the current source 101 provides current for the signal generator 102, the signal generator 102 generates a ramp signal according to the current output by the current source 101, the ramp signal is used as the input of the controller 103, and the controller 103 can adjust according to the voltage of the ramp signal Regarding the magnitude of the feedback voltage, the controller 103 outputs the adjusted feedback voltage to the current source 101 (that is, the adjusted feedback voltage is applied to the current source 101), and the current source 101 acts as a signal generator according to the magnitude of the adjusted feedback voltage 102 provides current to form a closed-loop feedback control of the current source 101-signal generator 102-controller 103-current source 101 to adjust the ramp signal output by the ramp generator 100, thereby improving the stability of the ramp signal.
  • multiple switches can be set between the current source 101, the signal generator 102 and the controller 103.
  • the current source 101 and the signal generator 102 are controlled to be disconnected, and the signal generator 102 is controlled.
  • the controller 103 are charged separately.
  • the current source 101 is controlled to connect with the signal generator 102, and the signal generator 102 is controlled to discharge at the same time to generate a ramp signal.
  • the relationship between the voltage generated by the discharge of the controller 103 and the voltage generated by the controller 103 is used to adjust the feedback voltage generated by the controller 103, and finally the current output by the current source 101 is adjusted according to the adjusted feedback voltage.
  • the controller 103 may include an integrator, the output of the integrator is connected to the input of the current source 101, and the input of the integrator is connected to the output of the signal generator 102.
  • the controller 103 may include a differential integrator, and the differential integrator includes a differential module and an integrator.
  • the input terminal of the differential module is used as the input terminal of the controller 103 to connect to the output terminal of the signal generator 102, the output terminal of the differential module is connected to the input terminal of the integrator, and the output terminal of the integrator is used as the output terminal of the controller 103 and the current source The input terminal of 101 is connected.
  • the differential module is configured to perform differential processing between the output voltage of the signal generator 102 and the first voltage V_L to obtain the differential voltage output by the differential module.
  • the differential module then inputs the obtained differential voltage to the integrator, and the output voltage of the signal generator 102 includes the initial voltage being the reset voltage V_H, and the voltage value of the ramp signal output by the preset duration.
  • the integrator is configured to integrate the differential voltage to obtain the feedback voltage.
  • the first voltage V_L is the ideal voltage value of the ramp signal output by the preset duration when the initial voltage loaded on the signal generator 102 is the reset voltage V_H, that is, it can be understood that the first voltage V_L is the output of the signal generator 102 The lowest voltage of the ramp signal.
  • the differential module includes at least any one of the following: a resistor or a capacitor.
  • the integrator includes at least any of the following:
  • Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
  • the integrator in this embodiment can adopt any one of the above-mentioned different types of integrators, which can be specifically selected according to actual requirements by those skilled in the art.
  • the single-ended integrator included in the above integrator means that the input terminal of the integrator is the only port.
  • a multi-terminal integrator means that the input terminal of the integrator includes at least two ports.
  • the analog integrator included in the above integrator is an integrator that continuously integrates a signal.
  • the digital integrator is an integrator that uses numerical methods to integrate the sampled signal after directly sampling the signal according to the sampling theorem.
  • the above-mentioned integrator includes an active integrator, which means that the integrator includes an integrator that needs to be connected to a power source; a passive integrator means that the integrator includes an integrator that does not need to be connected to a power source.
  • a several-level circuit includes several energy storage elements, that is, a first-level circuit includes one energy storage element. There are two energy storage elements in the second-order circuit. Among them, the energy storage element can be an inductor or a capacitor.
  • a single-ended first-order active digital integrator includes a first-order integrator with a unique input port that integrates a sampled signal, and the integrator includes at least one device that needs to be connected to a power source.
  • the single-ended first-order active analog integrator includes a first-order integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
  • the single-ended first-order passive digital integrator includes a first-order integrator with a unique input port that integrates a sampled signal, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the single-ended first-order passive analog integrator includes a first-order integrator with a single input port that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the single-ended multi-stage active digital integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
  • the single-ended multi-stage active analog integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
  • a single-ended multi-stage passive digital integrator is a multi-stage integrator that integrates a sampled signal with a unique input port, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the single-ended multi-stage passive analog integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the multi-terminal first-order active analog integrator includes a first-order integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
  • the multi-terminal first-order passive digital integrator includes a first-order integrator with at least two input ports for integrating a sampled signal, and the integrator includes at least one device that does not need to be connected to a power source.
  • the multi-terminal first-order passive analog integrator includes a first-order integrator with at least two input ports that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the multi-terminal multi-stage active digital integrator includes a multi-stage integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
  • the multi-terminal multi-stage active analog integrator includes a multi-stage integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
  • the multi-terminal multi-stage passive digital integrator has at least two input ports and integrates the sampling signal, and the integrator includes at least one device that does not need to be connected to a power supply.
  • the multi-terminal multi-stage passive analog integrator includes a multi-stage integrator with at least two input ports that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power source.
  • the signal generator 102 may include at least one of the following generators:
  • First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
  • the generator in this embodiment may adopt any one of the above-mentioned different types of generators, which can be specifically selected according to actual requirements by those skilled in the art.
  • the above-mentioned generators include analog generators that process continuous signals; digital generators use numerical methods to process the sampled signals after directly sampling the signal according to the sampling theorem.
  • the above-mentioned generator includes an active generator means that the generator includes a generator that needs to be connected to a power source; a passive generator means that the generator includes a generator that does not need to be connected to a power source.
  • a circuit of several levels includes several energy storage elements, that is, a circuit of one order includes one energy storage element.
  • the energy storage element can be an inductor or a capacitor.
  • the first-order active analog generator includes a first-order generator that processes continuous signals, and the generator includes at least one device that needs to be connected to a power source.
  • the first-order active digital generator includes a first-order generator that processes the sampling signal, and the generator includes at least one device that needs to be connected to a power source.
  • the first-order passive digital generator includes a first-order generator that processes the sampling signal, and the generator includes at least one device that does not need to be connected to a power source.
  • the first-order passive analog generator includes a first-order generator that processes continuous signals, and the generator includes at least one device that does not need to be connected to a power source.
  • the multi-stage active digital generator includes a multi-stage generator for processing sampling signals, and the generator includes at least one device that needs to be connected to a power source.
  • the multi-stage active analog generator includes a multi-stage generator that processes continuous signals, and the generator includes at least one device that needs to be connected to a power source.
  • the multi-stage passive digital generator includes a multi-stage generator that processes the sampling signal, and the generator includes at least one device that does not need to be connected to a power source.
  • the multi-stage passive analog generator includes a multi-stage generator that processes continuous signals, and the generator includes at least one device that does not need to be connected to a power source.
  • the current source 101 can be any device or circuit that can realize the voltage-to-current function.
  • the current source 101 can include at least any one of the following:
  • Field effect tube M1 mirror current source and resistance.
  • Fig. 2a is a circuit diagram of a ramp generator according to an exemplary embodiment.
  • the signal generator 102 is a first-order active analog generator, and the first-order active analog generator may include: An operational amplifier U1, a first capacitor C1, and a connection switch S0 and the first switch S1.
  • the output terminal of the current source 101 is connected to the first terminal of the first switch S1, the second terminal of the first switch S1 is connected to the inverting input terminal of the first operational amplifier U1, and the non-inverting input terminal of the first operational amplifier U1 is connected to the reference voltage Vref connection, the first terminal of the first capacitor C1 is connected to the inverting input terminal of the first operational amplifier U1, the second terminal of the first capacitor C1 is connected to the output terminal of the first operational amplifier U1, and the first terminal of the switch S0 is connected It is connected to the output terminal of the first operational amplifier U1, the second terminal of the connection switch S0 is used as the output terminal of the signal generator 102 to connect to the controller 103, and the output terminal of the first operational amplifier U1 is used as the output terminal of the ramp generator 100.
  • the integrator of the controller 103 is a single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier U2, a second capacitor C2, a fourth capacitor C4, and a fifth switch S5.
  • the first terminal of the second capacitor C2 serves as the input terminal of the controller 103, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is connected to the reference voltage Vref
  • the output terminal of the second operational amplifier U2 is used as the output terminal of the controller 103, the first terminal of the fifth switch S5 is connected to the first voltage V_L, and the second terminal of the fifth switch S5 is connected to the first terminal of the second capacitor C2 Connected, the first end of the fourth capacitor C4 is connected to the inverting input end of the second operational amplifier U2, and the second end of the fourth capacitor C4 is connected to the output end of the second operational amplifier U2.
  • a first switch S1 is provided between the current source 101 and the signal generator 102
  • a connection switch S0 is provided between the signal generator 102 and the controller 103
  • a connection switch S0 is provided between the drain of the current source and the reference voltage Vref.
  • a fifth switch S5 is provided between the first end of the second capacitor C2 and the reference voltage Vref.
  • the controller 103 can be used as an integrator and consists of a second operational amplifier U2, a second capacitor C2, and a fourth capacitor C4.
  • a stable ramp signal can be generated through the following steps:
  • Step 1) the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 can be charged in advance, and after the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 are charged, the first operational amplifier U1
  • the output voltage is the reset voltage V_H
  • the output voltage of the second operational amplifier U2 is the reference voltage Vref.
  • the reset voltage V_H is the charging voltage of the first capacitor C1, and the reset voltage V_H is greater than the first voltage V_L.
  • the state of the ramp generator 100 is shown in FIG. 2b.
  • Step 2) after the first preset time period has elapsed, the connection switch S0 is controlled to be closed, and the first switch S1 and the fifth switch S5 are controlled to be opened, so that the voltage value output by the controller 103 according to the ramp signal is the same as the first voltage V_L, The feedback voltage is controlled, and the feedback voltage is configured to control the current output by the current source 101.
  • the first voltage V_L is less than the reset voltage V_H.
  • step 1) to step 2) are repeated until the preset condition is met.
  • the charge on the second capacitor C2 is transferred to the side of the first operational amplifier U1, thereby controlling the feedback voltage to decrease so that the current source The output current of 101 increases, so as to achieve the purpose of reducing the voltage value of the ramp signal.
  • the charge on the second capacitor C2 is transferred to the side of the second operational amplifier U2, thereby controlling the feedback voltage to increase, so that the current source 101 outputs The current is reduced, so as to achieve the purpose of increasing the voltage value of the ramp signal.
  • the final state voltage value of the ramp signal is the voltage value corresponding to the final state in the process of changing the voltage value of the ramp signal from high to low (ie, the lowest voltage value in the process of changing the voltage value from high to low).
  • the preset condition can be, for example, repeating step 1) to step 2) until the final state voltage value of the ramp signal is equal to the first voltage V_L, at this time the ramp generator 100 stays in the state shown in FIG. 2b, by The signal generator 102 outputs a stable ramp signal. Or, repeat step 1) to step 2) according to the preset number of times, for example, repeat step 1) to step 2) 4 times, so that the ramp generator 100 stays in the state shown in FIG. 2b, and the signal generator 102 outputs a stable ramp signal.
  • Fig. 3 is a circuit diagram of another ramp generator according to an exemplary embodiment.
  • the single-ended first-order active analog integrator further includes: a third capacitor C3, a sixth switch S6, and a seventh Switch S7, eighth switch S8 and ninth switch S9, tenth switch S10 and eleventh switch S11.
  • the first terminal of the third capacitor C3 is connected to the second terminal of the second capacitor C2, the second terminal of the third capacitor C3 is connected to the inverting input terminal of the second operational amplifier U2, and the sixth switch S6 is set on the fourth capacitor C4
  • the tenth switch S10 is arranged between the first terminal of the third capacitor C3 and the reference voltage Vref, and the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2.
  • the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2.
  • the second end of the eighth switch S8 is connected to the second end of the fourth capacitor C4, the first end of the eighth switch S8 is connected to the output end of the second operational amplifier U2, and the seventh switch S7 is arranged at the second end of the second operational amplifier U2.
  • the ninth switch S9 is arranged between the second terminal of the fourth capacitor C4 and the reference voltage Vref.
  • Fig. 4 is a circuit diagram of another ramp generator according to an exemplary embodiment.
  • the first-order active analog generator may further include: a second switch S2, a third switch S3, and a fourth switch S4.
  • the first terminal of the fourth switch S4 is connected to the second terminal of the first capacitor C1, the second terminal of the fourth switch S4 is connected to the reset voltage V_H, and the first terminal of the third switch S3 is connected to the output terminal of the first operational amplifier U1
  • the second terminal of the third switch S3 is connected to the second terminal of the first capacitor C1, and the second switch S2 is arranged between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1.
  • Fig. 5a is a circuit diagram of another ramp generator according to an exemplary embodiment.
  • the field effect transistor M1 of the current source 101 may include: a twelfth switch S12.
  • the gate of the field effect transistor M1 is used as the input end of the current source 101, the source of the field effect transistor M1 is connected to the power supply VDD, the drain of the field effect transistor M1 is used as the output end of the current source 101, and the twelfth switch S12 is set in the field effect Between the drain of the tube M1 and the reference voltage Vref.
  • step 1) when step 1) is performed, the twelfth switch S12 can be controlled to open, and when step 2) is performed, the twelfth switch S12 can be controlled to be closed.
  • Taking the ramp generator shown in Fig. 5a as an example, specifically describing the steps of the ramp generator generating a ramp signal can include:
  • Step 11 In the early stage of the operation of the ramp generator 100, the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are charged first. At this time, control the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11 and the twelfth switch S12 to close, and control the connection switch S0 , The first switch S1, the third switch S3, the sixth switch S6, and the eighth switch S8 are turned off, so that the reset voltage V_H charges the first capacitor C1, and the reference voltage Vref charges the fourth capacitor C4, where the first voltage V_L is less than the reset voltage V_H. At this time, the state of the ramp generator 100 is as shown in FIG. 5b.
  • the first capacitor C1 is charged to the reset voltage V_H
  • the fourth capacitor C4 is charged to the reference voltage Vref
  • the voltage of the ramp signal output by the ramp generator 100 (that is, the ramp signal output by the first operational amplifier U1) is
  • a 1 represents the gain of the first operational amplifier U1.
  • Vramp 1 Vref
  • the feedback voltage output by the second operational amplifier U2 in the controller 103 Among them, A 2 represents the gain of the second operational amplifier U2, and Vos represents the offset voltage of the second operational amplifier U2.
  • providing the third capacitor C3 between the second capacitor C2 and the inverting input terminal of the second operational amplifier U2 can reduce the influence of the unstable ramp signal caused by the capacitor mismatch.
  • Step 12 after the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are fully charged, the third switch S3, the fifth switch S5, the eighth switch S8, the tenth switch S10, the eleventh switch S11, and the The twelfth switch S12 is closed, and the control connection switch S0, the first switch S1, the second switch S2, the fourth switch S4, the sixth switch S6, the seventh switch S7 and the ninth switch S9 are opened to make the first operational amplifier
  • the output voltage of U1 is the reset voltage V_H
  • the output voltage of the second operational amplifier U2 is the reference voltage Vref.
  • the state of the ramp generator 100 is as shown in FIG. 5c.
  • the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5c is Vramp 2 , and the controller 103 is shown in FIG. 5c.
  • the output feedback voltage in the state shown is Vfb 2 .
  • Step 13 control the first switch S1, the third switch S3, the fifth switch S5, the eighth switch S8, the tenth switch S10 and the eleventh switch S11 to close, and control the connection switch S0, the second switch S2, and the fourth switch S4, the sixth switch S6, the seventh switch S7, the ninth switch S9, and the twelfth switch S12 are turned off, so that the signal generator 102 outputs a ramp signal.
  • the state of the ramp generator 100 is as shown in FIG. 5d.
  • the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5d is Vramp 3
  • the feedback voltage output by the controller 103 in the state shown in FIG. 5d is Vfb 3
  • the signal generator 102 starts to generate a ramp signal
  • i represents the current generated in the field effect tube M1
  • t1 represents the start time of the field effect tube M1 generating charges
  • t2 represents the end time of the field effect tube M1 generating charges.
  • the amount of charge on the second capacitor C2 Q 2 (V_L-Vref)*C 2
  • the amount of charge on the third capacitor C3 Q 3 -Vos*C 3
  • the fourth capacitor The amount of charge on C4 Q 4 (Vfb 3 -Vref-Vos)*C 4 .
  • Step 21) after the first preset time period has elapsed, control the connection switch S0, the third switch S3, the sixth switch S6, the eighth switch S8, and the twelfth switch S12 to close, and control the first switch S1 and the second switch S2 ,
  • the fourth switch S4, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, and the eleventh switch S11 are turned off, so that the controller 103 is in accordance with the voltage value of the ramp signal and the first voltage V_L , Control the feedback voltage.
  • the state of the ramp generator 100 is as shown in FIG. 5e.
  • the ramp generator 100 switches from the state shown in FIG. 5d to the state shown in FIG. 5e.
  • the connection switch S0 is closed, the voltage at the first end of the second capacitor C2 is Is the first voltage V_L, and the voltage of the ramp signal output by the first operational amplifier U1 is the voltage of the second terminal of the first capacitor C1, that is, the reset voltage V_H. Since the reset voltage V_H is greater than the first voltage V_L, the charge from the second capacitor C2 The first end of is shifted toward the second end of the second capacitor C2.
  • the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5e is Vramp 4
  • the feedback voltage output by the controller 103 in the state shown in FIG. 5e is Vfb 4 .
  • the amount of charge Q 2 on the second capacitor C2 (Vramp 4 -Vref)*C 2
  • the amount of charge Q 3 on the third capacitor C3 -Vos*C 3
  • the voltage range of the ramp signal should be from the reset voltage V_H to the first voltage V_L, that is, the slope of the ramp signal should be
  • T represents the time when the ramp signal is generated
  • ID represents the current generated by the current source 101.
  • Vfb 4 When the voltage value of the ramp signal is greater than the first voltage V_L, Vfb 4 is reduced to increase the current output by the current source 101, thereby achieving the purpose of reducing the voltage value of the ramp signal. When the voltage value of the ramp signal is less than the first voltage V_L, Vfb 4 is increased to reduce the current output by the current source 101, thereby achieving the purpose of increasing the voltage value of the ramp signal.
  • step 13) to step 21) may be repeated until the voltage of the ramp signal stabilizes at the first voltage V_L.
  • a preset value for example, 4
  • step 13) to step 21) can be repeated 4 times, so that the ramp generator 100 stays in the state shown in FIG. 5d.
  • the voltage value of the ramp signal can also be monitored continuously, and step 1) to step 2) can be repeated until the difference between the voltage value of the ramp signal and the first voltage V_L is less than the preset threshold, and the ramp generator 100 stays at this time The state shown in Figure 5d.
  • the control of each switch can be realized by a timing module.
  • the timing module may include multiple counters, and each counter controls the closing and opening of each switch according to a preset period. . Take step 11) to step 12) as an example: in the initial stage of the ramp generator 100 working, the timer starts timing, and first controls the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7, and the ninth switch S7.
  • the switch S9, the tenth switch S10, the eleventh switch S11 and the twelfth switch S12 are closed, and the control connection switch S0, the first switch S1, the third switch S3, the sixth switch S6 and the eighth switch S8 are opened.
  • the ramp generator provided in this application includes a current source, a signal generator, and a controller.
  • the output terminal of the current source is connected to the input terminal of the signal generator, and the output terminal of the signal generator is connected to the controller.
  • the input terminal is connected, and the output terminal of the controller is connected to the input terminal of the current source.
  • the signal generator can generate a ramp signal according to the current output by the current source.
  • the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
  • the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.
  • Fig. 6 is a block diagram showing an analog-digital converter according to an exemplary embodiment.
  • the analog-digital converter includes: any of the ramp generators and comparators shown in Figs. 1 to 5a , Latches, registers and counters.
  • the output terminal of the ramp generator is connected to the first input terminal of the comparator, the second input terminal of the comparator is configured to receive the pixel signal, the output terminal of the comparator is connected to the input terminal of the latch, and the output of the latch
  • the terminal is connected with the first input terminal of the register, the output terminal of the counter is connected with the second input terminal of the register, and the output terminal of the register is used as the output terminal of the analog-digital converter.
  • the analog-digital converter may be a column-level single-slope ADC (English: Column Single-Slope ADC).
  • the process of converting an analog signal (ie, a pixel signal) into a digital signal can be: the comparator compares the pixel signal with the ramp signal generated by the ramp generator. Since the ramp signal is a step signal from a low level to a high level, the pixel signal at the beginning If the signal is greater than the ramp signal, the output of the comparator is low. When the pixel signal is less than the ramp signal at a certain moment, the output of the comparator changes from low to high, that is, a rising edge signal is generated, and the count value of the counter at the time when the rising edge signal is generated is saved in the register. The stored count value is the digital code (ie, digital signal) corresponding to the pixel signal.
  • the analog-to-digital converter includes a ramp generator, a comparator, a latch, a register, and a counter.
  • the output terminal of the ramp generator is connected to the first input terminal of the comparator.
  • the second input terminal is configured to receive the pixel signal
  • the output terminal of the comparator is connected to the input terminal of the latch
  • the output terminal of the latch is connected to the first input terminal of the register
  • the output terminal of the counter is connected to the second input terminal of the register.
  • the output terminal of the register is used as the output terminal of the analog-digital converter. Since the ramp generator can adjust the ramp generator to generate a ramp signal, the stability of the ramp signal is improved, thereby improving the processing accuracy of the analog-digital converter.
  • Fig. 7 is a flowchart showing a control method for generating a ramp signal according to an exemplary embodiment. As shown in Fig. 7, the method is applied to the ramp generator shown in Fig. 1, and includes the following steps:
  • step 201 the signal generator 102 generates a ramp signal according to the current output by the current source 101, and outputs the ramp signal to the controller 103.
  • step 202 the controller 103 adjusts the feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source 101.
  • Step 203 The current source 101 controls the current output by the current source 101 according to the adjusted feedback voltage.
  • the controller 103 includes a differential integrator, and the differential integrator includes a differential module and an integrator.
  • the output terminal of the differential module is connected with the input terminal of the integrator, the output terminal of the integrator is connected with the input terminal of the current source 101, and the input terminal of the differential module is connected with the output terminal of the signal generator 102.
  • Step 202 may include the following steps:
  • the output voltage of the signal generator 102 is differentially processed with the first voltage V_L through the differential module, and the obtained differential voltage is input to the integrator.
  • the output voltage of the signal generator 102 includes the initial voltage as the reset voltage V_H, and the preset duration The voltage value of the output ramp signal.
  • the differential voltage is integrated by the integrator to obtain the feedback voltage.
  • the differential module includes at least any one of the following: a resistor or a capacitor.
  • the integrator includes at least any of the following:
  • Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
  • the signal generator 102 includes at least any one of the following:
  • First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
  • the current source 101 includes at least any one of the following: a field effect tube M1, a mirror current source and a resistor.
  • the signal generator 102 is a first-order active analog generator, and the first-order active analog generator may include: a first operational amplifier U1, a first capacitor C1, a connection switch S0, and a first switch S1.
  • the output terminal of the current source 101 is connected to the first terminal of the first switch S1, the second terminal of the first switch S1 is connected to the inverting input terminal of the first operational amplifier U1, and the non-inverting input terminal of the first operational amplifier U1 is connected to the reference voltage Vref connection, the first terminal of the first capacitor C1 is connected to the inverting input terminal of the first operational amplifier U1, the second terminal of the first capacitor C1 is connected to the output terminal of the first operational amplifier U1, and the first terminal of the switch S0 is connected It is connected to the output terminal of the first operational amplifier U1, the second terminal of the connection switch S0 is used as the output terminal of the signal generator 102 to connect to the controller 103, and the output terminal of the first operational amplifier U1 is used as the output terminal of the ramp generator.
  • the integrator is a single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier U2, a second capacitor C2, a fourth capacitor C4, and a fifth switch S5.
  • the first terminal of the second capacitor C2 serves as the input terminal of the controller 103, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is connected to the reference voltage Vref
  • the output terminal of the second operational amplifier U2 is used as the output terminal of the controller 103, the first terminal of the fifth switch S5 is connected to the first voltage V_L, and the second terminal of the fifth switch S5 is connected to the first terminal of the second capacitor C2 Connected, the first end of the fourth capacitor C4 is connected to the inverting input end of the second operational amplifier U2, and the second end of the fourth capacitor C4 is connected to the output end of the second operational amplifier U2.
  • Step 201 can be implemented in the following ways:
  • Step A1 when the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are fully charged, the output voltage of the first operational amplifier U1 is the reset voltage V_H, and the output voltage of the second operational amplifier U2 is the reference voltage Vref, control The first switch S1 and the fifth switch S5 are closed, and the control connection switch S0 is opened to make the signal generator 102 output a ramp signal.
  • Step 202 can be implemented in the following ways:
  • Step B1 After the first preset time period has elapsed, control the connection switch S0 to close, control the first switch S1 and the fifth switch S5 to open, so that the controller 103 controls the feedback according to the voltage value of the ramp signal and the first voltage V_L
  • the voltage and the feedback voltage are configured to control the current output by the current source 101.
  • step A1 to step B1 are repeatedly executed until the preset condition is met.
  • step B1 may be:
  • the control connection switch S0 is closed, and the first switch S1 and the fifth switch S5 are controlled to open, so that the controller 103 decreases when the final voltage value of the ramp signal is greater than the first voltage V_L
  • the feedback voltage increases the feedback voltage when the final voltage value of the ramp signal is less than the first voltage V_L.
  • the final state voltage value of the ramp signal is the voltage value corresponding to the final state in the process of changing the voltage value of the ramp signal from high to low (ie, the lowest voltage value in the process of changing the voltage value from high to low).
  • the first-order active analog generator may further include: a second switch S2, a third switch S3, and a fourth switch S4.
  • the first terminal of the fourth switch S4 is connected to the second terminal of the first capacitor C1, the second terminal of the fourth switch S4 is connected to the reset voltage V_H, and the first terminal of the third switch S3 is connected to the output terminal of the first operational amplifier U1
  • the second terminal of the third switch S3 is connected to the second terminal of the first capacitor C1, and the second switch S2 is arranged between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1.
  • the single-ended first-order active analog integrator further includes: a seventh switch S7, an eighth switch S8, and a ninth switch S9.
  • the second end of the eighth switch S8 is connected to the second end of the fourth capacitor C4, the first end of the eighth switch S8 is connected to the output end of the second operational amplifier U2, and the seventh switch S7 is arranged at the second end of the second operational amplifier U2.
  • the ninth switch S9 is arranged between the second terminal of the fourth capacitor C4 and the reference voltage Vref.
  • Step 201 can be implemented in the following ways:
  • Step A11 control the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7 and the ninth switch S9 to close, and control the connection switch S0, the first switch S1, the third switch S3 and the eighth switch S8 to be off Turn on, so that the reset voltage V_H charges the first capacitor C1, and the reference voltage Vref charges the fourth capacitor C4.
  • Step A12 after the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 are charged, the third switch S3, the fifth switch S5, and the eighth switch S8 are controlled to close, and the connection switch S0, the first switch S1, and the first switch S1 are controlled to be closed.
  • the second switch S2, the fourth switch S4, the seventh switch S7, and the ninth switch S9 are turned off, so that the output voltage of the first operational amplifier U1 is the reset voltage V_H, and the output voltage of the second operational amplifier U2 is the reference voltage Vref.
  • Step A13 control the first switch S1, the third switch S3, the fifth switch S5 and the eighth switch S8 to be closed, and control the connection switch S0, the second switch S2, the fourth switch S4, the seventh switch S7 and the ninth switch S9 to be off Turn on so that the signal generator 102 outputs a ramp signal.
  • Step 202 can be implemented in the following ways:
  • Step B11 After the first preset time period has elapsed, control the connection switch S0, the third switch S3, and the eighth switch S8 to close, and control the first switch S1, the second switch S2, the fourth switch S4, the fifth switch S5, and the The seventh switch S7 and the ninth switch S9 are turned off, so that the controller 103 controls the feedback voltage according to the voltage value of the ramp signal and the first voltage V_L.
  • step A13 to step B11 are repeated until the preset condition is met.
  • the preset condition may be: the voltage value of the ramp signal is equal to the first voltage V_L. Or, the number of times of repeating step A13 to step B11 is equal to the preset value.
  • the field effect transistor M1 may further include: a twelfth switch S12.
  • the gate of the field effect transistor M1 is used as the input end of the current source 101, the source of the field effect transistor M1 is connected to the power supply VDD, the drain of the field effect transistor M1 is used as the output end of the current source 101, and the twelfth switch S12 is set in the field effect Between the drain of the tube M1 and the reference voltage Vref.
  • Step A11 also includes: controlling the twelfth switch S12 to close.
  • Step A12 also includes: controlling the twelfth switch S12 to close.
  • Step A13 also includes: controlling the twelfth switch S12 to turn off.
  • Step B11 also includes: controlling the twelfth switch S12 to close.
  • the single-ended first-order active analog integrator may further include: a third capacitor C3, a sixth switch S6, a tenth switch S10, and an eleventh switch S11.
  • the first terminal of the third capacitor C3 is connected to the second terminal of the second capacitor C2, the second terminal of the third capacitor C3 is connected to the inverting input terminal of the second operational amplifier U2, and the sixth switch S6 is set on the fourth capacitor C4
  • the tenth switch S10 is arranged between the first terminal of the third capacitor C3 and the reference voltage Vref, and the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2. Between the second end of and the first end of the fourth capacitor C4.
  • Step A11 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
  • Step A12 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
  • Step A13 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
  • Step B11 also includes: controlling the tenth switch S10 and the eleventh switch S11 to open, and controlling the sixth switch S6 to close.
  • the ramp generator includes a current source, a signal generator, and a controller.
  • the output terminal of the current source is connected to the input terminal of the signal generator, and the signal
  • the output terminal of the generator is connected with the input terminal of the controller, and the output terminal of the controller is connected with the input terminal of the current source.
  • the signal generator can generate a ramp signal according to the current output by the current source.
  • the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
  • the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.

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Abstract

本申请涉及一种斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法，涉及信号控制领域，该斜坡发生器包括：电流源、信号发生器和控制器，电流源的输出端与信号发生器的输入端连接，信号发生器的输出端与控制器的输入端连接，控制器的输出端与电流源的输入端连接，信号发生器配置成根据电流源输出的电流产生斜坡信号，控制器配置成根据斜坡信号调节反馈电压，调节后的反馈电压施加在电流源上，电流源配置成根据调节后的反馈电压控制电流源输出的电流。能够调节斜坡发生器产生的斜坡信号，提高斜坡信号的稳定性。

Description

斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法
相关申请的交叉引用
本申请要求于2019年04月18日提交中国专利局的申请号为201910315004.1、名称为“斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信号控制领域，具体地，涉及一种斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法。
背景技术
图像传感器作为图像采集系统的核心，通常会采用CMOS(英文：Complementary Metal Oxide Semiconductor，中文：互补金属氧化物半导体)图像传感器，CMOS图像传感器具有低功耗、动态范围大、体积小和成本低等优势，广泛应用于数码相机、扫描仪和摄像头等领域。其中，CMOS图像传感器中的ADC(英文：Analog-to-Digital Converter，中文：模拟数字转换器)决定了处理数据的速度和精度。CMOS图像传感器中的ADC通常包括有斜坡信号发生器，在现有技术中，斜坡信号发生器输出的斜坡信号通常是不可调的，而斜坡信号发生器的工艺或者所处外部环境可能会发生变化，因此会导致输出的斜坡信号不稳定，从而降低了ADC的处理精度。
发明内容
本申请的目的是提供一种斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法，用以解决现有技术中斜坡信号发生器输出的斜坡信号不稳定的问题。
为了实现上述目的，根据本申请实施例的第一方面，提供一种斜坡发生器，所述斜坡发生器包括：电流源、信号发生器和控制器，所述电流源的输出端与所述信号发生器的输入端连接，所述信号发生器的输出端与所述控制器的输入端连接，所述控制器的输出端与所述电流源的输入端连接；
所述信号发生器配置成根据所述电流源输出的电流产生斜坡信号；
所述控制器配置成根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源上；
所述电流源配置成根据所述调节后的反馈电压控制所述电流源输出的电流。
可选地，所述控制器包括差分积分器，所述差分积分器包括差分模块和积分器；所述差分模块的输出端与所述积分器的输入端连接，所述积分器的输出端与所述电流源的输入端连接，所述差分模块的输入端与所述信号发生器的输出端连接；
所述差分模块配置成将所述信号发生器的输出电压与第一电压进行差分处理，并将获得的差分电压输入至所述积分器，所述信号发生器的输出电压包括初始电压为复位电压，通过预设时长输出的所述斜坡信号的电压值；
所述积分器配置成将所述差分电压进行积分处理，以获得所述反馈电压。
可选地，所述差分模块至少包括以下任意一项：电阻或者电容；
所述积分器至少包括以下任意一项：
单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器。
可选地，所述积分器为所述单端一阶有源模拟积分器，所述单端一阶有源模拟积分器包括：第二运算放大器、第二电容、第四电容和第五开关；
所述第二电容的第一端作为所述控制器的输入端，所述第二电容的第二端与所述第二运算放大器的反相输入端连接，所述第二运算放大器的同相输入端与所述参考电压连接，所述第二运算放大器的输出端作为所述控制器的输出端，所述第五开关的第一端与所述第一电压连接，所述第五开关的第二端与所述第二电容的第一端连接，所述第四电容的第一端与所述第二运算放大器的反相输入端连接，所述第四电容的第二端与所述第二运算放大器的输出端连接。
可选地，所述单端一阶有源模拟积分器还包括：第三电容和第十开关；
所述第三电容的第一端与所述第二电容的第二端连接，所述第三电容的第二端与所述第二运算放大器的反相输入端连接，所述第十开关设置在所述第三电容的第一端与所述参考电压之间；
所述单端一阶有源模拟积分器还包括：第六开关、第七开关、第八开关、第九开关和第十一开关；
所述第八开关的第二端与所述第四电容的第二端连接，所述第八开关的第一端与所述第二运算放大器的输出端连接，所述第七开关设置在所述第二运算放大器的反相输入端与所述第二运算放大器的输出端之间，所述第九开关设置在所述第四电容的第二端与所述参考电压之间；所述第六开关设置在所述第四电容的第一端与所述第二运算放大器的反相输入端之间，所述第十一开关设置在所述第三电容的第二端与所述第四电容的第一端之间。
可选地，所述信号发生器至少包括以下任意一项：
一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器。
可选地，所述电流源至少包括以下任意一项：场效应管、镜像电流源和电阻。
可选地，所述信号发生器为所述一阶有源模拟发生器，所述一阶有源模拟发生器包括：第一运算放大器、第一电容、连接开关和第一开关；
所述电流源的输出端与所述第一开关的第一端连接，所述第一开关的第二端与所述第一运算放大器的反相输入端连接，所述第一运算放大器的同相输入端与参考电压连接，所述第一电容的第一端与所述第一运算放大器的反相输入端连接，所述第一电容的第二端与所述第一运算放大器的输出端连接，所述连接开关的第一端与所述第一运算放大器的输出端连接，所述连接开关的第二端作为所述信号发生器的输出端与所述控制器连接，所述第一运算放大器的输出端作为所述斜坡发生器的输出端；
所述一阶有源模拟发生器还包括：第二开关、第三开关和第四开关；
所述第四开关的第一端与所述第一电容的第二端连接，所述第四开关的第二端与复位电压连接，所述第三开关的第一端与所述第一运算放大器的输出端连接，所述第三开关的第二端与所述第一电容的第二端连接，所述第二开关设置在所述第一运算放大器的反相输入端与所述第一运算放大器的输出端之间。
可选地，所述场效应管还包括：第十二开关；
所述场效应管的栅极作为所述电流源的输入端，所述场效应管的源极与电源连接，所述场效应管的漏极作为所述电流源的输出端，所述第十二开关设置在所述场效应管的漏极与所述参考电压之间。
根据本申请实施例的第二方面，提供一种模拟数字转换器，应用于图像传感器，所述模拟数字转换器包括本申请实施例的第一方面所述的斜坡发生器、比较器、锁存器、寄存器和计数器；
所述斜坡发生器的输出端与所述比较器的第一输入端连接，所述比较器的第二输入端配置成接收像素信号，所述比较器的输出端与所述锁存器的输入端连接，所述锁存器的输出端与所述寄存器的第一输入端连接，所述计数器的输出端与所述寄存器的第二输入端连接，所述寄存器的输出端作为所述模拟数 字转换器的输出端。
根据本申请实施例的第三方面，提供一种产生斜坡信号的控制方法，应用于本申请实施例的第一方面所述的斜坡发生器，所述方法包括：
通过所述信号发生器根据所述电流源输出的电流产生斜坡信号，并将所述斜坡信号输出给所述控制器；
通过所述控制器根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源上；
所述电流源根据所述调节后的反馈电压控制所述电流源输出的电流。
可选地，所述控制器包括差分积分器，所述差分积分器包括差分模块和积分器；所述差分模块的输出端与所述积分器的输入端连接，所述积分器的输出端与所述电流源的输入端连接，所述差分模块的输入端与所述信号发生器的输出端连接；
所述通过所述控制器根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源上，包括：
通过所述差分模块将所述信号发生器的输出电压与第一电压进行差分处理，并将获得的差分电压输入至所述积分器，所述信号发生器的输出电压包括初始电压为复位电压，通过预设时长输出的所述斜坡信号的电压值；
通过所述积分器将所述差分电压进行积分处理，以获得所述反馈电压。
可选地，所述差分模块至少包括以下任意一项：电阻或者电容；
所述积分器至少包括以下任意一项：
单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器；
所述信号发生器至少包括以下任意一项：
一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器；
所述电流源至少包括以下任意一项：场效应管、镜像电流源和电阻。
可选地，所述信号发生器为所述一阶有源模拟发生器，所述一阶有源模拟发生器包括：第一运算放大器、第一电容、连接开关和第一开关；
所述电流源的输出端与所述第一开关的第一端连接，所述第一开关的第二端与所述第一运算放大器的反相输入端连接，所述第一运算放大器的同相输入端与参考电压(Vref)连接，所述第一电容的第一端与所述第一运算放大器的反相输入端连接，所述第一电容的第二端与所述第一运算放大器的输出端连接，所述连接开关的第一端与所述第一运算放大器的输出端连接，所述连接开关的第二端作为所述信号发生器的输出端与所述控制器连接，所述第一运算放大器的输出端作为所述斜坡发生器的输出端；
所述积分器为所述单端一阶有源模拟积分器，所述单端一阶有源模拟积分器包括：第二运算放大器、第二电容、第四电容和第五开关；
所述第二电容的第一端作为所述控制器的输入端，所述第二电容的第二端与所述第二运算放大器的反相输入端连接，所述第二运算放大器的同相输入端与所述参考电压连接，所述第二运算放大器的输出端作为所述控制器的输出端，所述第五开关的第一端与所述第一电压连接，所述第五开关的第二端与所述第二电容的第一端连接，所述第四电容的第一端与所述第二运算放大器的反相输入端连接，所述第四 电容的第二端与所述第二运算放大器的输出端连接；
所述通过所述信号发生器根据所述电流源输出的电流产生斜坡信号，并将所述斜坡信号输出给所述控制器，包括：
在所述第一电容、所述第二电容和所述第四电容完成充电，所述第一运算放大器的输出电压为所述复位电压，且所述第二运算放大器的输出电压为所述参考电压时，控制所述第一开关和所述第五开关闭合，控制所述连接开关断开，以使所述信号发生器输出斜坡信号；
所述通过所述控制器根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源上，包括：
在经过第一预设时长之后，控制所述连接开关闭合，控制所述第一开关和所述第五开关断开，以使所述控制器根据所述斜坡信号的电压值与所述第一电压，控制所述反馈电压，所述反馈电压配置成控制所述电流源输出的电流；
在经过第二预设时长之后，重复执行所述控制所述第一开关和所述第五开关闭合，控制所述连接开关断开，以使所述信号发生器输出斜坡信号，至所述在经过第一预设时长之后，控制所述连接开关闭合，控制所述第一开关和所述第五开关断开的步骤，直至满足预设条件。
可选地，所述在经过第一预设时长之后，控制所述连接开关闭合，控制所述第一开关和所述第五开关断开，以使所述控制器根据所述斜坡信号的电压值与所述第一电压，控制所述反馈电压，包括：
在经过第一预设时长之后，控制所述连接开关闭合，控制所述第一开关和所述第五开关断开，以使所述控制器在所述斜坡信号的末态电压值大于所述第一电压时，减小所述反馈电压，在所述斜坡信号的末态电压值小于所述第一电压时，增大所述反馈电压。
可选地，所述一阶有源模拟发生器还包括：第二开关、第三开关和第四开关；
所述第四开关的第一端与所述第一电容的第二端连接，所述第四开关的第二端与复位电压连接，所述第三开关的第一端与所述第一运算放大器的输出端连接，所述第三开关的第二端与所述第一电容的第二端连接，所述第二开关设置在所述第一运算放大器的反相输入端与所述第一运算放大器的输出端之间；
所述单端一阶有源模拟积分器还包括：第七开关、第八开关和第九开关；
所述第八开关的第二端与所述第四电容的第二端连接，所述第八开关的第一端与所述第二运算放大器的输出端连接，所述第七开关设置在所述第二运算放大器的反相输入端与所述第二运算放大器的输出端之间，第九开关设置在所述第四电容的第二端与所述参考电压之间；
所述通过所述信号发生器根据所述电流源输出的电流产生斜坡信号，并将所述斜坡信号输出给所述控制器，包括：
控制所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关闭合，控制所述连接开关、所述第一开关、所述第三开关和所述第八开关断开，以使所述复位电压为所述第一电容充电，所述参考电压为所述第四电容充电；
在所述第一电容、所述第二电容和所述第四电容完成充电后，控制所述第三开关、所述第五开关和所述第八开关闭合，控制所述连接开关、所述第一开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，以使所述第一运算放大器的输出电压为所述复位电压，且所述第二运算放大器的输出电压为所述参考电压；
控制所述第一开关、所述第三开关、所述第五开关和所述第八开关闭合，控制所述连接开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，以使所述信号发生器输出斜坡信号；
所述通过所述控制器根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源 上，包括：
在经过第一预设时长之后，控制所述连接开关、所述第三开关和所述第八开关闭合，控制所述第一开关、所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关断开，以使所述控制器根据所述斜坡信号的电压值与所述第一电压，控制所述反馈电压；
在经过第二预设时长之后，重复执行所述控制所述连接开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，至所述在经过第一预设时长之后，控制所述连接开关、所述第三开关和所述第八开关闭合，控制所述第一开关、所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关断开的步骤，直至满足所述预设条件。
可选地，所述预设条件为所述斜坡信号的电压值等于所述第一电压；或，
重复执行所述控制所述连接开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，至所述在经过第一预设时长之后，控制所述连接开关、所述第三开关和所述第八开关闭合，控制所述第一开关、所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关断开的步骤的次数等于预设值。
可选地，所述场效应管还包括：第十二开关；
所述场效应管的栅极作为所述电流源的输入端，所述场效应管的源极与电源连接，所述场效应管的漏极作为所述电流源的输出端，所述第十二开关设置在所述场效应管的漏极与所述参考电压之间；
所述控制所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关闭合，控制所述连接开关、所述第一开关、所述第三开关和所述第八开关断开，还包括：
控制所述第十二开关闭合；
所述控制所述第三开关所述第五开关和所述第八开关闭合，控制所述连接开关、所述第一开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十二开关闭合；
所述控制所述第一开关、所述第三开关、所述第五开关和所述第八开关闭合，控制所述连接开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十二开关断开；
所述控制所述连接开关、所述第三开关和所述第八开关闭合，控制所述第一开关、所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十二开关闭合。
可选地，所述单端一阶有源模拟积分器还包括：第三电容、第六开关、第十开关和第十一开关；
所述第三电容的第一端与所述第二电容的第二端连接，所述第三电容的第二端与所述第二运算放大器的反相输入端连接，所述第六开关设置在所述第四电容的第一端与所述第二运算放大器的反相输入端之间，所述第十开关设置在所述第三电容的第一端与所述参考电压之间，所述第十一开关设置在所述第三电容的第二端与所述第四电容的第一端之间；
所述控制所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关闭合，控制所述连接开关、所述第一开关、所述第三开关和所述第八开关断开，还包括：
控制所述第十开关和所述第十一开关闭合，控制所述第六开关断开；
所述在所述第一电容和所述第四电容完成充电后，控制所述第三开关、所述第五开关和所述第八开关闭合，控制所述连接开关、所述第一开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十开关和所述第十一开关闭合，控制所述第六开关断开；
所述控制所述第一开关、所述第三开关、所述第五开关和所述第八开关闭合，控制所述连接开关、所述第二开关、所述第四开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十开关和所述第十一开关闭合，控制所述第六开关断开；
所述控制所述连接开关、所述第三开关和所述第八开关闭合，控制所述第一开关、所述第二开关、所述第四开关、所述第五开关、所述第七开关和所述第九开关断开，还包括：
控制所述第十开关和所述第十一开关断开，控制所述第六开关闭合。
通过上述技术方案，本申请所提供的斜坡发生器包括电流源、信号发生器和控制器，其中，电流源的输出端与信号发生器的输入端连接，信号发生器的输出端与控制器的输入端连接，控制器的输出端与电流源的输入端连接。信号发生器能够根据电流源输出的电流产生斜坡信号，控制器根据信号发生器产生的斜坡信号来调节施加在电流源上的反馈电压，电流源根据调节后的反馈电压来控制电流源输出的电流，能够调节斜坡发生器产生斜坡信号，提高斜坡信号的稳定性。
本申请的其他特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本申请的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本申请，但并不构成对本申请的限制。在附图中：
图1是根据一示例性实施例示出的一种斜坡发生器的框图；
图2a是根据一示例性实施例示出的一种斜坡发生器的电路图；
图2b是根据图2a示出的斜坡发生器的一种状态的示意图；
图2c是根据图2a示出的斜坡发生器的另一种状态的示意图；
图3是根据一示例性实施例示出的另一种斜坡发生器的电路图；
图4是根据一示例性实施例示出的另一种斜坡发生器的电路图；
图5a是根据一示例性实施例示出的另一种斜坡发生器的电路图；
图5b是根据图5a示出的斜坡发生器的一种状态的示意图；
图5c是根据图5a示出的斜坡发生器的另一种状态的示意图；
图5d是根据图5a示出的斜坡发生器的另一种状态的示意图；
图5e是根据图5a示出的斜坡发生器的另一种状态的示意图；
图6是根据一示例性实施例示出的一种模拟数字转换器的框图；
图7是根据一示例性实施例示出的一种产生斜坡信号的控制方法的流程图。
附图标记说明
电流源 101           信号发生器 102
控制器 103           第一运算放大器 U1
第二运算放大器 U2    场效应管 M1
第一电容 C1          第二电容 C2
第三电容 C3          第四电容 C4
连接开关 S0          第一开关 S1
第二开关 S2          第三开关 S3
第四开关 S4          第五开关 S5
第六开关 S6          第七开关 S7
第八开关 S8          第九开关 S9
第十开关 S10         第十一开关 S11
第十二开关 S12     参考电压 Vref
复位电压 V_H       第一电压 V_L
电源 VDD           斜坡发生器 100
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
图1是根据一示例性实施例示出的一种斜坡发生器的框图，如图1所示，该斜坡发生器100包括：电流源101、信号发生器102和控制器103，电流源101的输出端与信号发生器102的输入端连接，信号发生器102的输出端与控制器103的输入端连接，控制器103的输出端与电流源101的输入端连接。
信号发生器102配置成根据电流源101输出的电流产生斜坡信号。
控制器103配置成根据斜坡信号调节反馈电压，调节后的反馈电压施加在电流源101上。
电流源101配置成根据调节后的反馈电压控制电流源101输出的电流。
举例来说，电流源101为信号发生器102提供电流，信号发生器102根据电流源101输出的电流产生斜坡信号，斜坡信号作为控制器103的输入，控制器103能够根据斜坡信号的电压大小调节反馈电压的大小，控制器103将调节后的反馈电压输出至电流源101(即调节后的反馈电压施加在电流源101上)，电流源101根据调节后的反馈电压的电压大小为信号发生器102提供电流，从而形成电流源101—信号发生器102—控制器103—电流源101的闭环反馈控制，以调节斜坡发生器100输出的斜坡信号，从而提高斜坡信号的稳定性。例如，可以在电流源101、信号发生器102和控制器103之间设置多个开关(例如可以是高速MOS开关)，首先控制电流源101与信号发生器102之间断开，控制信号发生器102和控制器103分别进行充电，当信号发生器102和控制器103完成充电后，再控制电流源101与信号发生器102连接，同时控制信号发生器102进行放电，以产生斜坡信号，根据斜坡信号的电压与控制器103放电产生的电压之间的关系，来调节控制器103生成的反馈电压，最后根据调节后的反馈电压来调整电流源101输出的电流。其中，控制器103可以包括积分器，积分器的输出端与电流源101的输入端连接，积分器的输入端与信号发生器102的输出端连接。
其中，控制器103可以包括差分积分器，差分积分器包括差分模块和积分器。差分模块的输入端作为控制器103的输入端与信号发生器102的输出端连接，差分模块的输出端与积分器的输入端连接，积分器的输出端作为控制器103的输出端与电流源101的输入端连接。
差分模块配置成将信号发生器102的输出电压与第一电压V_L进行差分处理，以获得差分模块输出的差分电压。差分模块再将获得的差分电压输入至积分器，信号发生器102的输出电压包括初始电压为复位电压V_H，通过预设时长输出的斜坡信号的电压值。积分器配置成将差分电压进行积分处理，以获得反馈电压。
其中，第一电压V_L是加载在信号发生器102上的初始电压为复位电压V_H时，通过预设时长输出的斜坡信号的理想电压值，即可以理解为第一电压V_L是信号发生器102输出的斜坡信号的最低电压。
在上述实施例的基础上，差分模块至少包括以下任意一项：电阻，或者电容。
积分器至少包括以下任意一项：
单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶 无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器。
具体地，本实施例中的积分器可以采用上述不同种类积分器中的任意一种，具体可以根据本领域技术人员根据实际要求进行选择。
举例来讲，上述积分器中包括单端的积分器是指该积分器的输入端为唯一的一个端口。
多端的积分器是指该积分器的输入端至少包括两个端口。
上述积分器中包括的模拟积分器是对信号进行连续积分的积分器。数字积分器是根据采样定理对信号直接采样后，利用数值方法对采样信号进行积分的积分器。
上述积分器中包括有源的积分器是指该积分器包括需要连接电源的积分器；无源的积分器是指该积分器包括不需要连接电源的积分器。
上述积分器中对于一阶或多阶的划分，可以按照本领域技术人员的惯用方法进行划分，例如，几阶电路包括几个储能元件，也就是说，一阶电路包括一个储能元件，二阶电路里有两个储能元件，其中，储能元件可以是电感，也可以是电容。
举例来讲，单端一阶有源数字积分器包括具有唯一输入端口的，对采样信号进行积分的一阶积分器，并且该积分器至少包括一个需要连接电源的器件。
单端一阶有源模拟积分器包括具有唯一输入端口的，对信号进行连续积分的一阶积分器，并且该积分器至少包括一个需要连接电源的器件。
单端一阶无源数字积分器包括具有唯一输入端口的，对采样信号进行积分的一阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
单端一阶无源模拟积分器包括具有唯一输入端口的，对信号进行连续积分的一阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
单端多阶有源数字积分器包括具有唯一输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个需要连接电源的器件。
单端多阶有源模拟积分器包括具有唯一输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个需要连接电源的器件。
单端多阶无源数字积分器具有唯一输入端口的，对采样信号进行积分的多阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
单端多阶无源模拟积分器包括具有唯一输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
多端一阶有源模拟积分器包括具有至少两个输入端口的，对信号进行连续积分的一阶积分器，并且该积分器至少包括一个需要连接电源的器件。
多端一阶无源数字积分器包括具有至少两个输入端口的，对采样信号进行积分的一阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
多端一阶无源模拟积分器包括具有至少两个输入端口的，对信号进行连续积分的一阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
多端多阶有源数字积分器包括具有至少两个输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个需要连接电源的器件。
多端多阶有源模拟积分器包括具有至少两个输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个需要连接电源的器件。
多端多阶无源数字积分器具有至少两个输入端口的，对采样信号进行积分的多阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
多端多阶无源模拟积分器包括具有至少两个输入端口的，对信号进行连续积分的多阶积分器，并且该积分器至少包括一个不需要连接电源的器件。
进一步地，在本申请提供的斜坡发生器中，信号发生器102至少可以包括以下一种发生器：
一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器。
具体地，本实施例中的发生器可以采用上述不同种类发生器中的任意一种，具体可以根据本领域技术人员根据实际要求进行选择。
举例来讲，上述发生器中包括模拟发生器是对连续信号进行处理的发生器；数字发生器是根据采样定理对信号直接采样后，利用数值方法对采样信号进行处理的发生器。
上述发生器中包括有源的发生器是指该发生器包括需要连接电源的发生器；无源的发生器是指该发生器包括不需要连接电源的发生器。
上述发生器中对于一阶或多阶的划分，可以按照本领域技术人员的惯用方法进行划分，例如，几阶电路包括几个储能元件，也就是说，一阶电路包括一个储能元件，二阶电路里有两个储能元件，其中，储能元件可以是电感，也可以是电容。
一阶有源模拟发生器包括具有对连续信号进行处理的一阶发生器，并且该发生器中至少包括一个需要连接电源的器件。
一阶有源数字发生器包括具有对采样信号进行处理的一阶发生器，并且该发生器至少包括一个需要连接电源的器件。
一阶无源数字发生器包括具有对采样信号进行处理的一阶发生器，并且该发生器至少包括一个不需要连接电源的器件。
一阶无源模拟发生器包括具有对连续信号进行处理的一阶发生器，并且该发生器中至少包括一个不需要连接电源的器件。
多阶有源数字发生器包括具有对采样信号进行处理的多阶发生器，并且该发生器至少包括一个需要连接电源的器件。
多阶有源模拟发生器包括具有对连续信号进行处理的多阶发生器，并且该发生器中至少包括一个需要连接电源的器件。
多阶无源数字发生器包括具有对采样信号进行处理的多阶发生器，并且该发生器至少包括一个不需要连接电源的器件。
多阶无源模拟发生器包括具有对连续信号进行处理的多阶发生器，并且该发生器中至少包括一个不需要连接电源的器件。进一步地，在上述实施例的基础上，电流源101可以实现电压转电流功能的器件或电路均可，举例来讲，电流源101至少可以包括以下任意一项：
场效应管M1、镜像电流源和电阻。
图2a是根据一示例性实施例示出的一种斜坡发生器的电路图，如图2a所示，信号发生器102为一阶有源模拟发生器，该一阶有源模拟发生器可以包括：第一运算放大器U1、第一电容C1、连接开关S0和第一开关S1。
电流源101的输出端与第一开关S1的第一端连接，第一开关S1的第二端与第一运算放大器U1的反相输入端连接，第一运算放大器U1的同相输入端与参考电压Vref连接，第一电容C1的第一端与第一运算放大器U1的反相输入端连接，第一电容C1的第二端与第一运算放大器U1的输出端连接，连接 开关S0的第一端与第一运算放大器U1的输出端连接，连接开关S0的第二端作为信号发生器102的输出端与控制器103连接，第一运算放大器U1的输出端作为斜坡发生器100的输出端。
控制器103的积分器为单端一阶有源模拟积分器，单端一阶有源模拟积分器包括：第二运算放大器U2、第二电容C2、第四电容C4和第五开关S5。
第二电容C2的第一端作为控制器103的输入端，第二电容C2的第二端与第二运算放大器U2的反相输入端连接，第二运算放大器U2的同相输入端与参考电压Vref连接，第二运算放大器U2的输出端作为控制器103的输出端，第五开关S5的第一端与第一电压V_L连接，第五开关S5的第二端与第二电容C2的第一端连接，第四电容C4的第一端与第二运算放大器U2的反相输入端连接，第四电容C4的第二端与第二运算放大器U2的输出端连接。
举例来说，电流源101与信号发生器102之间设置有第一开关S1，信号发生器102与控制器103之间设置有连接开关S0，电流源的漏极与参考电压Vref之间设置有第十二开关S12，第二电容C2的第一端与参考电压Vref之间设置有第五开关S5。控制器103可以作为一个积分器，由第二运算放大器U2、第二电容C2和第四电容C4组成。可以通过以下步骤来产生稳定的斜坡信号：
步骤1)，可以预先为第一电容C1、第二电容C2和第四电容C4充电，并在第一电容C1、第二电容C2和第四电容C4完成充电后，使第一运算放大器U1的输出电压为复位电压V_H，且第二运算放大器U2的输出电压为参考电压Vref。再控制第一开关S1和第五开关S5闭合，控制连接开关S0断开，以使信号发生器102输出斜坡信号。其中复位电压V_H为第一电容C1的充电电压，复位电压V_H大于第一电压V_L。此时，斜坡发生器100的状态如图2b所示。
步骤2)，在经过第一预设时长之后，控制连接开关S0闭合，控制第一开关S1和第五开关S5断开，以使控制器103根据斜坡信号输出的电压值与第一电压V_L，控制反馈电压，反馈电压配置成控制电流源101输出的电流。其中，第一电压V_L小于复位电压V_H，此时，斜坡发生器100的状态如图2c所示。
在经过第二预设时长之后，重复执行步骤1)至步骤2)，直至满足预设条件。
示例地，当斜坡信号的末态电压值大于第一电压V_L，根据电荷守恒原理，第二电容C2上的电荷向第一运算放大器U1一侧转移，从而控制反馈电压减小，以使电流源101输出的电流增大，从而达到降低斜坡信号的电压值的目的。当斜坡信号的末态电压值小于第一电压V_L，根据电荷守恒原理，第二电容C2上的电荷向第二运算放大器U2一侧转移，从而控制反馈电压增大，以使电流源101输出的电流减小，从而达到提高斜坡信号的电压值的目的。需要说明的是，斜坡信号的末态电压值为斜坡信号的电压值由高到低变化过程中的最后状态对应的电压值(即电压值由高到低变化过程中最低的电压值)。其中，预设条件例如可以是：重复执行步骤1)至步骤2)，直至斜坡信号的末态电压值等于第一电压V_L，此时斜坡发生器100停留在如图2b所示的状态，由信号发生器102输出稳定的斜坡信号。或者，按照预设的次数重复执行步骤1)至步骤2)，例如可以重复执行4次步骤1)至步骤2)，使斜坡发生器100停留在如图2b所示的状态，由信号发生器102输出稳定的斜坡信号。
图3是根据一示例性实施例示出的另一种斜坡发生器的电路图，如图3所示，单端一阶有源模拟积分器还包括：第三电容C3、第六开关S6、第七开关S7、第八开关S8和第九开关S9、第十开关S10和第十一开关S11。
第三电容C3的第一端与第二电容C2的第二端连接，第三电容C3的第二端与第二运算放大器U2的反相输入端连接，第六开关S6设置在第四电容C4的第一端与第二运算放大器U2的反相输入端之间，第十开关S10设置在第三电容C3的第一端与参考电压Vref之间，第十一开关S11设置在第三电容C3的第二端与第四电容C4的第一端之间。其中，在第二电容C2与第二运算放大器U2的反相输入端之间 设置第三电容C3能够减少因为电容失配导致斜坡信号不稳定的影响。
第八开关S8的第二端与第四电容C4的第二端连接，第八开关S8的第一端与第二运算放大器U2的输出端连接，第七开关S7设置在第二运算放大器U2的反相输入端与第二运算放大器U2的输出端之间，第九开关S9设置在第四电容C4的第二端与参考电压Vref之间。其中，在第二电容C2与第二运算放大器U2的反相输入端之间设置第三电容C3能够减少因为电容失配导致斜坡信号不稳定的影响。
图4是根据一示例性实施例示出的另一种斜坡发生器的电路图，如图4所示，一阶有源模拟发生器还可以包括：第二开关S2、第三开关S3和第四开关S4。
第四开关S4的第一端与第一电容C1的第二端连接，第四开关S4的第二端与复位电压V_H连接，第三开关S3的第一端与第一运算放大器U1的输出端连接，第三开关S3的第二端与第一电容C1的第二端连接，第二开关S2设置在第一运算放大器U1的反相输入端与第一运算放大器U1的输出端之间。
图5a是根据一示例性实施例示出的另一种斜坡发生器的电路图，如图5a所示，电流源101的场效应管M1可以包括：第十二开关S12。
场效应管M1的栅极作为电流源101的输入端，场效应管M1的源极与电源VDD连接，场效应管M1的漏极作为电流源101的输出端，第十二开关S12设置在场效应管M1的漏极与参考电压Vref之间。
示例地，在执行步骤1)时，可以控制第十二开关S12断开，执行步骤2)时，可以控制第十二开关S12闭合。
以图5a所示的斜坡发生器来举例，具体说明斜坡发生器产生斜坡信号的步骤，可以包括：
步骤11)，在斜坡发生器100的工作初期，先对第一电容C1、第二电容C2和第四电容C4进行充电。此时控制第二开关S2、第四开关S4、第五开关S5、第七开关S7、第九开关S9、第十开关S10、第十一开关S11和第十二开关S12闭合，控制连接开关S0、第一开关S1、第三开关S3、第六开关S6和第八开关S8断开，以使复位电压V_H为第一电容C1充电，参考电压Vref为第四电容C4充电，其中，第一电压V_L小于复位电压V_H。此时，斜坡发生器100的状态如图5b所示。
此时，第一电容C1被充电至复位电压V_H，第四电容C4被充电至参考电压Vref，斜坡发生器100输出的斜坡信号(即第一运算放大器U1输出的斜坡信号)的电压为
Figure PCTCN2019110218-appb-000001
其中A 1表示第一运算放大器U1的增益。当A 1足够大时，Vramp 1＝Vref，此时第一电容C1上的电荷量Q 1＝(Vref-V_H)*C 1，其中C 1表示第一电容C1的电容值。那么控制器103中第二运算放大器U2输出的反馈电压
Figure PCTCN2019110218-appb-000002
其中，其中A 2表示第二运算放大器U2的增益，Vos表示第二运算放大器U2的失调电压。同样地，当A 2足够大时，Vfb＝(Vref-Vos)。因此在图5b所示的状态下，第二电容C2上的电荷量Q 2＝(V_L-Vref)*C 2、第三电容C3上的电荷量Q 3＝-Vos*C 3、以及第四电容C4上的电荷量Q 4＝Vos*C 4，其中，C 2表示第二电容C2的电容值，其中C 3表示第三电容C3的电容值，其中C 4表示第四电容C4的电容值。其中，在第二电容C2与第二运算放大器U2的反相输入端之间设置第三电容C3能够减少因为电容失配导致斜坡信号不稳定的影响。
步骤12)，在第一电容C1、第二电容C2和第四电容C4完成充电后，控制第三开关S3、第五开关S5和第八开关S8、第十开关S10、第十一开关S11和第十二开关S12闭合，控制连接开关S0、第一开关S1、第二开关S2、第四开关S4、第六开关S6、第七开关S7和第九开关S9断开，以使第一运算放大器U1的输出电压为复位电压V_H，且第二运算放大器U2的输出电压为参考电压Vref。此时，斜坡发生器100的状态如图5c所示。
此时，第一电容C1、第二电容C2和第四电容C4已经完成充电，斜坡发生器100在图5c所示的状态下输出的斜坡信号的电压为Vramp 2，控制器103在图5c所示的状态下输出的反馈电压为Vfb 2。此时，第一电容C1上的电荷量为Q 1＝(Vref-Vramp 2)*C 1，根据电荷守恒定律可以得到(Vref-Vramp 2)*C 1＝(Vref-V_H)*C 1，那么可以确定Vramp 2＝V_H。第二电容C2上的电荷量不变，第三电容C3上的电荷量不变，而第四电容C4上的电荷量为Q 4＝(Vfb 2-Vos-Vref)*C 4，根据电荷守恒定律可以得到(Vfb 2-Vos-Vref)*C 4＝Vos*C 4，那么可以确定Vfb 2＝Vref。即，图5c所示的状态下第一运算放大器U1的输出电压为复位电压V_H，第二运算放大器U2的输出电压为参考电压Vref。
步骤13)，控制第一开关S1、第三开关S3、第五开关S5、第八开关S8、第十开关S10和第十一开关S11闭合，控制连接开关S0、第二开关S2、第四开关S4、第六开关S6、第七开关S7、第九开关S9和第十二开关S12断开，以使信号发生器102输出斜坡信号。此时，斜坡发生器100的状态如图5d所示。
此时，斜坡发生器100在图5d所示的状态下输出的斜坡信号的电压为Vramp 3，控制器103在图5d所示的状态下输出的反馈电压为Vfb 3。此时，信号发生器102开始产生斜坡信号，场效应管M1产生的电荷
Figure PCTCN2019110218-appb-000003
其中i表示场效应管M1中产生的电流，t1表示场效应管M1产生电荷的起始时间，t2表示场效应管M1产生电荷的结束时间。第一电容C1上的电荷量Q 1＝(Vref-Vramp 3)*C 1，根据电荷守恒定律可以得到-∫i*dt+(Vref-Vramp 3)*C 1＝(Vref-V_H)*C 1，那么可以得到
Figure PCTCN2019110218-appb-000004
而此时Vfb 3保持上一个状态不变(即Vfb 3＝Vref)。因此在图5d所示的状态下，第二电容C2上的电荷量Q 2＝(V_L-Vref)*C 2、第三电容C3上的电荷量Q 3＝-Vos*C 3、第四电容C4上的电荷量Q 4＝(Vfb 3-Vref-Vos)*C 4。
步骤21)，在经过第一预设时长之后，控制连接开关S0、第三开关S3、第六开关S6、第八开关S8和第十二开关S12闭合，控制第一开关S1、第二开关S2、第四开关S4、第五开关S5、第七开关S7、第九开关S9、第十开关S10和第十一开关S11断开，以使控制器103根据斜坡信号的电压值与第一电压V_L，控制反馈电压。此时，斜坡发生器100的状态如图5e所示。
此时，在经过第一预设时长之后，斜坡发生器100在由图5d所示的状态向图5e所示的状态切换，连接开关S0闭合的时刻，第二电容C2的第一端的电压为第一电压V_L，而第一运算放大器U1输出的斜坡信号的电压为第一电容C1的第二端的电压，即复位电压V_H，由于复位电压V_H大于第一电压V_L，电荷从第二电容C2的第一端向第二电容C2的第二端的方向转移。
斜坡发生器100在图5e所示的状态下输出的斜坡信号的电压为Vramp 4，控制器103在图5e所示的状态下输出的反馈电压为Vfb 4。此时，第二电容C2上的电荷量Q 2＝(Vramp 4-Vref)*C 2，第三电容C3上的电荷量Q 3＝-Vos*C 3，第四电容C4上的电荷量Q 4＝(Vfb 4-Vref)*C 4，根据电荷守恒定律可以得到：
Figure PCTCN2019110218-appb-000005
那么可以得到，
Figure PCTCN2019110218-appb-000006
在理想状态下，斜坡信号的电压范围应为复位电压V_H到第一电压V_L，即斜坡信号的斜率应为
Figure PCTCN2019110218-appb-000007
其中T表示斜坡信号产生的时间，ID表示电流源101产生的电流。当第一电容C1由于工艺或者所处外部环境产生变化，使得斜坡信号的电压没有下降到第一电压V_L时(即Vramp 4与第一电压V_L不相等时)，根据
Figure PCTCN2019110218-appb-000008
调节反馈电压，从而改变施加在电流源101上的电压，以使斜坡信号的电压达到第一电压V_L。当斜坡信号的电压值大于第一电压V_L时，Vfb 4减小，以使电流源101输出的电流增大，从而达到降低斜坡信号的电压值的目的。在斜坡信号的电压值小于第一电压V_L时，Vfb 4增大，以使电流源101输出的电流减小，从而达到提高斜坡信号的电压值的目的。
因此，可以在经过第二预设时长之后，重复执行步骤13)至步骤21)，直至斜坡信号的电压稳定在第一电压V_L。例如，可以设置一个预设值(例如可以是4)，重复执行步骤13)至步骤21)4次，使斜坡发生器100停留在如图5d所示的状态。或者，还可以一直监测斜坡信号的电压值，重复执行步骤1)至步骤2)，直至斜坡信号的电压值与第一电压V_L的差值小于预设的阈值，此时斜坡发生器100停留在如图5d所示的状态。
需要说明的是，上述实施例中，各个开关的控制可以通过时序模块来实现，例如，时序模块中可以包括多个计数器，每个计数器按照预设的周期对各个开关进行闭合和断开的控制。以步骤11)到步骤12)来举例：在斜坡发生器100工作的初始阶段，计时器开始计时，首先控制第二开关S2、第四开关S4、第五开关S5、第七开关S7、第九开关S9、第十开关S10、第十一开关S11和第十二开关S12闭合，控制连接开关S0、第一开关S1、第三开关S3、第六开关S6和第八开关S8断开。经过计时器计时到T1时刻，再控制第三开关S3、第五开关S5和第八开关S8、第十开关S10、第十一开关S11、第十二开关S12闭合，控制连接开关S0、第一开关S1、第二开关S2、第四开关S4、第六开关S6、第七开关S7 和第九开关S9断开。
综上所述，本申请所提供的斜坡发生器包括电流源、信号发生器和控制器，其中，电流源的输出端与信号发生器的输入端连接，信号发生器的输出端与控制器的输入端连接，控制器的输出端与电流源的输入端连接。信号发生器能够根据电流源输出的电流产生斜坡信号，控制器根据信号发生器产生的斜坡信号来调节施加在电流源上的反馈电压，电流源根据调节后的反馈电压来控制电流源输出的电流，能够调节斜坡发生器产生斜坡信号，提高斜坡信号的稳定性。
图6是根据一示例性实施例示出的一种模拟数字转换器的框图，如图6所示，模拟数字转换器包括：图1-图5a中所示的任一种斜坡发生器、比较器、锁存器、寄存器和计数器。
其中，斜坡发生器的输出端与比较器的第一输入端连接，比较器的第二输入端配置成接收像素信号，比较器的输出端与锁存器的输入端连接，锁存器的输出端与寄存器的第一输入端连接，计数器的输出端与寄存器的第二输入端连接，寄存器的输出端作为模拟数字转换器的输出端。
举例来说，该模拟数字转换器例如可以是列级单斜ADC(英文：Column Single-Slope ADC)。将模拟信号(即像素信号)转换为数字信号的过程可以是：比较器比较像素信号和斜坡发生器产生的斜坡信号，由于斜坡信号是低电平到高电平的台阶信号，因此开始时像素信号大于斜坡信号，比较器的输出为低电平。当某一时刻像素信号小于斜坡信号时，则比较器的输出由低电平变为高电平，即产生一个上升沿信号，将计数器在此上升沿信号产生时刻的计数值保存到寄存器中，保存的计数值即为像素信号对应的数字码(即数字信号)。
综上所述，本申请所提供的模拟数字转换器包括斜坡发生器、比较器、锁存器、寄存器和计数器，其中，斜坡发生器的输出端与比较器的第一输入端连接，比较器的第二输入端配置成接收像素信号，比较器的输出端与锁存器的输入端连接，锁存器的输出端与寄存器的第一输入端连接，计数器的输出端与寄存器的第二输入端连接，寄存器的输出端作为模拟数字转换器的输出端。由于斜坡发生器能够调节斜坡发生器产生斜坡信号，提高斜坡信号的稳定性，从而提高了模拟数字转换器的处理精度。
图7是根据一示例性实施例示出的一种产生斜坡信号的控制方法的流程图，如图7所示，该方法应用于图1所示的斜坡发生器，包括以下步骤：
步骤201，通过信号发生器102根据电流源101输出的电流产生斜坡信号，并将斜坡信号输出给控制器103。
步骤202，通过控制器103根据斜坡信号调节反馈电压，调节后的反馈电压施加在电流源101上。
步骤203，电流源101根据调节后的反馈电压控制电流源101输出的电流。
可选地，控制器103包括差分积分器，差分积分器包括差分模块和积分器。差分模块的输出端与积分器的输入端连接，积分器的输出端与电流源101的输入端连接，差分模块的输入端与信号发生器102的输出端连接。
步骤202可以包括以下步骤：
通过差分模块将信号发生器102的输出电压与第一电压V_L进行差分处理，并将获得的差分电压输入至积分器，信号发生器102的输出电压包括初始电压为复位电压V_H，通过预设时长输出的斜坡信号的电压值。
通过积分器将差分电压进行积分处理，以获得反馈电压。
进一步地，该产生斜坡信号的控制方法中，差分模块至少包括以下任意一项：电阻或者电容。
积分器至少包括以下任意一项：
单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶 无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器。
信号发生器102至少包括以下任意一项：
一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器。
电流源101至少包括以下任意一项：场效应管M1、镜像电流源和电阻。
可选地，信号发生器102为一阶有源模拟发生器，一阶有源模拟发生器可以包括：第一运算放大器U1、第一电容C1、连接开关S0和第一开关S1。
电流源101的输出端与第一开关S1的第一端连接，第一开关S1的第二端与第一运算放大器U1的反相输入端连接，第一运算放大器U1的同相输入端与参考电压Vref连接，第一电容C1的第一端与第一运算放大器U1的反相输入端连接，第一电容C1的第二端与第一运算放大器U1的输出端连接，连接开关S0的第一端与第一运算放大器U1的输出端连接，连接开关S0的第二端作为信号发生器102的输出端与控制器103连接，第一运算放大器U1的输出端作为斜坡发生器的输出端。
积分器为单端一阶有源模拟积分器，单端一阶有源模拟积分器包括：第二运算放大器U2、第二电容C2、第四电容C4和第五开关S5。
第二电容C2的第一端作为控制器103的输入端，第二电容C2的第二端与第二运算放大器U2的反相输入端连接，第二运算放大器U2的同相输入端与参考电压Vref连接，第二运算放大器U2的输出端作为控制器103的输出端，第五开关S5的第一端与第一电压V_L连接，第五开关S5的第二端与第二电容C2的第一端连接，第四电容C4的第一端与第二运算放大器U2的反相输入端连接，第四电容C4的第二端与第二运算放大器U2的输出端连接。
步骤201可以通过以下方式来实现：
步骤A1，在第一电容C1、第二电容C2和第四电容C4完成充电，第一运算放大器U1的输出电压为复位电压V_H，且第二运算放大器U2的输出电压为参考电压Vref时，控制第一开关S1和第五开关S5闭合，控制连接开关S0断开，以使信号发生器102输出斜坡信号。
步骤202可以通过以下方式来实现：
步骤B1，在经过第一预设时长之后，控制连接开关S0闭合，控制第一开关S1和第五开关S5断开，以使控制器103根据斜坡信号的电压值与第一电压V_L，控制反馈电压，反馈电压配置成控制电流源101输出的电流。
在经过第二预设时长之后，重复执行步骤A1至步骤B1，直至满足预设条件。
可选地，步骤B1的实现方式可以是：
在经过第一预设时长之后，控制连接开关S0闭合，控制第一开关S1和第五开关S5断开，以使控制器103在斜坡信号的末态电压值大于第一电压V_L时，减小反馈电压，在斜坡信号的末态电压值小于第一电压V_L时，增大反馈电压。需要说明的是，斜坡信号的末态电压值为斜坡信号的电压值由高到低变化过程中的最后状态对应的电压值(即电压值由高到低变化过程中最低的电压值)。
可选地，一阶有源模拟发生器还可以包括：第二开关S2、第三开关S3和第四开关S4。
第四开关S4的第一端与第一电容C1的第二端连接，第四开关S4的第二端与复位电压V_H连接，第三开关S3的第一端与第一运算放大器U1的输出端连接，第三开关S3的第二端与第一电容C1的第二端连接，第二开关S2设置在第一运算放大器U1的反相输入端与第一运算放大器U1的输出端之间。
单端一阶有源模拟积分器还包括：第七开关S7、第八开关S8和第九开关S9。
第八开关S8的第二端与第四电容C4的第二端连接，第八开关S8的第一端与第二运算放大器U2的输出端连接，第七开关S7设置在第二运算放大器U2的反相输入端与第二运算放大器U2的输出端之间，第九开关S9设置在第四电容C4的第二端与参考电压Vref之间。
步骤201可以通过以下方式来实现：
步骤A11，控制第二开关S2、第四开关S4、第五开关S5、第七开关S7和第九开关S9闭合，控制连接开关S0、第一开关S1、第三开关S3和第八开关S8断开，以使复位电压V_H为第一电容C1充电，参考电压Vref为第四电容C4充电。
步骤A12，在第一电容C1、第二电容C2和第四电容C4完成充电后，控制第三开关S3、第五开关S5和第八开关S8闭合，控制连接开关S0、第一开关S1、第二开关S2、第四开关S4、第七开关S7和第九开关S9断开，以使第一运算放大器U1的输出电压为复位电压V_H，且第二运算放大器U2的输出电压为参考电压Vref。
步骤A13，控制第一开关S1、第三开关S3、第五开关S5和第八开关S8闭合，控制连接开关S0、第二开关S2、第四开关S4、第七开关S7和第九开关S9断开，以使信号发生器102输出斜坡信号。
步骤202可以通过以下方式来实现：
步骤B11，在经过第一预设时长之后，控制连接开关S0、第三开关S3和第八开关S8闭合，控制第一开关S1、第二开关S2、第四开关S4、第五开关S5、第七开关S7和第九开关S9断开，以使控制器103根据斜坡信号的电压值与第一电压V_L，控制反馈电压。
在经过第二预设时长之后，重复执行步骤A13至步骤B11，直至满足预设条件。
其中，预设条件可以为：斜坡信号的电压值等于第一电压V_L。或者，重复执行步骤A13至步骤B11的次数等于预设值。
可选地，场效应管M1还可以包括：第十二开关S12。
场效应管M1的栅极作为电流源101的输入端，场效应管M1的源极与电源VDD连接，场效应管M1的漏极作为电流源101的输出端，第十二开关S12设置在场效应管M1的漏极与参考电压Vref之间。
步骤A11还包括：控制第十二开关S12闭合。
步骤A12还包括：控制第十二开关S12闭合。
步骤A13还包括：控制第十二开关S12断开。
步骤B11还包括：控制第十二开关S12闭合。
可选地，单端一阶有源模拟积分器还可以包括：第三电容C3、第六开关S6、第十开关S10和第十一开关S11。
第三电容C3的第一端与第二电容C2的第二端连接，第三电容C3的第二端与第二运算放大器U2的反相输入端连接，第六开关S6设置在第四电容C4的第一端与第二运算放大器U2的反相输入端之间，第十开关S10设置在第三电容C3的第一端与参考电压Vref之间，第十一开关S11设置在第三电容C3的第二端与第四电容C4的第一端之间。
步骤A11还包括：控制第十开关S10和第十一开关S11闭合，控制第六开关S6断开。
步骤A12还包括：控制第十开关S10和第十一开关S11闭合，控制第六开关S6断开。
步骤A13还包括：控制第十开关S10和第十一开关S11闭合，控制第六开关S6断开。
步骤B11还包括：控制第十开关S10和第十一开关S11断开，控制第六开关S6闭合。
关于上述实施例中的方法，其中执行各个步骤的具体方式已经在图1至图5a中所示的斜坡发生器对应的实施例中进行了详细描述，此处将不做详细阐述说明。
综上所述，本申请所提供的产生斜坡信号的控制方法，其中，斜坡发生器包括电流源、信号发生器 和控制器，其中，电流源的输出端与信号发生器的输入端连接，信号发生器的输出端与控制器的输入端连接，控制器的输出端与电流源的输入端连接。信号发生器能够根据电流源输出的电流产生斜坡信号，控制器根据信号发生器产生的斜坡信号来调节施加在电流源上的反馈电压，电流源根据调节后的反馈电压来控制电流源输出的电流，能够调节斜坡发生器产生斜坡信号，提高斜坡信号的稳定性。
以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，本领域技术人员在考虑说明书及实践本申请后，容易想到本申请的其它实施方案，均属于本申请的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。同时本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。本申请并不局限于上面已经描述出的精确结构，本申请的范围仅由所附的权利要求来限制。

Claims (10)

  1. 一种斜坡发生器，其特征在于，所述斜坡发生器包括：电流源(101)、信号发生器(102)和控制器(103)，所述电流源(101)的输出端与所述信号发生器(102)的输入端连接，所述信号发生器(102)的输出端与所述控制器(103)的输入端连接，所述控制器(103)的输出端与所述电流源(101)的输入端连接；
    所述信号发生器(102)配置成根据所述电流源(101)输出的电流产生斜坡信号；
    所述控制器(103)配置成根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源(101)上；
    所述电流源(101)配置成根据所述调节后的反馈电压控制所述电流源(101)输出的电流。
  2. 根据权利要求1所述的斜坡发生器，其特征在于，所述控制器(103)包括差分积分器，所述差分积分器包括差分模块和积分器；
    所述差分模块的输出端与所述积分器的输入端连接，所述积分器的输出端与所述电流源(101)的输入端连接，所述差分模块的输入端与所述信号发生器(102)的输出端连接；
    所述差分模块配置成将所述信号发生器(102)的输出电压与第一电压(V_L)进行差分处理，并将获得的差分电压输入至所述积分器，所述信号发生器(102)的输出电压包括初始电压为复位电压(V_H)，通过预设时长输出的所述斜坡信号的电压值；
    所述积分器配置成将所述差分电压进行积分处理，以获得所述反馈电压。
  3. 根据权利要求2所述的斜坡发生器，其特征在于，所述差分模块至少包括以下任意一项：电阻或者电容；
    所述积分器至少包括以下任意一项：
    单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器。
  4. 根据权利要求1-3任一项所述的斜坡发生器，其特征在于，所述信号发生器(102)至少包括以下任意一项：
    一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器。
  5. 根据权利要求4所述的斜坡发生器，其特征在于，所述电流源(101)至少包括以下任意一项：场效应管(M1)、镜像电流源和电阻。
  6. 一种模拟数字转换器，其特征在于，应用于图像传感器，所述模拟数字转换器包括权利要求1-5中任一项所述的斜坡发生器、比较器、锁存器、寄存器和计数器；
    所述斜坡发生器的输出端与所述比较器的第一输入端连接，所述比较器的第二输入端配置成接收像素信号，所述比较器的输出端与所述锁存器的输入端连接，所述锁存器的输出端与所述寄存器的第一输入端连接，所述计数器的输出端与所述寄存器的第二输入端连接，所述寄存器的输出端作为所述模拟数字转换器的输出端。
  7. 一种产生斜坡信号的控制方法，其特征在于，应用于权利要求1-5中任一项所述的斜坡发 生器，所述方法包括：
    通过所述信号发生器(102)根据所述电流源(101)输出的电流产生斜坡信号，并将所述斜坡信号输出给所述控制器(103)；
    通过所述控制器(103)根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源(101)上；
    所述电流源(101)根据所述调节后的反馈电压控制所述电流源(101)输出的电流。
  8. 根据权利要求7所述的方法，其特征在于，所述控制器(103)包括差分积分器，所述差分积分器包括差分模块和积分器；所述差分模块的输出端与所述积分器的输入端连接，所述积分器的输出端与所述电流源(101)的输入端连接，所述差分模块的输入端与所述信号发生器(102)的输出端连接；
    所述通过所述控制器(103)根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源(101)上，包括：
    通过所述差分模块将所述信号发生器(102)的输出电压与第一电压(V_L)进行差分处理，并将获得的差分电压输入至所述积分器，所述信号发生器(102)的输出电压包括初始电压为复位电压(V_H)，通过预设时长输出的所述斜坡信号的电压值；
    通过所述积分器将所述差分电压进行积分处理，以获得所述反馈电压。
  9. 根据权利要求8所述的方法，其特征在于，所述差分模块至少包括以下任意一项：电阻或者电容；
    所述积分器至少包括以下任意一项：
    单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器和单端多阶无源模拟积分器；
    所述信号发生器(102)至少包括以下任意一项：
    一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器；
    所述电流源(101)至少包括以下任意一项：场效应管(M1)、镜像电流源和电阻。
  10. 根据权利要求9所述的方法，其特征在于，所述信号发生器(102)为所述一阶有源模拟发生器，所述一阶有源模拟发生器包括：第一运算放大器(U1)、第一电容(C1)、连接开关(S0)和第一开关(S1)；
    所述电流源(101)的输出端与所述第一开关(S1)的第一端连接，所述第一开关(S1)的第二端与所述第一运算放大器(U1)的反相输入端连接，所述第一运算放大器(U1)的同相输入端与参考电压(Vref)连接，所述第一电容(C1)的第一端与所述第一运算放大器(U1)的反相输入端连接，所述第一电容(C1)的第二端与所述第一运算放大器(U1)的输出端连接，所述连接开关(S0)的第一端与所述第一运算放大器(U1)的输出端连接，所述连接开关(S0)的第二端作为所述信号发生器(102)的输出端与所述控制器(103)连接，所述第一运算放大器(U1)的输出端作为所述斜坡发生器的输出端；
    所述积分器为所述单端一阶有源模拟积分器，所述单端一阶有源模拟积分器包括：第二运算放大器(U2)、第二电容(C2)、第四电容(C4)和第五开关(S5)；
    所述第二电容(C2)的第一端作为所述控制器(103)的输入端，所述第二电容(C2)的第二端与所述第二运算放大器(U2)的反相输入端连接，所述第二运算放大器(U2)的同相输入端与 所述参考电压(Vref)连接，所述第二运算放大器(U2)的输出端作为所述控制器(103)的输出端，所述第五开关(S5)的第一端与所述第一电压(V_L)连接，所述第五开关(S5)的第二端与所述第二电容(C2)的第一端连接，所述第四电容(C4)的第一端与所述第二运算放大器(U2)的反相输入端连接，所述第四电容(C4)的第二端与所述第二运算放大器(U2)的输出端连接；
    所述通过所述信号发生器(102)根据所述电流源(101)输出的电流产生斜坡信号，并将所述斜坡信号输出给所述控制器(103)，包括：
    在所述第一电容(C1)、所述第二电容(C2)和所述第四电容(C4)完成充电，所述第一运算放大器(U1)的输出电压为复位电压(V_H)，且所述第二运算放大器(U2)的输出电压为所述参考电压(Vref)时，控制所述第一开关(S1)和所述第五开关(S5)闭合，控制所述连接开关(S0)断开，以使所述信号发生器(102)输出斜坡信号；
    所述通过所述控制器(103)根据所述斜坡信号调节反馈电压，调节后的所述反馈电压施加在所述电流源(101)上，包括：
    在经过第一预设时长之后，控制所述连接开关(S0)闭合，控制所述第一开关(S1)和所述第五开关(S5)断开，以使所述控制器(103)根据所述斜坡信号的电压值与所述第一电压(V_L)，控制所述反馈电压，所述反馈电压配置成控制所述电流源(101)输出的电流；
    在经过第二预设时长之后，重复执行所述控制所述第一开关(S1)和所述第五开关(S5)闭合，控制所述连接开关(S0)断开，以使所述信号发生器(102)输出斜坡信号，至所述在经过第一预设时长之后，控制所述连接开关(S0)闭合，控制所述第一开关(S1)和所述第五开关(S5)断开的步骤，直至满足预设条件。
PCT/CN2019/110218 2019-04-18 2019-10-09 斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法 WO2020211303A1 (zh)

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