WO2020211303A1 - 斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法 - Google Patents
斜坡发生器、模拟数字转换器和产生斜坡信号的控制方法 Download PDFInfo
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- WO2020211303A1 WO2020211303A1 PCT/CN2019/110218 CN2019110218W WO2020211303A1 WO 2020211303 A1 WO2020211303 A1 WO 2020211303A1 CN 2019110218 W CN2019110218 W CN 2019110218W WO 2020211303 A1 WO2020211303 A1 WO 2020211303A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- This application relates to the field of signal control, in particular to a ramp generator, an analog-digital converter, and a control method for generating ramp signals.
- CMOS Complementary Metal Oxide Semiconductor
- CMOS image sensors have low power consumption, large dynamic range, small size, and low cost. Advantages, widely used in digital cameras, scanners and cameras and other fields.
- the ADC (English: Analog-to-Digital Converter, Chinese: Analog-to-Digital Converter) in the CMOS image sensor determines the speed and accuracy of processing data.
- the ADC in the CMOS image sensor usually includes a ramp signal generator.
- the ramp signal output by the ramp signal generator is usually not adjustable, and the process of the ramp signal generator or the external environment may change , So it will cause the output ramp signal to be unstable, thereby reducing the processing accuracy of the ADC.
- the purpose of this application is to provide a ramp generator, an analog-digital converter and a control method for generating a ramp signal, so as to solve the problem of unstable ramp signal output by the ramp signal generator in the prior art.
- a ramp generator includes a current source, a signal generator, and a controller.
- the output terminal of the current source is connected to the signal
- the input terminal of the generator is connected, the output terminal of the signal generator is connected with the input terminal of the controller, and the output terminal of the controller is connected with the input terminal of the current source;
- the signal generator is configured to generate a ramp signal according to the current output by the current source
- the controller is configured to adjust a feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source;
- the current source is configured to control the current output by the current source according to the adjusted feedback voltage.
- the controller includes a differential integrator, the differential integrator includes a differential module and an integrator; the output terminal of the differential module is connected with the input terminal of the integrator, and the output terminal of the integrator is connected with The input terminal of the current source is connected, and the input terminal of the differential module is connected with the output terminal of the signal generator;
- the differential module is configured to perform differential processing between the output voltage of the signal generator and the first voltage, and input the obtained differential voltage to the integrator, and the output voltage of the signal generator includes the initial voltage being the reset voltage , The voltage value of the ramp signal output through the preset duration;
- the integrator is configured to perform integration processing on the differential voltage to obtain the feedback voltage.
- the differential module includes at least any one of the following: a resistor or a capacitor;
- the integrator includes at least any one of the following:
- Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
- the integrator is the single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier, a second capacitor, a fourth capacitor, and a fifth switch ;
- the first terminal of the second capacitor is used as the input terminal of the controller, the second terminal of the second capacitor is connected to the inverting input terminal of the second operational amplifier, and the non-inverting input of the second operational amplifier is Terminal is connected to the reference voltage, the output terminal of the second operational amplifier is used as the output terminal of the controller, the first terminal of the fifth switch is connected to the first voltage, and the first terminal of the fifth switch is The two ends are connected to the first end of the second capacitor, the first end of the fourth capacitor is connected to the inverting input end of the second operational amplifier, and the second end of the fourth capacitor is connected to the first end of the fourth capacitor. Two output terminals of the operational amplifier are connected.
- the single-ended first-order active analog integrator further includes: a third capacitor and a tenth switch;
- the first end of the third capacitor is connected to the second end of the second capacitor, the second end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the tenth switch is set Between the first end of the third capacitor and the reference voltage;
- the single-ended first-order active analog integrator further includes: a sixth switch, a seventh switch, an eighth switch, a ninth switch, and an eleventh switch;
- the second end of the eighth switch is connected to the second end of the fourth capacitor, the first end of the eighth switch is connected to the output end of the second operational amplifier, and the seventh switch is arranged on the Between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier, the ninth switch is arranged between the second terminal of the fourth capacitor and the reference voltage; the first The six switch is arranged between the first terminal of the fourth capacitor and the inverting input terminal of the second operational amplifier, and the eleventh switch is arranged between the second terminal of the third capacitor and the fourth capacitor. Between the first end of the capacitor.
- the signal generator includes at least any one of the following:
- First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
- the current source includes at least any one of the following: a field effect transistor, a mirror current source, and a resistor.
- the signal generator is the first-order active analog generator, and the first-order active analog generator includes: a first operational amplifier, a first capacitor, a connection switch, and a first switch;
- the output terminal of the current source is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the inverting input terminal of the first operational amplifier.
- the input terminal is connected to the reference voltage
- the first terminal of the first capacitor is connected to the inverting input terminal of the first operational amplifier
- the second terminal of the first capacitor is connected to the output terminal of the first operational amplifier
- the first terminal of the connection switch is connected to the output terminal of the first operational amplifier
- the second terminal of the connection switch is used as the output terminal of the signal generator to be connected to the controller, and the first operation
- the output terminal of the amplifier is used as the output terminal of the ramp generator;
- the first-order active analog generator further includes: a second switch, a third switch, and a fourth switch;
- the first end of the fourth switch is connected to the second end of the first capacitor, the second end of the fourth switch is connected to the reset voltage, and the first end of the third switch is connected to the first operation
- the output terminal of the amplifier is connected, the second terminal of the third switch is connected to the second terminal of the first capacitor, and the second switch is arranged at the inverting input terminal of the first operational amplifier and the first capacitor. Between the output terminals of the operational amplifier.
- the field effect tube further includes: a twelfth switch;
- the gate of the field effect tube is used as the input terminal of the current source, the source of the field effect tube is connected to a power source, and the drain of the field effect tube is used as the output terminal of the current source.
- the two switches are arranged between the drain of the field effect transistor and the reference voltage.
- an analog-to-digital converter applied to an image sensor.
- the analog-to-digital converter includes the ramp generator, a comparator, and a latch described in the first aspect of the embodiments of the present application.
- the output terminal of the ramp generator is connected to the first input terminal of the comparator, the second input terminal of the comparator is configured to receive a pixel signal, and the output terminal of the comparator is connected to the input terminal of the latch.
- the output of the latch is connected to the first input of the register, the output of the counter is connected to the second input of the register, and the output of the register serves as the analog digital The output of the converter.
- a control method for generating a ramp signal which is applied to the ramp generator described in the first aspect of the embodiments of the present application, and the method includes:
- the current source controls the current output by the current source according to the adjusted feedback voltage.
- the controller includes a differential integrator, the differential integrator includes a differential module and an integrator; the output terminal of the differential module is connected with the input terminal of the integrator, and the output terminal of the integrator is connected with The input terminal of the current source is connected, and the input terminal of the differential module is connected with the output terminal of the signal generator;
- the adjusting the feedback voltage by the controller according to the ramp signal and applying the adjusted feedback voltage to the current source includes:
- the output voltage of the signal generator and the first voltage are differentially processed by the differential module, and the obtained differential voltage is input to the integrator.
- the output voltage of the signal generator includes the initial voltage as the reset voltage, The voltage value of the ramp signal output through the preset duration;
- the differential voltage is integrated by the integrator to obtain the feedback voltage.
- the differential module includes at least any one of the following: a resistor or a capacitor;
- the integrator includes at least any one of the following:
- Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device
- the signal generator includes at least any one of the following:
- First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator;
- the current source includes at least any one of the following: a field effect tube, a mirror current source and a resistor.
- the signal generator is the first-order active analog generator, and the first-order active analog generator includes: a first operational amplifier, a first capacitor, a connection switch, and a first switch;
- the output terminal of the current source is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the inverting input terminal of the first operational amplifier.
- the input terminal is connected to a reference voltage (Vref)
- the first terminal of the first capacitor is connected to the inverting input terminal of the first operational amplifier
- the second terminal of the first capacitor is connected to the first operational amplifier.
- the output terminal is connected, the first terminal of the connection switch is connected to the output terminal of the first operational amplifier, the second terminal of the connection switch is used as the output terminal of the signal generator to be connected to the controller, the The output terminal of the first operational amplifier is used as the output terminal of the ramp generator;
- the integrator is the single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier, a second capacitor, a fourth capacitor, and a fifth switch;
- the first terminal of the second capacitor is used as the input terminal of the controller, the second terminal of the second capacitor is connected to the inverting input terminal of the second operational amplifier, and the non-inverting input of the second operational amplifier is Terminal is connected to the reference voltage, the output terminal of the second operational amplifier is used as the output terminal of the controller, the first terminal of the fifth switch is connected to the first voltage, and the first terminal of the fifth switch is The two ends are connected to the first end of the second capacitor, the first end of the fourth capacitor is connected to the inverting input end of the second operational amplifier, and the second end of the fourth capacitor is connected to the first end of the fourth capacitor. Two output terminals of the operational amplifier are connected;
- the generating a ramp signal by the signal generator according to the current output by the current source and outputting the ramp signal to the controller includes:
- the output voltage of the first operational amplifier is the reset voltage
- the output voltage of the second operational amplifier is the reference
- the adjusting the feedback voltage by the controller according to the ramp signal and applying the adjusted feedback voltage to the current source includes:
- connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the controller is connected to the first switch according to the voltage value of the ramp signal.
- connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the controller is controlled according to the voltage of the ramp signal And the first voltage to control the feedback voltage, including:
- connection switch is controlled to be closed, and the first switch and the fifth switch are controlled to be opened, so that the final state voltage value of the ramp signal of the controller is greater than the When the first voltage is used, the feedback voltage is reduced, and when the final state voltage value of the ramp signal is less than the first voltage, the feedback voltage is increased.
- the first-order active analog generator further includes: a second switch, a third switch, and a fourth switch;
- the first end of the fourth switch is connected to the second end of the first capacitor, the second end of the fourth switch is connected to the reset voltage, and the first end of the third switch is connected to the first operation
- the output terminal of the amplifier is connected, the second terminal of the third switch is connected to the second terminal of the first capacitor, and the second switch is arranged at the inverting input terminal of the first operational amplifier and the first capacitor. Between the output terminals of the operational amplifier;
- the single-ended first-order active analog integrator further includes: a seventh switch, an eighth switch and a ninth switch;
- the second end of the eighth switch is connected to the second end of the fourth capacitor, the first end of the eighth switch is connected to the output end of the second operational amplifier, and the seventh switch is arranged on the Between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier, a ninth switch is arranged between the second terminal of the fourth capacitor and the reference voltage;
- the generating a ramp signal by the signal generator according to the current output by the current source and outputting the ramp signal to the controller includes:
- the third switch, the fifth switch, and the eighth switch are controlled to close, and the connection switch, the connection switch, and the The first switch, the second switch, the fourth switch, the seventh switch, and the ninth switch are turned off so that the output voltage of the first operational amplifier is the reset voltage, and the The output voltage of the second operational amplifier is the reference voltage;
- the adjusting the feedback voltage by the controller according to the ramp signal, and applying the adjusted feedback voltage to the current source includes:
- connection switch, the third switch, and the eighth switch are controlled to close, and the first switch, the second switch, the fourth switch, and the first switch are controlled.
- the fifth switch, the seventh switch and the ninth switch are turned off, so that the controller controls the feedback voltage according to the voltage value of the ramp signal and the first voltage;
- control of the connection switch, the second switch, the fourth switch, the seventh switch, and the ninth switch is repeatedly executed until the After the first preset time period, control the connection switch, the third switch, and the eighth switch to close, and control the first switch, the second switch, the fourth switch, and the fifth switch , The step of turning off the seventh switch and the ninth switch until the preset condition is met.
- the preset condition is that the voltage value of the ramp signal is equal to the first voltage
- connection switch, the third switch and the eighth switch are closed to control the first switch, the second switch, the fourth switch, the fifth switch, the seventh switch and the The number of steps in which the ninth switch is turned off is equal to the preset value.
- the field effect tube further includes: a twelfth switch;
- the gate of the field effect tube is used as the input terminal of the current source, the source of the field effect tube is connected to a power source, and the drain of the field effect tube is used as the output terminal of the current source.
- the two switches are arranged between the drain of the field effect transistor and the reference voltage;
- the switch is disconnected from the eighth switch, and further includes:
- controlling said third switch, said fifth switch and said eighth switch are closed, and controlling said connection switch, said first switch, said second switch, said fourth switch, and said seventh switch Disconnecting from the ninth switch further includes:
- connection switch, the third switch, and the eighth switch are controlled to be closed, and the first switch, the second switch, the fourth switch, the fifth switch, and the seventh switch are controlled.
- the switch is disconnected from the ninth switch, and further includes:
- the single-ended first-order active analog integrator further includes: a third capacitor, a sixth switch, a tenth switch, and an eleventh switch;
- the first end of the third capacitor is connected to the second end of the second capacitor, the second end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the sixth switch is set Between the first terminal of the fourth capacitor and the inverting input terminal of the second operational amplifier, the tenth switch is arranged between the first terminal of the third capacitor and the reference voltage, so The eleventh switch is arranged between the second end of the third capacitor and the first end of the fourth capacitor;
- the switch is disconnected from the eighth switch, and further includes:
- the third switch, the fifth switch, and the eighth switch are controlled to close, and the connection switch, the first switch, and the The turning off of the second switch, the fourth switch, the seventh switch and the ninth switch further includes:
- connection switch, the third switch, and the eighth switch are controlled to be closed, and the first switch, the second switch, the fourth switch, the fifth switch, and the seventh switch are controlled.
- the switch is disconnected from the ninth switch, and further includes:
- the ramp generator provided by the present application includes a current source, a signal generator, and a controller.
- the output terminal of the current source is connected to the input terminal of the signal generator, and the output terminal of the signal generator is connected to the controller.
- the input terminal is connected, and the output terminal of the controller is connected to the input terminal of the current source.
- the signal generator can generate a ramp signal according to the current output by the current source.
- the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
- the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.
- Fig. 1 is a block diagram showing a ramp generator according to an exemplary embodiment
- Fig. 2a is a circuit diagram of a ramp generator according to an exemplary embodiment
- Fig. 2b is a schematic diagram of a state of the ramp generator shown in Fig. 2a;
- Fig. 2c is a schematic diagram of another state of the ramp generator shown in Fig. 2a;
- Fig. 3 is a circuit diagram showing another ramp generator according to an exemplary embodiment
- Fig. 4 is a circuit diagram showing another ramp generator according to an exemplary embodiment
- Fig. 5a is a circuit diagram of another ramp generator according to an exemplary embodiment
- Fig. 5b is a schematic diagram of a state of the ramp generator shown in Fig. 5a;
- Fig. 5c is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
- Fig. 5d is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
- Fig. 5e is a schematic diagram of another state of the ramp generator shown in Fig. 5a;
- Fig. 6 is a block diagram showing an analog-to-digital converter according to an exemplary embodiment
- Fig. 7 is a flowchart showing a control method for generating a ramp signal according to an exemplary embodiment.
- the third capacitor C3 The fourth capacitor C4
- the sixth switch S6 The seventh switch S7
- Fig. 1 is a block diagram showing a ramp generator according to an exemplary embodiment.
- the ramp generator 100 includes a current source 101, a signal generator 102, and a controller 103, and the output of the current source 101 The terminal is connected with the input terminal of the signal generator 102, the output terminal of the signal generator 102 is connected with the input terminal of the controller 103, and the output terminal of the controller 103 is connected with the input terminal of the current source 101.
- the signal generator 102 is configured to generate a ramp signal according to the current output by the current source 101.
- the controller 103 is configured to adjust the feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source 101.
- the current source 101 is configured to control the current output by the current source 101 according to the adjusted feedback voltage.
- the current source 101 provides current for the signal generator 102, the signal generator 102 generates a ramp signal according to the current output by the current source 101, the ramp signal is used as the input of the controller 103, and the controller 103 can adjust according to the voltage of the ramp signal Regarding the magnitude of the feedback voltage, the controller 103 outputs the adjusted feedback voltage to the current source 101 (that is, the adjusted feedback voltage is applied to the current source 101), and the current source 101 acts as a signal generator according to the magnitude of the adjusted feedback voltage 102 provides current to form a closed-loop feedback control of the current source 101-signal generator 102-controller 103-current source 101 to adjust the ramp signal output by the ramp generator 100, thereby improving the stability of the ramp signal.
- multiple switches can be set between the current source 101, the signal generator 102 and the controller 103.
- the current source 101 and the signal generator 102 are controlled to be disconnected, and the signal generator 102 is controlled.
- the controller 103 are charged separately.
- the current source 101 is controlled to connect with the signal generator 102, and the signal generator 102 is controlled to discharge at the same time to generate a ramp signal.
- the relationship between the voltage generated by the discharge of the controller 103 and the voltage generated by the controller 103 is used to adjust the feedback voltage generated by the controller 103, and finally the current output by the current source 101 is adjusted according to the adjusted feedback voltage.
- the controller 103 may include an integrator, the output of the integrator is connected to the input of the current source 101, and the input of the integrator is connected to the output of the signal generator 102.
- the controller 103 may include a differential integrator, and the differential integrator includes a differential module and an integrator.
- the input terminal of the differential module is used as the input terminal of the controller 103 to connect to the output terminal of the signal generator 102, the output terminal of the differential module is connected to the input terminal of the integrator, and the output terminal of the integrator is used as the output terminal of the controller 103 and the current source The input terminal of 101 is connected.
- the differential module is configured to perform differential processing between the output voltage of the signal generator 102 and the first voltage V_L to obtain the differential voltage output by the differential module.
- the differential module then inputs the obtained differential voltage to the integrator, and the output voltage of the signal generator 102 includes the initial voltage being the reset voltage V_H, and the voltage value of the ramp signal output by the preset duration.
- the integrator is configured to integrate the differential voltage to obtain the feedback voltage.
- the first voltage V_L is the ideal voltage value of the ramp signal output by the preset duration when the initial voltage loaded on the signal generator 102 is the reset voltage V_H, that is, it can be understood that the first voltage V_L is the output of the signal generator 102 The lowest voltage of the ramp signal.
- the differential module includes at least any one of the following: a resistor or a capacitor.
- the integrator includes at least any of the following:
- Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
- the integrator in this embodiment can adopt any one of the above-mentioned different types of integrators, which can be specifically selected according to actual requirements by those skilled in the art.
- the single-ended integrator included in the above integrator means that the input terminal of the integrator is the only port.
- a multi-terminal integrator means that the input terminal of the integrator includes at least two ports.
- the analog integrator included in the above integrator is an integrator that continuously integrates a signal.
- the digital integrator is an integrator that uses numerical methods to integrate the sampled signal after directly sampling the signal according to the sampling theorem.
- the above-mentioned integrator includes an active integrator, which means that the integrator includes an integrator that needs to be connected to a power source; a passive integrator means that the integrator includes an integrator that does not need to be connected to a power source.
- a several-level circuit includes several energy storage elements, that is, a first-level circuit includes one energy storage element. There are two energy storage elements in the second-order circuit. Among them, the energy storage element can be an inductor or a capacitor.
- a single-ended first-order active digital integrator includes a first-order integrator with a unique input port that integrates a sampled signal, and the integrator includes at least one device that needs to be connected to a power source.
- the single-ended first-order active analog integrator includes a first-order integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
- the single-ended first-order passive digital integrator includes a first-order integrator with a unique input port that integrates a sampled signal, and the integrator includes at least one device that does not need to be connected to a power supply.
- the single-ended first-order passive analog integrator includes a first-order integrator with a single input port that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
- the single-ended multi-stage active digital integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
- the single-ended multi-stage active analog integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that needs to be connected to a power source.
- a single-ended multi-stage passive digital integrator is a multi-stage integrator that integrates a sampled signal with a unique input port, and the integrator includes at least one device that does not need to be connected to a power supply.
- the single-ended multi-stage passive analog integrator includes a multi-stage integrator with a unique input port that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
- the multi-terminal first-order active analog integrator includes a first-order integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
- the multi-terminal first-order passive digital integrator includes a first-order integrator with at least two input ports for integrating a sampled signal, and the integrator includes at least one device that does not need to be connected to a power source.
- the multi-terminal first-order passive analog integrator includes a first-order integrator with at least two input ports that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power supply.
- the multi-terminal multi-stage active digital integrator includes a multi-stage integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
- the multi-terminal multi-stage active analog integrator includes a multi-stage integrator with at least two input ports that continuously integrates signals, and the integrator includes at least one device that needs to be connected to a power source.
- the multi-terminal multi-stage passive digital integrator has at least two input ports and integrates the sampling signal, and the integrator includes at least one device that does not need to be connected to a power supply.
- the multi-terminal multi-stage passive analog integrator includes a multi-stage integrator with at least two input ports that continuously integrates a signal, and the integrator includes at least one device that does not need to be connected to a power source.
- the signal generator 102 may include at least one of the following generators:
- First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
- the generator in this embodiment may adopt any one of the above-mentioned different types of generators, which can be specifically selected according to actual requirements by those skilled in the art.
- the above-mentioned generators include analog generators that process continuous signals; digital generators use numerical methods to process the sampled signals after directly sampling the signal according to the sampling theorem.
- the above-mentioned generator includes an active generator means that the generator includes a generator that needs to be connected to a power source; a passive generator means that the generator includes a generator that does not need to be connected to a power source.
- a circuit of several levels includes several energy storage elements, that is, a circuit of one order includes one energy storage element.
- the energy storage element can be an inductor or a capacitor.
- the first-order active analog generator includes a first-order generator that processes continuous signals, and the generator includes at least one device that needs to be connected to a power source.
- the first-order active digital generator includes a first-order generator that processes the sampling signal, and the generator includes at least one device that needs to be connected to a power source.
- the first-order passive digital generator includes a first-order generator that processes the sampling signal, and the generator includes at least one device that does not need to be connected to a power source.
- the first-order passive analog generator includes a first-order generator that processes continuous signals, and the generator includes at least one device that does not need to be connected to a power source.
- the multi-stage active digital generator includes a multi-stage generator for processing sampling signals, and the generator includes at least one device that needs to be connected to a power source.
- the multi-stage active analog generator includes a multi-stage generator that processes continuous signals, and the generator includes at least one device that needs to be connected to a power source.
- the multi-stage passive digital generator includes a multi-stage generator that processes the sampling signal, and the generator includes at least one device that does not need to be connected to a power source.
- the multi-stage passive analog generator includes a multi-stage generator that processes continuous signals, and the generator includes at least one device that does not need to be connected to a power source.
- the current source 101 can be any device or circuit that can realize the voltage-to-current function.
- the current source 101 can include at least any one of the following:
- Field effect tube M1 mirror current source and resistance.
- Fig. 2a is a circuit diagram of a ramp generator according to an exemplary embodiment.
- the signal generator 102 is a first-order active analog generator, and the first-order active analog generator may include: An operational amplifier U1, a first capacitor C1, and a connection switch S0 and the first switch S1.
- the output terminal of the current source 101 is connected to the first terminal of the first switch S1, the second terminal of the first switch S1 is connected to the inverting input terminal of the first operational amplifier U1, and the non-inverting input terminal of the first operational amplifier U1 is connected to the reference voltage Vref connection, the first terminal of the first capacitor C1 is connected to the inverting input terminal of the first operational amplifier U1, the second terminal of the first capacitor C1 is connected to the output terminal of the first operational amplifier U1, and the first terminal of the switch S0 is connected It is connected to the output terminal of the first operational amplifier U1, the second terminal of the connection switch S0 is used as the output terminal of the signal generator 102 to connect to the controller 103, and the output terminal of the first operational amplifier U1 is used as the output terminal of the ramp generator 100.
- the integrator of the controller 103 is a single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier U2, a second capacitor C2, a fourth capacitor C4, and a fifth switch S5.
- the first terminal of the second capacitor C2 serves as the input terminal of the controller 103, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is connected to the reference voltage Vref
- the output terminal of the second operational amplifier U2 is used as the output terminal of the controller 103, the first terminal of the fifth switch S5 is connected to the first voltage V_L, and the second terminal of the fifth switch S5 is connected to the first terminal of the second capacitor C2 Connected, the first end of the fourth capacitor C4 is connected to the inverting input end of the second operational amplifier U2, and the second end of the fourth capacitor C4 is connected to the output end of the second operational amplifier U2.
- a first switch S1 is provided between the current source 101 and the signal generator 102
- a connection switch S0 is provided between the signal generator 102 and the controller 103
- a connection switch S0 is provided between the drain of the current source and the reference voltage Vref.
- a fifth switch S5 is provided between the first end of the second capacitor C2 and the reference voltage Vref.
- the controller 103 can be used as an integrator and consists of a second operational amplifier U2, a second capacitor C2, and a fourth capacitor C4.
- a stable ramp signal can be generated through the following steps:
- Step 1) the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 can be charged in advance, and after the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 are charged, the first operational amplifier U1
- the output voltage is the reset voltage V_H
- the output voltage of the second operational amplifier U2 is the reference voltage Vref.
- the reset voltage V_H is the charging voltage of the first capacitor C1, and the reset voltage V_H is greater than the first voltage V_L.
- the state of the ramp generator 100 is shown in FIG. 2b.
- Step 2) after the first preset time period has elapsed, the connection switch S0 is controlled to be closed, and the first switch S1 and the fifth switch S5 are controlled to be opened, so that the voltage value output by the controller 103 according to the ramp signal is the same as the first voltage V_L, The feedback voltage is controlled, and the feedback voltage is configured to control the current output by the current source 101.
- the first voltage V_L is less than the reset voltage V_H.
- step 1) to step 2) are repeated until the preset condition is met.
- the charge on the second capacitor C2 is transferred to the side of the first operational amplifier U1, thereby controlling the feedback voltage to decrease so that the current source The output current of 101 increases, so as to achieve the purpose of reducing the voltage value of the ramp signal.
- the charge on the second capacitor C2 is transferred to the side of the second operational amplifier U2, thereby controlling the feedback voltage to increase, so that the current source 101 outputs The current is reduced, so as to achieve the purpose of increasing the voltage value of the ramp signal.
- the final state voltage value of the ramp signal is the voltage value corresponding to the final state in the process of changing the voltage value of the ramp signal from high to low (ie, the lowest voltage value in the process of changing the voltage value from high to low).
- the preset condition can be, for example, repeating step 1) to step 2) until the final state voltage value of the ramp signal is equal to the first voltage V_L, at this time the ramp generator 100 stays in the state shown in FIG. 2b, by The signal generator 102 outputs a stable ramp signal. Or, repeat step 1) to step 2) according to the preset number of times, for example, repeat step 1) to step 2) 4 times, so that the ramp generator 100 stays in the state shown in FIG. 2b, and the signal generator 102 outputs a stable ramp signal.
- Fig. 3 is a circuit diagram of another ramp generator according to an exemplary embodiment.
- the single-ended first-order active analog integrator further includes: a third capacitor C3, a sixth switch S6, and a seventh Switch S7, eighth switch S8 and ninth switch S9, tenth switch S10 and eleventh switch S11.
- the first terminal of the third capacitor C3 is connected to the second terminal of the second capacitor C2, the second terminal of the third capacitor C3 is connected to the inverting input terminal of the second operational amplifier U2, and the sixth switch S6 is set on the fourth capacitor C4
- the tenth switch S10 is arranged between the first terminal of the third capacitor C3 and the reference voltage Vref, and the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2.
- the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2.
- the second end of the eighth switch S8 is connected to the second end of the fourth capacitor C4, the first end of the eighth switch S8 is connected to the output end of the second operational amplifier U2, and the seventh switch S7 is arranged at the second end of the second operational amplifier U2.
- the ninth switch S9 is arranged between the second terminal of the fourth capacitor C4 and the reference voltage Vref.
- Fig. 4 is a circuit diagram of another ramp generator according to an exemplary embodiment.
- the first-order active analog generator may further include: a second switch S2, a third switch S3, and a fourth switch S4.
- the first terminal of the fourth switch S4 is connected to the second terminal of the first capacitor C1, the second terminal of the fourth switch S4 is connected to the reset voltage V_H, and the first terminal of the third switch S3 is connected to the output terminal of the first operational amplifier U1
- the second terminal of the third switch S3 is connected to the second terminal of the first capacitor C1, and the second switch S2 is arranged between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1.
- Fig. 5a is a circuit diagram of another ramp generator according to an exemplary embodiment.
- the field effect transistor M1 of the current source 101 may include: a twelfth switch S12.
- the gate of the field effect transistor M1 is used as the input end of the current source 101, the source of the field effect transistor M1 is connected to the power supply VDD, the drain of the field effect transistor M1 is used as the output end of the current source 101, and the twelfth switch S12 is set in the field effect Between the drain of the tube M1 and the reference voltage Vref.
- step 1) when step 1) is performed, the twelfth switch S12 can be controlled to open, and when step 2) is performed, the twelfth switch S12 can be controlled to be closed.
- Taking the ramp generator shown in Fig. 5a as an example, specifically describing the steps of the ramp generator generating a ramp signal can include:
- Step 11 In the early stage of the operation of the ramp generator 100, the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are charged first. At this time, control the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11 and the twelfth switch S12 to close, and control the connection switch S0 , The first switch S1, the third switch S3, the sixth switch S6, and the eighth switch S8 are turned off, so that the reset voltage V_H charges the first capacitor C1, and the reference voltage Vref charges the fourth capacitor C4, where the first voltage V_L is less than the reset voltage V_H. At this time, the state of the ramp generator 100 is as shown in FIG. 5b.
- the first capacitor C1 is charged to the reset voltage V_H
- the fourth capacitor C4 is charged to the reference voltage Vref
- the voltage of the ramp signal output by the ramp generator 100 (that is, the ramp signal output by the first operational amplifier U1) is
- a 1 represents the gain of the first operational amplifier U1.
- Vramp 1 Vref
- the feedback voltage output by the second operational amplifier U2 in the controller 103 Among them, A 2 represents the gain of the second operational amplifier U2, and Vos represents the offset voltage of the second operational amplifier U2.
- providing the third capacitor C3 between the second capacitor C2 and the inverting input terminal of the second operational amplifier U2 can reduce the influence of the unstable ramp signal caused by the capacitor mismatch.
- Step 12 after the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are fully charged, the third switch S3, the fifth switch S5, the eighth switch S8, the tenth switch S10, the eleventh switch S11, and the The twelfth switch S12 is closed, and the control connection switch S0, the first switch S1, the second switch S2, the fourth switch S4, the sixth switch S6, the seventh switch S7 and the ninth switch S9 are opened to make the first operational amplifier
- the output voltage of U1 is the reset voltage V_H
- the output voltage of the second operational amplifier U2 is the reference voltage Vref.
- the state of the ramp generator 100 is as shown in FIG. 5c.
- the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5c is Vramp 2 , and the controller 103 is shown in FIG. 5c.
- the output feedback voltage in the state shown is Vfb 2 .
- Step 13 control the first switch S1, the third switch S3, the fifth switch S5, the eighth switch S8, the tenth switch S10 and the eleventh switch S11 to close, and control the connection switch S0, the second switch S2, and the fourth switch S4, the sixth switch S6, the seventh switch S7, the ninth switch S9, and the twelfth switch S12 are turned off, so that the signal generator 102 outputs a ramp signal.
- the state of the ramp generator 100 is as shown in FIG. 5d.
- the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5d is Vramp 3
- the feedback voltage output by the controller 103 in the state shown in FIG. 5d is Vfb 3
- the signal generator 102 starts to generate a ramp signal
- i represents the current generated in the field effect tube M1
- t1 represents the start time of the field effect tube M1 generating charges
- t2 represents the end time of the field effect tube M1 generating charges.
- the amount of charge on the second capacitor C2 Q 2 (V_L-Vref)*C 2
- the amount of charge on the third capacitor C3 Q 3 -Vos*C 3
- the fourth capacitor The amount of charge on C4 Q 4 (Vfb 3 -Vref-Vos)*C 4 .
- Step 21) after the first preset time period has elapsed, control the connection switch S0, the third switch S3, the sixth switch S6, the eighth switch S8, and the twelfth switch S12 to close, and control the first switch S1 and the second switch S2 ,
- the fourth switch S4, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, and the eleventh switch S11 are turned off, so that the controller 103 is in accordance with the voltage value of the ramp signal and the first voltage V_L , Control the feedback voltage.
- the state of the ramp generator 100 is as shown in FIG. 5e.
- the ramp generator 100 switches from the state shown in FIG. 5d to the state shown in FIG. 5e.
- the connection switch S0 is closed, the voltage at the first end of the second capacitor C2 is Is the first voltage V_L, and the voltage of the ramp signal output by the first operational amplifier U1 is the voltage of the second terminal of the first capacitor C1, that is, the reset voltage V_H. Since the reset voltage V_H is greater than the first voltage V_L, the charge from the second capacitor C2 The first end of is shifted toward the second end of the second capacitor C2.
- the voltage of the ramp signal output by the ramp generator 100 in the state shown in FIG. 5e is Vramp 4
- the feedback voltage output by the controller 103 in the state shown in FIG. 5e is Vfb 4 .
- the amount of charge Q 2 on the second capacitor C2 (Vramp 4 -Vref)*C 2
- the amount of charge Q 3 on the third capacitor C3 -Vos*C 3
- the voltage range of the ramp signal should be from the reset voltage V_H to the first voltage V_L, that is, the slope of the ramp signal should be
- T represents the time when the ramp signal is generated
- ID represents the current generated by the current source 101.
- Vfb 4 When the voltage value of the ramp signal is greater than the first voltage V_L, Vfb 4 is reduced to increase the current output by the current source 101, thereby achieving the purpose of reducing the voltage value of the ramp signal. When the voltage value of the ramp signal is less than the first voltage V_L, Vfb 4 is increased to reduce the current output by the current source 101, thereby achieving the purpose of increasing the voltage value of the ramp signal.
- step 13) to step 21) may be repeated until the voltage of the ramp signal stabilizes at the first voltage V_L.
- a preset value for example, 4
- step 13) to step 21) can be repeated 4 times, so that the ramp generator 100 stays in the state shown in FIG. 5d.
- the voltage value of the ramp signal can also be monitored continuously, and step 1) to step 2) can be repeated until the difference between the voltage value of the ramp signal and the first voltage V_L is less than the preset threshold, and the ramp generator 100 stays at this time The state shown in Figure 5d.
- the control of each switch can be realized by a timing module.
- the timing module may include multiple counters, and each counter controls the closing and opening of each switch according to a preset period. . Take step 11) to step 12) as an example: in the initial stage of the ramp generator 100 working, the timer starts timing, and first controls the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7, and the ninth switch S7.
- the switch S9, the tenth switch S10, the eleventh switch S11 and the twelfth switch S12 are closed, and the control connection switch S0, the first switch S1, the third switch S3, the sixth switch S6 and the eighth switch S8 are opened.
- the ramp generator provided in this application includes a current source, a signal generator, and a controller.
- the output terminal of the current source is connected to the input terminal of the signal generator, and the output terminal of the signal generator is connected to the controller.
- the input terminal is connected, and the output terminal of the controller is connected to the input terminal of the current source.
- the signal generator can generate a ramp signal according to the current output by the current source.
- the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
- the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.
- Fig. 6 is a block diagram showing an analog-digital converter according to an exemplary embodiment.
- the analog-digital converter includes: any of the ramp generators and comparators shown in Figs. 1 to 5a , Latches, registers and counters.
- the output terminal of the ramp generator is connected to the first input terminal of the comparator, the second input terminal of the comparator is configured to receive the pixel signal, the output terminal of the comparator is connected to the input terminal of the latch, and the output of the latch
- the terminal is connected with the first input terminal of the register, the output terminal of the counter is connected with the second input terminal of the register, and the output terminal of the register is used as the output terminal of the analog-digital converter.
- the analog-digital converter may be a column-level single-slope ADC (English: Column Single-Slope ADC).
- the process of converting an analog signal (ie, a pixel signal) into a digital signal can be: the comparator compares the pixel signal with the ramp signal generated by the ramp generator. Since the ramp signal is a step signal from a low level to a high level, the pixel signal at the beginning If the signal is greater than the ramp signal, the output of the comparator is low. When the pixel signal is less than the ramp signal at a certain moment, the output of the comparator changes from low to high, that is, a rising edge signal is generated, and the count value of the counter at the time when the rising edge signal is generated is saved in the register. The stored count value is the digital code (ie, digital signal) corresponding to the pixel signal.
- the analog-to-digital converter includes a ramp generator, a comparator, a latch, a register, and a counter.
- the output terminal of the ramp generator is connected to the first input terminal of the comparator.
- the second input terminal is configured to receive the pixel signal
- the output terminal of the comparator is connected to the input terminal of the latch
- the output terminal of the latch is connected to the first input terminal of the register
- the output terminal of the counter is connected to the second input terminal of the register.
- the output terminal of the register is used as the output terminal of the analog-digital converter. Since the ramp generator can adjust the ramp generator to generate a ramp signal, the stability of the ramp signal is improved, thereby improving the processing accuracy of the analog-digital converter.
- Fig. 7 is a flowchart showing a control method for generating a ramp signal according to an exemplary embodiment. As shown in Fig. 7, the method is applied to the ramp generator shown in Fig. 1, and includes the following steps:
- step 201 the signal generator 102 generates a ramp signal according to the current output by the current source 101, and outputs the ramp signal to the controller 103.
- step 202 the controller 103 adjusts the feedback voltage according to the ramp signal, and the adjusted feedback voltage is applied to the current source 101.
- Step 203 The current source 101 controls the current output by the current source 101 according to the adjusted feedback voltage.
- the controller 103 includes a differential integrator, and the differential integrator includes a differential module and an integrator.
- the output terminal of the differential module is connected with the input terminal of the integrator, the output terminal of the integrator is connected with the input terminal of the current source 101, and the input terminal of the differential module is connected with the output terminal of the signal generator 102.
- Step 202 may include the following steps:
- the output voltage of the signal generator 102 is differentially processed with the first voltage V_L through the differential module, and the obtained differential voltage is input to the integrator.
- the output voltage of the signal generator 102 includes the initial voltage as the reset voltage V_H, and the preset duration The voltage value of the output ramp signal.
- the differential voltage is integrated by the integrator to obtain the feedback voltage.
- the differential module includes at least any one of the following: a resistor or a capacitor.
- the integrator includes at least any of the following:
- Single-ended first-order active digital integrator single-ended first-order active analog integrator, single-ended first-order passive digital integrator, single-ended first-order passive analog integrator, single-ended multi-stage active digital integrator, Single-ended multi-stage active analog integrator, single-ended multi-stage passive digital integrator, single-ended multi-stage passive analog integrator, multi-terminal first-order active digital integrator, multi-terminal first-order active analog integrator, multi-terminal one -Order passive digital integrator, multi-terminal first-order passive analog integrator, multi-terminal multi-stage active digital integrator, multi-terminal multi-stage active analog integrator, multi-terminal multi-stage passive digital integrator and multi-terminal multi-stage passive analog integrator Device.
- the signal generator 102 includes at least any one of the following:
- First-order active digital generator first-order active analog generator, first-order passive digital generator, first-order passive analog generator, multi-stage active digital generator, multi-stage active analog generator, multi-stage Passive digital generator and multi-stage passive analog generator.
- the current source 101 includes at least any one of the following: a field effect tube M1, a mirror current source and a resistor.
- the signal generator 102 is a first-order active analog generator, and the first-order active analog generator may include: a first operational amplifier U1, a first capacitor C1, a connection switch S0, and a first switch S1.
- the output terminal of the current source 101 is connected to the first terminal of the first switch S1, the second terminal of the first switch S1 is connected to the inverting input terminal of the first operational amplifier U1, and the non-inverting input terminal of the first operational amplifier U1 is connected to the reference voltage Vref connection, the first terminal of the first capacitor C1 is connected to the inverting input terminal of the first operational amplifier U1, the second terminal of the first capacitor C1 is connected to the output terminal of the first operational amplifier U1, and the first terminal of the switch S0 is connected It is connected to the output terminal of the first operational amplifier U1, the second terminal of the connection switch S0 is used as the output terminal of the signal generator 102 to connect to the controller 103, and the output terminal of the first operational amplifier U1 is used as the output terminal of the ramp generator.
- the integrator is a single-ended first-order active analog integrator, and the single-ended first-order active analog integrator includes: a second operational amplifier U2, a second capacitor C2, a fourth capacitor C4, and a fifth switch S5.
- the first terminal of the second capacitor C2 serves as the input terminal of the controller 103, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is connected to the reference voltage Vref
- the output terminal of the second operational amplifier U2 is used as the output terminal of the controller 103, the first terminal of the fifth switch S5 is connected to the first voltage V_L, and the second terminal of the fifth switch S5 is connected to the first terminal of the second capacitor C2 Connected, the first end of the fourth capacitor C4 is connected to the inverting input end of the second operational amplifier U2, and the second end of the fourth capacitor C4 is connected to the output end of the second operational amplifier U2.
- Step 201 can be implemented in the following ways:
- Step A1 when the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are fully charged, the output voltage of the first operational amplifier U1 is the reset voltage V_H, and the output voltage of the second operational amplifier U2 is the reference voltage Vref, control The first switch S1 and the fifth switch S5 are closed, and the control connection switch S0 is opened to make the signal generator 102 output a ramp signal.
- Step 202 can be implemented in the following ways:
- Step B1 After the first preset time period has elapsed, control the connection switch S0 to close, control the first switch S1 and the fifth switch S5 to open, so that the controller 103 controls the feedback according to the voltage value of the ramp signal and the first voltage V_L
- the voltage and the feedback voltage are configured to control the current output by the current source 101.
- step A1 to step B1 are repeatedly executed until the preset condition is met.
- step B1 may be:
- the control connection switch S0 is closed, and the first switch S1 and the fifth switch S5 are controlled to open, so that the controller 103 decreases when the final voltage value of the ramp signal is greater than the first voltage V_L
- the feedback voltage increases the feedback voltage when the final voltage value of the ramp signal is less than the first voltage V_L.
- the final state voltage value of the ramp signal is the voltage value corresponding to the final state in the process of changing the voltage value of the ramp signal from high to low (ie, the lowest voltage value in the process of changing the voltage value from high to low).
- the first-order active analog generator may further include: a second switch S2, a third switch S3, and a fourth switch S4.
- the first terminal of the fourth switch S4 is connected to the second terminal of the first capacitor C1, the second terminal of the fourth switch S4 is connected to the reset voltage V_H, and the first terminal of the third switch S3 is connected to the output terminal of the first operational amplifier U1
- the second terminal of the third switch S3 is connected to the second terminal of the first capacitor C1, and the second switch S2 is arranged between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1.
- the single-ended first-order active analog integrator further includes: a seventh switch S7, an eighth switch S8, and a ninth switch S9.
- the second end of the eighth switch S8 is connected to the second end of the fourth capacitor C4, the first end of the eighth switch S8 is connected to the output end of the second operational amplifier U2, and the seventh switch S7 is arranged at the second end of the second operational amplifier U2.
- the ninth switch S9 is arranged between the second terminal of the fourth capacitor C4 and the reference voltage Vref.
- Step 201 can be implemented in the following ways:
- Step A11 control the second switch S2, the fourth switch S4, the fifth switch S5, the seventh switch S7 and the ninth switch S9 to close, and control the connection switch S0, the first switch S1, the third switch S3 and the eighth switch S8 to be off Turn on, so that the reset voltage V_H charges the first capacitor C1, and the reference voltage Vref charges the fourth capacitor C4.
- Step A12 after the first capacitor C1, the second capacitor C2, and the fourth capacitor C4 are charged, the third switch S3, the fifth switch S5, and the eighth switch S8 are controlled to close, and the connection switch S0, the first switch S1, and the first switch S1 are controlled to be closed.
- the second switch S2, the fourth switch S4, the seventh switch S7, and the ninth switch S9 are turned off, so that the output voltage of the first operational amplifier U1 is the reset voltage V_H, and the output voltage of the second operational amplifier U2 is the reference voltage Vref.
- Step A13 control the first switch S1, the third switch S3, the fifth switch S5 and the eighth switch S8 to be closed, and control the connection switch S0, the second switch S2, the fourth switch S4, the seventh switch S7 and the ninth switch S9 to be off Turn on so that the signal generator 102 outputs a ramp signal.
- Step 202 can be implemented in the following ways:
- Step B11 After the first preset time period has elapsed, control the connection switch S0, the third switch S3, and the eighth switch S8 to close, and control the first switch S1, the second switch S2, the fourth switch S4, the fifth switch S5, and the The seventh switch S7 and the ninth switch S9 are turned off, so that the controller 103 controls the feedback voltage according to the voltage value of the ramp signal and the first voltage V_L.
- step A13 to step B11 are repeated until the preset condition is met.
- the preset condition may be: the voltage value of the ramp signal is equal to the first voltage V_L. Or, the number of times of repeating step A13 to step B11 is equal to the preset value.
- the field effect transistor M1 may further include: a twelfth switch S12.
- the gate of the field effect transistor M1 is used as the input end of the current source 101, the source of the field effect transistor M1 is connected to the power supply VDD, the drain of the field effect transistor M1 is used as the output end of the current source 101, and the twelfth switch S12 is set in the field effect Between the drain of the tube M1 and the reference voltage Vref.
- Step A11 also includes: controlling the twelfth switch S12 to close.
- Step A12 also includes: controlling the twelfth switch S12 to close.
- Step A13 also includes: controlling the twelfth switch S12 to turn off.
- Step B11 also includes: controlling the twelfth switch S12 to close.
- the single-ended first-order active analog integrator may further include: a third capacitor C3, a sixth switch S6, a tenth switch S10, and an eleventh switch S11.
- the first terminal of the third capacitor C3 is connected to the second terminal of the second capacitor C2, the second terminal of the third capacitor C3 is connected to the inverting input terminal of the second operational amplifier U2, and the sixth switch S6 is set on the fourth capacitor C4
- the tenth switch S10 is arranged between the first terminal of the third capacitor C3 and the reference voltage Vref, and the eleventh switch S11 is arranged between the third capacitor C3 and the inverting input terminal of the second operational amplifier U2. Between the second end of and the first end of the fourth capacitor C4.
- Step A11 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
- Step A12 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
- Step A13 also includes: controlling the tenth switch S10 and the eleventh switch S11 to close, and controlling the sixth switch S6 to open.
- Step B11 also includes: controlling the tenth switch S10 and the eleventh switch S11 to open, and controlling the sixth switch S6 to close.
- the ramp generator includes a current source, a signal generator, and a controller.
- the output terminal of the current source is connected to the input terminal of the signal generator, and the signal
- the output terminal of the generator is connected with the input terminal of the controller, and the output terminal of the controller is connected with the input terminal of the current source.
- the signal generator can generate a ramp signal according to the current output by the current source.
- the controller adjusts the feedback voltage applied to the current source according to the ramp signal generated by the signal generator.
- the current source controls the current output by the current source according to the adjusted feedback voltage. , It can adjust the ramp generator to generate the ramp signal and improve the stability of the ramp signal.
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Abstract
Description
Claims (10)
- 一种斜坡发生器,其特征在于,所述斜坡发生器包括:电流源(101)、信号发生器(102)和控制器(103),所述电流源(101)的输出端与所述信号发生器(102)的输入端连接,所述信号发生器(102)的输出端与所述控制器(103)的输入端连接,所述控制器(103)的输出端与所述电流源(101)的输入端连接;所述信号发生器(102)配置成根据所述电流源(101)输出的电流产生斜坡信号;所述控制器(103)配置成根据所述斜坡信号调节反馈电压,调节后的所述反馈电压施加在所述电流源(101)上;所述电流源(101)配置成根据所述调节后的反馈电压控制所述电流源(101)输出的电流。
- 根据权利要求1所述的斜坡发生器,其特征在于,所述控制器(103)包括差分积分器,所述差分积分器包括差分模块和积分器;所述差分模块的输出端与所述积分器的输入端连接,所述积分器的输出端与所述电流源(101)的输入端连接,所述差分模块的输入端与所述信号发生器(102)的输出端连接;所述差分模块配置成将所述信号发生器(102)的输出电压与第一电压(V_L)进行差分处理,并将获得的差分电压输入至所述积分器,所述信号发生器(102)的输出电压包括初始电压为复位电压(V_H),通过预设时长输出的所述斜坡信号的电压值;所述积分器配置成将所述差分电压进行积分处理,以获得所述反馈电压。
- 根据权利要求2所述的斜坡发生器,其特征在于,所述差分模块至少包括以下任意一项:电阻或者电容;所述积分器至少包括以下任意一项:单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器、单端多阶无源模拟积分器、多端一阶有源数字积分器、多端一阶有源模拟积分器、多端一阶无源数字积分器、多端一阶无源模拟积分器、多端多阶有源数字积分器、多端多阶有源模拟积分器、多端多阶无源数字积分器和多端多阶无源模拟积分器。
- 根据权利要求1-3任一项所述的斜坡发生器,其特征在于,所述信号发生器(102)至少包括以下任意一项:一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器。
- 根据权利要求4所述的斜坡发生器,其特征在于,所述电流源(101)至少包括以下任意一项:场效应管(M1)、镜像电流源和电阻。
- 一种模拟数字转换器,其特征在于,应用于图像传感器,所述模拟数字转换器包括权利要求1-5中任一项所述的斜坡发生器、比较器、锁存器、寄存器和计数器;所述斜坡发生器的输出端与所述比较器的第一输入端连接,所述比较器的第二输入端配置成接收像素信号,所述比较器的输出端与所述锁存器的输入端连接,所述锁存器的输出端与所述寄存器的第一输入端连接,所述计数器的输出端与所述寄存器的第二输入端连接,所述寄存器的输出端作为所述模拟数字转换器的输出端。
- 一种产生斜坡信号的控制方法,其特征在于,应用于权利要求1-5中任一项所述的斜坡发 生器,所述方法包括:通过所述信号发生器(102)根据所述电流源(101)输出的电流产生斜坡信号,并将所述斜坡信号输出给所述控制器(103);通过所述控制器(103)根据所述斜坡信号调节反馈电压,调节后的所述反馈电压施加在所述电流源(101)上;所述电流源(101)根据所述调节后的反馈电压控制所述电流源(101)输出的电流。
- 根据权利要求7所述的方法,其特征在于,所述控制器(103)包括差分积分器,所述差分积分器包括差分模块和积分器;所述差分模块的输出端与所述积分器的输入端连接,所述积分器的输出端与所述电流源(101)的输入端连接,所述差分模块的输入端与所述信号发生器(102)的输出端连接;所述通过所述控制器(103)根据所述斜坡信号调节反馈电压,调节后的所述反馈电压施加在所述电流源(101)上,包括:通过所述差分模块将所述信号发生器(102)的输出电压与第一电压(V_L)进行差分处理,并将获得的差分电压输入至所述积分器,所述信号发生器(102)的输出电压包括初始电压为复位电压(V_H),通过预设时长输出的所述斜坡信号的电压值;通过所述积分器将所述差分电压进行积分处理,以获得所述反馈电压。
- 根据权利要求8所述的方法,其特征在于,所述差分模块至少包括以下任意一项:电阻或者电容;所述积分器至少包括以下任意一项:单端一阶有源数字积分器、单端一阶有源模拟积分器、单端一阶无源数字积分器、单端一阶无源模拟积分器、单端多阶有源数字积分器、单端多阶有源模拟积分器、单端多阶无源数字积分器和单端多阶无源模拟积分器;所述信号发生器(102)至少包括以下任意一项:一阶有源数字发生器、一阶有源模拟发生器、一阶无源数字发生器、一阶无源模拟发生器、多阶有源数字发生器、多阶有源模拟发生器、多阶无源数字发生器和多阶无源模拟发生器;所述电流源(101)至少包括以下任意一项:场效应管(M1)、镜像电流源和电阻。
- 根据权利要求9所述的方法,其特征在于,所述信号发生器(102)为所述一阶有源模拟发生器,所述一阶有源模拟发生器包括:第一运算放大器(U1)、第一电容(C1)、连接开关(S0)和第一开关(S1);所述电流源(101)的输出端与所述第一开关(S1)的第一端连接,所述第一开关(S1)的第二端与所述第一运算放大器(U1)的反相输入端连接,所述第一运算放大器(U1)的同相输入端与参考电压(Vref)连接,所述第一电容(C1)的第一端与所述第一运算放大器(U1)的反相输入端连接,所述第一电容(C1)的第二端与所述第一运算放大器(U1)的输出端连接,所述连接开关(S0)的第一端与所述第一运算放大器(U1)的输出端连接,所述连接开关(S0)的第二端作为所述信号发生器(102)的输出端与所述控制器(103)连接,所述第一运算放大器(U1)的输出端作为所述斜坡发生器的输出端;所述积分器为所述单端一阶有源模拟积分器,所述单端一阶有源模拟积分器包括:第二运算放大器(U2)、第二电容(C2)、第四电容(C4)和第五开关(S5);所述第二电容(C2)的第一端作为所述控制器(103)的输入端,所述第二电容(C2)的第二端与所述第二运算放大器(U2)的反相输入端连接,所述第二运算放大器(U2)的同相输入端与 所述参考电压(Vref)连接,所述第二运算放大器(U2)的输出端作为所述控制器(103)的输出端,所述第五开关(S5)的第一端与所述第一电压(V_L)连接,所述第五开关(S5)的第二端与所述第二电容(C2)的第一端连接,所述第四电容(C4)的第一端与所述第二运算放大器(U2)的反相输入端连接,所述第四电容(C4)的第二端与所述第二运算放大器(U2)的输出端连接;所述通过所述信号发生器(102)根据所述电流源(101)输出的电流产生斜坡信号,并将所述斜坡信号输出给所述控制器(103),包括:在所述第一电容(C1)、所述第二电容(C2)和所述第四电容(C4)完成充电,所述第一运算放大器(U1)的输出电压为复位电压(V_H),且所述第二运算放大器(U2)的输出电压为所述参考电压(Vref)时,控制所述第一开关(S1)和所述第五开关(S5)闭合,控制所述连接开关(S0)断开,以使所述信号发生器(102)输出斜坡信号;所述通过所述控制器(103)根据所述斜坡信号调节反馈电压,调节后的所述反馈电压施加在所述电流源(101)上,包括:在经过第一预设时长之后,控制所述连接开关(S0)闭合,控制所述第一开关(S1)和所述第五开关(S5)断开,以使所述控制器(103)根据所述斜坡信号的电压值与所述第一电压(V_L),控制所述反馈电压,所述反馈电压配置成控制所述电流源(101)输出的电流;在经过第二预设时长之后,重复执行所述控制所述第一开关(S1)和所述第五开关(S5)闭合,控制所述连接开关(S0)断开,以使所述信号发生器(102)输出斜坡信号,至所述在经过第一预设时长之后,控制所述连接开关(S0)闭合,控制所述第一开关(S1)和所述第五开关(S5)断开的步骤,直至满足预设条件。
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