WO2020210932A1 - 电容器和半导体芯片 - Google Patents

电容器和半导体芯片 Download PDF

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Publication number
WO2020210932A1
WO2020210932A1 PCT/CN2019/082621 CN2019082621W WO2020210932A1 WO 2020210932 A1 WO2020210932 A1 WO 2020210932A1 CN 2019082621 W CN2019082621 W CN 2019082621W WO 2020210932 A1 WO2020210932 A1 WO 2020210932A1
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Prior art keywords
conductor
capacitor
metal
blocks
layer
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PCT/CN2019/082621
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English (en)
French (fr)
Inventor
夏文彬
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/082621 priority Critical patent/WO2020210932A1/zh
Priority to CN201980095469.9A priority patent/CN113711322B/zh
Publication of WO2020210932A1 publication Critical patent/WO2020210932A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • This application relates to the field of electronic technology, in particular to a capacitor and a semiconductor chip.
  • MOM Metal-oxide-metal
  • MIM metal-insulator-metal
  • the capacitor in the prior art includes a plurality of electrode plates and a dielectric between the electrode plates, which is usually realized by a plurality of conductor layers and corresponding dielectric layers.
  • the electrode plate may be located on a metal layer
  • the dielectric may be located on a dielectric layer between different metal layers.
  • the antenna effect (Antenna Effect) introduced by the capacitor will increase, resulting in performance degradation. That is, there is a large area of metal wire or metal body in the metal layer.
  • the metal wire or metal body is equivalent to an antenna. Since charges are generated during the chip production process, the antenna collects these charges, thereby causing an antenna effect. Especially when the area of the metal wire or metal body is larger, the accumulated charge is more. When the accumulated charge reaches a certain amount of charge, it will be discharged, which may cause failure of other devices connected to the metal wire. Therefore, the antenna effect introduced by the capacitor will be an urgent problem to be solved.
  • the embodiments of the present application provide a capacitor and a semiconductor chip to reduce the antenna effect introduced by the capacitor.
  • the first aspect of the present application provides a capacitor, including: a first electrode plate arranged on the first conductor layer; a second electrode plate arranged on the second conductor layer; wherein the first conductor The layer and the second conductor layer are separated by at least one dielectric layer, and at least one of the first electrode plate and the second electrode plate includes at least one slot.
  • at least one electrode plate includes one or more slots, the area and charge collection capacity of the at least one electrode plate are reduced, thereby reducing the antenna effect in the manufacturing process.
  • the slot can be used to reduce the stress of at least one electrode plate and avoid the expansion and warpage caused by the manufacturing process.
  • the capacitor further includes: a plurality of conductor blocks arranged on at least one third conductor layer, and the at least one third conductor layer is located between the first conductor layer and the second conductor layer. Between the conductor layers, the first conductor layer, the second conductor layer and the at least one third conductor layer are separated by the at least one dielectric layer; wherein the plurality of conductor blocks include at least one first conductor Block and at least one second conductor block, the at least one first conductor block is coupled to the first plate through at least one first through hole, and the at least one second conductor block is coupled to the first plate through at least one second through hole The second plate.
  • any through hole can fully connect the conductor blocks in different third conductor layers, reduce the wiring resistance of the conductor blocks in different third conductor layers, and improve the quality factor (Q) value of the capacitor.
  • the above capacitors include two types of capacitors.
  • the first type of capacitor is one or more main capacitors formed by a plate and one or more conductor blocks
  • the second type of capacitor is a side formed by a plurality of conductor blocks and a plurality of through holes.
  • the capacitance value of the entire capacitor includes the capacitance value of the main capacitor and the capacitance value of the sidewall capacitor.
  • each first conductor block in any third conductor layer is adjacent to one or more second conductor blocks in any third conductor layer.
  • the first conductor block and the adjacent one or more second conductor blocks can be used to form a sidewall capacitor to improve the performance of the entire capacitor.
  • all the multiple adjacent blocks of each first conductor block are second conductor blocks.
  • all of the multiple adjacent blocks are four second conductor blocks.
  • the four second conductor blocks are the left adjacent block, the right adjacent block, and the upper adjacent block of each first conductor block. The adjacent block and the lower adjacent block.
  • the at least one third conductor layer is a plurality of third conductor layers; one of any first conductor block in any third conductor layer and another third conductor layer
  • the first conductor block is coupled through a first through hole
  • any second conductor block in any third conductor layer and a second conductor block in the other third conductor layer pass through a second through hole.
  • the holes are coupled, and the other third conductor layer is adjacent to any one of the third conductor layers in a vertical direction.
  • At least one of the first conductor layer, the second conductor layer, and the at least one third conductor layer is a metal layer.
  • the projections of the first electrode plate, the second electrode plate, and the plurality of conductor blocks in the vertical direction overlap.
  • the projections of the first electrode plate and the second electrode plate in the vertical direction overlap.
  • the vertical direction is a direction perpendicular to any one layer, such as the first conductor layer, the second conductor layer, at least one third conductor layer, or the at least one dielectric layer.
  • the at least one dielectric layer includes oxide.
  • the capacitor includes a metal-oxide-metal MOM capacitor.
  • the first electrode plate or the second electrode plate is coupled to a power line or a ground line.
  • the capacitor is applied to the power line or the ground line as a decoupling capacitor (DECAP), and the manufacturing process of the capacitor can be maintained roughly by the manufacturing process of other devices on the existing power line or ground line. Consistent.
  • DECAP decoupling capacitor
  • a second aspect of the present application provides a capacitor, including: a first electrode plate arranged on a first conductor layer; a second electrode plate arranged on a second conductor layer; a plurality of conductor blocks arranged on at least one first conductor layer; Three conductor layers, the at least one third conductor layer is located between the first conductor layer and the second conductor layer; wherein the plurality of conductor blocks includes at least one first conductor block and at least one second conductor The at least one first conductor block is coupled to the first electrode plate through at least one first through hole, and the at least one second conductor block is coupled to the second electrode plate through at least one second through hole.
  • the at least one third conductor layer does not include a complete plate but a plurality of conductor blocks, there is no conductor with a large area that can collect charges, thereby reducing the antenna effect in the manufacturing process. Furthermore, any through hole can fully connect the conductor blocks in different third conductor layers, reduce the wiring resistance of the conductor blocks in different third conductor layers, and improve the quality factor (Q) value of the capacitor.
  • each first conductor block in any third conductor layer is adjacent to one or more second conductor blocks in any third conductor layer.
  • the first conductor block and the adjacent one or more second conductor blocks can be used to form a sidewall capacitor to improve the performance of the entire capacitor.
  • all the multiple adjacent blocks of each first conductor block are second conductor blocks.
  • all of the multiple adjacent blocks are four second conductor blocks.
  • the four second conductor blocks are the left adjacent block, the right adjacent block, and the upper adjacent block of each first conductor block. The adjacent block and the lower adjacent block.
  • At least one of the first electrode plate and the second electrode plate includes at least one slot.
  • the slot can be used to reduce the stress of at least one electrode plate and avoid the expansion and warpage caused by the manufacturing process.
  • the projections of the first electrode plate, the second electrode plate, and the plurality of conductor blocks in the vertical direction overlap.
  • the projection occupies a smaller area, reduces the volume of the capacitor, and provides more flexibility for the wiring layout of the first electrode plate and the second electrode plate.
  • the at least one third conductor layer is a plurality of third conductor layers; one of any first conductor block in any third conductor layer and another third conductor layer
  • the first conductor block is coupled through a first through hole
  • any second conductor block in any third conductor layer and a second conductor block in the other third conductor layer pass through a second through hole.
  • the holes are coupled, and the other third conductor layer is adjacent to any one of the third conductor layers in a vertical direction.
  • the vertical direction is a direction perpendicular to any one layer, such as the first conductor layer, the second conductor layer, at least one third conductor layer, or the at least one dielectric layer.
  • At least one of the first conductor layer, the second conductor layer, and the at least one third conductor layer is a metal layer.
  • the first conductor layer, the second conductor layer, and the at least one third conductor layer are separated by a dielectric layer.
  • the dielectric layer includes oxide.
  • the capacitor includes a metal-oxide-metal MOM capacitor.
  • the first electrode plate or the second electrode plate is coupled to a power line or a ground line.
  • the capacitor is applied to the power line or the ground line as a decoupling capacitor (DECAP), and the manufacturing process of the capacitor can be maintained roughly by the manufacturing process of other devices on the existing power line or ground line. Consistent.
  • DECAP decoupling capacitor
  • the third aspect of the present application provides a semiconductor chip, including the capacitor mentioned in the first aspect, the second aspect or any one of the possible implementation manners.
  • the semiconductor chip is a radio frequency chip.
  • the fourth aspect of the present application provides a circuit board, which includes the capacitor mentioned in the first aspect, the second aspect, or any one of the possible implementation manners.
  • FIG. 1 is a schematic diagram of a capacitor built in a semiconductor chip in an embodiment of the application
  • FIG. 2 is a schematic diagram of the structure of a capacitor in an embodiment of the application.
  • FIG. 3 is a schematic diagram of a plurality of layers used to form a capacitor in an embodiment of the application
  • Fig. 4 is a two-dimensional top view of a capacitor in an embodiment of the application.
  • Figure 5 is a two-dimensional top view of another capacitor in an embodiment of the application.
  • Fig. 6 is a two-dimensional top view of another capacitor in an embodiment of the application.
  • FIG. 7 is a schematic diagram of the projection relationship in the vertical direction between the two plates and the conductor block of another capacitor in an embodiment of the application.
  • FIG. 1 is a schematic diagram of a capacitor 10 built in a semiconductor chip 01 in an embodiment of the application.
  • the semiconductor chip 01 may also be referred to as a chip for short, which may be a collection of integrated circuits formed on a substrate of an integrated circuit fabricated by an integrated circuit process.
  • the substrate is usually a semiconductor material such as silicon.
  • the outside of the substrate after the integrated circuit is formed is usually encapsulated by a semiconductor packaging material.
  • the integrated circuit may include various types of functional devices, and each type of functional device includes transistors such as logic gate circuits, metal-oxide-semiconductor (MOS) transistors, bipolar transistors or diodes, and may also include capacitors, resistors, or inductors. part.
  • Functional devices can work independently or under the action of necessary driver software, and can realize various functions such as communication, calculation, or storage.
  • the semiconductor chip 01 may include an application processor chip, a video processor chip, a communication chip, a control chip, an artificial intelligence chip, a radio frequency chip, or a system on chip (SoC, System on Chip) that integrates any of the above chips. ), this embodiment does not limit this.
  • the capacitor 10 provided in this embodiment may be a MOM capacitor, but is not limited to this, and may also be an MIM capacitor, depending on whether the material used to form the dielectric layer of the capacitor 10 is oxide or other materials. It can be understood that the capacitor 10 provided in the example of FIG. 1 is integrated inside the semiconductor chip 01, and the capacitor 10 may further include a first terminal and a second terminal for connecting the capacitor 10 to other functional circuits inside the semiconductor chip 01 . Although the following embodiments are described by taking this integration scenario as an example, it can be understood that the capacitor 10 may also be located outside the semiconductor chip 01 used for logic operations or processing, and exist as an independent device. That is, the capacitor 10 may be a discrete device.
  • FIG. 2 provides a schematic diagram of the structure of a capacitor 10 in an embodiment of the present application.
  • X represents the length direction or the horizontal direction
  • Y represents the width direction or the depth direction
  • Z represents the height direction or the vertical direction.
  • the X direction and the Y direction are used to form a horizontal plane
  • the Z direction is perpendicular to the horizontal plane.
  • the capacitor 10 is a MOM capacitor.
  • the capacitor 10 is formed on multiple metal layers of a semiconductor by using an integrated circuit manufacturing process. E.g. In the vertical direction Z, the metal layers 1 to 4 are included from top to bottom.
  • any one or more dielectric layers may include oxide. It can be understood that the material of the dielectric layer may also include other dielectric materials besides oxide.
  • FIG. 3 is a schematic diagram of a plurality of layers for forming a capacitor 10 provided by an embodiment of the present invention.
  • two poles of the capacitor 10 such as the first pole A and the second pole B, may be formed in a plurality of metal layers. Each pole is used to couple to one end of the capacitor 10, such as the first and second ends as shown in FIG. 1.
  • the first and second ends may be wires or wires that couple the first pole A and the second pole B.
  • Conductor, the wire or conductor is used for coupling to other functional circuits or the wire of one pole, or the conductor is used for coupling to the functional circuit, and the wire of the other pole is used for coupling to ground or other potentials.
  • metal layer 1 is the upper metal layer
  • metal layer 4 is the lower metal layer
  • metal layers 2 and 3 are the middle metal layers, located Between metal layer 1 and metal layer 4.
  • the first pole A includes a pole plate labeled A (referred to as an upper pole plate) located in the metal layer 1 and a plurality of metal blocks labeled A located in the metal layers 2 and 3.
  • the second pole B includes a pole plate labeled B (referred to as a lower pole plate) located in the metal layer 4, and a plurality of metal blocks labeled B located in the metal layers 2 and 3.
  • At least one slot may be included on any one or both of the upper electrode plate and the lower electrode plate, and the slot provided on any electrode plate is equivalent to punching holes on the electrode plate.
  • the slot part of the hole is hollowed out, or removed or filled with other materials, such as non-conducting materials, so that the plate is no longer a complete piece of metal or conductor.
  • the existence of at least one slot makes the area of the pole plate smaller.
  • these slots on the two plates can be used to reduce the area and charge collection capacity of the plates, thereby reducing the antenna effect, and further can be used to reduce the stress on the two plates and avoid making Expansion and warpage caused by the process.
  • the shape of any slot can be flexibly set, including but not limited to rectangle, diamond, circle, triangle, etc.
  • the slot gap in the embodiment of the present invention is rectangular, which is only used for example but not for limitation.
  • metal block marked A is coupled with the upper electrode plate through multiple through holes, thereby forming the first One pole A.
  • a plurality of metal blocks marked as B are coupled with the lower electrode plate through a plurality of through holes, thereby forming a second electrode B.
  • the wire or conductor serving as one end of the capacitor 10 can be coupled to the upper plate or the lower plate (not shown in the figure) to connect to other devices or functional circuits.
  • any plate and multiple metal blocks can be used to form multiple main capacitors, for example, plate B and any metal block A form a main capacitor CC.
  • a plurality of metal blocks and a plurality of through holes are used to form sidewall capacitors.
  • the two metal blocks B located on the metal layers 2 and 3 on the left and the corresponding two through holes are used for A conductor post is formed, and the two metal blocks A on the right side of the conductor post and the corresponding two through holes are used to form another conductor post, and these two conductor posts can be used to form a sidewall capacitor C.
  • the intermediate metal layers 2 and 3 do not include complete plates, but multiple independent metal blocks, there is no large-area conductor that can collect charges, thereby reducing the antenna in the manufacturing process. effect. Further, any through hole can fully connect different metal blocks in different metal layers, reduce the wiring resistance between the different metal blocks, and improve the quality factor (Q) value of the capacitor 10.
  • the number of intermediate metal layers can be set arbitrarily, that is, set to any positive integer.
  • this embodiment can be extended to a three-layer metal layer structure with only one intermediate metal layer or an eleven-layer metal layer structure with nine intermediate metal layers, which is not specifically limited in this embodiment.
  • the greater the number of intermediate metal layers and the longer the length of the conductor post the greater the capacitance value of the sidewall capacitor, resulting in a greater overall capacitance value.
  • a metal layer is used to form the pole of the capacitor, but in fact, any one or more metal layers can be replaced by a conductor layer including other conductive materials, and achieve similar technical effects.
  • the metal electrode plate may be replaced by a conductive plate formed of other conductive materials
  • the metal block may be replaced by a conductive block formed of other conductive materials.
  • a plurality of metal blocks marked A and a plurality of metal blocks marked B may be arranged in a certain manner.
  • any metal block labeled A may be adjacent to one or more metal blocks labeled B.
  • the neighbor here may be the closest distance or the distance within a certain range, which is not specifically limited in this embodiment.
  • a plurality of metal blocks are arranged in a straight line along the length direction X (assumed as the horizontal direction in FIG. 4) and the width direction Y (assumed as the vertical direction in FIG. 4) on the metal layer .
  • Each metal block includes four adjacent metal blocks, namely a left adjacent block, a right adjacent block, an upper adjacent block, and a lower adjacent block.
  • the four adjacent blocks of each metal block marked A are all metal blocks marked B, on the contrary, the four adjacent blocks of each metal block marked B are all marked A
  • the metal blocks are arranged so that a plurality of metal blocks marked A and a plurality of metal blocks marked B are arranged at intervals in the form of ABAB, that is, a network structure is formed, so that the overall performance of the capacitor 10 is optimized.
  • ABAB that is, a network structure is formed
  • the arrangement of multiple metal blocks can be flexibly adjusted, instead of being arranged at intervals as shown in Figure 4.
  • Figure 5 Take Figure 5 as an example.
  • the adjacent blocks of a metal block include the left adjacent block, the right adjacent block, the upper adjacent block, and the lower adjacent block, as well as the upper left adjacent block, the upper right adjacent block, the lower left adjacent block, and The lower right adjacent block, that is, a total of eight adjacent blocks.
  • a metal block labeled B forms five sidewall capacitors C with the upper adjacent block, the lower adjacent block, the right adjacent block, the upper left adjacent block, and the lower left adjacent block.
  • any metal block can form a sidewall capacitor C with eight surrounding metal blocks.
  • eight adjacent blocks of a metal block marked as B namely left adjacent block, right adjacent block, upper adjacent block, lower adjacent block, upper left adjacent block, upper right adjacent block, and lower left adjacent block
  • the adjacent block and the lower right adjacent block are both metal blocks marked A, thereby forming eight sidewall capacitors C.
  • this article will not introduce them in detail, and those skilled in the art can make adjustments according to the enlightenment given in this embodiment without departing from the protection scope of the present invention.
  • FIG. 7 a schematic diagram of the projection relationship between the two pole plates and the metal block in the vertical direction is given.
  • the projection distance of the two plates on the horizontal plane is opened to reduce the volume of the capacitor 10 and provide more flexibility for the wiring layout of the two plates.
  • the area sizes of the upper electrode plate A and the lower electrode plate B are different, but it can be understood that one or both of the sizes and shapes of the two can be selectively the same or different.
  • the projections of the two in the vertical direction can be completely consistent.
  • the distribution modes of the multiple metal blocks of the multiple intermediate metal layers may be the same or different. If the multiple metal blocks of the multiple intermediate metal layers are distributed in the same manner, as shown in FIG. 7, in the top view formed by observing the capacitor 10 in the vertical direction Z, the metal blocks in one intermediate metal layer are adjacent to the upper middle Corresponding metal blocks in the metal layer or the adjacent middle metal layer below are overlapped, and the two metal blocks are coupled through a through hole, and the upper and lower sides are along the Z direction.
  • the metal blocks in one intermediate metal layer are adjacent to the upper adjacent intermediate metal layer or the lower adjacent
  • the corresponding metal blocks in the middle metal layer of is not overlapped, and the through holes used to couple the two metal blocks will no longer extend in the vertical direction Z, but will be bent or inclined for coupling the two metal blocks .
  • the structure of the above capacitor 10 can be realized by using a Back End OF Line (BEOL) process.
  • BEOL Back End OF Line
  • the overall capacitance value can exceed that of a conventional capacitor under the same horizontal area, so that the capacitor 10 It can be used in various application scenarios, especially for signal filtering or power ground decoupling capacitor (DECAP) and other scenarios.
  • DECAP power ground decoupling capacitor
  • the capacitor 10 in FIG. 2 may not have an intermediate metal layer, that is, the capacitor 10 includes an upper electrode plate and a lower electrode plate, and one or more dielectric layers may be included between the upper electrode plate and the lower electrode plate, And one or all of the upper plate and the lower plate may have at least one slot, so as to reduce the area of the plate, thereby reducing the antenna effect, and reducing the stress of the two plates, avoiding the production process. Swelling and warping problems.
  • the intermediate metal layer and the metal blocks therein are only optional solutions of the embodiment. Even if these intermediate metal layers and metal blocks do not exist, the technical effect can be achieved to a certain extent.
  • the presence of the intermediate metal layer and the metal block can further achieve technical effects, such as avoiding expansion and warping caused by the manufacturing process, which will not be repeated here. It can be understood that if the at least one slot does not exist on the two pole plates, only the design of the intermediate metal layer and the metal block as shown in FIG. 2 can also achieve technical effects to a certain extent.
  • one of the upper plate or the lower plate may be selectively coupled to the power line or the ground line in the semiconductor chip 01.
  • the upper electrode plate and the lower electrode plate may be respectively coupled to the power line and the ground line in the semiconductor chip 01 to realize the filtering function.
  • the capacitor 10 is applied to at least one of the power line or the ground line as a decoupling capacitor (DECAP), and the manufacturing process of the capacitor 10 can use the existing power line or other devices on the ground line
  • DECAP decoupling capacitor
  • the production process remains roughly the same, simplifying the production process.
  • the manufacturing process and layout design of the capacitor 10 are very close to those of the capacitor 10 shown in FIG. 2. Therefore, the capacitor 10 is applied to the power line or ground line. Therefore, the capacitor 10 can be manufactured without major modifications to the manufacturing process and layout design of the existing device. On the basis of the filter function, the manufacturing process and layout design difficulty of the capacitor 10 are simplified.

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Abstract

一种电容器，被内置于半导体芯片中，包括两个极板，这两个极板分别分布于该半导体芯片中的两个金属层上。在这两个金属层之间还分布有多个金属层，每个金属层上分布有多个金属块。所述多个金属块包括多个第一金属块和多个第二金属块，所述多个第一金属块通过多个第一通孔耦合至一个极板，所述多个第二金属块通过多个第二通孔耦合至另一极板。每两个相邻的金属层被介质层所隔离。每个极板上可包括一个或多个槽隙。该电容器可以有效降低天线效应。

Description

电容器和半导体芯片 技术领域
本申请涉及电子技术领域，尤其涉及一种电容器和半导体芯片。
背景技术
随着集成电路制作工艺的演进，各类器件，例如电容器的制作工艺尺寸不断减小，其中金属-氧化物-金属(MOM，Metal-Oxide-Metal)电容器和金属-绝缘体-金属(MIM，Metal-Insulator-Metal)电容器是常见的两类电容器。现有技术中的电容器包括多个极板以及位于极板之间的介质，这通常由多个导体层和对应的介质层实现。例如，极板可以位于金属层，介质可以位于不同金属层之间的介质层。随着制作工艺的演进，电容器引入的天线效应(Antenna Effect)会增加，从而带来性能退化。即，金属层中存在大面积的金属线或金属体，该金属线或金属体相当于天线，由于在芯片生产过程中会产生电荷，该天线会收集这些电荷，从而导致天线效应。特别是当金属线或金属体面积越大时，积累的电荷越多。当积累的电荷达到一定电荷量后将会放电，可能造成连接在金属线上的其他器件失效。因此，电容器引入的天线效应将是一个亟待解决的问题。
发明内容
本申请的实施例提供一种电容器和半导体芯片，以减少电容器引入的天线效应。
有鉴于此，本申请第一方面提供了一种电容器，包括：第一极板，被布置于第一导体层；第二极板，被布置于第二导体层；其中，所述第一导体层和所述第二导体层被至少一个介质层隔离，所述第一极板和所述第二极板中的至少一个极板上包括至少一个槽隙。根据以上技术方案，由于至少一个极板上包括一个或多个槽隙，该至少一个极板的面积和电荷收集能力被降低，从而降低制作工艺中的天线效应。进一步地。该槽隙可用于降低至少一个极板的应力，避免制作工艺导致的膨胀曲翘问题。
在一种可能的实现方式中，所述电容器还包括：多个导体块，被布置于至少一个第三导体层，所述至少一个第三导体层位于所述第一导体层和所述第二导体层之间，所述第一导体层、所述第二导体层和所述至少一个第三导体层被所述至少一个介质层隔离；其中，所述多个导体块包括至少一个第一导体块和至少一个第二导体块，所述至少一个第一导体块通过至少一个第一通孔耦合至所述第一极板，所述至少一个第二导体块通过至少一个第二通孔耦合至所述第二极板。
根据以上技术方案，由于至少一个第三导体层中并不包括完整的极板，而是包括多个导体块，因此不存在大面积的可收集电荷的导体，从而进一步降低制作工艺中的天线效应。进一步地，任一通孔可充分连接处于不同第三导体层中的导体块，降低不同第三导体层中的导体块的走线电阻，提高该电容器的品质因数(Q)值。
在以上电容器中包括两类电容器，第一类电容器是一极板与一个或多个导体块形成的一个或多个主电容器，第二类电容器是多个导体块和多个通孔形成的侧壁电容器， 整个电容器的电容值包括主电容器的电容值和侧壁电容器的电容值。
在一种可能的实现方式中，任一第三导体层中的每个第一导体块与所述任一第三导体层中的一个或多个第二导体块相邻。采用该技术方案，第一导体块和相邻的一个或多个第二导体块可用于形成侧壁电容器，以提升整个电容器的性能。
在另一种可能的实现方式中，所述每个第一导体块的全部多个相邻块均是第二导体块。在另一种可能的实现方式中，所述全部多个相邻块是四个第二导体块。在另一种可能的实现方式中，在所述任一第三导体层中，所述四个第二导体块是所述每个第一导体块的左相邻块、右相邻块、上相邻块和下相邻块。采用本技术方案，让同一个第三导体层中的多个第二导体块和多个第二导体块间隔排列，即形成网状结构，使得电容器的整体性能得到优化。
在另一种可能的实现方式中，所述至少一个第三导体层是多个第三导体层；任一第三导体层中的任一第一导体块与另一第三导体层中的一个第一导体块通过一第一通孔相耦合，所述任一第三导体层中的任一第二导体块与所述另一第三导体层中的一个第二导体块通过一第二通孔相耦合，所述另一第三导体层与所述任一第三导体层在垂直方向上相邻。该结构有利于充分利用多个通孔形成侧壁电容器，提高电容器性能。
在另一种可能的实现方式中，所述第一导体层、所述第二导体层和所述至少一个第三导体层中的至少一个导体层是金属层。
在另一种可能的实现方式中，所述第一极板、所述第二极板和所述多个导体块在垂直方向上的投影相重叠。在另一种可能的实现方式中，所述第一极板和所述第二极板在垂直方向上的投影相重叠。采用该技术方案，所述投影占据更小的面积，缩小了电容器的体积，为所述第一极板和所述第二极板的连线布局提供更多灵活性。
可选地，所述垂直方向是垂直于任意一个层，如第一导体层、第二导体层、至少一个第三导体层或所述至少一个介质层，的方向。
在另一种可能的实现方式中，所述至少一个介质层包括氧化物。在另一种可能的实现方式中，所述电容器包括金属-氧化物-金属MOM电容器。
在另一种可能的实现方式中，所述第一极板或所述第二极板被耦合至电源线或接地线。采用本技术方案，该电容器被应用于电源线或接地线，作为去耦电容(DECAP)使用，且该电容器的制作过程可以用现有的电源线或接地线上的其他器件的制作过程保持大致一致。
本申请第二方面提供了一种电容器，包括：第一极板，被布置于第一导体层；第二极板，被布置于第二导体层；多个导体块，被布置于至少一个第三导体层，所述至少一个第三导体层位于所述第一导体层和所述第二导体层之间；其中，所述多个导体块包括至少一个第一导体块和至少一个第二导体块，所述至少一个第一导体块通过至少一个第一通孔耦合至所述第一极板，所述至少一个第二导体块通过至少一个第二通孔耦合至所述第二极板。
根据以上技术方案，由于至少一个第三导体层中并不包括完整的极板，而是包括多个导体块，因此不存在大面积的可收集电荷的导体，从而降低制作工艺中的天线效应。进一步地，任一通孔可充分连接处于不同第三导体层中的导体块，降低不同第三导体层中的导体块的走线电阻，提高该电容器的品质因数(Q)值。
在一种可能的实现方式中，任一第三导体层中的每个第一导体块与所述任一第三导体层中的一个或多个第二导体块相邻。采用该技术方案，第一导体块和相邻的一个或多个第二导体块可用于形成侧壁电容器，以提升整个电容器的性能。
在另一种可能的实现方式中，所述每个第一导体块的全部多个相邻块均是第二导体块。在另一种可能的实现方式中，所述全部多个相邻块是四个第二导体块。在另一种可能的实现方式中，在所述任一第三导体层中，所述四个第二导体块是所述每个第一导体块的左相邻块、右相邻块、上相邻块和下相邻块。采用本技术方案，让同一个第三导体层中的多个第二导体块和多个第二导体块间隔排列，即形成网状结构，使得电容器的整体性能得到优化。
在另一种可能的实现方式中，所述第一极板和所述第二极板中的至少一个极板上包括至少一个槽隙。该槽隙可用于降低至少一个极板的应力，避免制作工艺导致的膨胀曲翘问题。
在另一种可能的实现方式中，所述第一极板、所述第二极板和所述多个导体块在垂直方向上的投影相重叠。采用该技术方案，所述投影占据更小的面积，缩小了电容器的体积，为所述第一极板和所述第二极板的连线布局提供更多灵活性。
在另一种可能的实现方式中，所述至少一个第三导体层是多个第三导体层；任一第三导体层中的任一第一导体块与另一第三导体层中的一个第一导体块通过一第一通孔相耦合，所述任一第三导体层中的任一第二导体块与所述另一第三导体层中的一个第二导体块通过一第二通孔相耦合，所述另一第三导体层与所述任一第三导体层在垂直方向上相邻。该结构有利于充分利用多个通孔形成侧壁电容器，提高电容器性能。
可选地，所述垂直方向是垂直于任意一个层，如第一导体层、第二导体层、至少一个第三导体层或所述至少一个介质层，的方向。
在另一种可能的实现方式中，所述第一导体层、所述第二导体层和所述至少一个第三导体层中的至少一个导体层是金属层。在另一种可能的实现方式中，所述第一导体层、所述第二导体层和所述至少一个第三导体层被介质层隔离。可选地，所述介质层包括氧化物。
在另一种可能的实现方式中，所述电容器包括金属-氧化物-金属MOM电容器。
在另一种可能的实现方式中，所述第一极板或所述第二极板被耦合至电源线或接地线。采用本技术方案，该电容器被应用于电源线或接地线，作为去耦电容(DECAP)使用，且该电容器的制作过程可以用现有的电源线或接地线上的其他器件的制作过程保持大致一致。
本申请第三方面提供了半导体芯片，包括以上第一方面、第二方面或其中任一可能的实现方式中提到的电容器。可选地，该半导体芯片是射频芯片。
本申请第四方面提供了一种电路板，包括以上第一方面、第二方面或其中任一可能的实现方式中提到的电容器。
本申请的以上方面或可能的实现方案在以下实施例的描述中会更加清楚易懂。
附图说明
图1为本申请实施例中一种内置于半导体芯片的电容器的示意图；
图2为本申请实施例中一种电容器的结构示意图；
图3为本申请实施例中一种用于形成电容器的多个层的示意图；
图4为本申请实施例中一种电容器的二维俯视图；
图5为本申请实施例中另一种电容器的二维俯视图；
图6为本申请实施例中另一种电容器的二维俯视图；
图7为本申请实施例中另一种电容器的两个极板与导体块在垂直方向上的投影关系的示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请实施例方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本申请的说明书实施例和权利要求书及上述附图中的术语“第一”、“第二”、和“第三”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”以及其任何变形，意图在于覆盖不排他的包含，例如，包含了一系列模块或单元。本实施例所描述的耦合一词，可以用于实现不同元件、部件或模块之间的互相联系，包括了任意电连接形式，如直接接触，通过导线、通孔、通孔槽、或其他器件连接等方式。
在现代通信或电子系统中，电容器被越来越广泛地应用，例如应用在半导体芯片中或其他类型的电路，如印制电路板(PCB，Printed Circuit Board)中。图1为本申请实施例中一种内置于半导体芯片01的电容器10的示意图。该半导体芯片01也可以简称为芯片，其可以是利用集成电路工艺制作在集成电路的衬底上形成的集成电路的集合，衬底通常是例如硅一类的半导体材料。形成集成电路后的衬底的外部通常被半导体封装材料封装。所述集成电路可以包括各类功能器件，每一类功能器件包括逻辑门电路、金属-氧化物-半导体(MOS)晶体管、双极晶体管或二极管等晶体管，也可包括电容器、电阻或电感等其他部件。功能器件可以独立工作或者在必要的驱动软件的作用下工作，可以实现通信、运算、或存储等各类功能。例如，半导体芯片01可以包括应用处理器芯片、视频处理器芯片、通信芯片、控制芯片、人工智能芯片、射频芯片、或集成了以上各芯片中任意多个功能的片上系统(SoC，System on Chip)，本实施例对此不作限制。
本实施例的提供的电容器10可以是MOM电容器，但不限于此，也可以是MIM电容器，这取决于用于形成该电容器10的介质层所使用的材料是氧化物还是其他材料。可以理解，图1的示例提供的电容器10被集成在半导体芯片01内部，该电容器10可进一步包括第一端和第二端，用于将该电容器10接入到半导体芯片01内部的其他功能电路。后续实施例虽然以该集成场景为例进行描述，可以理解，电容器10也可以位于用于逻辑运算或处理的半导体芯片01之外，作为独立的器件存在。即，电容器10可以是一个分立的器件。
为了更清晰的理解电容器10的结构，图2提供了本申请实施例中一种电容器10的结构示意图。在该三维的结构示意图中，存在X、Y和Z三个方向，X代表长度方向或水平方向，Y代表宽度方向或深度方向，Z代表高度方向或垂直方向。其中，X方向和Y方向用于形成水平面，Z方向则垂直于该水平面。在该三维结构中，电容器10是MOM电容器。 该电容器10通过采用集成电路制作工艺在半导体的多个金属层上形成。例如。在垂直方向Z上，从上到下包括金属层1至4。每两个相邻的金属层之间被介质层所分隔。每个金属层或介质层垂直于所述垂直方向Z，并位于由长度方向X和宽度方向Y所形成的一个水平面上。由于电容器10是MOM电容器，任一个或多个介质层可以是包括氧化物。可以理解，该介质层的材料也可以包括除了氧化物之外的其他介质材料。
具体可参见图3，为本发明实施例提供的一种用于形成电容器10的多个层的示意图。在半导体制作工艺中，可以在多个金属层中形成电容器10的两个极，例如第一极A和第二极B。每个极用于耦合至电容器10的一端，如图1所示的第一端和第二端，该第一端和第二端可以是耦合该第一极A和第二极B的导线或导体，该导线或导体用于耦合至其他功能电路或者其中一极的导线，或导体用于耦合至功能电路，另一极的导线用于耦合至地或其他电位。在垂直方向上，每两个相邻的金属层之间具有一个介质层。
以图2并结合图3所示，在沿垂直方向Z排列的多个金属层中，金属层1是上金属层，金属层4是下金属层，金属层2和3是中间金属层，位于金属层1和金属层4之间。第一极A包括位于金属层1中的一个被标记为A的极板(被称为上极板)，以及位于金属层2和3中多个被标记为A的金属块。第二极B包括位于金属层4中的一个被标记为B的极板(被称为下极板)，以及位于金属层2和3中多个被标记为B的金属块。在上极板和下极板中的任一个或全部两个极板上可以包括至少一个槽隙，设置在任一极板上的所述槽隙相当于是在该极板上打孔，该极板的槽隙部位被挖空、或去除或被其他材料，如非导体材料填充，以使得极板不再是完整的一块金属或导体。至少一个槽隙的存在使得极板的面积变小。如图2所示，这两个极板上的这些槽隙可以用于减少极板的面积和电荷收集能力，从而降低天线效应，并且进一步地可用于降低该两个极板的应力，避免制作工艺导致的膨胀曲翘问题。可选地，任一槽隙的形状可以灵活设置的，包括但不限于矩形、菱形、圆形、三角形等。本发明实施例的槽隙是矩形的，仅用于举例但不用于限定。
进一步地，如图2和图3所示，在金属层2和3中，可以存在多个金属块，其中被标记为A的金属块通过多个通孔与上极板相耦合，从而形成第一极A。类似地，多个被标记为B的金属块通过多个通孔与下极板相耦合，从而形成第二极B。作为电容器10的一端的导线或导体可以耦合在上极板或下极板上(图中未示出)，以用于连通其他器件或功能电路。
在图2中，在垂直方向Z上，任一极板与多个金属块可用于形成的多个主电容器，例如极板B与任一金属块A会形成一个主电容器CC。在沿水平面延伸的方向上，多个金属块和多个通孔用于形成的侧壁电容器，例如左侧的位于金属层2和3的两个金属块B和对应的两个通孔用于形成一个导体柱，该导体柱右侧的两个金属块A和对应的两个通孔用于形成另一个导体柱，这两个导体柱可用于形成侧壁电容器C。整个电容器10的电容值包括多个主电容器的电容值和多个侧壁电容器的电容值，即整体电容值C_total＝nC+mCC，n和m为正整数，取决于导体柱或者金属块的数量。在以上方案中，由于中间金属层2和3中并不包括完整的极板，而是包括多个独立的金属块，因此不存在大面积的可收集电荷的导体，从而降低制作工艺中的天线效应。进一步地，任一通孔可充分连接处于不同金属层中的不同金属块，降低所述不同金属块之间的走 线电阻，提高该电容器10的品质因数(Q)值。
可以理解，在以上图2所示技术方案中，存在两个中间金属层2和3，实际上，中间金属层的数量可以任意设定，即设为任意正整数。例如，本实施例可扩展为仅有一个中间金属层的三层金属层结构或者有九个中间金属层的十一层金属层结构，本实施例不做具体严格限定。中间金属层的数量越多，导体柱的长度越长，侧壁电容器的电容值越大，从而导致更大的整体电容值。此外，本实施例以金属层形成电容器的极，但实际上，任一个或多个金属层可以被包括其他导电材料的导体层来代替，并达到类似的技术效果。因此，金属极板可以是被其他导电材料形成的导电极板代替，金属块可以是被其他导电材料形成的导体块代替。后文仅以金属层、金属极板和金属块为例作介绍，但不用于严格限定。
在该沿垂直方向Z观察电容器所形成的俯视图中，对于任意一个中间金属层，多个被标记为A的金属块和多个被标记为B的金属块可以以一定方式排列。例如，任一被标记为A的金属块可以与一个或多个被标记为B的金属块相邻。这里的相邻可以是距离最近或距离处于一定范围内，本实施例对此不做具体限定。参照图4所示的俯视图，多个金属块在金属层上沿长度方向X(假定为图4中的水平方向)和宽度方向Y(假定为图4中的竖直方向)，以直线形式排列。每个金属块包括四个相邻的金属块，分别是左相邻块、右相邻块、上相邻块和下相邻块。例如，每个被标记为A的金属块的四个相邻块均是被标记为B的金属块，反之，每个被标记为B的金属块的四个相邻块均是被标记为A的金属块，以使得多个被标记为A的金属块和多个被标记为B的金属块以ABAB形式间隔排列，即形成网状结构，使得电容器10的整体性能得到优化。例如，对于任一个被标记为A的金属块而言，其与相邻四个被标记为B的金属块之间形成四个侧壁电容器C。
在实际应用中，多个金属块的排列方式可以做灵活调整，而不再是如图4的间隔排列。以图5为例，在从左向右的方向，即长度方向X上，存在两个被标记为A或B的金属块相邻的情况，即不再是像图4那样以ABAB形式间隔排列，而是以AABBAA方式排列。此时的一个金属块的相邻块除了包括左相邻块、右相邻块、上相邻块和下相邻块，还可包括左上相邻块、右上相邻块、左下相邻块和右下相邻块，即一共八个相邻块。一个被标记为B的金属块与上相邻块、下相邻块、右相邻块、左上相邻块和左下相邻块形成五个侧壁电容器C。
在另一种替换的金属块排列方式中，如图6所示，任一金属块可以与周围的八个金属块形成侧壁电容器C。例如，一个被标记为B的金属块的八个相邻块，即左相邻块、右相邻块、上相邻块、下相邻块、左上相邻块、右上相邻块、左下相邻块和右下相邻块，均为被标记为A的金属块，从而形成八个侧壁电容器C。关于多个金属块的排布方式的其他可能的变形，本文不做详细介绍，本领域技术人员可以根据本实施例给出的启示进行自行调整，而不脱离本发明的保护范围。
进一步地，如图7所示，给出了两个极板与金属块在垂直方向上的投影关系的示意图。所述上极板、下极板和位于多个中间金属层中的所述多个金属块在垂直方向Z上的投影彼此相重叠，以使得所述投影占据俯视图的面积更小，不会拉开两个极板在水平面上投影的距离，以缩小电容器10的体积，为所述两个极板的连线布局提供更多灵活性。在图7中，上极板A和下极板B的面积大小不同，但可以理解，二者的大小和形状中的一个或两者均可以选择性相同或不同。当上极板A和下极板B的大小和形状 完全相同，二者在垂直方向上的投影可以完全吻合。
可以理解，对于图2的立体结构而言，多个中间金属层的多个金属块的分布方式可以相同或不同。如果多个中间金属层的多个金属块的分布方式相同，则如图7所示，在沿垂直方向Z观察电容器10形成的俯视图中，一个中间金属层中的金属块与上方相邻的中间金属层或下方相邻的中间金属层中对应金属块是重合的，且这两个金属块通过通孔相耦合，所述上方和下方是沿Z方向的。当存在多个中间金属层的时候，在沿一个金属块的垂直方向Z上，由多个金属层的多个金属块和对应多个通孔形成导体柱，多个导体柱用于形成侧壁电容器，该结构充分利用多个通孔提高电容器性能。需理解，以上实施例中的通孔沿垂直方向Z延伸，但实际上通孔的延伸方向可以不是严格按照Z方向，即便存在弯曲或倾斜的通孔也不影响技术方案的实施。如果多个中间金属层的多个金属块的分布方式不同，则在沿垂直方向Z观察电容器10形成的俯视图中，一个中间金属层中的金属块与上方相邻的中间金属层或下方相邻的中间金属层中对应金属块是不重合的，用于耦合这两个金属块的通孔将不再沿垂直方向Z延伸，而是存在弯曲或倾斜，以用于耦合所述两个金属块。
以上电容器10的结构可使用后道工序(Back End OF Line，BEOL)工艺来实现，当该器件的垂直深度大时，在相同水平面积下，整体电容值能超过传统电容器，以使得该电容器10能够使用在各类应用场景，尤其适用于信号滤波或电源地去耦合电容(DECAP)等场景。
可以理解，在图2的电容器10中，可以不具有中间金属层，即电容器10包括上极板和下极板，所述上极板和下极板之间可以包括一个或多个介质层，且上极板和下极板中的一个或全部极板可以具有至少一个槽隙，以达成减少极板的面积，从而降低天线效应，并降低该两个极板的应力，避免制作工艺导致的膨胀曲翘问题。中间金属层以及其中金属块仅是实施例可选的方案，即便不存在这些中间金属层和金属块，也可以在一定程度上达到技术效果。当然，中间金属层和金属块的存在可以进一步实现技术效果，例如避免制作工艺导致的膨胀曲翘等，此处不做赘述。可以理解，如果在两个极板上不存在所述至少一个槽隙，仅通过如图2中的中间金属层和金属块的设计也可以一定程度上达到技术效果。
在本发明实施例中，所述上极板或所述下极板之一可以选择性被耦合至半导体芯片01中的电源线或接地线。可替换地，所述上极板和所述下极板可以分别耦合至半导体芯片01中的电源线和接地线，以实现滤波功能。采用本技术方案，该电容器10被应用于电源线或接地线中至少一个，作为去耦电容(DECAP)使用，且该电容器10的制作过程可以用现有的电源线或接地线上的其他器件的制作过程保持大致一致，简化制作过程。在电源线或接地线上，存在一些现有器件，其制作过程和版图设计与图2中所示的电容器10的制作过程和版图设计很接近，因此将本电容器10应用于电源线或接地线，可以无需对所述现有器件的制作过程和版图设计进行较大幅度的修改即可制作出电容器10，在实现滤波功能的基础上，简化电容器10的制作过程和版图设计的难度。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述 各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。例如，装置实施例中的一些具体操作可以参考之前的方法实施例。

Claims (14)

  1. 一种电容器，其特征在于，包括：
    第一极板，被布置于第一导体层；
    第二极板，被布置于第二导体层；其中，
    所述第一导体层和所述第二导体层被至少一个介质层隔离，所述第一极板和所述第二极板中的至少一个极板上包括至少一个槽隙。
  2. 根据权利要求1所述电容器，其特征在于，还包括：多个导体块，被布置于至少一个第三导体层，所述至少一个第三导体层位于所述第一导体层和所述第二导体层之间，所述第一导体层、所述第二导体层和所述至少一个第三导体层被所述至少一个介质层隔离；其中，所述多个导体块包括至少一个第一导体块和至少一个第二导体块，所述至少一个第一导体块通过至少一个第一通孔耦合至所述第一极板，所述至少一个第二导体块通过至少一个第二通孔耦合至所述第二极板。
  3. 根据权利要求2所述电容器，其特征在于，任一第三导体层中的每个第一导体块与所述任一第三导体层中的一个或多个第二导体块相邻。
  4. 根据权利要求3所述电容器，其特征在于，所述每个第一导体块的全部多个相邻块均是第二导体块。
  5. 根据权利要求4所述电容器，其特征在于，所述全部多个相邻块是四个第二导体块。
  6. 根据权利要求5所述电容器，其特征在于，在所述任一第三导体层中，所述四个第二导体块是所述每个第一导体块的左相邻块、右相邻块、上相邻块和下相邻块。
  7. 根据权利要求2至6中任一项所述电容器，其特征在于，所述至少一个第三导体层是多个第三导体层；任一第三导体层中的任一第一导体块与另一第三导体层中的一个第一导体块通过一第一通孔相耦合，所述任一第三导体层中的任一第二导体块与所述另一第三导体层中的一个第二导体块通过一第二通孔相耦合，所述另一第三导体层与所述任一第三导体层在垂直方向上相邻。
  8. 根据权利要求2至7中任一项所述电容器，其特征在于，所述第一导体层、所述第二导体层和所述至少一个第三导体层中的至少一个导体层是金属层。
  9. 根据权利要求2至8中任一项所述电容器，其特征在于，所述第一极板、所述第二极板和所述多个导体块在垂直方向上的投影相重叠。
  10. 根据权利要求1至8中任一项所述电容器，其特征在于，所述第一极板和所述第二极板在垂直方向上的投影相重叠。
  11. 根据权利要求1至10中任一项所述电容器，其特征在于，所述至少一个介质层包括氧化物。
  12. 根据权利要求1至11中任一项所述电容器，其特征在于，所述电容器包括金属-氧化物-金属MOM电容器。
  13. 根据权利要求1至12中任一项所述电容器，其特征在于，所述第一极板或所述第二极板被耦合至电源线或接地线。
  14. 一种半导体芯片，其特征在于，包括如权利要求1至13中任一项所述电容器。
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