WO2020207009A1 - 基于深硅刻蚀模板量子点转移工艺的微米全色qled阵列器件及其制备方法 - Google Patents

基于深硅刻蚀模板量子点转移工艺的微米全色qled阵列器件及其制备方法 Download PDF

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WO2020207009A1
WO2020207009A1 PCT/CN2019/116991 CN2019116991W WO2020207009A1 WO 2020207009 A1 WO2020207009 A1 WO 2020207009A1 CN 2019116991 W CN2019116991 W CN 2019116991W WO 2020207009 A1 WO2020207009 A1 WO 2020207009A1
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micro
photoresist
layer
light
quantum dots
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PCT/CN2019/116991
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French (fr)
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刘斌
蒋迪
余俊驰
王轩
潘丹峰
谢自力
周玉刚
陈敦军
修向前
张�荣
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南京大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials

Definitions

  • the invention relates to a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process and a preparation method thereof, and belongs to the technical field of semiconductor lighting and display.
  • LED light-emitting diodes As a currently widely used lighting source, light-emitting diodes have the advantages of high efficiency, good impact resistance and seismic performance, high reliability, long life, and environmental protection compared to traditional lighting sources.
  • Group III nitride materials are direct band gap semiconductors whose band gap covers the infrared-visible light-ultraviolet bands, and have become the main materials used in current solid-state high-efficiency lighting technologies.
  • LED light source Compared with traditional incandescent lighting, LED light source has the advantages of using low-voltage power supply, less energy consumption, strong applicability, high stability, short response time, no pollution to the environment, multi-color light, etc., although the price is more expensive than existing lighting equipment , Is still considered a better lighting device.
  • White light LEDs used in lighting can be realized in the following two ways. The first is to combine blue LEDs with phosphors to form white light; the second is a variety of monochromatic light mixing methods, namely RGB-LED. The second method can achieve higher quantum efficiency lighting quality.
  • Micro-LED has become a hot spot of current research and application due to its advantages such as fast response speed, low working voltage, stable and reliable performance, high luminous efficiency, and wide operating temperature range. It is used in a wide range of fields such as flat display, television, military, communications, criminal, medicine, fire protection, aerospace, satellite positioning, instrumentation, and handheld computers. Micro-LED has higher brightness, better luminous efficiency and lower power consumption than existing OLED technology. The outstanding characteristics of Micro-LED will enable it to have a better display effect on TVs and other devices. At present, Micro-LED mainly adopts the micro-pillar structure, because the micro-pillar has certain advantages in many aspects such as light output and electroluminescence spectrum transfer.
  • micro-hole Micro-LED protects the quantum dots, reduces physical damage caused by the outside world, and the micro-hole structure increases the quantum well and quantum The contact area of the point can better realize the color conversion.
  • a method for preparing micron full-color QLED array devices based on the quantum dot transfer process of deep silicon etching template is proposed. The whole process adopts the micro-machining method to transfer the quantum dots to the Micro-LED to prepare the QLED. The cost is low and the The operability is strong, the yield is high, and the full-color LED display can be realized.
  • the purpose of the present invention is to prepare a micron full-color QLED array device by using a deep silicon etching template quantum dot transfer process.
  • a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process.
  • the substrate material is a standard blue/violet LED epitaxial wafer.
  • the QLED array device is etched to form a p-type GaN layer and a quantum well
  • the source layer, an array of square mesa structure as deep as the n-type GaN layer, each square mesa is isolated from each other, each square mesa forms a Micro-LED, and each square mesa is etched to form a p-type GaN layer/quantum Well active layer/n-type GaN layer with micro-holes to form a micro-hole array;
  • It also includes a p-type array electrode vapor-deposited on the p-type GaN layer of the micro-hole array, and an n-type electrode vapor-deposited on the n-type GaN layer;
  • Each 2*2 of the square mesa structure constitutes an RGB pixel unit.
  • each RGB pixel unit a rectangular isolation groove etched to the n-type GaN layer is provided between two adjacent square mesa, and the isolation groove is filled with light-absorbing material to isolate light;
  • the red/green/yellow/blue quantum dots are filled into the micron holes by using a deep silicon etching template.
  • the third is to isolate the light.
  • the isolation groove filling material is made of light-absorbing materials, which can absorb the light emitted by the quantum wells on the sidewalls of the square mesa, prevent the blue light emitted by the quantum wells from affecting the light emission of the quantum dots, and prevent the different emission of different micro-hole arrays. The colors of light influence each other.
  • the deep silicon etching template adopts deep silicon etching technology to etch through the silicon wafer to form hollows on the surface of the silicon wafer corresponding to the positions of the microholes filled with red/green/yellow/blue quantum dots
  • the square hole structure and the "cross" alignment mark are also provided at the corresponding position on the surface of the Micro-LED array device to align the deep silicon etching template with the Micro-LED array device, and then rotate Coating quantum dots to prepare QLED devices; among them, the "cross" mark can be set at the four corners or the diagonal or a certain corner of each array.
  • the red light quantum dots are group II-VI core-shell structure CdSe/ZnS quantum dots or perovskite CsPbBr 3 quantum dots.
  • the green light quantum dots are II-VI group core-shell structure CdSe/ZnS quantum dots or perovskite CsPbBr 3 quantum dots.
  • the yellow light quantum dots are group II-VI core-shell structure CdSe/ZnS quantum dots or perovskite CsPbBr 3 quantum dots.
  • the area of the micro-hole array is greater than or equal to 4 inches; the diameter of the micro-holes is 20-100 ⁇ m, the period is 100-200 ⁇ m, the spacing between Micro-LEDs is 80-100 ⁇ m, and the depth of the micro-holes is 200 nm-1.5 ⁇ m.
  • the isolation groove deep to the n-type GaN layer between adjacent micro-hole mesa formed by etching, the width is 10-20 ⁇ m, the length is equal to the side length of the square mesa, and the isolation groove is filled with light absorption Material Vantablack or silver, used to isolate different colors of light.
  • the invention also discloses a method for preparing the above-mentioned micron full-color QLED array device, the steps of which include:
  • the p-type GaN layer and quantum well layer are etched anisotropically with metal as a mask, and the metal square mesa array structure, the isolation trench structure in the adjacent micro-hole area and the " The "cross" alignment mark is transferred to the n-type GaN layer;
  • micro-hole structure First use PECVD technology to evaporate the dielectric layer on the GaN square mesa array structure, spin-coat photoresist on the surface of the dielectric layer, and pre-bake it; use UV lithography technology to use photolithography
  • the photoresist of the square mesa array structure is overlaid to form a micro-hole pattern; first, RIE technology is used to etch the dielectric layer and then ICP technology to etch the p-type GaN layer; finally a micro-hole array is obtained, where the depth of the micro-hole can be engraved Etched to the p-type GaN layer, quantum well layer or n-type GaN layer;
  • a deep silicon etching template quantum dot transfer process is used to fill the quantum dots in the micro-holes.
  • the side length of the square hole in the deep silicon etching template is 90-180 ⁇ m
  • the depth is such that the silicon wafer is cut through
  • the thickness of the silicon wafer is 200-500 ⁇ m.
  • the longest length of the "cross" alignment mark in the deep silicon etching template and the "cross” alignment mark in the micron full-color QLED array device is 40 ⁇ m, and the width at the widest part is 20 ⁇ m.
  • micro-LED array is spin-coated with quantum dots of the corresponding color through the hole-shaped structure on the deep silicon etching template, and the micro-LED array device after the spin-coated quantum dots is dried, and then the deep silicon etching is removed.
  • Eclipse template
  • the deep silicon etching template is placed above the Micro-LED, and the "cross" alignment mark on the silicon chip is aligned with the "cross” lithography mark on the Micro-LED array device under the microscope
  • the solvent is toluene, chloroform, and hexane.
  • the n-type electrode is Ti/Al/Ni/Au metal
  • the p-type electrode is Ni/Au metal
  • the thickness of the dielectric layer is 150-250 nm, and the material is SiO 2 .
  • the thickness of the metal mask layer is 30-100 nm, and Ni or Cr is selected.
  • the invention also discloses a deep silicon etching template for filling quantum dots, which is characterized in that the deep silicon etching template is a silicon wafer, and the surface of the silicon wafer is formed by deep silicon etching technology and is to be filled with red light. /Green/Yellow/Blue quantum dots corresponding to the hollow square hole structure and "cross" alignment mark, in the Micro-LED array device that needs to be filled with red/green/yellow/blue quantum dots Corresponding positions on the surface are also engraved with "cross" alignment marks to align the deep silicon etching template with the Micro-LED array device.
  • the "cross" mark is arranged at the four corners or diagonal corners or a certain corner of the deep silicon etching template.
  • the hollow hole structure is a square hole, a rectangular hole, a round hole, or an elliptical hole, and the size of the hole should completely expose the microhole to be filled with the quantum dot.
  • the invention also discloses a method for filling quantum dots with deep silicon etching technology, the steps of which include:
  • steps (3)-(4) fill the quantum dots filled with red light and/or green light and/or yellow light into the quantum dot filling holes on the top surface of the device as required, Complete filling.
  • the present invention designs and prepares a micron full-color QLED array device based on the deep silicon etching template quantum dot transfer process.
  • the red light quantum of the II-VI group core-shell structure CdSe/ZnS is transferred through the deep silicon etching template quantum dot transfer process.
  • Dots, green light quantum dots and yellow light quantum dots are filled into the corresponding micro-holes of each 2 ⁇ 2 RGB pixel dot.
  • Quantum dots of different colors are excited by blue LEDs to excite red, green, and yellow light to realize each RGB pixel Multi-color display of dots.
  • the microporous structure protects the quantum dots, reducing physical damage caused by the outside world, and the microporous structure increases the quantum well
  • the contact area with quantum dots can better realize color conversion.
  • a micro-hole deep silicon etching template is used for spin coating quantum dots.
  • the operation is simple, the spin coating quality is high, and the equipment is less effective.
  • the requirements are lower, and the existing commonly used micro-processing equipment can be used to complete the spin coating, without the need to purchase inkjet printing equipment, and the cost is lower.
  • the use of micro-processing technology to manufacture Micro-LED array devices has made a greater breakthrough in the research of Micro-LED.
  • the prepared QLED array devices have realized four-color display, which has promoted the development of semiconductor displays.
  • Figure 1 is a schematic diagram of the structure of an In x Ga 1-x N/GaN quantum well LED substrate grown by the MOCVD method.
  • Fig. 2 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (1) of the Micro-LED array and its preparation method of the present invention.
  • FIG. 3 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (2) of the Micro-LED array and its preparation method of the present invention.
  • Figure 4-5 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (3) of the Micro-LED array and its preparation method of the present invention.
  • Fig. 6 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (4) of the Micro-LED array and its preparation method of the present invention.
  • FIG. 7 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (5) of the Micro-LED array and its preparation method of the present invention.
  • FIG. 8 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (6) of the Micro-LED array and its preparation method of the present invention.
  • 9-11 are schematic diagrams of the structure of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in each operation in step (7) of the Micro-LED array and its preparation method of the present invention.
  • FIG. 12 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (8) of the Micro-LED array and its preparation method of the present invention.
  • FIG. 13 is a schematic structural diagram of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (9) of the Micro-LED array and its preparation method of the present invention.
  • FIGS. 14-15 are schematic diagrams of the structure of the micron full-color QLED array device based on the deep silicon etching template quantum dot transfer process obtained in each operation of the Micro-LED array and its preparation method step (10) of the present invention.
  • 16-17 are schematic diagrams of the structure of the micron panchromatic QLED array device based on the deep silicon etching template quantum dot transfer process obtained in each step of the Micro-LED array and its preparation method step (11) of the present invention.
  • FIG. 18-19 is a schematic diagram of the structure of a micron full-color QLED array device based on a deep silicon etching template quantum dot transfer process obtained in step (12) of the Micro-LED array and its preparation method of the present invention
  • FIG. 20 is a schematic diagram of the porous deep silicon etching template structure obtained in step (1) of the method for preparing the porous deep silicon etching template in the deep silicon etching template quantum dot transfer process of the present invention.
  • FIG. 21 is a schematic diagram of the surface structure of the hole-shaped silicon wafer mask with the square "cross" mark obtained in step (2) of the method for preparing the hole-shaped deep silicon etching template in the deep silicon etching template quantum dot transfer process of the present invention.
  • FIG. 22 is a schematic diagram of the alignment of the four-corner "cross" mark hole-shaped deep silicon etching template with the Micro-LED array device obtained in step (1) of the quantum dot transfer process of the deep silicon etching template of the present invention.
  • Figure 23 is a Micro-LED array device obtained by spin-coating red light quantum dots on a hole-shaped deep silicon etching template with a four-corner "cross" mark obtained in step (2) of the deep silicon etching template quantum dot transfer process of the present invention Surface schematic.
  • Figure 24-29 shows the quantum dot transfer process step (3) of the deep silicon etching template of the present invention, changing the position of the square hole in the deep silicon etching template with the four-corner "cross” mark, and repeating the quantum dot transfer process step (1)- (2) Schematic diagram of the device obtained by each step twice.
  • FIG. 30 is a schematic diagram of the surface structure of a hole-shaped silicon wafer mask with a diagonal "cross" mark obtained in step (2) of the method for preparing a hole-shaped deep silicon etching template in a quantum dot transfer process for deep silicon etching template of the present invention.
  • FIG. 31 is a schematic diagram of the alignment of the deep silicon etching template with the diagonal "cross" mark hole-shaped deep silicon etching template and the Micro-LED array device obtained in step (1) of the quantum dot transfer process of the deep silicon etching template of the present invention.
  • Fig. 32 is a Micro-LED array obtained by spin-coating red light quantum dots on a hole-shaped deep silicon etching template with diagonal "ten" marks obtained in step (2) of the deep silicon etching template quantum dot transfer process of the present invention Schematic diagram of the device surface.
  • FIG. 33 is a schematic cross-sectional view of a micron panchromatic QLED array device based on the deep silicon etching template quantum dot transfer process of the present invention.
  • FIG. 34 is a schematic diagram of the surface of a micron full-color QLED array device based on the deep silicon etching template quantum dot transfer process of the present invention.
  • Embodiment 1 Micron panchromatic QLED array device based on deep silicon etching template quantum dot transfer process
  • a standard blue LED epitaxial wafer with pn structure includes a sapphire substrate 1; a gallium nitride buffer layer 2 grown on a sapphire substrate; N-type gallium nitride layer 3 on the buffer layer; quantum well active layer 4 grown on the n-type gallium nitride layer; p-type gallium nitride layer 5 grown on the quantum well active layer.
  • the specific preparation method of the Micro-LED array device is as follows:
  • SiO 2 dielectric layer 6 is evaporated on the In x Ga 1-x N/GaN quantum well blue LED epitaxial wafer.
  • the method of PECVD growth of SiO 2 is to pass a mixture of 5% SiH 4 /N 2 and N 2 O into the reaction chamber with flow rates of 100 sccm and 450 sccm, respectively, under the conditions of a pressure of 300 mTorr, a power of 10 W, and a temperature of 350 °C.
  • SiH x +O ⁇ SiO 2 (+H 2 ) reaction SiO 2 is deposited on the surface of the epitaxial wafer for 7 minutes and 10 seconds;
  • RIE reactive ion etching
  • the photoresist layer 7 and the metal nickel film 8 on the photoresist layer were peeled off with acetone solution ultrasonic for 10 minutes to obtain a large-area ordered square mesa array pattern, a rectangular isolation groove pattern between adjacent micro holes and adjacent
  • the "cross" alignment mark between the mesa, the distance between adjacent mesa is 80 ⁇ m, the width of the isolation groove is 10 ⁇ m, the longest length of the "cross” alignment mark is 40 ⁇ m, and the widest width is 20 ⁇ m, as shown in the figure 5 shown;
  • a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power 150W, pressure 4Pa, etching time 3 minutes, etch the dielectric layer SiO 2 longitudinally with nickel as a mask, the metal square mesa structure, the rectangular isolation groove structure between adjacent micro-holes and the adjacent square mesa
  • the "cross" alignment mark of is transferred to the dielectric layer 6;
  • the "cross" alignment mark, the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 9 minutes and 30 seconds, and the etching depth is about 950nm, forming The distance between adjacent Micro-LEDs is 80 ⁇ m;
  • wet etching is used to remove the metal mask layer 8 and the dielectric layer 6.
  • the specific method is to soak the sample in an aqueous nitric acid solution and a buffered oxide etching solution (BOE) for the respective time. 1 minute and 40 seconds, the etching damage of gallium nitride and the sidewall of the quantum well can also be reduced during the soaking process;
  • BOE buffered oxide etching solution
  • PECVD plasma enhanced chemical vapor deposition
  • a layer of photoresist 10 on the surface of the sample bake it for 10 minutes before 90°C, and then use ultraviolet lithography technology to over-etch the photoresist with a photolithography plate to form a micro-hole pattern with a diameter of 20 ⁇ m and a period of 100 ⁇ m ,Develop, post-bake at 110°C for 1 minute.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa, the etching time is 3 minutes, and the dielectric layer SiO 2 6 is etched longitudinally with the photoresist 10 as a mask.
  • a mixed gas of Cl 2 and BCl 3 is introduced into the reaction chamber, and the photoresist 10 and the dielectric layer 9 are used as masks for anisotropic etching
  • the p-type gallium nitride layer 5, the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 2 minutes, the etching depth is about 200nm, and the diameter is 20 ⁇ m.
  • the sample is soaked in a buffered oxide etching solution (BOE) for 1 minute to remove the SiO 2 dielectric layer 9 and the residual photoresist layer 10 on the dielectric layer. And reduce the etching damage of gallium nitride and quantum well surface and sidewall;
  • BOE buffered oxide etching solution
  • n-type electrodes (10) Preparation of n-type electrodes. Spin-coat a layer of photoresist 12 on the sample surface, bake it for 10 minutes before 90°C, use ultraviolet lithography technology to engrave the n-type electrode pattern on the photoresist onto the photoresist, develop, and post-bake at 110°C 1 minute. Then, as shown in Figure 14, using reactive ion etching (RIE) technology, a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa
  • the etching time is 3 minutes
  • the SiO 2 dielectric layer film 11 is etched with the photoresist 12 as a mask
  • the n-type electrode pattern is transferred to the n-type gallium nitride 3.
  • PVD physical vapor deposition
  • the photoresist 12 and the metal film 13 on the photoresist layer are peeled off using acetone ultrasound, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C., and time 30 seconds to realize the ohmic contact of titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal and n-type gallium nitride.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power is 150 W, pressure is 4 Pa, and etching time For 3 minutes, the SiO 2 dielectric layer film 11 is etched using the photoresist 14 as a mask, and the p-type electrode pattern is transferred to the p-type gallium nitride 5.
  • a physical vapor deposition (PVD) process is used to sequentially vapor-deposit two metals, nickel (Ni) and gold (Au), with thicknesses of 150 nm/200 nm on the surface of the sample as the p-type electrode 15.
  • the photoresist 14 and the metal film 15 on the photoresist layer are peeled off, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C. and time 30 seconds to realize the ohmic contact between nickel (Ni)/gold (Au) metal and p-type gallium nitride, as shown in FIG. 17.
  • the filling sequence of the red light/green light/yellow light quantum dots can be replaced at will, which will not have any impact on the quality and performance of the device.
  • the "cross" alignment mark can also be arranged on the diagonal or any corner of the device and the silicon chip.
  • Embodiment 2 Micron panchromatic QLED array device based on deep silicon etching template quantum dot transfer process
  • a standard blue LED epitaxial wafer with pn structure includes a sapphire substrate 1; a gallium nitride buffer layer 2 grown on a sapphire substrate; N-type gallium nitride layer 3 on the buffer layer; quantum well active layer 4 grown on the n-type gallium nitride layer; p-type gallium nitride layer 5 grown on the quantum well active layer.
  • the specific preparation method of the Micro-LED array device is as follows:
  • SiO 2 dielectric layer 6 is evaporated on the In x Ga 1-x N/GaN quantum well blue LED epitaxial wafer.
  • the method of PECVD growth of SiO 2 is to pass a mixture of 5% SiH 4 /N 2 and N 2 O into the reaction chamber with flow rates of 100 sccm and 450 sccm, respectively, under the conditions of a pressure of 300 mTorr, a power of 10 W, and a temperature of 350 °C.
  • SiH x +O ⁇ SiO 2 (+H 2 ) reaction deposit SiO 2 on the surface of the epitaxial wafer for 9 minutes and 30 seconds;
  • RIE reactive ion etching
  • the photoresist layer 7 and the metal nickel film 8 on the photoresist layer were peeled off with acetone solution ultrasonic for 10 minutes to obtain a large-area ordered square mesa array pattern, a rectangular isolation groove pattern between adjacent micro holes and adjacent
  • the "cross" alignment mark between the mesa, the distance between adjacent mesa is 90 ⁇ m, the width of the isolation groove is 16 ⁇ m, the longest length of the "cross” alignment mark is 40 ⁇ m, and the widest width is 20 ⁇ m, as shown in the figure 5 shown;
  • a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power 150W, pressure 4Pa, etching time 4 minutes, using metallic nickel as a mask to etch the dielectric layer SiO 2 vertically, separating the metal square mesa structure, the rectangular isolation groove structure between adjacent micro-holes and the adjacent square mesa
  • the "cross" alignment mark of is transferred to the dielectric layer 6;
  • the "cross" alignment mark, the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 9 minutes and 30 seconds, and the etching depth is about 950nm, forming The distance between adjacent Micro-LEDs is 90 ⁇ m;
  • wet etching is used to remove the metal mask layer 8 and the dielectric layer 6.
  • the specific method is to soak the sample in an aqueous nitric acid solution and a buffered oxide etching solution (BOE) for the respective time. 1 minute and 40 seconds, the etching damage of gallium nitride and the sidewall of the quantum well can also be reduced during the soaking process;
  • BOE buffered oxide etching solution
  • PECVD plasma enhanced chemical vapor deposition
  • a layer of photoresist 10 on the surface of the sample bake it for 10 minutes before 90°C, and then use ultraviolet lithography technology to overetch the photoresist with a photolithography plate to form a micro-hole pattern with a diameter of 50 ⁇ m and a period of 150 ⁇ m ,Develop, post-bake at 110°C for 1 minute.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa, the etching time is 4 minutes, and the dielectric layer SiO 2 6 is etched longitudinally with the photoresist 10 as a mask.
  • a mixed gas of Cl 2 and BCl 3 is introduced into the reaction chamber, and the photoresist 10 and the dielectric layer 9 are used as masks for anisotropic etching
  • the p-type gallium nitride layer 5, the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 9 minutes, the etching depth is about 900nm, and the diameter is 50 ⁇ m, A micro-hole array with a period of 150 ⁇ m and a depth of 900 nm;
  • the sample is soaked in a buffered oxide etching solution (BOE) for 1 minute to remove the SiO 2 dielectric layer 9 and the residual photoresist layer 10 on the dielectric layer. And reduce the etching damage of gallium nitride and quantum well surface and sidewall;
  • BOE buffered oxide etching solution
  • n-type electrodes (10) Preparation of n-type electrodes. Spin-coat a layer of photoresist 12 on the sample surface, bake it for 10 minutes before 90°C, use ultraviolet lithography technology to engrave the n-type electrode pattern on the photoresist onto the photoresist, develop, and post-bake at 110°C 1 minute. Then, as shown in Figure 14, using reactive ion etching (RIE) technology, a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa
  • the etching time is 4 minutes
  • the SiO 2 dielectric layer film 11 is etched with the photoresist 12 as a mask
  • the n-type electrode pattern is transferred to the n-type gallium nitride 3.
  • PVD physical vapor deposition
  • the photoresist 12 and the metal film 13 on the photoresist layer are peeled off using acetone ultrasound, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C., and time 30 seconds to realize the ohmic contact of titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal and n-type gallium nitride.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power is 150 W, pressure is 4 Pa, and etching time For 4 minutes, the SiO 2 dielectric layer film 9 is etched using the photoresist 14 as a mask, and the p-type electrode pattern is transferred to the p-type gallium nitride 3.
  • a physical vapor deposition (PVD) process was used to sequentially vapor-deposit two metals, nickel (Ni) and gold (Au), with a thickness of 150 nm/300 nm on the surface of the sample as the p-type electrode 15.
  • the photoresist 14 and the metal film 15 on the photoresist layer are peeled off, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C. and time 30 seconds to realize the ohmic contact between nickel (Ni)/gold (Au) metal and p-type gallium nitride, as shown in FIG. 17.
  • the filling sequence of the red light/green light/yellow light quantum dots can be replaced at will, which will not have any impact on the quality and performance of the device.
  • the "cross" alignment mark can also be arranged on the diagonal or any corner of the device and the silicon chip.
  • Embodiment 3 Micron panchromatic QLED array device based on deep silicon etching template quantum dot transfer process
  • a standard blue LED epitaxial wafer with pn structure includes a sapphire substrate 1; a gallium nitride buffer layer 2 grown on a sapphire substrate; N-type gallium nitride layer 3 on the buffer layer; quantum well active layer 4 grown on the n-type gallium nitride layer; p-type gallium nitride layer 5 grown on the quantum well active layer.
  • the specific preparation method of the Micro-LED array device is as follows:
  • SiO 2 dielectric layer 6 is evaporated on the In x Ga 1-x N/GaN quantum well blue LED epitaxial wafer.
  • the method of PECVD growth of SiO 2 is to pass a mixture of 5% SiH 4 /N 2 and N 2 O into the reaction chamber with flow rates of 100 sccm and 450 sccm, respectively, under the conditions of a pressure of 300 mTorr, a power of 10 W, and a temperature of 350 °C.
  • SiH x +O ⁇ SiO 2 (+H 2 ) reaction SiO 2 is deposited on the surface of the epitaxial wafer for 11 minutes and 50 seconds;
  • RIE reactive ion etching
  • the photoresist layer 7 and the metal nickel film 8 on the photoresist layer were peeled off with acetone solution ultrasonic for 10 minutes to obtain a large-area ordered square mesa array pattern, a rectangular isolation groove pattern between adjacent micro holes and adjacent
  • the "cross" alignment mark between the mesa, the distance between adjacent mesa is 100 ⁇ m, the width of the isolation groove is 20 ⁇ m, the longest length of the "cross” alignment mark is 40 ⁇ m, and the widest width is 20 ⁇ m, as shown in the figure 5 shown;
  • a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power 150W, pressure 4Pa, etching time 5 minutes, using metallic nickel as a mask to etch the dielectric layer SiO 2 longitudinally, separating the metal square mesa structure, the rectangular isolation groove structure between adjacent micro-holes and the adjacent square mesa
  • the "cross" alignment mark of is transferred to the dielectric layer 6;
  • the "cross" alignment mark, the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 9 minutes and 30 seconds, and the etching depth is about 950nm, forming The distance between adjacent Micro-LEDs is 100 ⁇ m;
  • wet etching is used to remove the metal mask layer 8 and the dielectric layer 6.
  • the specific method is to soak the sample in an aqueous nitric acid solution and a buffered oxide etching solution (BOE) for the respective time. 1 minute and 40 seconds, the etching damage of gallium nitride and the sidewall of the quantum well can also be reduced during the soaking process;
  • BOE buffered oxide etching solution
  • the plasma enhanced chemical vapor deposition (PECVD) technology is used to vaporize a 250nm thick SiO 2 dielectric layer 9 as a mask, and 5% SiH 4 /N 2 is passed into the reaction chamber.
  • SiH x +O ⁇ SiO 2 (+H 2 ) reaction it is deposited on the sample surface A layer of SiO 2 .
  • a layer of photoresist 10 on the surface of the sample bake it for 10 minutes before 90°C, and then use ultraviolet lithography technology to engrave the photoresist with a photolithography plate to form micro-hole patterns with a diameter of 100 ⁇ m and a period of 200 ⁇ m ,Develop, post-bake at 110°C for 1 minute.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa, the etching time is 5 minutes, and the dielectric layer SiO 2 6 is etched longitudinally with the photoresist 10 as a mask.
  • a mixed gas of Cl 2 and BCl 3 is introduced into the reaction chamber, and the photoresist 10 and the dielectric layer 9 are used as masks for anisotropic etching
  • the p-type gallium nitride layer 5, the etching conditions are Cl 2 : 24 sccm, BCl 3 : 3 sccm, ICP power is 600 W, RF power is 10 W, pressure is 6.5 mTorr, time is 10 minutes and 20 seconds, and the etching depth is about 1.2 ⁇ m.
  • the sample is soaked in a buffered oxide etching solution (BOE) for 1 minute to remove the SiO 2 dielectric layer 9 and the residual photoresist layer 10 on the dielectric layer. And reduce the etching damage of gallium nitride and quantum well surface and sidewall;
  • BOE buffered oxide etching solution
  • n-type electrodes (10) Preparation of n-type electrodes. Spin-coat a layer of photoresist 12 on the sample surface, bake it for 10 minutes before 90°C, use ultraviolet lithography to engrave the n-type electrode pattern on the photoresist onto the photoresist, develop, and post-bake at 110°C 1 minute. Then, as shown in Figure 14, using reactive ion etching (RIE) technology, a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, and the power is 150W ,
  • the pressure is 4 Pa
  • the etching time is 5 minutes
  • the SiO 2 dielectric layer film 11 is etched with the photoresist 12 as a mask
  • the n-type electrode pattern is transferred to the n-type gallium nitride 3.
  • PVD physical vapor deposition
  • the photoresist 12 and the metal film 13 on the photoresist layer are peeled off using acetone ultrasound, and the sample is washed and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C., and time 30 seconds to realize the ohmic contact of titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal and n-type gallium nitride.
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, power is 150 W, pressure is 4 Pa, and etching time
  • the SiO 2 dielectric layer film 9 is etched using the photoresist 14 as a mask, and the p-type electrode pattern is transferred to the p-type gallium nitride 3.
  • a physical vapor deposition (PVD) process was used to sequentially vapor-deposit two metals, nickel (Ni) and gold (Au), with thicknesses of 200 nm/300 nm on the surface of the sample as the p-type electrode 15.
  • the photoresist 14 and the metal film 15 on the photoresist layer are peeled off, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C. and time 30 seconds to realize the ohmic contact between nickel (Ni)/gold (Au) metal and p-type gallium nitride, as shown in FIG. 17.
  • the filling sequence of the red light/green light/yellow light quantum dots can be replaced at will, which will not have any impact on the quality and performance of the device.
  • the "cross" alignment mark can also be arranged on the four corners or any one of the corners of the device and the silicon chip.
  • Embodiment 4 Micron panchromatic QLED array device based on deep silicon etching template quantum dot transfer process
  • the epitaxial wafer structure selected for the substrate material in this embodiment is a standard violet LED epitaxial wafer with pn structure, including a sapphire substrate 1; a gallium nitride buffer layer 2 grown on a sapphire substrate; an n layer grown on the buffer layer Type gallium nitride layer 3; quantum well active layer 4 grown on the n-type gallium nitride layer; p-type gallium nitride layer 5 grown on the quantum well active layer.
  • the specific preparation method of the Micro-LED array device is as follows:
  • PECVD plasma enhanced chemical vapor deposition
  • the deposition layer of 250nm thick SiO 2 dielectric layer 6 on the In x Ga 1-x N / GaN quantum wells blue LED epitaxial wafer PECVD growth and SiO 2
  • the flow rate is 100sccm and 450sccm, respectively, under the conditions of pressure 300mTorr, power 10W, and temperature 350°C, through SiH x +O ⁇ SiO 2 (+H 2 ) reacts to deposit SiO 2 on the surface of the epitaxial wafer for 11 minutes and 50 seconds;
  • RIE reactive ion etching
  • the photoresist layer 7 and the metal nickel film 8 on the photoresist layer were peeled off with acetone solution ultrasonic for 10 minutes to obtain a large-area ordered square mesa array pattern, a rectangular isolation groove pattern between adjacent micro holes and adjacent
  • the distance between adjacent mesa is 100 ⁇ m
  • the width of the isolation groove is 20 ⁇ m
  • the longest length of the "cross” alignment mark is 40 ⁇ m
  • the widest width is 20 ⁇ m;
  • RIE reactive ion etching
  • etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 9 minutes and 30 seconds, and the etching depth is about 950nm, forming adjacent Micro-LED The distance between them is 100 ⁇ m;
  • PECVD plasma enhanced chemical vapor deposition
  • a layer of photoresist 10 on the surface of the sample bake it for 10 minutes before 90°C, and then use ultraviolet lithography technology to engrave the photoresist with a photolithography plate to form micro-hole patterns with a diameter of 100 ⁇ m and a period of 200 ⁇ m ,Develop, post-bake at 110°C for 1 minute.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, the power is 150 W, the pressure is 4 Pa, and the etching For 5 minutes, the dielectric layer SiO 2 6 is etched longitudinally using the photoresist 10 as a mask.
  • ICP inductively coupled plasma etching
  • a mixed gas of Cl 2 and BCl 3 is passed into the reaction chamber, and the p-type gallium nitride layer is anisotropically etched using the photoresist 10 and the dielectric layer 9 as masks 5.
  • the etching conditions are Cl 2 : 24sccm, BCl 3 : 3sccm, ICP power is 600W, RF power is 10W, pressure is 6.5mTorr, time is 15 minutes, and the etching depth is about 1.5 ⁇ m, to obtain a diameter, 100 ⁇ m, period 200 ⁇ m, depth 1.5 ⁇ m micro-hole array;
  • n-type electrodes (10) Preparation of n-type electrodes. Spin-coat a layer of photoresist 12 on the sample surface, bake it for 10 minutes before 90°C, use ultraviolet lithography technology to engrave the n-type electrode pattern on the photoresist onto the photoresist, develop, and post-bake at 110°C 1 minute. Then, using reactive ion etching (RIE) technology, a mixed gas of CF 4 and O 2 is introduced into the reaction chamber.
  • RIE reactive ion etching
  • the gas flow rate is: CF 4 : 30 sccm, O 2 : 10 sccm, the power is 150 W, the pressure is 4 Pa, and the etching For 5 minutes, the SiO 2 dielectric layer film 11 is etched using the photoresist 12 as a mask, and the n-type electrode pattern is transferred to the n-type gallium nitride 3.
  • PVD physical vapor deposition
  • the gas flow is: CF 4 : 30sccm, O 2 : 10sccm, power is 150W, pressure is 4Pa, and etching time
  • the SiO 2 dielectric layer film 9 is etched using the photoresist 14 as a mask, and the p-type electrode pattern is transferred to the p-type gallium nitride 3.
  • a physical vapor deposition (PVD) process was used to sequentially vapor-deposit two metals, nickel (Ni) and gold (Au), with a thickness of 250 nm/300 nm on the surface of the sample as the p-type electrode 15.
  • the photoresist 14 and the metal film 15 on the photoresist layer are peeled off, and the sample is cleaned and dried. Finally, thermal annealing is performed under the conditions of N 2 , temperature 750° C., and time 30 seconds to realize the ohmic contact between nickel (Ni)/gold (Au) metal and p-type gallium nitride.
  • the positions of the square micro-holes in the deep silicon etching template are changed to prepare three new deep silicon etching templates, and steps (1) and (2) are repeated three times .
  • the red light quantum dot solution, the green light quantum dot solution and the yellow light quantum dot solution are respectively filled into the micro-holes of each RGB pixel unit to realize the four-color display of each RGB pixel.
  • the cross-sectional schematic diagram of the obtained device is shown in Fig. 33, and the surface schematic diagram is shown in Fig. 34.
  • the filling sequence of the red light/green light/yellow light quantum dots can be replaced at will, which will not have any impact on the quality and performance of the device.
  • the "cross" alignment mark can also be arranged on the four corners or any one of the corners of the device and the silicon chip.
  • the hollow holes of the deep silicon etching template are all square holes. In fact, it is feasible to make rectangular holes, round holes, or oval holes from the hollow holes. You only need to pay attention to the size of the holes. It suffices to completely expose the micropores to be filled with quantum dots, and not expose the micropores to be filled with quantum dots of other colors.

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Abstract

一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件。在蓝光LED外延片上设有贯穿p型GaN层（5）、量子阱有源层（4），深至n型GaN层（3）的阵列式正方形台面结构，其上刻蚀形成微米孔。台面结构每2*2个构成一个RGB像素单元，四个微米孔中，分别填充有红光、绿光、黄光量子点，一个自身发蓝光/填充蓝光量子点。在硅片上利用深硅刻蚀技术刻穿硅片上的微米孔，将硅片上的微米孔与Micro-LED上的量子点填充区域对齐，将量子点通过硅片上的微米孔旋涂进Micro-LED中。并公开了其制备方法。三块不同的深硅刻蚀掩膜板可完成对Micro-LED中绿光、红光、黄光量子点的旋涂，实现RGB像素单元的全色显示，形成QLED阵列器件。

Description

基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件及其制备方法 技术领域
本发明涉及一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件及其制备方法，属于半导体照明与显示技术领域。
背景技术
发光二极管作为目前广泛使用的照明光源，相对于传统照明光源来说具有效率高，抗冲击和抗震性能好，可靠性高，寿命长，绿色环保等优点。III族氮化物材料为直接带隙半导体，其带隙覆盖了红外-可见光-紫外波段，成为了当前固态高效照明技术使用的主要材料。相对于传统白炽灯照明，LED光源具有使用低压电源、耗能少、适用性强、稳定性高、响应时间短、对环境无污染、多色发光等的优点，虽然价格较现有照明器材昂贵，仍被认为是较好的照明器件。照明中使用的白光LED可通过以下两种方式实现，第一种是将蓝光LED与荧光粉配合形成白光；第二种是多种单色光混合方法，即RGB-LED。其中第二种方法可以获得更高量子效率的照明品质。
近年来，关于LED的研究发展迅速，其中Micro-LED因具有响应速度快、工作电压较低、性能稳定可靠、发光效率高、工作温度范围宽等优点，成为了当前研究和应用的热点。在平面显示、电视、军事、通信、刑事、医学、消防、航空航天、卫星定位、仪器仪表、掌中电脑等广阔的领域得到应用。Micro-LED比现有的OLED技术亮度更高、发光效率更好、功耗更低。Micro-LED出色的特性将使得它可以在电视等设备上有更佳的显示效果。目前，Micro-LED主要采用的是微米柱结构，因为微米柱在光输出、电致发光谱的转移等许多方面都具有一定的优势。但普通的Micro-LED在实现多色显示方面仍具有很大的困难，如工艺复杂，难以实现多色量子点的填充与转移。因此，我们采用微米孔新型Micro-LED，相比于微米柱结构，微米孔结构起到对量子点的保护作用，减少了外界带来的物理损伤，而且微米孔结构增大了量子阱与量子点的接触面积，更好地实现色转换。并提出了一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的制备方法，全程采用微加工的方法，将量子点转移到Micro-LED上，制备QLED，成本低，可操作性强，成品率高，可实现LED的 全色显示。
发明内容
本发明的目的在于利用深硅刻蚀模板量子点转移工艺制备一种微米全色QLED阵列器件。
本发明的目的通过以下技术方案实现：
一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件，其衬底材料为标准蓝光/紫光LED外延片，所述QLED阵列器件刻蚀形成贯穿p型GaN层、量子阱有源层，深至n型GaN层的阵列式正方形台面结构，各正方形台面相互隔离，每个正方形台面均构成一个Micro-LED，在每个正方形台面上刻蚀形成深至p型GaN层/量子阱有源层/n型GaN层的微米孔，形成微米孔阵列；
还包括一p型阵列电极，蒸镀在微米孔阵列的p型GaN层上，一n型电极，蒸镀在n型GaN层上；
所述正方形台面结构每2*2个构成一个RGB像素单元，每个RGB像素单元的四个微米孔里面，一个填充有红光量子点，一个填充有绿光量子点，一个填充黄光量子点，一个自身发出蓝光/在紫光LED外延片微米孔填充蓝光量子点；
在每个RGB像素单元内，相邻的两个正方形台面之间设有刻蚀到n型GaN层的长方形隔离槽，隔离槽中填充吸光材料，用来隔离光；
所述红光/绿光/黄光/蓝光量子点采用深硅刻蚀模板填充到微米孔中。隔离槽的作用有三个，一是起到隔离相邻正方形台面的作用，二是起到消除刻蚀正方形台面带来的侧壁损伤，减小微米孔LED的漏电流，提高发光性能的作用，三是起到隔离光的作用，隔离槽填充材料选用吸光材料，能够将正方形台面侧壁量子阱发出的光吸收，防止量子阱发出的蓝光影响量子点发光，也防止不同微米孔阵列发出的不同颜色的光相互影响。
优选的，所述深硅刻蚀模板是采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光/绿光/黄光/蓝光量子点的微孔位置对应的镂空正方形孔结构和“十”字对准标记，在Micro-LED阵列器件的表面对应位置也设有“十”字对准标记，以便将深硅刻蚀模板与Micro-LED阵列器件对齐，然后旋涂量子点，制备QLED器件；其中“十”字标记可设置在每个阵列的四角或对角或某一个角的位置。
优选的，所述红光量子点为II-VI族核壳结构CdSe/ZnS量子点或钙钛矿CsPbBr 3量子点。
优选的，所述绿光量子点为II-VI族核壳结构CdSe/ZnS量子点或钙钛矿CsPbBr 3量子点。
优选的，所述黄光量子点为II-VI族核壳结构CdSe/ZnS量子点或钙钛矿CsPbBr 3量子点。
优选的，微米孔阵列的面积大于等于4英寸；微米孔直径为20-100μm，周期为100-200μm，Micro-LED之间的间距为80-100μm，微米孔深度为200nm-1.5μm。
优选的，微米全色QLED阵列器件中刻蚀形成的相邻微米孔台面之间有深至n型GaN层的隔离槽，宽度为10-20μm，长度等于正方形台面边长，隔离槽内填充吸光材料Vantablack或银，用来隔离不同颜色的光。
本发明还公开了上述的微米全色QLED阵列器件的制备方法，其步骤包括：
1)利用PECVD技术在蓝光LED外延片上蒸镀一层介质层；
2)在介质层表面旋涂一层光刻胶层，并对其进行前烘，利用紫外光刻技术将光刻板上有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的隔离槽图形和相邻正方形台面之间的“十”字对准标记图形转移到光刻胶层上，然后显影、后烘；
3)采用RIE技术，通入O 2去除经显影去除了大部分光刻胶的区域的少量光刻胶残余层，然后利用PVD工艺蒸镀一层金属掩膜层，再进行剥离，去除光刻胶层及光刻胶层上的金属薄膜层，得到大面积有序金属正方形台面阵列图形、隔离槽图形和相邻正方形台面之间的“十”字对准标记图形；
4)采用RIE技术，以金属为掩膜纵向刻蚀介质层，将金属正方形台面阵列结构、隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至介质层；
5)采用ICP技术，以金属为掩膜各向异性刻蚀p型GaN层和量子阱层，将金属正方形台面阵列结构、相邻微米孔区域的隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至n型GaN层；
6)采用湿法腐蚀法，去除正方形台面阵列结构、相邻微米孔区域的隔离槽结构和相邻正方形台面之间的“十”字对准标记图形上的金属掩膜层和介质层，形成相互隔离的GaN正方形台面阵列结构，并修复GaN及量子阱侧壁的刻蚀损伤；
7)制备微米孔结构，先采用PECVD技术在GaN正方形台面阵列结构上蒸镀介质层，在介质层表面旋涂光刻胶，并对其进行前烘；利用紫外光刻技术使用光刻版在正方形台面阵列结构的光刻胶上套刻形成微米孔图形；先采用RIE技术，刻蚀介质层再利用ICP技术，刻蚀p型GaN层；最终得到微米孔阵列，其中微米孔的深度可刻蚀到p型GaN层、量子阱层或者n型GaN层；
8)利用湿法腐蚀，去除正方形台面阵列结构上的介质层及介质层上残留的光刻胶，并修复GaN及量子阱表面和侧壁的刻蚀损伤；
9)再次在蓝光LED外延片上蒸镀一层介质层；
10)制备N型电极，在介质层表面旋涂光刻胶，利用紫外光刻技术将光刻板上的n型电极图形套刻到光刻胶上；采用RIE技术，以光刻胶为掩膜刻蚀介质层将n型电极图形转移至n型GaN层；采用PVD工艺蒸镀一层金属作为n型电极；然后剥离去掉光刻胶以及光刻胶层上的金属薄膜，洗净并烘干样品；最后利用热退火实现金属与n型GaN的欧姆接触；
11)制备P型电极，重新旋涂一层光刻胶，利用紫外光刻技术使用光刻版在光刻胶上套刻形成p型电极图形；采用RIE技术，以光刻胶为掩膜刻蚀介质层薄膜，将p型电极图形转移至p型GaN层；然后采用PVD工艺蒸镀一层金属作为p型电极；利用湿法腐蚀去掉光刻胶及光刻胶层上的金属薄膜层，洗净并烘干样品；最后利用热退火实现金属与p型GaN的欧姆接触；
12)填充隔离槽中的吸光材料，重新旋涂一层光刻胶，利用紫外光刻技术使用光刻板在光刻胶上套刻形成隔离槽图形；向样品表面旋涂一层吸光材料，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀去掉光刻胶及其上面的吸光材料，洗净并烘干样品；
13)采用深硅刻蚀模板量子点转移工艺在微米孔中填充量子点。
2、深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法：
1)截取等于或稍大于正方形台面阵列的硅片，在硅片表面旋涂AZ4620正性光刻胶，对其进行前烘，利用紫外光刻技术将光刻版表面图形转移到硅片表面，然后显影、后烘；
2)利用光刻胶作为掩膜，采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光/绿光/黄光/蓝光量子点的微米孔位置对应的镂空正方形孔结构和“十”字对准标记，制成红光/绿光/黄光/蓝光深硅刻蚀模板。
优选的，所述深硅刻蚀模板中正方形孔的边长为90-180μm，深度为将硅片刻穿，硅片厚度为200-500μm。
优选的，深硅刻蚀模板中“十”字对准标记与微米全色QLED阵列器件中的“十”字对准标记最长处长度为40μm，最宽处宽度为20μm。
3、深硅刻蚀模板量子点转移工艺：
1)将红光/绿光/黄光中任一深硅刻蚀模板放置在Micro-LED上，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻标记在显微镜下对准；
2)通过该深硅刻蚀模板上的孔形结构向Micro-LED阵列旋涂对应颜色的量子点，并将旋涂完量子点的Micro-LED阵列器件烘干，然后取下该深硅刻蚀模板；
3)采用另外两种颜色的深硅刻蚀模板，重复步骤1)-2)两次，可以将另外两种颜色的量子点填充至每一个RGB像素单元的微米孔内，制备形成QLED阵列器件。
通过深硅刻蚀模板量子点转移工艺填充量子点的过程具体为：
A、将红光量子点、绿光量子点和黄光量子点分别溶于溶剂中。
B、深硅刻蚀模板放置在Micro-LED上方，并将硅片上的“十”字对准标记与Micro-LED阵列器件上的“十”字光刻标记在显微镜下对准
C、移动显微镜载物台，将量子点旋涂到深硅刻蚀模板上，量子点通过硅片上的微米孔进入Micro-LED阵列中的微米孔中；
D、将喷涂完量子点溶液的Micro-LED阵列器件置于烘干台上烘干。
E、取下深硅刻蚀模板，制备成QLED，实现QLED器件的多色显示。
优选的，所述溶剂为甲苯、氯仿、己烷。
优选的，所述n型电极为Ti/Al/Ni/Au金属，p型电极为Ni/Au金属。
优选的，所述介质层厚度为150-250nm，材质为SiO 2。
优选的，所述金属掩膜层的厚度为30-100nm，选用Ni或Cr。
本发明还公开了一种用于填充量子点的深硅刻蚀模板，其特征在于：所述深硅刻蚀模板为硅片，在硅片表面采用深硅刻蚀技术形成与待填充红光/绿光/黄光/蓝光量子点的微孔位置对应的镂空正方形孔结构和“十”字对准标记，在需填充红光/绿光/黄光/蓝光量子点的Micro-LED阵列器件的表面对应位置也刻上“十”字对准标记，以便将深硅刻蚀模板与Micro-LED阵列器件对齐。
优选的，所述“十”字标记设置在深硅刻蚀模板的四角或对角或某一个角的位置。
优选的，所述镂空孔结构为正方形孔、长方形孔或圆形孔、椭圆形孔，孔的大小应当将待填充量子点的微孔完全露出。
本发明还公开了一种采用深硅刻蚀技术填充量子点的方法，其步骤包括：
1)截取等于或稍大于待填充量子点的器件顶表面的硅片，在硅片表面旋涂光刻胶，对其进行前烘，利用紫外光刻技术将光刻版待填充量子点的器件顶表面的图形转移到硅片表面，然后显影、后烘；
2)利用光刻胶作为掩膜，采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光和/或绿光和/或黄光量子点的微孔位置对应的镂空方形孔结构和“十”字对准标记，制成对应的红光和/或绿光和/或黄光深硅刻蚀模板，并在器件顶表面对应位置也刻蚀出“十”字对准标记；
3)将红光深硅刻蚀模板放置在待填充量子点的器件顶表面上，并将硅片上的“十”字对准标记与器件顶表面上的“十”字光刻标记在显微镜下对准；
4)通过红光/绿光/黄光深硅刻蚀模板上的孔形结构向器件顶表面上旋涂红光/绿光/黄光量子点，并将旋涂完量子点的器件烘干，然后取下红光/绿光/黄光深硅刻蚀模板；
5)进行其他颜色量子点的填充，步骤与步骤(3)-(4)相同，根据需要将 红光和/或绿光和/或黄光量子点填充至器件顶表面的量子点填充孔内，完成填充。
本发明设计并制备了一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件，通过深硅刻蚀模板量子点转移工艺将II-VI族核壳结构CdSe/ZnS的红光量子点、绿光量子点和黄光量子点填充至每一个2×2 RGB像素点的对应的微米孔内，不同颜色量子点经过蓝光LED激发出红光、绿光、黄光，实现了每个RGB像素点的多色显示。相对于普通Micro-LED直接将量子点旋涂到P型氮化镓表面，微米孔结构起到对量子点的保护作用，减少了外界带来的物理损伤，而且微米孔结构增大了量子阱与量子点的接触面积，更好地实现色转换。本发明中，相对于目前常规的喷墨打印的量子点填充方法，采用了微米孔深硅刻蚀模板的微加工方法来进行旋涂量子点，操作简便，旋涂质量高，且对设备的要求较低，可利用现有的常用的微加工设备完成旋涂，不需要专门采购喷墨打印设备，成本较低。采用微加工工艺对Micro-LED阵列器件进行制造，使Micro-LED的研究有了更大的突破，制备的QLED阵列器件实现了四色显示，推动了半导体显示的发展。
附图说明
图1为采用MOCVD法生长的In xGa 1-xN/GaN量子阱LED基片的结构示意图。
图2为本发明Micro-LED阵列及其制备方法步骤(1)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图3为本发明Micro-LED阵列及其制备方法步骤(2)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图4-5为本发明Micro-LED阵列及其制备方法步骤(3)中每次操作所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图6为本发明Micro-LED阵列及其制备方法步骤(4)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图7为本发明Micro-LED阵列及其制备方法步骤(5)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图8为本发明Micro-LED阵列及其制备方法步骤(6)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图9-11为本发明Micro-LED阵列及其制备方法步骤(7)中每次操作所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图12为本发明Micro-LED阵列及其制备方法步骤(8)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图13为本发明Micro-LED阵列及其制备方法步骤(9)所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图14-15为本发明Micro-LED阵列及其制备方法步骤(10)每次操作所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图16-17为本发明Micro-LED阵列及其制备方法步骤(11)每步所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图。
图18-19为本发明Micro-LED阵列及其制备方法步骤(12)每次所得的基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的结构示意图
图20为本发明深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法步骤(1)所得的孔形深硅刻蚀模板结构示意图。
图21为本发明深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法步骤(2)所得的四角“十”字标记孔形硅片掩模板表面结构示意图。
图22为本发明深硅刻蚀模板量子点转移工艺步骤(1)所得的四角“十”字标记孔形深硅刻蚀模板与Micro-LED阵列器件对齐示意图。
图23为本发明深硅刻蚀模板量子点转移工艺步骤(2)所得的在具有四角“十”字标记的孔形深硅刻蚀模板上旋涂红光量子点后得到的Micro-LED阵列器件表面示意图。
图24-29为本发明发明深硅刻蚀模板量子点转移工艺步骤(3)中改变四角“十”字标记深硅刻蚀模板中正方形孔的位置，重复量子点转移工艺步骤(1)-(2)2次每步所得的器件示意图。
图30为本发明深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法步骤(2)所得的对角“十”字标记孔形硅片掩模板表面结构示意图。
图31为本发明深硅刻蚀模板量子点转移工艺步骤(1)所得的对角“十”字标记孔形深硅刻蚀模板与Micro-LED阵列器件对齐示意图。
图32为本发明深硅刻蚀模板量子点转移工艺步骤(2)所得的在具有对角“十” 字标记的孔形深硅刻蚀模板上旋涂红光量子点后得到的Micro-LED阵列器件表面示意图。
图33为本发明基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的截面示意图。
图34为本发明基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件的表面示意图。
具体实施方式
以下是结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件
本实施案例中衬底材料选择的外延片结构如图1所示，具有p-n结构的标准蓝光LED外延片，包括蓝宝石衬底1；生长在蓝宝石衬底上的氮化镓缓冲层2；生长在缓冲层上的n型氮化镓层3；生长在n型氮化镓层上的量子阱有源层4；生长在量子阱有源层上的p型氮化镓层5。
Micro-LED阵列器件的具体制备方法如下：
(1)如图2所示，采用等离子体增强化学气相沉积(PECVD)技术，在In xGa 1-xN/GaN量子阱蓝光LED外延片上蒸镀一层150nm厚的SiO 2介质层6，PECVD生长SiO 2的方式为，向反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，在压强300mTorr，功率10W，温度350℃的条件下，经过SiH x+O→SiO 2(+H 2)反应在外延片表面沉积SiO 2，时间为7分10秒；
(2)如图3所示，在SiO 2介质层上旋涂光刻胶7，并对其进行90℃的前烘，时间为10分钟；然后利用紫外光刻技术，使光刻版上的图形转移到在光刻胶上，形成有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的长方形隔离槽图形和相邻正方形台面之间每个阵列四角的“十”字对准标记，然后显影，110℃后烘1分钟；
(3)采用反应离子刻蚀(RIE)技术，通入O 2，气流量为10sccm，压强3Pa，功率50W，经20秒去除光刻胶的残余层。然后利用物理气相沉积(PVD)工艺在 样品表面蒸镀金属镍(Ni)30nm厚作为掩膜8，如图4所示，蒸发速率为0.5A/s。然后利用丙酮溶液超声10分钟剥离光刻胶层7及光刻胶层上的金属镍薄膜8，得到大面积有序的正方形台面阵列图形、相邻微米孔之间的长方形隔离槽图形和相邻台面之间的“十”字对准标记，相邻台面之间的间距为80μm，隔离槽宽度为10μm，“十”字对准标记最长处长度为40μm，最宽处宽度为20μm，如图5所示；
(4)如图6所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间3分钟，以金属镍为掩膜纵向刻蚀介质层SiO 2，将金属正方形台面结构、相邻微米孔之间的长方形隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至介质层6；
(5)如图7所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以金属8和介质层6为掩膜各向异性刻蚀p型氮化镓层5和量子阱层4至n型氮化镓层3，形成大面积且相互隔离的正方形台面结构、相邻微米孔之间的长方形隔离槽和相邻正方形台面之间的“十”字对准标记，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间9分30秒，刻蚀深度约950nm，形成的相邻Micro-LED之间的间距为80μm；
(6)如图8所示，采用湿法腐蚀，去掉金属掩膜层8和介质层6，具体方法为将样品先后放进硝酸水溶液和缓冲氧化物刻蚀液(BOE)中浸泡，时间分别为1分钟和40秒，浸泡过程中也可以减少氮化镓及量子阱侧壁的刻蚀损伤；
(7)如图9所示，先采用等离子体增强化学气相沉积(PECVD)技术蒸镀一层150nm厚的SiO 2介质层9作为掩膜，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为7分10秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2。然后在样品表面旋涂一层光刻胶10，90℃前烘10分钟，再利用紫外光刻技术，使用光刻版在光刻胶上套刻形成直径为20μm，周期为100μm的微米孔图形，显影，在110℃下后烘1分钟。然后如图10所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm， 功率为150W，压强4Pa，刻蚀时间3分钟，以光刻胶10为掩膜纵向刻蚀介质层SiO 2 6。如图11所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以光刻胶10和介质层9为掩膜各向异性刻蚀p型氮化镓层5，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间2分钟，刻蚀深度约200nm，得到直径20μm，周期100μm，深度200nm的微米孔阵列；
(8)如图12所示，利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去SiO 2介质层9和介质层上的残余光刻胶层10，并减少氮化镓及量子阱表面和侧壁的刻蚀损伤；
(9)如图13所示，采用等离子体增强化学气相沉积(PECVD)技术，在样品表面蒸镀一层150nm厚的SiO 2介质层11，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为7分10秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2；
(10)制备n型电极。在样品表面旋涂一层光刻胶12，90℃前烘10分钟，利用紫外光刻技术将光刻版上的n型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。然后如图14所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间3分钟，以光刻胶12为掩膜刻蚀SiO 2介质层薄膜11，将n型电极图形转移至n型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀钛(Ti)/铝(Al)/镍(Ni)/金(Au)四种金属，厚度分别为20nm/50nm/30nm/100nm，作为n型电极13。然后如图15所示，利用丙酮超声，将光刻胶12以及光刻胶层上的金属薄膜13剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现钛(Ti)/铝(Al)/镍(Ni)/金(Au)金属与n型氮化镓的欧姆接触。
(11)制备p型电极。如图16所示，在样品表面旋涂一层光刻胶14，90℃前烘10分钟，利用紫外光刻技术将光刻版上的p型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W， 压强4Pa，刻蚀时间3分钟，以光刻胶14为掩膜刻蚀SiO 2介质层薄膜11，将p型电极图形转移至p型氮化镓5。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀镍(Ni)/金(Au)两种金属，厚度分别为150nm/200nm，作为p型电极15。利用丙酮超声，将光刻胶14以及光刻胶层上的金属薄膜15剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现镍(Ni)/金(Au)金属与p型氮化镓的欧姆接触，如图17所示。
(12)填充隔离槽中的吸光材料，如图18所示，在样品表面重新旋涂一层光刻胶16，90℃前烘10分钟，利用紫外光刻技术使用光刻板在光刻胶上套刻形成长方形隔离槽图形，显影，在110℃下后烘1分钟；向样品表面旋涂一层吸光材料Vantablack17，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去光刻胶16及其上面的吸光材料17，洗净并烘干样品，如图19所示。
深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法：
(1)制备深硅刻蚀模板，在洗净的200μm厚的硅片18表面旋涂AZ4620正性光刻胶19，95℃下前烘4分钟，然后利用紫外光刻技术将光刻版表面周期性正方形孔和每个阵列四角的“十”字对准标记图形转移到硅片表面，显影、110℃后烘5分钟，正方形孔的边长为90μm，“十”字对准标记中长方形的长为40μm，宽为20μm，如图20所示；
(2)利用光刻胶作为掩膜，采用深硅刻蚀技术，在反应腔内通入C 4F 8和SF 6气体，刻蚀42分40秒，刻穿硅片，在硅片表面形成镂空的正方形孔结构和“十”字对准标记，如图21所示。
深硅刻蚀模板量子点转移工艺：
(1)将深硅刻蚀模板放置在Micro-LED上方，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻对准标记在显微镜下对准，如图22所示；
(2)将II-VI族核壳结构CdSe/ZnS红光量子点、绿光量子点和黄光量子点分别溶于甲苯溶剂中，之后将红光量子点溶液20旋涂在深硅刻蚀模板表面，量子点通过深硅刻蚀模板上的正方形孔进入到Micro-LED阵列器件中。将旋涂完量子点的Micro-LED与深硅刻蚀模板置于60℃烘干台上烘干。如图23所示，去 掉深硅刻蚀模板，Micro-LED阵列器件上每个RGB像素点中仅有一个涂有红光量子点；
(3)根据上述孔形深硅刻蚀模板的制备方法，改变深硅刻蚀模板中正方形微米孔的位置，制备两块新的深硅刻蚀模板，重复步骤(1)和(2)两次，如图24-29所示，分别将绿光量子点溶液21和黄光量子点溶液22填充至每一个RGB像素单元的微米孔内，实现每个RGB像素点的四色显示，所得器件截面示意图如图33所示，表面示意图如图34所示。
当然，对于本实施例而言，红光/绿光/黄光量子点的填充顺序可以随意替换，对器件的质量和性能不会有任何影响。
对于本实施例而言，“十”字对准标记也可以设置在器件和硅片的对角或其中任意一角。
实施例2基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件
本实施案例中衬底材料选择的外延片结构如图1所示，具有p-n结构的标准蓝光LED外延片，包括蓝宝石衬底1；生长在蓝宝石衬底上的氮化镓缓冲层2；生长在缓冲层上的n型氮化镓层3；生长在n型氮化镓层上的量子阱有源层4；生长在量子阱有源层上的p型氮化镓层5。
Micro-LED阵列器件的具体制备方法如下：
(1)如图2所示，采用等离子体增强化学气相沉积(PECVD)技术，在In xGa 1-xN/GaN量子阱蓝光LED外延片上蒸镀一层200nm厚的SiO 2介质层6，PECVD生长SiO 2的方式为，向反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，在压强300mTorr，功率10W，温度350℃的条件下，经过SiH x+O→SiO 2(+H 2)反应在外延片表面沉积SiO 2，时间为9分30秒；
(2)如图3所示，在SiO 2介质层上旋涂光刻胶7，并对其进行90℃的前烘，时间为10分钟；然后利用紫外光刻技术，使光刻版上的图形转移到在光刻胶上，形成有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的长方形隔离槽图形和相邻正方形台面之间每个阵列四角的“十”字对准标记，然后显影，110℃后烘1分钟；
(3)采用反应离子刻蚀(RIE)技术，通入O 2，气流量为10sccm，压强3Pa，功率50W，经20秒去除光刻胶的残余层。然后利用物理气相沉积(PVD)工艺在 样品表面蒸镀金属镍(Ni)30nm厚作为掩膜8，如图4所示，蒸发速率为0.5A/s。然后利用丙酮溶液超声10分钟剥离光刻胶层7及光刻胶层上的金属镍薄膜8，得到大面积有序的正方形台面阵列图形、相邻微米孔之间的长方形隔离槽图形和相邻台面之间的“十”字对准标记，相邻台面之间的间距为90μm，隔离槽宽度为16μm，“十”字对准标记最长处长度为40μm，最宽处宽度为20μm，如图5所示；
(4)如图6所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间4分钟，以金属镍为掩膜纵向刻蚀介质层SiO 2，将金属正方形台面结构、相邻微米孔之间的长方形隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至介质层6；
(5)如图7所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以金属8和介质层6为掩膜各向异性刻蚀p型氮化镓层5和量子阱层4至n型氮化镓层3，形成大面积且相互隔离的正方形台面结构、相邻微米孔之间的长方形隔离槽和相邻正方形台面之间的“十”字对准标记，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间9分30秒，刻蚀深度约950nm，形成的相邻Micro-LED之间的间距为90μm；
(6)如图8所示，采用湿法腐蚀，去掉金属掩膜层8和介质层6，具体方法为将样品先后放进硝酸水溶液和缓冲氧化物刻蚀液(BOE)中浸泡，时间分别为1分钟和40秒，浸泡过程中也可以减少氮化镓及量子阱侧壁的刻蚀损伤；
(7)如图9所示，先采用等离子体增强化学气相沉积(PECVD)技术蒸镀一层200nm厚的SiO 2介质层9作为掩膜，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为9分30秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2。然后在样品表面旋涂一层光刻胶10，90℃前烘10分钟，再利用紫外光刻技术，使用光刻版在光刻胶上套刻形成直径为50μm，周期为150μm的微米孔图形，显影，在110℃下后烘1分钟。然后如图10所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm， 功率为150W，压强4Pa，刻蚀时间4分钟，以光刻胶10为掩膜纵向刻蚀介质层SiO 2 6。如图11所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以光刻胶10和介质层9为掩膜各向异性刻蚀p型氮化镓层5，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间9分钟，刻蚀深度约900nm，得到直径50μm，周期150μm，深度900nm的微米孔阵列；
(8)如图12所示，利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去SiO 2介质层9和介质层上的残余光刻胶层10，并减少氮化镓及量子阱表面和侧壁的刻蚀损伤；
(9)如图13所示，采用等离子体增强化学气相沉积(PECVD)技术，在样品表面蒸镀一层200nm厚的SiO 2介质层11，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为9分30秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2；
(10)制备n型电极。在样品表面旋涂一层光刻胶12，90℃前烘10分钟，利用紫外光刻技术将光刻版上的n型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。然后如图14所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间4分钟，以光刻胶12为掩膜刻蚀SiO 2介质层薄膜11，将n型电极图形转移至n型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀钛(Ti)/铝(Al)/镍(Ni)/金(Au)四种金属，厚度分别为50nm/100nm/50nm/150nm，作为n型电极13。然后如图15所示，利用丙酮超声，将光刻胶12以及光刻胶层上的金属薄膜13剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现钛(Ti)/铝(Al)/镍(Ni)/金(Au)金属与n型氮化镓的欧姆接触。
(11)制备p型电极。如图16所示，在样品表面旋涂一层光刻胶14，90℃前烘10分钟，利用紫外光刻技术将光刻版上的p型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W， 压强4Pa，刻蚀时间4分钟，以光刻胶14为掩膜刻蚀SiO 2介质层薄膜9，将p型电极图形转移至p型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀镍(Ni)/金(Au)两种金属，厚度分别为150nm/300nm，作为p型电极15。利用丙酮超声，将光刻胶14以及光刻胶层上的金属薄膜15剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现镍(Ni)/金(Au)金属与p型氮化镓的欧姆接触，如图17所示。
(12)填充隔离槽中的吸光材料，如图18所示，在样品表面重新旋涂一层光刻胶16，90℃前烘10分钟，利用紫外光刻技术使用光刻板在光刻胶上套刻形成长方形隔离槽图形，显影，在110℃下后烘1分钟；向样品表面旋涂一层吸光材料Vantablack17，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去光刻胶16及其上面的吸光材料17，洗净并烘干样品，如图19所示。
深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法：
(1)制备深硅刻蚀模板，在洗净的400μm厚的硅片18表面旋涂AZ4620正性光刻胶19，95℃下前烘4分钟，然后利用紫外光刻技术将光刻版表面周期性正方形孔和每个阵列四角的“十”字对准标记图形转移到硅片表面，显影、110℃后烘5分钟，正方形孔的边长为134μm，“十”字对准标记中长方形的长为40μm，宽为20μm，如图20所示；
(2)利用光刻胶作为掩膜，采用深硅刻蚀技术，在反应腔内通入C 4F 8和SF 6气体，刻蚀57分12秒，刻穿硅片，在硅片表面形成镂空的正方形孔结构和“十”字对准标记，如图21所示。
深硅刻蚀模板量子点转移工艺：
(1)将深硅刻蚀模板放置在Micro-LED上方，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻对准标记在显微镜下对准，如图22所示；
(2)将II-VI族核壳结构CdSe/ZnS红光量子点、绿光量子点和黄光量子点分别溶于甲苯溶剂中，之后将红光量子点溶液20旋涂在深硅刻蚀模板表面，量子点通过深硅刻蚀模板上的正方形孔进入到Micro-LED阵列器件中。将旋涂完量子点的Micro-LED与深硅刻蚀模板置于60℃烘干台上烘干。如图23所示，去 掉深硅刻蚀模板，Micro-LED阵列器件上每个RGB像素点中仅有一个涂有红光量子点；
(3)根据上述孔形深硅刻蚀模板的制备方法，改变深硅刻蚀模板中正方形微米孔的位置，制备两块新的深硅刻蚀模板，重复步骤(1)和(2)两次，如图24-29所示，分别将绿光量子点溶液21和黄光量子点溶液22填充至每一个RGB像素单元的微米孔内，实现每个RGB像素点的四色显示，所得器件截面示意图如图33所示，表面示意图如图34所示。
当然，对于本实施例而言，红光/绿光/黄光量子点的填充顺序可以随意替换，对器件的质量和性能不会有任何影响。
对于本实施例而言，“十”字对准标记也可以设置在器件和硅片的对角或其中任意一角。
实施例3基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件
本实施案例中衬底材料选择的外延片结构如图1所示，具有p-n结构的标准蓝光LED外延片，包括蓝宝石衬底1；生长在蓝宝石衬底上的氮化镓缓冲层2；生长在缓冲层上的n型氮化镓层3；生长在n型氮化镓层上的量子阱有源层4；生长在量子阱有源层上的p型氮化镓层5。
Micro-LED阵列器件的具体制备方法如下：
(1)如图2所示，采用等离子体增强化学气相沉积(PECVD)技术，在In xGa 1-xN/GaN量子阱蓝光LED外延片上蒸镀一层250nm厚的SiO 2介质层6，PECVD生长SiO 2的方式为，向反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，在压强300mTorr，功率10W，温度350℃的条件下，经过SiH x+O→SiO 2(+H 2)反应在外延片表面沉积SiO 2，时间为11分50秒；
(2)如图3所示，在SiO 2介质层上旋涂光刻胶7，并对其进行90℃的前烘，时间为10分钟；然后利用紫外光刻技术，使光刻版上的图形转移到在光刻胶上，形成有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的长方形隔离槽图形和相邻正方形台面之间每个阵列对角的“十”字对准标记，然后显影，110℃后烘1分钟；
(3)采用反应离子刻蚀(RIE)技术，通入O 2，气流量为10sccm，压强3Pa，功率50W，经20秒去除光刻胶的残余层。然后利用物理气相沉积(PVD)工艺在 样品表面蒸镀金属镍(Ni)100nm厚作为掩膜8，如图4所示，蒸发速率为0.5A/s。然后利用丙酮溶液超声10分钟剥离光刻胶层7及光刻胶层上的金属镍薄膜8，得到大面积有序的正方形台面阵列图形、相邻微米孔之间的长方形隔离槽图形和相邻台面之间的“十”字对准标记，相邻台面之间的间距为100μm，隔离槽宽度为20μm，“十”字对准标记最长处长度为40μm，最宽处宽度为20μm，如图5所示；
(4)如图6所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以金属镍为掩膜纵向刻蚀介质层SiO 2，将金属正方形台面结构、相邻微米孔之间的长方形隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至介质层6；
(5)如图7所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以金属8和介质层6为掩膜各向异性刻蚀p型氮化镓层5和量子阱层4至n型氮化镓层3，形成大面积且相互隔离的正方形台面结构、相邻微米孔之间的长方形隔离槽和相邻正方形台面之间的“十”字对准标记，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间9分30秒，刻蚀深度约950nm，形成的相邻Micro-LED之间的间距为100μm；
(6)如图8所示，采用湿法腐蚀，去掉金属掩膜层8和介质层6，具体方法为将样品先后放进硝酸水溶液和缓冲氧化物刻蚀液(BOE)中浸泡，时间分别为1分钟和40秒，浸泡过程中也可以减少氮化镓及量子阱侧壁的刻蚀损伤；
(7)如图9所示，先采用等离子体增强化学气相沉积(PECVD)技术蒸镀一层250nm厚的SiO 2介质层9作为掩膜，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为11分50秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2。然后在样品表面旋涂一层光刻胶10，90℃前烘10分钟，再利用紫外光刻技术，使用光刻版在光刻胶上套刻形成直径为100μm，周期为200μm的微米孔图形，显影，在110℃下后烘1分钟。然后如图10所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm， 功率为150W，压强4Pa，刻蚀时间5分钟，以光刻胶10为掩膜纵向刻蚀介质层SiO 2 6。如图11所示，采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以光刻胶10和介质层9为掩膜各向异性刻蚀p型氮化镓层5，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间10分20秒，刻蚀深度约1.2μm，得到直径100μm，周期200μm，深度1.2μm的微米孔阵列；
(8)如图12所示，利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去SiO 2介质层9和介质层上的残余光刻胶层10，并减少氮化镓及量子阱表面和侧壁的刻蚀损伤；
(9)如图13所示，采用等离子体增强化学气相沉积(PECVD)技术，在样品表面蒸镀一层250nm厚的SiO 2介质层11，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为11分50秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2；
(10)制备n型电极。在样品表面旋涂一层光刻胶12，90℃前烘10分钟，利用紫外光刻技术将光刻版上的n型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。然后如图14所示，利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以光刻胶12为掩膜刻蚀SiO 2介质层薄膜11，将n型电极图形转移至n型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀钛(Ti)/铝(Al)/镍(Ni)/金(Au)四种金属，厚度分别为100nm/150nm/200nm/400nm，作为n型电极13。然后如图15所示，利用丙酮超声，将光刻胶12以及光刻胶层上的金属薄膜13剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现钛(Ti)/铝(Al)/镍(Ni)/金(Au)金属与n型氮化镓的欧姆接触。
(11)制备p型电极。如图16所示，在样品表面旋涂一层光刻胶14，90℃前烘10分钟，利用紫外光刻技术将光刻版上的p型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W， 压强4Pa，刻蚀时间5分钟，以光刻胶14为掩膜刻蚀SiO 2介质层薄膜9，将p型电极图形转移至p型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀镍(Ni)/金(Au)两种金属，厚度分别为200nm/300nm，作为p型电极15。利用丙酮超声，将光刻胶14以及光刻胶层上的金属薄膜15剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现镍(Ni)/金(Au)金属与p型氮化镓的欧姆接触，如图17所示。
(12)填充隔离槽中的吸光材料，如图18所示，在样品表面重新旋涂一层光刻胶16，90℃前烘10分钟，利用紫外光刻技术使用光刻板在光刻胶上套刻形成长方形隔离槽图形，显影，在110℃下后烘1分钟；向样品表面旋涂一层吸光材料Vantablack17，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去光刻胶16及其上面的吸光材料17，洗净并烘干样品，如图19所示。
深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法：
(1)制备深硅刻蚀模板，在洗净的500μm厚的硅片18表面旋涂AZ4620正性光刻胶19，95℃下前烘4分钟，然后利用紫外光刻技术将光刻版表面周期性正方形孔和每个阵列对角的“十”字对准标记图形转移到硅片表面，显影、110℃后烘5分钟，正方形孔的边长为180μm，“十”字对准标记中长方形的长为40μm，宽为20μm，如图20所示；
(2)利用光刻胶作为掩膜，采用深硅刻蚀技术，在反应腔内通入C 4F 8和SF 6气体，刻蚀95分20秒，刻穿硅片，在硅片表面形成镂空的正方形孔结构和“十”字对准标记，如图30所示。
深硅刻蚀模板量子点转移工艺：
(1)将深硅刻蚀模板放置在Micro-LED上方，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻对准标记在显微镜下对准，如图31所示；
(2)将II-VI族核壳结构CdSe/ZnS红光量子点、绿光量子点和黄光量子点分别溶于甲苯溶剂中，之后将红光量子点溶液20旋涂在深硅刻蚀模板表面，量子点通过深硅刻蚀模板上的正方形孔进入到Micro-LED阵列器件中。将旋涂完量子点的Micro-LED与深硅刻蚀模板置于60℃烘干台上烘干。如图32所示，去 掉深硅刻蚀模板，Micro-LED阵列器件上每个RGB像素点中仅有一个涂有红光量子点；
(3)根据上述孔形深硅刻蚀模板的制备方法，改变深硅刻蚀模板中正方形微米孔的位置，制备两块新的深硅刻蚀模板，重复步骤(1)和(2)两次，分别将绿光量子点溶液21和黄光量子点溶液22填充至每一个RGB像素单元的微米孔内，实现每个RGB像素点的四色显示，所得器件截面示意图如图33所示，表面示意图如图34所示。
当然，对于本实施例而言，红光/绿光/黄光量子点的填充顺序可以随意替换，对器件的质量和性能不会有任何影响。
对于本实施例而言，“十”字对准标记也可以设置在器件和硅片的四角或其中任意一角。
实施例4基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件
本实施案例中衬底材料选择的外延片结构，具有p-n结构的标准紫光LED外延片，包括蓝宝石衬底1；生长在蓝宝石衬底上的氮化镓缓冲层2；生长在缓冲层上的n型氮化镓层3；生长在n型氮化镓层上的量子阱有源层4；生长在量子阱有源层上的p型氮化镓层5。
Micro-LED阵列器件的具体制备方法如下：
(1)采用等离子体增强化学气相沉积(PECVD)技术，在In xGa 1-xN/GaN量子阱蓝光LED外延片上蒸镀一层250nm厚的SiO 2介质层6，PECVD生长SiO 2的方式为，向反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，在压强300mTorr，功率10W，温度350℃的条件下，经过SiH x+O→SiO 2(+H 2)反应在外延片表面沉积SiO 2，时间为11分50秒；
(2)在SiO 2介质层上旋涂光刻胶7，并对其进行90℃的前烘，时间为10分钟；然后利用紫外光刻技术，使光刻版上的图形转移到在光刻胶上，形成有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的长方形隔离槽图形和相邻正方形台面之间每个阵列对角的“十”字对准标记，然后显影，110℃后烘1分钟；
(3)采用反应离子刻蚀(RIE)技术，通入O 2，气流量为10sccm，压强3Pa，功率50W，经20秒去除光刻胶的残余层。然后利用物理气相沉积(PVD)工艺在 样品表面蒸镀金属镍(Ni)50nm厚作为掩膜8，蒸发速率为0.5A/s。然后利用丙酮溶液超声10分钟剥离光刻胶层7及光刻胶层上的金属镍薄膜8，得到大面积有序的正方形台面阵列图形、相邻微米孔之间的长方形隔离槽图形和相邻台面之间的“十”字对准标记，相邻台面之间的间距为100μm，隔离槽宽度为20μm，“十”字对准标记最长处长度为40μm，最宽处宽度为20μm；
(4)利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以金属镍为掩膜纵向刻蚀介质层SiO 2，将金属正方形台面结构、相邻微米孔之间的长方形隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至介质层6；
(5)采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以金属8和介质层6为掩膜各向异性刻蚀p型氮化镓层5和量子阱层4至n型氮化镓层3，形成大面积且相互隔离的正方形台面结构、相邻微米孔之间的长方形隔离槽和相邻正方形台面之间的“十”字对准标记，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间9分30秒，刻蚀深度约950nm，形成的相邻Micro-LED之间的间距为100μm；
(6)采用湿法腐蚀，去掉金属掩膜层8和介质层6，具体方法为将样品先后放进硝酸水溶液和缓冲氧化物刻蚀液(BOE)中浸泡，时间分别为1分钟和40秒，浸泡过程中也可以减少氮化镓及量子阱侧壁的刻蚀损伤；
(7)先采用等离子体增强化学气相沉积(PECVD)技术蒸镀一层250nm厚的SiO 2介质层9作为掩膜，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为11分50秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2。然后在样品表面旋涂一层光刻胶10，90℃前烘10分钟，再利用紫外光刻技术，使用光刻版在光刻胶上套刻形成直径为100μm，周期为200μm的微米孔图形，显影，在110℃下后烘1分钟。然后利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以光刻胶10为掩膜纵向刻蚀介质层SiO 2 6。采用电感耦合等离子体刻蚀(ICP)技术，向反应腔内通入Cl 2和BCl 3的混合气体，以 光刻胶10和介质层9为掩膜各向异性刻蚀p型氮化镓层5，刻蚀条件为Cl 2：24sccm，BCl 3：3sccm，ICP功率为600W，RF功率为10W，压强6.5mTorr，时间15分钟，刻蚀深度约1.5μm，得到直径、100μm，周期200μm，深度1.5μm的微米孔阵列；
(8)利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去SiO 2介质层9和介质层上的残余光刻胶层10，并减少氮化镓及量子阱表面和侧壁的刻蚀损伤；
(9)采用等离子体增强化学气相沉积(PECVD)技术，在样品表面蒸镀一层250nm厚的SiO 2介质层11，在反应腔内通入5％SiH 4/N 2和N 2O的混合气体，流量分别为100sccm和450sccm，压强300mTorr，功率10W，温度350℃，时间为11分50秒，经过SiH x+O→SiO 2(+H 2)反应在样品表面沉积一层SiO 2；
(10)制备n型电极。在样品表面旋涂一层光刻胶12，90℃前烘10分钟，利用紫外光刻技术将光刻版上的n型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。然后利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以光刻胶12为掩膜刻蚀SiO 2介质层薄膜11，将n型电极图形转移至n型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀钛(Ti)/铝(Al)/镍(Ni)/金(Au)四种金属，厚度分别为100nm/150nm/200nm/400nm，作为n型电极13。然后利用丙酮超声，将光刻胶12以及光刻胶层上的金属薄膜13剥离，洗净并烘干样品。最后在N 2，温度750℃，时间30秒的条件下热退火，实现钛(Ti)/铝(Al)/镍(Ni)/金(Au)金属与n型氮化镓的欧姆接触。
(11)制备p型电极。在样品表面旋涂一层光刻胶14，90℃前烘10分钟，利用紫外光刻技术将光刻版上的p型电极图形套刻到光刻胶上，显影，在110℃下后烘1分钟。利用反应离子刻蚀(RIE)技术，向反应腔内通入CF 4和O 2的混合气体，气体的流量为：CF 4:30sccm，O 2:10sccm，功率为150W，压强4Pa，刻蚀时间5分钟，以光刻胶14为掩膜刻蚀SiO 2介质层薄膜9，将p型电极图形转移至p型氮化镓3。采用物理气相沉积(PVD)工艺在样品表面依次蒸镀镍(Ni)/金(Au)两种金属，厚度分别为250nm/300nm，作为p型电极15。利用丙酮超声，将光刻胶14以及光刻胶层上的金属薄膜15剥离，洗净并烘干样品。最后在 N 2，温度750℃，时间30秒的条件下热退火，实现镍(Ni)/金(Au)金属与p型氮化镓的欧姆接触。
(12)填充隔离槽中的吸光材料，在样品表面重新旋涂一层光刻胶16，90℃前烘10分钟，利用紫外光刻技术使用光刻板在光刻胶上套刻形成长方形隔离槽图形，显影，在110℃下后烘1分钟；向样品表面旋涂一层吸光材料银17，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀，将样品放在缓冲氧化物刻蚀液(BOE)中浸泡1分钟，除去光刻胶16及其上面的吸光材料17，洗净并烘干样品。
深硅刻蚀模板量子点转移工艺中的孔形深硅刻蚀模板的制备方法：
(1)制备深硅刻蚀模板，在洗净的500μm厚的硅片18表面旋涂AZ4620正性光刻胶19，95℃下前烘4分钟，然后利用紫外光刻技术将光刻版表面周期性正方形孔和每个阵列对角的“十”字对准标记图形转移到硅片表面，显影、110℃后烘5分钟，正方形孔的边长为180μm，“十”字对准标记中长方形的长为40μm，宽为20μm；
(2)利用光刻胶作为掩膜，采用深硅刻蚀技术，在反应腔内通入C 4F 8和SF 6气体，刻蚀95分20秒，刻穿硅片，在硅片表面形成镂空的正方形孔结构和“十”字对准标记。
深硅刻蚀模板量子点转移工艺：
(1)将深硅刻蚀模板放置在Micro-LED上方，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻对准标记在显微镜下对准；
(2)将钙钛矿CsPbBr 3蓝光量子点、红光量子点、绿光量子点和黄光量子点分别溶于甲苯溶剂中，之后将蓝光量子点溶液旋涂在深硅刻蚀模板表面，量子点通过深硅刻蚀模板上的正方形孔进入到Micro-LED阵列器件中。将旋涂完量子点的Micro-LED与深硅刻蚀模板置于60℃烘干台上烘干。去掉深硅刻蚀模板，Micro-LED阵列器件上每个RGB像素点中仅有一个涂有蓝光量子点；
(3)根据上述孔形深硅刻蚀模板的制备方法，改变深硅刻蚀模板中正方形微米孔的位置，制备三块新的深硅刻蚀模板，重复步骤(1)和(2)三次。分别将红光量子点溶液、绿光量子点溶液和黄光量子点溶液填充至每一个RGB像素单元的微米孔内，实现每个RGB像素点的四色显示。所得器件截面示意图如图 33所示，表面示意图如图34所示。
当然，对于本实施例而言，红光/绿光/黄光量子点的填充顺序可以随意替换，对器件的质量和性能不会有任何影响。
对于本实施例而言，“十”字对准标记也可以设置在器件和硅片的四角或其中任意一角。
在本发明的上述实施例中，深硅刻蚀模板的镂空孔都采用正方形孔，事实上镂空孔做出长方形孔或圆形孔、椭圆形孔都是可行的，只需要注意孔的大小可以将待填充量子点的微孔完全露出，且不会露出待填充其他颜色量子点的微孔即可。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受上述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (14)

  1. 一种基于深硅刻蚀模板量子点转移工艺的微米全色QLED阵列器件，其衬底材料为标准蓝光/紫光LED外延片，所述QLED阵列器件刻蚀形成贯穿p型GaN层、量子阱有源层，深至n型GaN层的阵列式正方形台面结构，各正方形台面相互隔离，每个正方形台面均构成一个Micro-LED，在每个正方形台面上刻蚀形成深至p型GaN层/量子阱有源层/n型GaN层的微米孔，形成微米孔阵列；
    还包括一p型阵列电极，蒸镀在微米孔阵列的p型GaN层上，一n型电极，蒸镀在n型GaN层上；
    所述正方形台面结构每2*2个构成一个RGB像素单元，每个RGB像素单元的四个微米孔里面，一个填充有红光量子点，一个填充有绿光量子点，一个填充黄光量子点，一个自身发出蓝光/填充蓝光量子点；
    其特征在于：在每个RGB像素单元内，相邻的两个正方形台面之间设有刻蚀到n型GaN层的长方形隔离槽，隔离槽中填充吸光材料，用来隔离光；
    所述红光/绿光/黄光/蓝光量子点采用深硅刻蚀模板填充到微米孔中。
  2. 根据权利要求1所述的微米全色QLED阵列器件，其特征在于：所述深硅刻蚀模板是采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光/绿光/黄光/蓝光量子点的微孔位置对应的镂空正方形孔结构和“十”字对准标记，在Micro-LED阵列器件的表面对应位置也设有“十”字对准标记，以便将深硅刻蚀模板与Micro-LED阵列器件对齐，然后旋涂量子点，制备QLED器件；其中“十”字标记设置在每个阵列的四角或对角或某一个角的位置。
  3. 根据权利要求1所述的微米全色QLED阵列器件，其特征在于：设有微米孔阵列的区域面积大于等于4英寸；微米孔直径为20-100μm，周期为100-200μm，Micro-LED之间的间距为80-100μm，微米孔深度为200nm-1.5μm。
  4. 根据权利要求1、2或3所述的微米全色QLED阵列器件，其特征在于：相邻正方形台面之间设有隔离槽，隔离槽宽度为10-20μm，长度等于正方形台面边长，深度为950nm，隔离槽中填充吸光材料，所述吸光材料为Vantablack或银。
  5. 根据权利要求1-4中任一项所述的微米全色QLED阵列器件的制备方法，其步骤包括：
    1)利用PECVD技术在蓝光/紫光LED延片上蒸镀一层介质层；
    2)在介质层表面旋涂一层光刻胶层，并对其进行前烘，利用紫外光刻技术 将光刻板上有序的正方形台面阵列图形、正方形台面中分隔相邻微米孔区域的隔离槽图形和相邻正方形台面之间的“十”字对准标记图形转移到光刻胶层上，然后显影、后烘；
    3)采用RIE技术，通入O 2去除经显影去除了大部分光刻胶的区域的少量光刻胶残余层，然后利用PVD工艺蒸镀一层金属掩膜层，再进行剥离，去除光刻胶层及光刻胶层上的金属薄膜层，得到大面积有序金属正方形台面阵列图形、隔离槽图形和“十”字对准标记图形；
    4)采用RIE技术，以金属为掩膜纵向刻蚀介质层，将金属正方形台面阵列结构、隔离槽结构和“十”字对准标记结构转移至介质层；
    5)采用ICP技术，以金属为掩膜各向异性刻蚀p型GaN层和量子阱层，将金属正方形台面阵列结构、相邻微米孔区域的隔离槽结构和相邻正方形台面之间的“十”字对准标记转移至n型GaN层；
    6)采用湿法腐蚀法，去除正方形台面阵列结构和相邻正方形台面之间的“十”字对准标记上的金属掩膜层和介质层，形成相互隔离的GaN正方形台面阵列结构，并修复GaN及量子阱侧壁的刻蚀损伤；
    7)制备微米孔结构，先采用PECVD技术在GaN正方形台面阵列结构上蒸镀介质层，在介质层表面旋涂光刻胶，并对其进行前烘；利用紫外光刻技术使用光刻版在正方形台面阵列结构的光刻胶上套刻形成微米孔图形；先采用RIE技术，刻蚀介质层再利用ICP技术，刻蚀p型GaN层；最终得到微米孔阵列，其中微米孔的深度可刻蚀到p型GaN层、量子阱层或者n型GaN层；
    8)利用湿法腐蚀，去除正方形台面阵列结构上的介质层及介质层上残留的光刻胶，并修复GaN及量子阱表面和侧壁的刻蚀损伤；
    9)再次在蓝光LED外延片上蒸镀一层介质层；
    10)制备N型电极，在介质层表面旋涂光刻胶，利用紫外光刻技术将光刻板上的n型电极图形套刻到光刻胶上；采用RIE技术，以光刻胶为掩膜刻蚀介质层将n型电极图形转移至n型GaN层；采用PVD工艺蒸镀一层金属作为n型电极；然后剥离去掉光刻胶以及光刻胶层上的金属薄膜，洗净并烘干样品；最后利用热退火实现金属与n型GaN的欧姆接触；
    11)制备P型电极，重新旋涂一层光刻胶，利用紫外光刻技术使用光刻版在光刻胶上套刻形成p型电极图形；采用RIE技术，以光刻胶为掩膜刻蚀介质层薄膜，将p型电极图形转移至p型GaN层；然后采用PVD工艺蒸镀一层金属作为p型电极；利用湿法腐蚀去掉光刻胶及光刻胶层上的金属薄膜层，洗净并烘干样品；最后利用热退火实现金属与p型GaN的欧姆接触；
    12)填充隔离槽中的吸光材料。重新旋涂一层光刻胶，利用紫外光刻技术使用光刻板在光刻胶上套刻形成隔离槽图形；向样品表面旋涂一层吸光材料，没有光刻胶的区域吸光材料进入隔离槽内；然后利用湿法腐蚀去掉光刻胶及其上面的吸光材料，洗净并烘干样品；
    13)采用深硅刻蚀模板量子点转移工艺在微米孔中填充量子点。
  6. 根据权利要求5所述的微米全色QLED阵列器件的制备方法，其特征在于步骤13中先要制作深硅刻蚀模板，具体为：
    1)截取等于或稍大于正方形台面阵列的硅片，在硅片表面旋涂AZ4620正性光刻胶，对其进行前烘，利用紫外光刻技术将光刻版表面图形转移到硅片表面，然后显影、后烘；
    2)利用光刻胶作为掩膜，采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光/绿光/黄光量子点的微孔位置对应的镂空正方形孔结构和“十”字对准标记，制成红光/绿光/黄光深硅刻蚀模板，并在样品表面对应位置也刻蚀出“十”字对准标记。
  7. 根据权利要求6所述的微米全色QLED阵列器件的制备方法，其特征在于：所述深硅刻蚀模板中正方形孔的边长为90-180μm，深度大于或等于硅片厚度，将硅片刻穿，硅片厚度为200-500μm，深硅刻蚀模板中“十”字对准标记与微米全色QLED阵列器件中的“十”字对准标记最长处长为40μm，最宽处宽度为20μm。
  8. 根据权利要求7所述的微米全色QLED阵列器件的制备方法，其特征在于步骤13中填充量子点的步骤具体为：
    1)将红光/绿光/黄光中任一深硅刻蚀模板放置在Micro-LED上，并将硅片上的“十”字对准标记与Micro-LED阵列上的“十”字光刻标记 在显微镜下对准；
    2)通过该深硅刻蚀模板上的孔形结构向Micro-LED阵列旋涂对应颜色的量子点，并将旋涂完量子点的Micro-LED阵列器件烘干，然后取下该深硅刻蚀模板；
    3)采用另外两种颜色的深硅刻蚀模板，重复步骤1)-2)两次，可以将另外两种颜色的量子点填充至每一个RGB像素单元的微米孔内，制备形成QLED阵列器件。
  9. 根据权利要求8所述的微米全色QLED阵列器件的制备方法，其特征在于：所述n型电极为Ti/Al/Ni/Au金属，p型电极为Ni/Au金属，介质层厚度为150-250nm，材质为SiO 2，金属掩膜层的厚度为30-100nm，材质为Ni。
  10. 根据权利要求5中所述的微米全色QLED阵列器件的制备方法，其特征在于：所述红光/绿光/黄光量子点为II-VI族核壳结构CdSe/ZnS量子点或钙钛矿CsPbBr 3量子点。
  11. 一种用于填充量子点的深硅刻蚀模板，其特征在于：所述深硅刻蚀模板为硅片，在硅片表面采用深硅刻蚀技术形成与待填充红光/绿光/黄光/蓝光量子点的微孔位置对应的镂空孔结构和“十”字对准标记，在需填充红光/绿光/黄光/蓝光量子点的Micro-LED阵列器件的表面对应位置也刻上“十”字对准标记，以便将深硅刻蚀模板与Micro-LED阵列器件对齐。
  12. 根据权利要求11所述的深硅刻蚀模板，其特征在于：所述“十”字标记设置在深硅刻蚀模板的四角或对角或某一个角的位置。
  13. 根据权利要求11或12所述的深硅刻蚀模板，其特征在于：所述镂空孔结构为正方形孔、长方形孔或圆形孔、椭圆形孔，孔的大小应当将待填充量子点的微孔完全露出。
  14. 一种采用深硅刻蚀技术填充量子点的方法，其步骤包括：
    1)截取等于或稍大于待填充量子点的器件顶表面的硅片，在硅片表面旋涂光刻胶，对其进行前烘，利用紫外光刻技术将光刻版待填充量子点的器件顶表面的图形转移到硅片表面，然后显影、后烘；
    2)利用光刻胶作为掩膜，采用深硅刻蚀技术，刻穿硅片，在硅片表面形成与填充有红光和/或绿光和/或黄光量子点的微孔位置对应的镂空方形孔结构和 “十”字对准标记，制成对应的红光和/或绿光和/或黄光深硅刻蚀模板，并在器件顶表面对应位置也刻蚀出“十”字对准标记；
    3)将红光深硅刻蚀模板放置在待填充量子点的器件顶表面上，并将硅片上的“十”字对准标记与器件顶表面上的“十”字光刻标记在显微镜下对准；
    4)通过红光/绿光/黄光深硅刻蚀模板上的孔形结构向器件顶表面上旋涂红光/绿光/黄光量子点，并将旋涂完量子点的器件烘干，然后取下红光/绿光/黄光深硅刻蚀模板；
    5)进行其他颜色量子点的填充，步骤与步骤(3)-(4)相同，根据需要将红光和/或绿光和/或黄光量子点填充至器件顶表面的量子点填充孔内，完成填充。
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