WO2020199065A1 - 一种可变增益放大器及相控阵收发机 - Google Patents

一种可变增益放大器及相控阵收发机 Download PDF

Info

Publication number
WO2020199065A1
WO2020199065A1 PCT/CN2019/080704 CN2019080704W WO2020199065A1 WO 2020199065 A1 WO2020199065 A1 WO 2020199065A1 CN 2019080704 W CN2019080704 W CN 2019080704W WO 2020199065 A1 WO2020199065 A1 WO 2020199065A1
Authority
WO
WIPO (PCT)
Prior art keywords
active transistor
variable gain
transistor
cascode
amplifier
Prior art date
Application number
PCT/CN2019/080704
Other languages
English (en)
French (fr)
Inventor
崔科技
王永利
卢磊
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980094109.7A priority Critical patent/CN113728550A/zh
Priority to PCT/CN2019/080704 priority patent/WO2020199065A1/zh
Priority to EP19922592.1A priority patent/EP3940953A4/en
Publication of WO2020199065A1 publication Critical patent/WO2020199065A1/zh
Priority to US17/490,900 priority patent/US20220021363A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45188—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/306—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage being a parallel resonance circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45302—Indexing scheme relating to differential amplifiers the common gate stage of a cascode dif amp being controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45318—Indexing scheme relating to differential amplifiers the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45662—Indexing scheme relating to differential amplifiers the LC comprising inductive coupled loading elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45704—Indexing scheme relating to differential amplifiers the LC comprising one or more parallel resonance circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45731—Indexing scheme relating to differential amplifiers the LC comprising a transformer

Definitions

  • This application relates to the field of circuit technology, and in particular to a variable gain amplifier and a phased array transceiver.
  • VGA variable gain amplifier
  • GPS global positioning system
  • phased array technology has gradually become the direction of 5G communication.
  • 5G fifth-generation mobile communication
  • the VGA is needed to change the gain in the system.
  • the VGA in the phased array has its special requirements: First, in the phased array system, when the VGA changes the gain, the phase of the output signal needs to be kept constant to avoid changing the antenna's gain when switching the gain. Transceiving angle; secondly, for the large-bandwidth scenario of the millimeter wave frequency band, for signals in the same bandwidth, it is necessary to ensure that the signals at different frequencies have the same gain step.
  • FIG. 1 shows a circuit topology for realizing a VGA through a cascode structure.
  • the M 2 tube can be called a common grid tube; the M 3 tube can be called a common source tube.
  • the circuit structure composed of M 2 and M 3 can also be called a Cascode structure (cascode structure).
  • M 1 may be regarded as co-tube grid tubes, major diversion effect, M is a source electrode coupled to the drain of M 3. When the M 1 tube is turned off, all AC current flows into Z L , and the gain of the VGA is relatively large.
  • Z L can be regarded as the equivalent impedance of the output matching network and the next stage circuit; when the M 1 tube is turned on, the AC current By being shunted by the M 1 tube, the current flowing into the Z L decreases, and the gain of the VGA decreases.
  • the VGA shown in Figure 1 has the following problems: First, when switching the cascode tube, the M 1 tube directly introduces the AC current to the AC ground (power supply voltage), but for signals of different frequencies, the ratio of the AC current is different. , So the VGA shown in Figure 1 has different gain steps for different frequency signals. Secondly, when the M 1 tube is turned on and off, the load capacitance of the output matching network is different, and the output phase of the VGA under different gains is not constant.
  • the embodiments of the present application provide a variable gain amplifier and a phased array transceiver, so that the variable gain amplifier can maintain a constant phase when switching gains, and the gain step is stable with frequency.
  • an embodiment of the present application provides a variable gain amplifier, which includes: an amplifying circuit for amplifying an input signal; a control circuit for controlling the gain of the amplifying circuit by adjusting the output current of the amplifying circuit ; Inductive load and inductive regulating circuit, the inductive load is coupled with the signal output terminal of the amplifying circuit, and the inductive regulating circuit is coupled with the inductive load by mutual inductance.
  • variable gain amplifier can be coupled to the next-stage circuit through an inductive load.
  • the amplification function can be realized by the amplifying circuit, and the gain variable can be realized by the control circuit.
  • the inductive adjustment circuit coupled with the inductive load mutual inductance can also realize the calibration of the output signal phase and gain step of the variable gain amplifier.
  • the inductive adjustment circuit may include an inductor.
  • the inductor may be a tunable inductor.
  • the phase and gain step of the output signal of the variable gain amplifier can be adjusted to different degrees through the adjustable inductor, thereby improving the accuracy of the calibration and making the calibration effect better.
  • the inductive adjustment circuit may also include an adjustable resistor connected in parallel with the adjustable inductor.
  • the inductive adjustment circuit may also include a variable capacitor connected in parallel with the adjustable inductor.
  • variable gain amplifier in addition to calibrating the variable gain amplifier through the mutual inductance of the inductance and the inductive load, the variable gain amplifier can also be calibrated by switching the resistance value of the adjustable resistor and the capacitance value of the variable capacitor, thereby calibrating the variable gain amplifier. Any gain state of the gain amplifier is controlled to make the calibration effect better.
  • the amplifying circuit may include a first active transistor, the source of the first active transistor is coupled to ground, the drain of the first active transistor is the signal output terminal of the amplifying circuit, and the The gate is used to input the input signal.
  • the amplification function of the variable gain amplifier can be realized by an active transistor.
  • control circuit is used to adjust the bias voltage of the gate of the first active transistor.
  • the amplifying circuit further includes: a second active transistor, the second active transistor and the first active transistor constitute a differential amplifying circuit;
  • the control circuit includes: a third active transistor and a fourth active transistor; wherein, the third active transistor The source of the active transistor is coupled to ground, the drain of the third active transistor is coupled to the drain of the second active transistor; the source of the fourth active transistor is coupled to ground, and the drain of the fourth active transistor is coupled to the first The drain of the active transistor is coupled; the gate of the third active transistor and the gate of the fourth active transistor are both used to receive a control voltage to control on-off, or the gates of the third active transistor and the fourth active transistor The bias voltage of the pole is adjustable.
  • the amplification of the differential input signal can be realized through the first active transistor and the second active transistor; the third active transistor and the fourth active transistor are respectively connected to the second active transistor and the first active transistor. Inject reverse current to realize the adjustable gain of the variable gain amplifier.
  • the amplifying circuit includes: a first cascode amplifier; the drain of the first cascode tube in the first cascode amplifier is the signal output terminal of the amplifying circuit, and the first cascode amplifier
  • the gate of the first common source tube in the amplifier is used for inputting input signals, and the source of the first common source tube is coupled to ground.
  • the amplification function of the variable gain amplifier can be realized by the first cascode amplifier.
  • control circuit includes: a first active transistor; the source of the first active transistor is connected to the source of the first cascode transistor; the drain of the first active transistor is coupled to the first power supply voltage, or, The drain of an active transistor is coupled to one end of the inductive adjustment circuit, and the other end of the inductive adjustment circuit is coupled to the second power supply voltage; the gate of the first active transistor is used to receive the control voltage to control the conduction of the first active transistor. Or the bias voltage of the gate of the first active transistor is adjustable.
  • the first active transistor can shunt the current of the first cascode amplifier, so as to realize the variable gain of the variable gain amplifier.
  • control circuit is used to adjust the bias voltage of the first common source transistor.
  • the amplifier circuit further includes: a second cascode amplifier; the second cascode amplifier and the first cascode amplifier form a differential amplifier circuit; the second cascode amplifier includes a second cascode amplifier; Two common gate transistors and a second common source transistor; the control circuit includes: a first active transistor and a second active transistor; the source of the first active transistor is coupled to ground, and the drain of the first active transistor is connected to the second common The drain of the source transistor is coupled; the source of the second active transistor is coupled to ground; the drain of the second active transistor is coupled to the drain of the first common source transistor; the gate of the first active transistor is coupled to the second active transistor The gates of the transistors are both used to receive a control voltage to control on-off, or the bias voltages of the gates of the first active transistor and the second active transistor are adjustable.
  • the first cascode amplifier and the second cascode amplifier can be used to achieve the amplification of the differential input signal; the first active transistor and the second active transistor are respectively transmitted to the second cascode amplifier Inject a reverse current with the first cascode amplifier to realize the adjustable gain of the variable gain amplifier.
  • the amplifier circuit further includes: a second cascode amplifier; the second cascode amplifier and the first cascode amplifier form a differential amplifier circuit; the second cascode amplifier includes a second cascode amplifier; Two cascodes and a second cascode; the control circuit includes: a first active transistor and a second active transistor; the source of the first active transistor is coupled with the source of the first cascode, the first active The drain of the transistor is coupled with the drain of the second cascode; the source of the second active transistor is coupled with the source of the second cascode, and the drain of the second active transistor is coupled with the drain of the first cascode.
  • Polar coupling; both the gate of the first active transistor and the gate of the second active transistor are used to receive a control voltage to control on-off, or the bias voltage of the gates of the first active transistor and the second active transistor Adjustable.
  • the first cascode amplifier and the second cascode amplifier can be used to achieve the amplification of the differential input signal; the first active transistor and the second active transistor are respectively transmitted to the second cascode amplifier Inject a reverse current with the first cascode amplifier to realize the adjustable gain of the variable gain amplifier.
  • the embodiments of the present application provide a phased array transceiver.
  • the phased array transceiver includes a plurality of phased array channels, and each phased array channel includes a series-connected low noise amplifier, a phase shifter, and the first
  • the variable gain amplifier provided in one aspect or any possible design in the first aspect; wherein the phase shifter is used to realize the fixed phase shift of the input signal; the variable gain amplifier is used to realize the variable gain of the input signal and maintain The fixed phase shift of the input signal does not change.
  • variable gain amplifier provided in the first aspect or any possible design of the first aspect is used in the phased array transceiver. Since the variable gain amplifier can calibrate the phase of the output signal, the input signal can be kept fixed The phase shift is unchanged, the beam transmission and reception in a fixed direction is realized, and the beam accuracy is improved.
  • Fig. 1 is a schematic structural diagram of a variable gain amplifier provided in the prior art
  • FIG. 2 is a schematic diagram of the structure of an active VGA provided by the prior art
  • FIG. 3 is a schematic structural diagram of a first variable gain amplifier provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a second variable gain amplifier provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a third variable gain amplifier provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a fourth variable gain amplifier provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a fifth variable gain amplifier provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a sixth variable gain amplifier provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a seventh variable gain amplifier provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of an eighth variable gain amplifier provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a ninth variable gain amplifier provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a tenth variable gain amplifier provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of an eleventh variable gain amplifier provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a twelfth variable gain amplifier provided by an embodiment of the application.
  • 15 is a schematic structural diagram of a thirteenth type of variable gain amplifier provided by an embodiment of the application.
  • 16 is a schematic structural diagram of a fourteenth variable gain amplifier provided by an embodiment of the application.
  • FIG. 17 is a schematic structural diagram of a phased array transceiver provided by an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of another phased array transceiver provided by an embodiment of the application.
  • the existing active VGA has problems such as inconstant phase and unstable gain step due to frequency change when switching the gain.
  • the cascode structure active VGA shown in Figure 1 in the high gain mode, all AC current I flows into Z L through the cascode tube M 2 , where Z L can be regarded as the output matching network and the next The equivalent impedance of the first-stage circuit; in the low gain mode, the M 1 tube shunts the AC current, and the gain of the VGA decreases. Since the M 1 tube has two states of on and off when switching the gain, and the M 1 tube will change the load capacitance of the output matching network when it is turned on and off, it outputs in the low gain mode and the high gain mode. The load capacitance of the matching network is different, so the phase of the active VGA is not constant when switching the gain.
  • the M 1 tube introduces AC current into the AC ground (supply voltage), but for signals of different frequencies, the ratio of the M 1 tube into the AC current is different. Therefore, the VGA pair shown in Figure 1 is different The gain step of the frequency signal is different.
  • the embodiments of the present application provide a variable gain amplifier and a phased array transceiver, so that the variable gain amplifier can maintain a constant phase when switching gains, and the gain step is stable with frequency.
  • the embodiments of the present application may be applied to application scenarios that require high phase accuracy and gain step accuracy of the VGA.
  • the phased array antenna may be composed of multiple transceiver channels, and each transceiver channel includes a low noise amplifier (LNA), a phase shifter (PS), and a VGA.
  • LNA low noise amplifier
  • PS phase shifter
  • VGA VGA
  • each receiving channel needs to be switched to a fixed phase shift.
  • the phase shifts of the four receiving channels are ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4, and the phase shift is realized by PS.
  • the VGA of each transceiver channel introduces a phase shift when switching the gain.
  • the high frequency of the radio frequency signal for example, it can be the 28GHz band or the 38GHz band where the New Radio (NR) band is located
  • the delay of the LNA, VGA and other amplifier modules on the transceiver channel It will also cause large phase fluctuations.
  • the phase shift of the transmitting and receiving channel is not fixed, which ultimately affects the direction and gain of the beam.
  • phased array antennas have high requirements for phase accuracy and gain stepping accuracy, and it is difficult to meet the needs of phased array antennas using traditional active VGAs.
  • the transmitted signal and the received signal of the vehicle-mounted radar are millimeter waves, so the phase accuracy (equivalent to delay) is very high, and the VGA needs to ensure a constant phase in the switching gain.
  • the traditional active VGA is difficult to meet its usage requirements.
  • the VGA provided in the embodiments of this application can be used to make the VGA switch gain
  • the phase can be kept constant, and the gain step is stable with frequency.
  • example (a) (same principle as the VGA shown in Figure 1) adopts the method of switching the common gate tube.
  • the M 1 tube is turned on, the AC current is shunted by the M 1 tube to achieve gain switching;
  • example (b ) The method of switching the bias of the common source tube is adopted.
  • the transconductance of the M 1 tube also changes to achieve variable gain; example (c) uses the M 1 tube to inject reverse
  • the AC current method is used to reduce the final AC current flowing to the output (M 1 tube can be turned on and off or the gate bias voltage can be adjusted) to achieve the function of gain switching; example (d) is similar to example (c), A common gate tube M 1 is used to control the reverse current.
  • the differential structure is taken as an example for illustration.
  • the active VGA can also adopt a single-ended structure.
  • the active transistor adopts a complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) process.
  • CMOS complementary metal oxide semiconductor
  • the active transistor can also adopt other processes, such as bipolar junction transistors. transistor, BJT) process, the specific types and processes of active transistors are not limited in the embodiments of this application.
  • variable gain amplifier 300 includes:
  • the amplifying circuit 301 is used to amplify the input signal.
  • the control circuit 302 is used to control the gain of the amplifier circuit 301 by adjusting the output current of the amplifier circuit 301.
  • the inductive load 303 and the inductive adjustment circuit 304, the inductive load 303 is coupled with the signal output end of the amplifying circuit 301, the inductive adjustment circuit 304 and the inductive load 303 are mutually inductively coupled (also called magnetic coupling), and the inductive adjustment circuit 304 is adjustable.
  • the amplifying circuit 301 can be used to amplify the input signal, that is, to achieve a fixed gain of the input signal; the control circuit 302 can adjust the gain of the amplifying circuit 301.
  • the amplifying circuit 301, the control circuit 302, and the inductive load 303 can be regarded as active VGAs in the prior art.
  • the embodiment of the present application adds an inductive adjustment circuit 304 on the basis of the existing active VGA, so that the phase of the output signal of the variable gain amplifier 300 is consistent with the phase of the input signal, and the frequency of the input signal is different.
  • the gain step of the variable gain amplifier 300 is the same (that is, the output signal phase and gain step of the variable gain amplifier 300 are calibrated).
  • the drain of the common gate transistor is the signal output terminal of the amplifier circuit 301; when the amplifier circuit 301 is a transistor, the drain of the transistor is the signal output terminal of the amplifier circuit 301.
  • the signal output terminal reference may be made to the prior art for details, and examples are not described here.
  • the inductive load 303 is coupled between the signal output terminal of the amplifying circuit 301 and the output terminal of the variable gain amplifier 300, wherein the amplifying circuit 301 is coupled to the next stage circuit through the inductive load 303, specifically, the next stage circuit is Connect the variable gain amplifier 300 to the output terminal.
  • the inductive load 303 may be an output matching network, or a device such as a balun.
  • the variable gain amplifier 300 may be coupled to the next stage circuit through the inductive load 303.
  • the inductive adjustment circuit 304 can be regarded as a device independent of the inductive load 303. Specifically, the inductive adjustment circuit 304 can be independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300. Alternatively, the inductive adjustment circuit 304 can be connected in series to the control circuit 302.
  • the phase of the output signal and the gain step of the variable gain amplifier 300 can be calibrated through mutual inductance between the inductive load 303 and the inductive adjustment circuit 304.
  • the inductive adjustment circuit 304 may include an inductor. It should be noted that when the inductive load 303 is a balun, the inductive load 303 usually includes a primary coil and a secondary coil that is mutually inductively coupled with the primary coil. The primary coil is coupled to the signal output terminal of the amplifying circuit 301, and the secondary coil It is coupled to the next-level circuit, and the inductive adjustment circuit 304 in this application is an inductance independent of the inductive load 303, which is also mutually inductively coupled with the primary coil, but is different from the secondary coil. Other types of output matching networks are similar to this, and will not be repeated here.
  • the inductor may be an adjustable inductor.
  • the inductance in the inductive adjustment circuit 304 is an adjustable inductance, the phase and gain step of the output signal of the variable gain amplifier 300 can be adjusted to different degrees through the inductive adjustment circuit 304, thereby improving the accuracy of the calibration and making the calibration Better results.
  • the inductive adjustment circuit 304 may also include an adjustable resistor connected in parallel with the adjustable inductor.
  • the inductive adjustment circuit 304 may also include a variable capacitor connected in parallel with the adjustable inductor.
  • variable gain amplifier 300 in addition to calibrating the variable gain amplifier 300 through the mutual inductance coupling between the inductor and the inductive load 303, the variable gain amplifier 300 can also be calibrated by switching the resistance value of the adjustable resistor and the capacitance value of the variable capacitor. Calibration, thereby controlling any gain state of the variable gain amplifier 300, makes the calibration effect of the inductive adjustment circuit 304 better.
  • the inductive adjustment circuit 304 may be independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300, or may be arranged in the control circuit 302. Taking the inductive adjustment circuit 304 connected in series in the control circuit 302 as an example, a specific example of the variable gain amplifier 300 provided in the embodiment of the present application may be shown in FIG. 4.
  • FIG. 4 shows a single-ended variable gain amplifier.
  • M 1 and M 3 form an amplifying circuit 301;
  • L1 and RL can be regarded as inductive loads and are connected to the output terminal of M 1 ;
  • L2 can be regarded as an inductive regulating circuit;
  • M 2 can be regarded as a control circuit 302.
  • M 2 is off, L2 is similar to an open circuit, which has no effect on the main amplification path M 1 +L1, and the variable gain amplifier achieves high gain;
  • M 2 is closed, M 2 shunts the current input to the variable gain amplifier ,
  • the shunted AC current affects the output through the mutual inductance between L2 and L1, achieving the low gain of the variable gain amplifier while calibrating the output signal.
  • FIG. 4 also shows the equivalent structure of the above-mentioned variable gain amplifier. Among them, the direct coupling of L1 and L2 is equivalent to the inductance M. Then, in the low gain mode, the output before and after calibration are:
  • the output difference before and after calibration is mainly sM*I, where sM is the frequency domain impedance of the inductor M. Since the calibrated output signal contains the sM term, which can affect the phase of the output signal in the low gain mode, it can be used to calibrate the phase of the output signal of the variable gain amplifier.
  • sM is a frequency-dependent impedance, so it can be used to calibrate the gain step at different frequencies, making the gain step of the variable gain amplifier stable with frequency.
  • the output signal phase and gain step calibration can be achieved through the mutual inductance of the inductive load 303 and the inductive adjustment circuit 304, and the calibration principle is similar to the above example. It will not be repeated in the embodiments of this application.
  • the amplifying circuit 301 is used to amplify an input signal.
  • the amplifying circuit 301 may adopt a single-ended structure or a differential structure.
  • the structure with basic amplifying function in the amplifying circuit 301 can be composed of an active transistor or a cascode amplifier; among them, each cascode amplifier includes a cascode tube and a cascode amplifier. Common source tube.
  • variable gain amplifier provided by the embodiment of the present application is applicable to various structures, and various structures of the variable gain amplifier are introduced below.
  • CMOS technology is used as an example for the active transistors.
  • active transistors can also use other processes.
  • the names of the ports of the active transistor will be different, but the functions are basically the same.
  • the active transistor is BJT
  • the base in BJT is equivalent to the gate in CMOS
  • the collector in BJT is equivalent to the drain in CMOS
  • the emitter in BJT is equivalent to the source in CMOS. Therefore, the variable gain amplifier based on the MOS tube in this application can be equivalent to the variable gain amplifier based on BJT.
  • variable gain amplifier 300 when the structure with the basic amplifying function in the amplifying circuit 301 is composed of an active transistor and a cascode amplifier are respectively introduced below.
  • the structure with basic amplifying function in the amplifying circuit 301 is composed of an active transistor
  • the amplifying circuit 301 may include a first active transistor, the source of the first active transistor is coupled to ground, the drain of the first active transistor is the signal output terminal of the amplifying circuit 301, and the gate of the first active transistor Used to input the input signal.
  • the source of the first active transistor is coupled to ground, which can mean that the first active transistor is directly grounded, or the first active transistor is grounded through an inductor, a capacitor, or other devices.
  • the meaning of coupling to ground is the same, which will not be explained in detail later.
  • the amplifying function of the input signal by the amplifying circuit 301 can be realized by the first active transistor.
  • the control circuit 302 adjusts the gain of the amplifying circuit 301, different implementations can be selected according to different structures and different requirements of the variable gain amplifier.
  • the active transistor adopts a gate input signal and a source coupled to ground.
  • an active transistor can also adopt a source input signal and a gate coupled to ground. In this way, the embodiment of the present application does not specifically limit this.
  • the control circuit 302 can be used to adjust the bias voltage of the gate of the first active transistor.
  • the bias voltage of the gate of the first active transistor changes, the transconductance of the first active transistor is changed, thereby changing the conduction current of the first active transistor, and changing the gain of the amplifying circuit 301.
  • the inductive adjustment circuit 304 is independently provided from the amplifying circuit 301 and the control circuit 302. That is, the inductive adjustment circuit 304 is independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300.
  • variable gain amplifier may be as shown in FIG. 5.
  • the inductive load Ll can be considered, in parallel with L2, R and C can be considered as an inductive control circuit, M 1 can be regarded as a first active transistor.
  • the on-current of M 1 can be changed by adjusting the bias voltage Vbias, thereby changing the gain of the variable gain amplifier.
  • the amplifying circuit 301 in addition to the first active transistor, also includes a second active transistor.
  • the second active transistor and the first active transistor form a differential amplifier circuit 301;
  • the control circuit 302 includes: Three active transistors and a fourth active transistor.
  • the source of the third active transistor is coupled to ground, the drain of the third active transistor is coupled to the drain of the second active transistor; the source of the fourth active transistor is coupled to ground, and the drain of the fourth active transistor is grounded.
  • the electrode is coupled with the drain of the first active transistor, and the gate of the third active transistor and the gate of the fourth active transistor are both used to receive a control voltage to control on-off, or the third active transistor and the fourth active transistor
  • the bias voltage of the gate of the source transistor is adjustable.
  • the third active transistor and the fourth active transistor are controlled by the same control voltage, and the third active transistor and the fourth active transistor can be turned on or turned off at the same time; or, the third active transistor and the The bias voltages applied to the gates of the four active transistors are the same, and the transconductances of the third active transistor and the fourth active transistor are the same, so that the amplification factors of the two differential components are the same.
  • the amplifying function of the differential input signal of the amplifying circuit 301 can be realized by the first active transistor and the second active transistor.
  • the third active transistor is used to inject reverse current into the second active transistor
  • the fourth active transistor is used to inject reverse current into the first active transistor; when reverse current is injected, the output current of the variable gain amplifier Decrease, the gain decreases.
  • the control circuit 302 adjusts the gain of the amplifying circuit 301, it can control the on and off of the third active transistor and the fourth active transistor by controlling the voltage, so as to realize the high and low gain switching of the variable gain amplifier.
  • the on-current of the third active transistor and the fourth active transistor can be changed by adjusting the bias voltage of the third active transistor and the fourth active transistor, so as to change the magnitude of the reverse current injected, thereby changing The gain of the variable gain amplifier.
  • the inductive adjustment circuit 304 is set independently of the amplifying circuit 301 and the control circuit 302. That is, the inductive adjustment circuit 304 is independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300.
  • the inductive adjustment circuit 304 coupled with the inductive load 303 in mutual inductance can realize the calibration of the phase and gain step of the output signal of the variable gain amplifier.
  • variable gain amplifier may be as shown in FIG. 6.
  • the collection of L1 and the output matching network can be regarded as an inductive load.
  • L1 is separated from the output matching network to indicate the inductance L1 and the inductive adjustment circuit in the inductive load Mutual inductance coupling.
  • the inductor L1 can be regarded as a part of the output matching network.
  • the parallel adjustable resistor R, variable capacitor C and L2 can be regarded as an inductive adjustment circuit, M 1 on the left can be regarded as the first active transistor, M 1 on the right can be regarded as the second active transistor; M 2 on the left It can be regarded as the third active transistor, and the M 2 on the right can be regarded as the fourth active transistor.
  • M may be changed by the conduction current of the bias voltage Vbias is adjusted M 2, thereby changing the gain; reverse current can also be achieved by adjusting the on-off M 2 Inject and cut, and then change the gain.
  • the resistance value of R and the capacitance value of C can be changed in the RLC network of mutual inductance with L1.
  • variable gain amplifier with a differential structure
  • the function of amplifying a differential component can be realized by multiple active transistors connected in parallel.
  • the variable gain amplifier should also include multiple control circuits corresponding to multiple active transistors.
  • M 1 may be arranged off the active transistor bias voltage adjustable or adjustable, so that the gain of the variable gain amplifier changes more diverse. Therefore, in the schematic of FIG. 6, M 1 is also set to be adjustable. Adjusting M 1 and M 2 at the same time can make the gain of the variable gain amplifier more varied.
  • the structure with basic amplifying function in the amplifying circuit 301 is composed of a cascode amplifier
  • the amplifying circuit 301 may include: a first cascode amplifier; the drain of the first cascode tube in the first cascode amplifier is the signal output terminal of the amplifying circuit 301, and the first cascode amplifier The gate of the first common source transistor in is used for inputting input signals, and the source of the first common source transistor is coupled to ground.
  • the connection relationship between the first cascode tube and the first cascode tube may be: the drain of the first cascode tube is the signal output terminal of the amplifying circuit 301, and the first cascode tube
  • the gate of the tube is used to input the bias voltage
  • the source of the first cascode is coupled with the drain of the first cascode
  • the gate of the first cascode is used to input the input signal
  • the The source is coupled to ground.
  • the amplifying function of the input signal by the amplifying circuit 301 can be realized by the first cascode amplifier.
  • the control circuit 302 adjusts the gain of the amplifying circuit 301, different implementations can be selected according to different structures and different requirements of the variable gain amplifier.
  • the control circuit 302 includes: a first active transistor.
  • the source of the first active transistor is connected to the source of the first cascode transistor; the drain of the first active transistor is coupled to the first power supply voltage, or the drain of the first active transistor is connected to the inductive adjustment circuit
  • One end of 304 is coupled, and the other end of the inductive adjustment circuit 304 is coupled to the second power supply voltage; the gate of the first active transistor is used to receive a control voltage to control the on and off of the first active transistor, or the The bias voltage of the gate is adjustable.
  • the power supply that provides the first power supply voltage and the second power supply voltage may be the same power supply, or may be two power supplies with the same specifications.
  • the first active transistor is used to shunt the current of the first cascode amplifier, so as to change the output current of the first cascode amplifier, thereby changing the gain of the variable gain amplifier.
  • the output signal phase and gain step of the variable gain amplifier can be calibrated.
  • the inductive adjustment circuit 304 is connected in series In the control circuit 302; if the drain of the first active transistor is coupled to the first power supply voltage, the inductive adjustment circuit 304 is arranged independently of the amplifying circuit 301 and the control circuit 302, and the inductive adjustment circuit 304 is arranged close to the inductive load 303 and The side away from the output terminal of the variable gain amplifier 300.
  • a possible structure of the variable gain amplifier may be as shown in Fig. 7 As shown (in FIG. 7, the same power supply is taken as an example for providing the first power supply voltage and the power supply for providing the first power supply voltage).
  • M 1 can be regarded as the first cascode transistor
  • M 3 can be regarded as the first cascode transistor
  • M 2 can be regarded as the first active transistor
  • the collection of L1 and the output matching network can be regarded as an inductive load.
  • L2 can be regarded as an inductive regulating circuit.
  • the drain of M 2 is connected to the power supply voltage through L2.
  • M 2 is a gate for receiving a control voltage to control on-off M 2 or M 2 of the gate bias voltage is adjustable in order to achieve adjustable gain.
  • L2 and L1 have mutual inductance to calibrate the output signal phase and gain step of the variable gain amplifier.
  • variable gain amplifier shown in Figure 7 when M 2 is turned off, L2 is similar to an open circuit, and the inductance has no effect in the M 2 shunt branch, and its inductance value can be regarded as infinite; when M 2 is closed, M 2 The branch where it is located can be regarded as a shunt branch.
  • the shunted AC current affects the output through the mutual inductance between L2 and L1. At this time, the inductance value of L2 is no longer infinite. Therefore, it can be seen that under the control of M 2 (equivalent to the control circuit 302), the inductance value of the inductor L2 (equivalent to the inductive adjustment circuit 304) can be adjusted.
  • the inductive adjustment circuit 304 is adjustable.
  • the inductive adjustment circuit may further include an adjustable resistor R and a variable capacitor C connected in parallel with L2 respectively, as shown in FIG. 8. With the scheme shown in Figure 8, any gain state of the variable gain amplifier can be controlled, and the calibration effect is better.
  • a possible structure of the variable gain amplifier may be as shown in FIG. 9.
  • M 1 can be regarded as the first cascode transistor
  • M 3 can be regarded as the first cascode transistor
  • M 2 can be regarded as the first active transistor
  • the collection of L1 and the output matching network can be regarded as an inductive load.
  • the parallel connection of L2, R and C can be regarded as an inductive regulating circuit.
  • the drain of M 2 is connected to the power supply voltage.
  • the RLC network including L2 is independent of the control circuit settings.
  • M 2 is a gate for receiving a control voltage to control on-off M 2 or M 2 of the gate bias voltage is adjustable in order to achieve adjustable gain.
  • the RLC network and L1 have mutual inductance to calibrate the output signal phase and gain step of the variable gain amplifier.
  • variable gain amplifier can also adopt a differential structure.
  • a variable gain amplifier adopting a differential structure may be as shown in FIG. 10.
  • M 1 can be regarded as the first common gate transistor
  • M 3 can be regarded as the first common source transistor
  • M 2 can be regarded as the first active transistor
  • the collection of L1 and the output matching network can be regarded as an inductive load
  • L2 can be regarded as an inductive load. It is regarded as an inductive regulating circuit.
  • the gain can be variable; through the mutual inductance of L1 and L2, the output signal phase and gain step of the variable gain amplifier can be calibrated.
  • the inductive adjustment circuit may also include an adjustable resistor R and a variable capacitor C in parallel with L2, as shown in FIG. 11.
  • the inductive adjustment circuit can also be set independently of the control circuit, as shown in Figure 12.
  • variable gain amplifier of the differential structure the function of amplifying a differential component can be realized by multiple cascode amplifiers connected in parallel, and each cascode amplifier contains M 1 and M 3 .
  • the variable gain amplifier should also include multiple control circuits (ie multiple M 2 ) corresponding to multiple cascode amplifiers one-to-one.
  • M 1 may be arranged off the active transistor bias voltage adjustable or adjustable, so that the gain of the variable gain amplifier changes more diverse.
  • M 1 is also arranged adjustable. Adjusting M 1 and M 2 at the same time can make the gain of the variable gain amplifier more varied.
  • variable gain amplifier provided in the first implementation mode can be regarded as an improvement (adding an inductive adjustment circuit) on the basis of the example (a) in FIG. 2.
  • control circuit 302 is used to adjust the bias voltage of the first common source transistor.
  • the bias voltage of the gate of the first common source transistor is changed, the conduction current of the first common source transistor will be changed, thereby changing the gain of the amplifying circuit 301.
  • the inductive adjustment circuit 304 can be set independently of the amplifying circuit 301 and the control circuit 302. That is, the inductive adjustment circuit 304 is independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300.
  • the inductive adjustment circuit 304 coupled with the inductive load 303 mutual inductance can realize the calibration of the output signal phase and gain step of the variable gain amplifier.
  • variable gain amplifier may be as shown in FIG. 13.
  • L1 can be regarded as an inductive load
  • the parallel adjustable inductance L2 adjustable resistor R and variable capacitor C can be regarded as an inductive adjustment circuit
  • M 1 can be regarded as the first common gate transistor
  • M 2 can be seen It is the first common source tube.
  • the on-current of M 2 can be changed by adjusting the bias voltage Vbias, thereby changing the gain of the variable gain amplifier.
  • the resistance value of R and the capacitance value of C can be changed in the RLC network of mutual inductance with L1.
  • variable gain amplifier adopts a single-ended structure as an example for illustration.
  • variable gain amplifier can also adopt a differential structure. Gain adjustment is achieved by changing the bias voltage of the two common source transistors in the differential structure, and through two inductive adjustment circuits that mutually induct two inductive loads. The output signal phase and gain step of the variable gain amplifier are calibrated, and the specific implementation is not repeated here.
  • variable gain amplifier provided in the second implementation mode can be regarded as an improvement (adding an inductive adjustment circuit) on the basis of the example (b) in FIG. 2.
  • the amplifying circuit 301 also includes a second cascode amplifier; the second cascode amplifier and the first cascode amplifier form a differential amplifier circuit 301 ;
  • the second cascode amplifier includes a second cascode tube and a second cascode tube.
  • the connection relationship between the second cascode tube and the second cascode tube in the second cascode amplifier can refer to the connection relationship between the first cascode tube and the first cascode tube in the first cascode tube. I won't repeat it here.
  • the control circuit 302 includes: a first active transistor and a second active transistor; wherein the source of the first active transistor is coupled to ground, and the drain of the first active transistor is coupled to the drain of the second common source transistor; The sources of the two active transistors are coupled to ground, the drain of the second active transistor is coupled to the drain of the first common source transistor, and the gate of the first active transistor and the gate of the second active transistor are both used for receiving The voltage is controlled to control on and off, or the bias voltages of the gates of the first active transistor and the second active transistor are adjustable.
  • the first active transistor and the second active transistor are controlled by the same control voltage, and the first active transistor and the second active transistor are turned on or turned off at the same time; or, the first active transistor and The bias voltage applied to the gate of the second active transistor is the same, so that the amplification of the two differential components is the same.
  • the amplifying function of the differential input signal by the amplifying circuit 301 can be realized by the first cascode amplifier and the second cascode amplifier.
  • the first active transistor is used to inject reverse current into the second cascode amplifier
  • the second active transistor is used to inject reverse current into the first cascode amplifier.
  • the control circuit 302 adjusts the gain of the amplifying circuit 301, it can control the on and off of the first active transistor and the second active transistor by controlling the voltage, so as to realize the high and low gain switching of the variable gain amplifier; or, it can adjust the first active transistor and the second active transistor.
  • the bias voltage of one active transistor and the second active transistor changes the conduction current, thereby changing the magnitude of the injected reverse current, and then changing the gain of the variable gain amplifier.
  • the inductive adjustment circuit 304 can be set independently of the amplifying circuit 301 and the control circuit 302. That is, the inductive adjustment circuit 304 is independently arranged on the side close to the inductive load 303 and far from the output terminal of the variable gain amplifier 300.
  • the inductive adjustment circuit 304 coupled with the inductive load 303 in mutual inductance can realize the calibration of the output signal phase and gain step of the variable gain amplifier.
  • variable gain amplifier may be as shown in FIG. 14.
  • the set of L1 and the output matching network can be regarded as an inductive load
  • the parallel adjustable inductor L2, adjustable resistor R and variable capacitor C can be regarded as an inductive adjustment circuit
  • M 1 on the left can be regarded as the first Common source tube
  • M 1 on the right can be regarded as the second common source tube
  • M 3 on the left can be regarded as the first cascode tube
  • M 3 on the right can be regarded as the second cascode tube
  • M 2 on the left can be regarded as the second cascode tube
  • the first active transistor, M 2 on the right can be regarded as the second active transistor.
  • the variable gain amplifier shown in FIG. 14 can be varied by adjusting the bias voltage M 2 M 2 conduct current, thereby changing the gain of the variable gain amplifier; or M is achieved by adjusting the trans-off 2 Injecting and cutting off the current to change the gain of the variable gain amplifier.
  • M1 is also set to be adjustable. Adjusting M1 and M2 at the same time can make the gain of the variable gain amplifier more varied.
  • variable gain amplifier provided in the third implementation mode can be regarded as an improvement (adding an inductive adjustment circuit) on the basis of the example (c) in FIG. 2.
  • the amplifier circuit 301 also includes a second cascode amplifier; the second cascode amplifier and the first cascode amplifier form a differential amplifier circuit 301 ;
  • the second cascode amplifier includes a second cascode tube and a second cascode tube.
  • the connection relationship between the second cascode tube and the second cascode tube in the second cascode amplifier can refer to the connection relationship between the first cascode tube and the first cascode tube in the first cascode tube. I won't repeat it here.
  • the control circuit 302 includes: a first active transistor and a second active transistor; wherein, the source of the first active transistor is coupled to the source of the first cascode transistor, and the drain of the first active transistor is coupled to the second common gate.
  • the drain of the gate tube is coupled; the source of the second active transistor is coupled with the source of the second cascode, the drain of the second active transistor is coupled with the drain of the first cascode, the first active transistor.
  • the gate of the second active transistor and the gate of the second active transistor are used to receive a control voltage to control on-off, or the bias voltages of the gates of the first active transistor and the second active transistor are adjustable.
  • the first active transistor and the second active transistor are controlled by the same control voltage, and the first active transistor and the second active transistor are turned on or turned off at the same time; or, the first active transistor and the second active transistor
  • the bias voltage applied to the gate of the transistor is the same, so that the amplification factor of the two differential components is the same.
  • the amplifying function of the differential input signal by the amplifying circuit 301 can be realized by the first cascode amplifier and the second cascode amplifier.
  • the first active transistor is used to inject reverse current into the second cascode amplifier
  • the second active transistor is used to inject reverse current into the first cascode amplifier.
  • the control circuit 302 adjusts the gain of the amplifying circuit 301, it can control the on and off of the first active transistor and the second active transistor by controlling the voltage, so as to realize the high and low gain switching of the variable gain amplifier; or, it can adjust the first active transistor and the second active transistor.
  • the bias voltage of one active transistor and the second active transistor changes the conduction current, thereby changing the magnitude of the injected reverse current, and then changing the gain of the variable gain amplifier.
  • the inductive adjustment circuit 304 can be set independently of the amplifying circuit 301 and the control circuit 302. That is, the inductive adjustment circuit 304 is independently arranged on the side close to the inductive load and far from the output terminal of the variable gain amplifier 300.
  • the inductive adjustment circuit 304 coupled with the inductive load 303 in mutual inductance can realize the calibration of the output signal phase and gain step of the variable gain amplifier.
  • variable gain amplifier may be as shown in FIG. 15.
  • the set of L1 and the output matching network can be regarded as an inductive load
  • the parallel adjustable inductor L2, adjustable resistor R and variable capacitor C can be regarded as an inductive adjustment circuit
  • M 1 on the left can be regarded as the first Common gate
  • M 1 on the right can be regarded as the second cascode
  • M 3 on the left can be regarded as the first common source
  • M 3 on the right can be regarded as the second common source
  • M 2 on the left can be regarded as The first active transistor
  • M 2 on the right can be regarded as the second active transistor.
  • the variable gain amplifier shown in FIG. 15 can be varied by adjusting the bias voltage M 2 M 2 conduct current, thereby changing the gain of the variable gain amplifier; or M is achieved by adjusting the trans-off 2 Injecting and cutting off the current to change the gain of the variable gain amplifier.
  • M1 is also set to be adjustable. Adjusting M1 and M2 at the same time can make the gain of the variable gain amplifier more varied.
  • variable gain amplifier provided in the fourth implementation mode can be regarded as an improvement (adding an inductive adjustment circuit) on the basis of the example (d) in FIG. 2.
  • the active transistor is an N-channel CMOS as an example.
  • the active transistor can also be a P-channel CMOS, or an NPN triode or a PNP triode.
  • the ground port of the active transistor and the port connected to the power supply voltage may be different, and the specific grounding and power connection methods are the same as those in the prior art, and will not be repeated in the embodiments of this application.
  • variable gain amplifier provided by the embodiment of the present application can be divided into two parts: the variable gain amplifier core circuit and the calibration unit, as shown in FIG. 16.
  • the variable gain amplifier core circuit can adopt any active VGA topology in the prior art.
  • the inductive adjustment circuit that is, the RLC network in FIG. 16
  • the inductive load that is, the overall output matching network and L1 in FIG. 16
  • the phase and gain step of the output signal of the VGA are calibrated through the inductive adjustment circuit 304.
  • the inductive adjustment circuit 304 can be applied to other amplifiers with a switching gain function, such as a low-noise amplifier (LNA), in addition to being applied to a VGA.
  • LNA low-noise amplifier
  • Amplifiers with switching gain function also have problems such as inconstant phase and unstable gain step due to frequency changes.
  • the inductive adjustment circuit 304 is provided in this type of amplifier, and the output signal phase and gain step of the amplifier can also be calibrated.
  • the embodiment of the application also provides a phased array transceiver.
  • the phased array transceiver includes a plurality of phased array channels, and each phased array channel includes a low noise amplifier, a phase shifter, and a variable gain amplifier 300 connected in series; wherein, the phase shifter is used for The fixed phase shift of the input signal is realized; the variable gain amplifier 300 is used to realize the variable gain of the input signal and keep the fixed phase shift of the input signal unchanged.
  • the phased array transceiver shown in Figure 17 can be used to transmit and receive beams in a fixed direction.
  • the phase shift will be introduced when the low noise amplifier and the variable gain amplifier switch the gain, and the delay of each device in the phased array channel It will also cause phase errors, causing each phased array channel to be unable to maintain the fixed phase shift achieved by the phase shifter, and ultimately affect the beam direction and gain.
  • the variable gain amplifier 300 provided by the embodiment of the present application, since the variable gain amplifier 300 can calibrate the phase of the output signal, the fixed phase shift of the input signal can be kept unchanged, the beam transmission and reception in a fixed direction can be realized, and the beam can be improved. Accuracy.
  • phased array transceiver provided by the embodiment of the present application, the sequence of the low noise amplifier, phase shifter, and variable gain amplifier 300 is not specifically limited.
  • FIG. 17 shows only one Specific examples.
  • phased array transceiver including four phased array channels may be as shown in FIG. 18.
  • Each phased array channel includes an LNA, a phase shifter (PS), and the VGA provided in any of the foregoing embodiments.
  • PS phase shifter
  • each channel needs to be switched to a fixed phase shift, such as ⁇ 1, ⁇ 2, ⁇ 3, and ⁇ 4.
  • the phase shift is realized by PS, and the accuracy of the phase shift affects The beam accuracy and gain of the phased array transceiver.
  • LNA and VGA will introduce phase shift when switching gains, and the delay of LNA and VGA will also cause phase shift.
  • the VGA provided by the embodiment of this application can realize variable gain while switching gain between LNA and VGA.
  • the phase shift introduced at the time is calibrated, so the fixed phase shift of each phased array channel can be kept unchanged, thereby improving the beam accuracy.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

一种可变增益放大器及相控阵收发机，用以使得可变增益放大器切换增益时可以保持相位恒定，且增益步进随频率稳定。可变增益放大器包括：放大电路，用于放大输入信号；控制电路，用于通过调节放大电路的输出电流，控制放大电路的增益；感性负载和感性调节电路，感性负载与放大电路的信号输出端相耦合，感性调节电路与感性负载互感耦合，感性调节电路可调。

Description

一种可变增益放大器及相控阵收发机 技术领域
本申请涉及电路技术领域，尤其涉及一种可变增益放大器及相控阵收发机。
背景技术
可变增益放大器(variable gain amplifier，VGA)是一种常见的电路器件，可用于对信号进行放大，且放大倍数可调。VGA广泛应用于声波、雷达、全球定位系统(global positioning system，GPS)接收机等多种设备中。
随着第五代移动通信(5G)技术的发展，相控阵技术已逐步成为5G通信发展的方向。对于射频链路来说，当某一级电路的输入信号较强时，则需降低该模块前级或其自身的增益以避免输出饱和。而系统中改变增益则需要用到VGA。与传统低频电路相比，相控阵中的VGA有其特殊要求：首先，在相控阵系统中，VGA改变增益时，需要保证输出信号的相位恒定，以避免在切换增益时改变了天线的收发角度；其次，针对毫米波频段的大带宽场景，对于同一带宽内的信号，需保证不同频率下的信号具有相同的增益步进。
实际应用中，VGA可以通过有源电路实现。示例性地，图1示出了一种通过共源共栅结构实现VGA的电路拓扑。其中，M 2管可以称为共栅管；M 3管可以称为共源管。M 2和M 3组成的电路结构也可以称为Cascode结构(共源共栅结构)。在图1中，M 1管也可以看做是共栅管，主要起分流作用，M 1管的源极耦合到M 3的漏极。当M 1管关断时，交流电流全部流入Z L，VGA的增益较大，其中Z L可以视为输出匹配网络以及下一级电路的等效阻抗；当M 1管导通时，交流电流被M 1管分流，流入Z L的电流减小，VGA的增益减小。
但是，图1所示的VGA存在如下问题：首先，在切换共栅管时，M 1管直接将交流电流导入到交流地(电源电压)，但对于不同频率的信号，导入交流电流的比例不同，因此图1所示的VGA对不同频率信号的增益步进不同。其次，M 1管在导通和关断时，输出匹配网络的负载电容不同，VGA在不同增益下的输出相位不恒定。
此外，对于其他有源VGA，也存在着如图1所示VGA存在的相位不恒定、随频率变化导致增益步进不稳定等问题。因此，急需一种可变增益放大器，使得可变增益放大器切换增益时可以保持相位恒定，且增益步进随频率稳定。
发明内容
本申请实施例提供了一种可变增益放大器及相控阵收发机，使得可变增益放大器在切换增益时可以保持相位恒定，且增益步进随频率稳定。
第一方面，本申请实施例提供一种可变增益放大器，该可变增益放大器包括：放大电路，用于放大输入信号；控制电路，用于通过调节放大电路的输出电流，控制放大电路的增益；感性负载和感性调节电路，感性负载与放大电路的信号输出端相耦合，感性调节电路与感性负载互感耦合。
此外，可变增益放大器可通过感性负载耦合至下一级电路。
采用上述方案，可通过放大电路实现放大功能，通过控制电路实现增益可变。此外，还可通过与感性负载互感耦合的感性调节电路，实现对可变增益放大器的输出信号相位和 增益步进的校准。
其中，感性调节电路可以包括电感。可选地，该电感可以是可调电感。
采用上述方案，可以通过可调电感对可变增益放大器的输出信号的相位以及增益步进进行不同程度的调节，从而提高校准的精确度，使得校准效果更好。
在一种可能的设计中，感性调节电路还可包括与可调电感并联的可调电阻。
在一种可能的设计中，感性调节电路还可包括与可调电感并联的可变电容。
采用上述方案，除了通过电感和感性负载的互感对可变增益放大器进行校准外，还可通过切换可调电阻的阻值以及可变电容的容值对可变增益放大器进行校准，从而对可变增益放大器的任意增益状态进行控制，使得校准效果更好。
在一种可能的设计中，放大电路可以包括第一有源晶体管，第一有源晶体管的源极耦合接地，第一有源晶体管的漏极为放大电路的信号输出端，第一有源晶体管的栅极用于输入输入信号。
采用上述方案，可以通过一个有源晶体管实现可变增益放大器的放大功能。
进一步地，控制电路用于调节第一有源晶体管的栅极的偏置电压。
采用上述方案，当第一有源晶体管的栅极的偏置电压改变时，会改变第一有源晶体管的跨导，从而改变第一有源晶体管的导通电流，改变放大电路的增益。
进一步地，放大电路还包括：第二有源晶体管，第二有源晶体管和第一有源晶体管构成差分放大电路；控制电路包括：第三有源晶体管和第四有源晶体管；其中，第三有源晶体管的源极耦合接地，第三有源晶体管的漏极与第二有源晶体管的漏极耦合；第四有源晶体管的源极耦合接地，第四有源晶体管的漏极与第一有源晶体管的漏极耦合；第三有源晶体管的栅极和第四有源晶体管的栅极均用于接收控制电压以控制通断，或者第三有源晶体管和第四有源晶体管的栅极的偏置电压可调。
采用上述方案，可以通过第一有源晶体管和第二有源晶体管实现对差分输入信号的放大；通过第三有源晶体管和第四有源晶体管分别向第二有源晶体管和第一有源晶体管注入反向电流，来实现可变增益放大器的增益可调。
在一种可能的设计中，放大电路包括：第一共源共栅放大器；第一共源共栅放大器中的第一共栅管的漏极为放大电路的信号输出端，第一共源共栅放大器中的第一共源管的栅极用于输入输入信号，第一共源管的源极耦合接地。
采用上述方案，可以通过第一共源共栅放大器实现可变增益放大器的放大功能。
进一步地，控制电路包括：第一有源晶体管；第一有源晶体管的源极与第一共栅管的源极连接；第一有源晶体管的漏极耦合至第一电源电压，或者，第一有源晶体管的漏极与感性调节电路的一端耦合、感性调节电路的另一端耦合至第二电源电压；第一有源晶体管的栅极用于接收控制电压以控制第一有源晶体管的通断，或者第一有源晶体管的栅极的偏置电压可调。
采用上述方案，第一有源晶体管可以对第一共源共栅放大器的电流进行分流，从而实现可变增益放大器的增益可变。
在一种可能的设计中，控制电路用于调节第一共源管的偏置电压。
采用上述方案，当第一共源管的栅极的偏置电压改变时，会改变第一共源管的导通电流，从而改变放大电路的增益。
在一种可能的设计中，放大电路还包括：第二共源共栅放大器；第二共源共栅放大器 与第一共源共栅放大器构成差分放大电路；第二共源共栅放大器包括第二共栅管和第二共源管；控制电路包括：第一有源晶体管和第二有源晶体管；第一有源晶体管的源极耦合接地，第一有源晶体管的漏极与第二共源管的漏极耦合；第二有源晶体管的源极耦合接地，第二有源晶体管的漏极与第一共源管的漏极耦合；第一有源晶体管的栅极和第二有源晶体管的栅极均用于接收控制电压以控制通断，或者第一有源晶体管和第二有源晶体管的栅极的偏置电压可调。
采用上述方案，可以通过第一共源共栅放大器和第二共源共栅放大器实现对差分输入信号的放大；通过第一有源晶体管和第二有源晶体管分别向第二共源共栅放大器和第一共源共栅放大器注入反向电流，来实现可变增益放大器的增益可调。
在一种可能的设计中，放大电路还包括：第二共源共栅放大器；第二共源共栅放大器与第一共源共栅放大器构成差分放大电路；第二共源共栅放大器包括第二共栅管和第二共源管；控制电路包括：第一有源晶体管和第二有源晶体管；第一有源晶体管的源极与第一共栅管的源极耦合，第一有源晶体管的漏极与第二共栅管的漏极耦合；第二有源晶体管的源极与第二共栅管的源极耦合，第二有源晶体管的漏极与第一共栅管的漏极耦合；第一有源晶体管的栅极和第二有源晶体管的栅极均用于接收控制电压以控制通断，或者第一有源晶体管和第二有源晶体管的栅极的偏置电压可调。
采用上述方案，可以通过第一共源共栅放大器和第二共源共栅放大器实现对差分输入信号的放大；通过第一有源晶体管和第二有源晶体管分别向第二共源共栅放大器和第一共源共栅放大器注入反向电流，来实现可变增益放大器的增益可调。
第二方面，本申请实施例提供一种相控阵收发机，相控阵收发机包括多个相控阵通道，每个相控阵通道中包括串联的低噪声放大器、移相器以及上述第一方面或第一方面中任一可能的设计中提供的可变增益放大器；其中，移相器用于实现输入信号的固定相移；可变增益放大器用于实现输入信号的可变增益、且保持输入信号的固定相移不变。
采用上述相控阵收发机，可以实现固定方向上的波束收发。在相控阵收发机中采用第一方面或第一方面中任一可能的设计中提供的可变增益放大器，由于该可变增益放大器可以对输出信号相位进行校准，因而可保持输入信号的固定相移不变，实现固定方向上的波束收发，提高波束精度。
附图说明
图1为现有技术提供的一种可变增益放大器的结构示意图；
图2为现有技术提供的有源VGA的结构示意图；
图3为本申请实施例提供的第一种可变增益放大器的结构示意图；
图4为本申请实施例提供的第二种可变增益放大器的结构示意图；
图5为本申请实施例提供的第三种可变增益放大器的结构示意图；
图6为本申请实施例提供的第四种可变增益放大器的结构示意图；
图7为本申请实施例提供的第五种可变增益放大器的结构示意图；
图8为本申请实施例提供的第六种可变增益放大器的结构示意图；
图9为本申请实施例提供的第七种可变增益放大器的结构示意图；
图10为本申请实施例提供的第八种可变增益放大器的结构示意图；
图11为本申请实施例提供的第九种可变增益放大器的结构示意图；
图12为本申请实施例提供的第十种可变增益放大器的结构示意图；
图13为本申请实施例提供的第十一种可变增益放大器的结构示意图；
图14为本申请实施例提供的第十二种可变增益放大器的结构示意图；
图15为本申请实施例提供的第十三种可变增益放大器的结构示意图；
图16为本申请实施例提供的第十四种可变增益放大器的结构示意图；
图17为本申请实施例提供的一种相控阵收发机的结构示意图；
图18为本申请实施例提供的另一种相控阵收发机的结构示意图。
具体实施方式
如背景技术中所述，现有的有源VGA在切换增益时存在相位不恒定、随频率变化导致增益步进不稳定等问题。以图1所示的共源共栅结构有源VGA为例，在高增益模式下，交流电流I全部通过共栅管M 2流入Z L，其中，Z L可以视为输出匹配网络以及下一级电路的等效阻抗；在低增益模式下，M 1管对交流电流进行分流，VGA的增益减小。由于在切换增益时，M 1管有导通和关断两种状态，而M 1管在导通和关断时会改变输出匹配网络的负载电容，因而在低增益模式和高增益模式下输出匹配网络的负载电容不同，因而在切换增益时有源VGA会出现相位不恒定的现象。
此外，在低增益模式下，M 1管将交流电流导入交流地(电源电压)，但是，对于不同频率的信号，M 1管导入交流电流的比例不同，因此，图1所示的VGA对不同频率信号的增益步进不同。
基于此，本申请实施例提供了一种可变增益放大器及相控阵收发机，使得可变增益放大器切换增益时可以保持相位恒定，且增益步进随频率稳定。
需要说明的是，本申请实施例中，多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。本申请中所提到的“耦合”，是指电学连接，具体可以包括直接连接或者间接连接两种方式。下面，对本申请实施例的应用场景加以简单介绍。
本申请实施例可以应用于对VGA的相位精度以及增益步进精度要求较高的应用场景中。
示例性地，在5G毫米波频段下，相控阵天线可以由多个收发通道组成，每个收发通道包括低噪声放大器(low noise amplifier，LNA)、移相器(PS)和VGA。为了实现固定方向波束的收发，每个接收通道需要切换到固定的相移。例如，四个接收通道的相移分别是φ1、φ2、φ3、φ4，该相移由PS实现。
但是，每个收发通道的VGA在切换增益时会引入相移。此外，对于5G毫米波频段，由于射频信号的频率较高(例如可以是新无线(New Radio,NR)频段所在的28GHz频段或者38GHz频段)，收发通道上的LNA、VGA等放大器模块的时延也会引起较大的相位波动。收发通道的相移不固定，最终影响波束的方向和增益。其次，针对毫米波频段的大带宽场景，对于同一带宽内不同频率的信号，由于VGA切换增益时对地导入交流电流的比例不同，因而收发通道难以保证不同频率的信号具有相同的增益步进。
因此，在5G毫米波频段下，相控阵天线对相位精度以及增益步进精度要求较高，采用传统的有源VGA难以满足相控阵天线的使用需求。
示例性地，在车载毫米波雷达系统中，车载雷达的发射信号和接收信号为毫米波，因而对相位精度(等价于延时)的要求很高，VGA在切换增益需保证相位恒定，采用传统的有源VGA难以满足其使用需求。
综上，针对5G毫米波频段下的相控阵天线以及车载毫米波雷达等对相位精度以及增益步进精度要求较高的应用场景中，可以采用本申请实施例提供的VGA，使得VGA切换增益时可以保持相位恒定，且增益步进随频率稳定。
参见图2，为四种现有有源VGA的结构示意图。其中，示例(a)(与图1所示的VGA工作原理相同)采用了切换共栅管的方式，当M 1管打开时，交流电流被M 1管分流，以实现增益切换；示例(b)采用了切换共源管的偏置的方法，当偏置电压Vbias改变时，M 1管的跨导也随之改变，以实现可变增益；示例(c)采用了M 1管注入反向交流电流的方式，以减小最终流向输出的交流电流(M 1管的通断可配置或者栅极偏置电压可调)，实现增益切换的功能；示例(d)和示例(c)类似，采用了共栅管M 1来进行反向电流的控制。
需要说明的是，在图2的示例中，均以差分结构为例进行示意。实际应用中，有源VGA还可采用单端结构。此外，在图2的示例中，有源晶体管采用互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺，实际应用中，有源晶体管也可以采用其他工艺，例如双极结型晶体管(bipolar junction transistor，BJT)工艺，本申请实施例中对有源晶体管的具体类型和工艺不做限定。
下面将结合附图对本申请实施例作进一步地详细描述。
参见图3，为本申请实施例提供的一种可变增益放大器300的结构示意图。可变增益放大器300包括：
放大电路301，用于放大输入信号。
控制电路302，用于通过调节放大电路301的输出电流，控制放大电路301的增益。
感性负载303和感性调节电路304，感性负载303与放大电路301的信号输出端相耦合，感性调节电路304与感性负载303互感耦合(也叫磁耦合)，感性调节电路304可调。
需要说明的是，本申请实施例中，放大电路301可以用于放大输入信号，即实现输入信号的固定增益；控制电路302可以对放大电路301的增益进行调节。放大电路301、控制电路302和感性负载303可以视为现有技术中的有源VGA。本申请实施例在现有有源VGA的基础上增加感性调节电路304，使得可变增益放大器300的输出信号的相位与输入信号的相位一致，并且在输入信号的频率不同的情况下，保持可变增益放大器300的增益步进相同(即校准可变增益放大器300的输出信号相位和增益步进)。
本实施例中，示例性的，当放大电路301为Cascode放大器时，其中共栅管的漏极是放大电路301的信号输出端；当放大电路301为晶体管时，晶体管的漏极为放大电路301的信号输出端，具体可以参考现有技术，此处不一一举例说明。
其中，感性负载303耦合于放大电路301的信号输出端以及可变增益放大器300的输出端之间，其中，放大电路301通过感性负载303耦合到下一级电路，具体的，下一级电路是连接可变增益放大器300到输出端的。示例性地，感性负载303可以为输出匹配网络，或者巴伦(balun)等器件。此外，可变增益放大器300可通过感性负载303耦合至下一级电路。
其中，感性调节电路304可以视为独立于感性负载303的器件。具体地，感性调节电路304可以独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。或者，感性调节电路304可以串接于控制电路302中。
本申请实施例中，通过感性负载303和感性调节电路304互感，可以校准可变增益放大器300的输出信号相位和增益步进。
具体实现时，感性调节电路304可以包括电感。需要说明的是，当感性负载303为巴伦时，感性负载303中通常会包括初级线圈以及与该初级线圈互感耦合的次级线圈，初级线圈耦合至放大电路301的信号输出端，次级线圈则耦合至下一级电路，而本申请中感性调节电路304，则是一个独立于感性负载303之外的一个电感，该电感同样与初级线圈互感耦合，但是不同于次级线圈。其它类型的输出匹配网络与此类似，不再赘述。该电感可以是可调电感。若感性调节电路304中的电感是可调电感，则可以通过感性调节电路304对可变增益放大器300的输出信号的相位以及增益步进进行不同程度的调节，从而提高校准的精确度，使得校准效果更好。
在一种可能的设计中，感性调节电路304中还可以包括与该可调电感并联的可调电阻。
在一种可能的设计中，感性调节电路304中还可以包括与该可调电感并联的可变电容。
在上述实现方式中，除了通过电感和感性负载303的互感耦合对可变增益放大器300进行校准外，还可通过切换可调电阻的阻值以及可变电容的容值对可变增益放大器300进行校准，从而对可变增益放大器300的任意增益状态进行控制，使得感性调节电路304的校准效果更好。
如前所述，本申请实施例中，感性调节电路304可以独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧，也可以设置在控制电路302中。以感性调节电路304串接在控制电路302中为例，本申请实施例中提供的可变增益放大器300的一种具体示例可以如图4所示。
图4示出了一种单端结构的可变增益放大器。其中，M 1和M 3组成放大电路301；L1和R L可视为感性负载，与M 1的输出端连接；L2可以视为感性调节电路；M 2可视为控制电路302。当M 2关断时，L2类似于开路，其对主放大路径M 1+L1无影响，可变增益放大器实现高增益；当M 2闭合时，M 2对输入可变增益放大器的电流进行分流，分流的交流电流通过L2和L1之间的互感影响输出，实现可变增益放大器的低增益的同时对输出信号进行校准。
基于L1和L2的互感，图4中还示出了上述可变增益放大器的等效结构。其中，L1和L2的直接耦合被等效为电感M。那么，在低增益模式下，校准前后的输出分别为：
Figure PCTCN2019080704-appb-000001
Figure PCTCN2019080704-appb-000002
通过上式可以看出，校准前后的输出差别主要为sM*I，其中sM为电感M的频域阻抗。由于校准后的输出信号中包含sM项，而sM项可以在低增益模式下对输出信号的相位产生影响，因而可用于对可变增益放大器的输出信号相位进行校准。此外，sM是一个和频率相关的阻抗，因而可以用于校准不同频率下的增益步进，使得可变增益放大器的增益步 进随频率稳定。
此外，对于本申请实施例中提供的其他结构的可变增益放大器，均可通过感性负载303和感性调节电路304的互感来实现输出信号相位和增益步进的校准，其校准原理与上述举例类似，本申请实施例中不再赘述。
本申请实施例中，放大电路301用于放大输入信号，具体实现时，放大电路301可以采用单端结构，也可以采用差分结构。此外，放大电路301中具有基本放大功能的结构可以由一个有源晶体管组成，也可以由共源共栅(Cascode)放大器组成；其中，每个共源共栅放大器中包括一个共栅管和一个共源管。
本申请实施例提供的可变增益放大器适用于各种结构，下面对于可变增益放大器的各种结构进行介绍。
需要说明的是，在以下示例中，均以有源晶体管采用CMOS工艺为例进行示意。实际应用中，有源晶体管还可以采用其他工艺。当有源晶体管采用其他工艺时，有源晶体管的各个端口的名称会有所不同，但功能基本一致。示例性地，有源晶体管为BJT时，BJT中的基极相当于CMOS中的栅极；BJT中的集电极相当于CMOS中的漏极；BJT中的发射极相当于CMOS中的源极。因此，本申请中基于MOS管实现的可变增益放大器，可以与基于BJT实现的可变增益放大器等同。
由于有源晶体管采用其他工艺时的实现方式与原理与采用CMOS工艺时类似，因此本申请实施例中均以有源晶体管采用CMOS工艺为例进行示意，不再对采用其他工艺时的具体实现方式做详细介绍。
下面将分别介绍放大电路301中具有基本放大功能的结构由一个有源晶体管组成以及由共源共栅放大器组成时，可变增益放大器300的一些具体实现方式。
一、放大电路301中具有基本放大功能的结构由一个有源晶体管组成
具体实现时，放大电路301可以包括第一有源晶体管，第一有源晶体管的源极耦合接地，第一有源晶体管的漏极为放大电路301的信号输出端，第一有源晶体管的栅极用于输入输入信号。
其中，第一有源晶体管的源极耦合接地，其含义可以是：第一有源晶体管直接接地，或者第一有源晶体管通过电感、电容等器件接地。此外，在本申请实施例的其他示例中，耦合接地的含义相同，后续将不再详细解释。
在上述实现方式中，可以通过第一有源晶体管实现放大电路301对输入信号的放大功能。控制电路302在调节放大电路301的增益时，可以根据可变增益放大器的不同结构以及不同的需求选择不同的实现方式。
需要说明的是，在本申请实施例的示例中，有源晶体管采用栅极输入信号、源极耦合接地的方式，实际应用中，有源晶体管也可以采用源极输入信号、栅极耦合接地的方式，本申请实施例对此不做具体限定。
实现方式一
控制电路302在调节放大电路301的增益时，可用于调节第一有源晶体管的栅极的偏置电压。当第一有源晶体管的栅极的偏置电压改变时，会改变第一有源晶体管的跨导，从而改变第一有源晶体管的导通电流，改变放大电路301的增益。
在实现方式一中，感性调节电路304独立于放大电路301和控制电路302单独设置。 即，感性调节电路304独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。
示例性地，上述可变增益放大器的一种可能的实现方式可以如图5所示。在图5中，L1可视为感性负载，并联的L2、R和C可视为感性调节电路，M 1可以视为第一有源晶体管。在图5所示的可变增益放大器中，可通过调节偏置电压Vbias来改变M 1的导通电流，进而改变可变增益放大器的增益。
此外，在对可变增益放大器的输出信号相位和增益步进进行校准时，可通过改变与L1互感的感性调节电路中L2的电感值、R的电阻值以及C的电容值中的一个或多个来实现。
实现方式二
在实现方式二中，除了第一有源晶体管之外，放大电路301中还包括第二有源晶体管，第二有源晶体管和第一有源晶体管构成差分放大电路301；控制电路302包括：第三有源晶体管和第四有源晶体管。
其中，第三有源晶体管的源极耦合接地，第三有源晶体管的漏极与第二有源晶体管的漏极耦合；第四有源晶体管的源极耦合接地，第四有源晶体管的漏极与第一有源晶体管的漏极耦合，第三有源晶体管的栅极和第四有源晶体管的栅极均用于接收控制电压以控制通断，或者第三有源晶体管和第四有源晶体管的栅极的偏置电压可调。
也就是说，第三有源晶体管和第四有源晶体管受同一控制电压控制，第三有源晶体管和第四有源晶体管可以同时导通或者同时关断；或者，第三有源晶体管和第四有源晶体管的栅极施加的偏置电压相同，第三有源晶体管和第四有源晶体管的跨导相同，使得两个差分分量的放大倍数相同。
在上述实现方式中，可以通过第一有源晶体管和第二有源晶体管实现放大电路301对差分输入信号的放大功能。第三有源晶体管用于向第二有源晶体管注入反向电流，第四有源晶体管用于向第一有源晶体管注入反向电流；当注入反向电流时，可变增益放大器的输出电流减小，增益减小。控制电路302在调节放大电路301的增益时，可通过控制电压来控制第三有源晶体管和第四有源晶体管的通断，从而实现可变增益放大器的高低增益切换。或者，可通过调节第三有源晶体管和第四有源晶体管的偏置电压来改变第三有源晶体管和第四有源晶体管的导通电流，从而改变注入的反向电流的大小，进而改变可变增益放大器的增益。
在实现方式二中，感性调节电路304独立于放大电路301和控制电路302单独设置。即，感性调节电路304独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。通过与感性负载303互感耦合的感性调节电路304，可实现对可变增益放大器的输出信号相位和增益步进的校准。
示例性地，上述可变增益放大器的一种可能的实现方式可以如图6所示。在图6中，L1和输出匹配网络的集合可视为感性负载，在本申请实施例的附图中，将L1从输出匹配网络中独立出来是为了表示感性负载中的电感L1与感性调节电路互感耦合。实际实现时，电感L1可以视为输出匹配网络中的一部分。并联的可调电阻R、可变电容C和L2可视为感性调节电路，左边的M 1可以视为第一有源晶体管，右边的M 1可以视为第二有源晶体管；左边的M 2可以视为第三有源晶体管，右边的M 2可以视为第四有源晶体管。在图6所示的可变增益放大器中，可通过调节M 2的偏置电压Vbias来改变M 2的导通电流，进而改变增益；也可通过调节M 2的通断来实现反向电流的注入与切断，进而改变增益。
此外，在对可变增益放大器的输出信号相位和增益步进进行校准时，可通过改变与L1互感的RLC网络中L2的电感值、R的电阻值以及C的电容值中的一个或多个来实现。
需要说明的是，实际应用中，差分结构的可变增益放大器中，放大一个差分分量的功能可以由多个并联的有源晶体管实现。相应地，可变增益放大器中还应包含与多个有源晶体管一一对应的多个控制电路。在这种情况下，M 1也可以设置成通断可调或偏置电压可调的有源晶体管，从而使得可变增益放大器的增益变化更多样。因此，在图6的示意中，也将M 1设置成可调。同时调节M 1和M 2，可以使得可变增益放大器的增益变化更多样。
二、放大电路301中具有基本放大功能的结构由共源共栅放大器组成
具体实现时，放大电路301可以包括：第一共源共栅放大器；第一共源共栅放大器中的第一共栅管的漏极为放大电路301的信号输出端，第一共源共栅放大器中的第一共源管的栅极用于输入输入信号，第一共源管的源极耦合接地。
具体地，在第一共源共栅放大器中，第一共栅管和第一共源管的连接关系可以是：第一共栅管的漏极为放大电路301的信号输出端，第一共栅管的栅极用于输入偏置电压，第一共栅管的源极与第一共源管的漏极耦合；第一共源管的栅极用于输入输入信号，第一共源管的源极耦合接地。
在上述实现方式中，可以通过第一共源共栅放大器实现放大电路301对输入信号的放大功能。控制电路302在调节放大电路301的增益时，可以根据可变增益放大器的不同结构以及不同的需求选择不同的实现方式。
实现方式一
在实现方式一中，控制电路302包括：第一有源晶体管。其中，第一有源晶体管的源极与第一共栅管的源极连接；第一有源晶体管的漏极耦合至第一电源电压，或者，第一有源晶体管的漏极与感性调节电路304的一端耦合、感性调节电路304的另一端耦合至第二电源电压；第一有源晶体管的栅极用于接收控制电压以控制第一有源晶体管的通断，或者第一有源晶体管的栅极的偏置电压可调。
其中，提供第一电源电压和第二电源电压的电源可以是同一电源，也可以是具有相同规格的两个电源。
在实现方式一中，第一有源晶体管用于对第一共源共栅放大器的电流进行分流，从而改变第一共源共栅放大器的输出电流，进而改变可变增益放大器的增益。此外，通过感性负载303和感性调节电路304的互感，可以对可变增益放大器的输出信号相位和增益步进进行校准。
不难看出，在实现方式一中，若第一有源晶体管的漏极与感性调节电路304的一端耦合、感性调节电路304的另一端耦合至第二电源电压，则感性调节电路304串接在控制电路302中；若第一有源晶体管的漏极耦合至第一电源电压，则感性调节电路304独立于放大电路301和控制电路302单独设置，感性调节电路304设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。
示例性地，若第一有源晶体管的漏极与感性调节电路304一端耦合、感性调节电路304的另一端耦合至第二电源电压，则可变增益放大器的一种可能的结构可以如图7所示(图7中以提供第一电源电压和提供第一电源电压的电源为同一电源为例进行示意)。图7中，M 1可视为第一共栅管，M 3可视为第一共源管，M 2可视为第一有源晶体管，L1和输出匹配网络的集合可以视为感性负载，L2可以视为感性调节电路。M 2的漏极通过L2与电源电 压连接。其中，M 2的栅极用于接收控制电压以控制M 2的通断，或者M 2的栅极的偏置电压可调，从而实现增益可调。L2与L1互感，从而对可变增益放大器的输出信号相位和增益步进进行校准。
在图7所示的可变增益放大器中，M 2关断时，L2类似于开路，电感在M 2分流支路中不起作用，其电感值可以视为无穷大；M 2闭合时，M 2所在支路可以视为分流支路，分流的交流电流通过L2和L1之间的互感影响输出，此时L2的电感值不再是无穷大。因此可以看出，在M 2(相当于控制电路302)的控制下，可以实现电感L2(相当于感性调节电路304)的电感值可调。也就是说，本申请实施例中，感性调节电路304是可调的。此外，图7所示的可变增益放大器中，感性调节电路还可包括分别与L2并联的可调电阻R和可变电容C，如图8所示。采用图8所示的方案，可以对可变增益放大器的任意增益状态进行控制，校准效果更好。
示例性地，若第一有源晶体管的漏极耦合至第一电源电压，则可变增益放大器的一种可能的结构可以如图9所示。图9中，M 1可视为第一共栅管，M 3可视为第一共源管，M 2可视为第一有源晶体管，L1和输出匹配网络的集合可以视为感性负载，并联的L2、R和C可以视为感性调节电路。M 2的漏极与电源电压连接。包括L2的RLC网络独立于控制电路设置。其中，M 2的栅极用于接收控制电压以控制M 2的通断，或者M 2的栅极的偏置电压可调，从而实现增益可调。RLC网络与L1互感，从而对可变增益放大器的输出信号相位和增益步进进行校准。
此外，在实现方式一中，可变增益放大器还可采用差分结构。
示例性地，采用差分结构的可变增益放大器可以如图10所示。其中，M 1可以视为第一共栅管，M 3可视为第一共源管，M 2可视为第一有源晶体管，L1和输出匹配网络的集合可视为感性负载，L2可视为感性调节电路。通过M 2分流或者通过调节M 2的偏置电压，可以实现增益可变；通过L1与L2互感，可以对可变增益放大器的输出信号相位以及增益步进进行校准。
此外，感性调节电路中还可包括分别与L2并联的可调电阻R和可变电容C，如图11所示。感性调节电路还可以独立于控制电路设置，如图12所示。
需要说明的是，实际应用中，差分结构的可变增益放大器中，放大一个差分分量的功能可以由多个并联的共栅共源放大器实现，每个共栅共源放大器均包含M 1和M 3。相应地，可变增益放大器还应包含与多个共栅共源放大器一一对应的多个控制电路(即多个M 2)。在这种情况下，M 1也可以设置成通断可调或偏置电压可调的有源晶体管，从而使得可变增益放大器的增益变化更多样。因此，在图11～图12的示意中，也将M 1设置成可调。同时调节M 1和M 2，可以使得可变增益放大器的增益变化更多样。
不难看出，实现方式一中提供的可变增益放大器，可以视为在图2的示例(a)的基础上改进(增加感性调节电路)得到。
实现方式二
在实现方式二中，控制电路302用于调节第一共源管的偏置电压。当第一共源管的栅极的偏置电压改变时，会改变第一共源管的导通电流，从而改变放大电路301的增益。
在实现方式二中，感性调节电路304可独立于放大电路301和控制电路302单独设置。即，感性调节电路304独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。通过与感性负载303互感耦合的感性调节电路304可实现对可变增益放大器的 输出信号相位和增益步进的校准。
示例性地，上述可变增益放大器的一种可能的实现方式可以如图13所示。
在图13中，L1可视为感性负载，并联的可调电感L2、可调电阻R和可变电容C可视为感性调节电路，M 1可视为第一共栅管，M 2可视为第一共源管。在图13所示的可变增益放大器中，可通过调节偏置电压Vbias来改变M 2的导通电流，进而改变可变增益放大器的增益。
此外，在对可变增益放大器的输出信号相位和增益步进进行校准时，可通过改变与L1互感的RLC网络中L2的电感值、R的电阻值以及C的电容值中的一个或多个来实现。
需要说明的是，在图13的示例中，是以可变增益放大器采用单端结构为例进行示意。具体实现时，可变增益放大器也可以采用差分结构，通过改变差分结构中的两个共源管的偏置电压来实现增益调节，并通过与两个感性负载分别互感的两个感性调节电路来对可变增益放大器的输出信号相位和增益步进进行校准，具体实现方式此处不再赘述。
不难看出，实现方式二中提供的可变增益放大器，可以视为在图2的示例(b)的基础上改进(增加感性调节电路)得到。
实现方式三
在实现方式三中，除了第一共源共栅放大器之外，放大电路301还包括第二共源共栅放大器；第二共源共栅放大器与第一共源共栅放大器构成差分放大电路301；第二共源共栅放大器包括第二共栅管和第二共源管。其中，第二共源共栅放大器中第二共栅管和第二共源管的连接关系可以参考第一共源共栅管中第一共栅管和第一共源管的连接关系，此处不再赘述。
控制电路302包括：第一有源晶体管和第二有源晶体管；其中，第一有源晶体管的源极耦合接地，第一有源晶体管的漏极与第二共源管的漏极耦合；第二有源晶体管的源极耦合接地，第二有源晶体管的漏极与第一共源管的漏极耦合，第一有源晶体管的栅极和第二有源晶体管的栅极均用于接收控制电压以控制通断，或者第一有源晶体管和第二有源晶体管的栅极的偏置电压可调。
在实现方式三中，第一有源晶体管和第二有源晶体管受同一控制电压控制，第一有源晶体管和第二有源晶体管同时导通或者同时关断；或者，第一有源晶体管和第二有源晶体管的栅极施加的偏置电压相同，从而使得两个差分分量的放大倍数相同。
在上述实现方式中，可以通过第一共源共栅放大器和第二共源共栅放大器实现放大电路301对差分输入信号的放大功能。第一有源晶体管用于向第二共源共栅放大器注入反向电流，第二有源晶体管用于向第一共源共栅放大器注入反向电流。当注入反向电流时，可变增益放大器的输出电流减小、增益减小。控制电路302在调节放大电路301的增益时，可通过控制电压来控制第一有源晶体管和第二有源晶体管的通断，从而实现可变增益放大器的高低增益切换；或者，可通过调节第一有源晶体管和第二有源晶体管的偏置电压来改变导通电流，从而改变注入的反向电流的大小，进而改变可变增益放大器的增益。
在实现方式三中，感性调节电路304可独立于放大电路301和控制电路302单独设置。即，感性调节电路304独立设置于靠近感性负载303、且远离可变增益放大器300的输出端的一侧。通过与感性负载303互感耦合的感性调节电路304可实现对可变增益放大器的输出信号相位和增益步进的校准。
示例性地，上述可变增益放大器的一种可能的实现方式可以如图14所示。在图14中， L1和输出匹配网络的集合可视为感性负载，并联的可调电感L2、可调电阻R和可变电容C可视为感性调节电路，左边的M 1可以视为第一共源管，右边的M 1可以视为第二共源管；左边的M 3可以视为第一共栅管，右边的M 3可以视为第二共栅管；左边的M 2可以视为第一有源晶体管，右边的M 2可以视为第二有源晶体管。在图14所示的可变增益放大器中，可通过调节M 2的偏置电压来改变M 2的导通电流，进而改变可变增益放大器的增益；或者通过调节M 2的通断来实现反向电流的注入与切断，进而改变可变增益放大器的增益。
在对可变增益放大器的输出信号相位和增益步进进行校准时，可通过改变与L1互感的RLC网络中L2的电感值、R的电阻值以及C的电容值中的一个或多个来实现。
此外，在图14的示意中，也将M1设置成可调。同时调节M1和M2，可以使得可变增益放大器的增益变化更多样。
不难看出，实现方式三中提供的可变增益放大器，可以视为在图2的示例(c)的基础上改进(增加感性调节电路)得到。
实现方式四
在实现方式四中，除了第一共源共栅放大器之外，放大电路301还包括第二共源共栅放大器；第二共源共栅放大器与第一共源共栅放大器构成差分放大电路301；第二共源共栅放大器包括第二共栅管和第二共源管。其中，第二共源共栅放大器中第二共栅管和第二共源管的连接关系可以参考第一共源共栅管中第一共栅管和第一共源管的连接关系，此处不再赘述。
控制电路302包括：第一有源晶体管和第二有源晶体管；其中，第一有源晶体管的源极与第一共栅管的源极耦合，第一有源晶体管的漏极与第二共栅管的漏极耦合；第二有源晶体管的源极与第二共栅管的源极耦合，第二有源晶体管的漏极与第一共栅管的漏极耦合，第一有源晶体管的栅极和第二有源晶体管的栅极用于接收控制电压以控制通断，或者第一有源晶体管和第二有源晶体管的栅极的偏置电压可调。
其中，第一有源晶体管和第二有源晶体管受同一控制电压控制，第一有源晶体管和第二有源晶体管同时导通或者同时关断；或者，第一有源晶体管和第二有源晶体管的栅极施加的偏置电压相同，使得两个差分分量的放大倍数相同。
在上述实现方式中，可以通过第一共源共栅放大器和第二共源共栅放大器实现放大电路301对差分输入信号的放大功能。第一有源晶体管用于向第二共源共栅放大器注入反向电流，第二有源晶体管用于向第一共源共栅放大器注入反向电流。当注入反向电流时，可变增益放大器的输出电流减小、增益减小。控制电路302在调节放大电路301的增益时，可通过控制电压来控制第一有源晶体管和第二有源晶体管的通断，从而实现可变增益放大器的高低增益切换；或者，可通过调节第一有源晶体管和第二有源晶体管的偏置电压来改变导通电流，从而改变注入的反向电流的大小，进而改变可变增益放大器的增益。
在实现方式四中，感性调节电路304可独立于放大电路301和控制电路302单独设置。即，感性调节电路304独立设置于靠近感性负载、且远离可变增益放大器300的输出端的一侧。通过与感性负载303互感耦合的感性调节电路304可实现对可变增益放大器的输出信号相位和增益步进的校准。
示例性地，上述可变增益放大器的一种可能的实现方式可以如图15所示。在图15中，L1和输出匹配网络的集合可视为感性负载，并联的可调电感L2、可调电阻R和可变电容C可视为感性调节电路，左边的M 1可以视为第一共栅管，右边的M 1可以视为第二共栅管； 左边的M 3可以视为第一共源管，右边的M 3可以视为第二共源管；左边的M 2可以视为第一有源晶体管，右边的M 2可以视为第二有源晶体管。在图15所示的可变增益放大器中，可通过调节M 2的偏置电压来改变M 2的导通电流，进而改变可变增益放大器的增益；或者通过调节M 2的通断来实现反向电流的注入与切断，进而改变可变增益放大器的增益。
在对可变增益放大器的输出信号相位和增益步进进行校准时，可通过改变与L1互感的RLC网络中L2的电感值、R的电阻值以及C的电容值中的一个或多个来实现。
此外，在图15的示意中，也将M1设置成可调。同时调节M1和M2，可以使得可变增益放大器的增益变化更多样。
不难看出，实现方式四中提供的可变增益放大器，可以视为在图2的示例(d)的基础上改进(增加感性调节电路)得到。
需要说明的是，在上述几个示例中，均以有源晶体管为N沟道CMOS为例进行示意。实际实现时，有源晶体管还可以是P沟道CMOS，也可以是NPN三级管或者PNP三级管。当有源晶体管采用上述不同实现方式时，有源晶体管的接地端口和接电源电压的端口可能有所不同，接地和接电源的具体方式与现有技术相同，本申请实施例中不再赘述。
通过以上示例不难看出，本申请实施例提供的可变增益放大器可以划分为两个部分：可变增益的放大器核心电路和校准单元，如图16所示。当可变增益放大器采用单端结构时，其实现结构可以参见图16中的(a)示例；当可变增益放大器采用差分结构时，其实现结构可以参见图16中的(b)示例。其中，可变增益的放大器核心电路可以采用现有技术中的任一有源VGA的拓扑结构。本申请实施例中，通过与感性负载(即图16中输出匹配网络和L1的整体)互感耦合的感性调节电路(即图16中的RLC网络)，可以对可变增益放大器的输出信号相位和增益步进进行校准。
同样需要说明的是，本申请实施例提供的VGA中，是通过感性调节电路304对VGA的输出信号相位和增益步进进行校准的。该感性调节电路304除了可应用于VGA中之外，还可应用于其他具有切换增益功能的放大器，例如低噪声放大器(low-noise amplifier，LNA)。具有切换增益功能的放大器同样存在相位不恒定、随频率变化导致增益步进不稳定等问题。在这类放大器中设置感性调节电路304，同样可以对该放大器的输出信号相位和增益步进进行校准。
本申请实施例还提供一种相控阵收发机。如图17所示，该相控阵收发机包括多个相控阵通道，每个相控阵通道中包括串联的低噪声放大器、移相器以及可变增益放大器300；其中，移相器用于实现输入信号的固定相移；可变增益放大器300用于实现输入信号的可变增益、且保持输入信号的固定相移不变。
采用图17所示的相控阵收发机，可以实现固定方向上的波束收发。在相控阵收发机中，若采用现有技术提供的可变增益放大器，由于低噪声放大器和可变增益放大器在切换增益时均会引入相移，且相控阵通道中各器件的时延也会引起相位误差，导致每个相控阵通道无法保持由移相器实现的固定相移，最终影响波束方向和增益。而采用本申请实施例提供的可变增益放大器300，由于可变增益放大器300可以对输出信号相位进行校准，因而可保持输入信号的固定相移不变，实现固定方向上的波束收发，提高波束精度。
需要说明的是，在本申请实施例提供的相控阵收发机中，对低噪声放大器、移相器以 及可变增益放大器300的串联顺序不做具体限定，图17示出的仅为一种具体示例。
示例性地，包含四个相控阵通道的相控阵收发机的结构示意图可以如图18所示。每个相控阵通道内包含LNA、移相器(phase shifter，PS)和前述任一实施例中提供的VGA。在相控阵收发机中，为了收发固定方向的波束，每一个通道需切换到固定的相移，例如分别是φ1、φ2、φ3、φ4，该相移由PS实现，该相移的精度影响了相控阵收发机的波束精度和增益。通常情况下，LNA和VGA在切换增益会引入相移，LNA和VGA的时延也会引起相移，而采用本申请实施例提供的VGA在实现可变增益的同时可以对LNA和VGA切换增益时引入的相移进行校准，因而可以保持每个相控阵通道的固定相移不变，从而提高波束精度。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种可变增益放大器，其特征在于，包括：
    放大电路，用于放大输入信号；
    控制电路，用于通过调节所述放大电路的输出电流，控制所述放大电路的增益；
    感性负载和感性调节电路，所述感性负载与所述放大电路的信号输出端相耦合，所述感性调节电路与所述感性负载互感耦合,所述感性调节电路可调。
  2. 如权利要求1所述的可变增益放大器，其特征在于，所述感性调节电路包括可调电感。
  3. 如权利要求2所述的可变增益放大器，其特征在于，所述感性调节电路还包括与所述可调电感并联的可调电阻。
  4. 如权利要求2或3所述的可变增益放大器，其特征在于，所述感性调节电路还包括与所述可调电感并联的可变电容。
  5. 如权利要求1～4任一项所述的可变增益放大器，其特征在于，所述放大电路包括第一有源晶体管，所述第一有源晶体管的源极耦合接地，所述第一有源晶体管的漏极为所述放大电路的信号输出端，所述第一有源晶体管的栅极用于输入所述输入信号。
  6. 如权利要求5所述的可变增益放大器，其特征在于，所述控制电路用于调节所述第一有源晶体管的栅极的偏置电压。
  7. 如权利要求5所述的可变增益放大器，其特征在于，所述放大电路还包括：第二有源晶体管，所述第二有源晶体管和所述第一有源晶体管构成差分放大电路；
    所述控制电路包括：第三有源晶体管和第四有源晶体管；
    所述第三有源晶体管的源极耦合接地，所述第三有源晶体管的漏极与所述第二有源晶体管的漏极耦合；所述第四有源晶体管的源极耦合接地，所述第四有源晶体管的漏极与所述第一有源晶体管的漏极耦合；所述第三有源晶体管的栅极和所述第四有源晶体管的栅极均用于接收控制电压以控制通断，或者所述第三有源晶体管和所述第四有源晶体管的栅极的偏置电压可调。
  8. 如权利要求1～4任一项所述的可变增益放大器，其特征在于，所述放大电路包括：第一共源共栅放大器；
    所述第一共源共栅放大器中的第一共栅管的漏极为所述放大电路的信号输出端，所述第一共源共栅放大器中的第一共源管的栅极用于输入所述输入信号，所述第一共源管的源极耦合接地。
  9. 如权利要求8所述的可变增益放大器，其特征在于，所述控制电路包括：第一有源晶体管；
    所述第一有源晶体管的源极与所述第一共栅管的源极连接；所述第一有源晶体管的漏极耦合至第一电源电压，或者，所述第一有源晶体管的漏极与所述感性调节电路的一端耦合、所述感性调节电路的另一端耦合至第二电源电压；所述第一有源晶体管的栅极用于接收控制电压以控制所述第一有源晶体管的通断，或者所述第一有源晶体管的栅极的偏置电压可调。
  10. 如权利要求8所述的可变增益放大器，其特征在于，所述控制电路用于调节所述第一共源管的偏置电压。
  11. 如权利要求8所述的可变增益放大器，其特征在于，所述放大电路还包括：第二共源共栅放大器；所述第二共源共栅放大器与所述第一共源共栅放大器构成差分放大电路；所述第二共源共栅放大器包括第二共栅管和第二共源管；
    所述控制电路包括：第一有源晶体管和第二有源晶体管；
    所述第一有源晶体管的源极耦合接地，所述第一有源晶体管的漏极与所述第二共源管的漏极耦合；所述第二有源晶体管的源极耦合接地，所述第二有源晶体管的漏极与所述第一共源管的漏极耦合；所述第一有源晶体管的栅极和所述第二有源晶体管的栅极均用于接收控制电压以控制通断，或者所述第一有源晶体管和所述第二有源晶体管的栅极的偏置电压可调。
  12. 如权利要求8所述的可变增益放大器，其特征在于，所述放大电路还包括：第二共源共栅放大器；所述第二共源共栅放大器与所述第一共源共栅放大器构成差分放大电路；所述第二共源共栅放大器包括第二共栅管和第二共源管；
    所述控制电路包括：第一有源晶体管和第二有源晶体管；
    所述第一有源晶体管的源极与所述第一共栅管的源极耦合，所述第一有源晶体管的漏极与所述第二共栅管的漏极耦合；所述第二有源晶体管的源极与所述第二共栅管的源极耦合，所述第二有源晶体管的漏极与所述第一共栅管的漏极耦合；所述第一有源晶体管的栅极和所述第二有源晶体管的栅极均用于接收控制电压以控制通断，或者所述第一有源晶体管和所述第二有源晶体管的栅极的偏置电压可调。
  13. 如权利要求1～12任一项所述的可变增益放大器，其特征在于，所述可变增益放大器通过所述感性负载耦合至下一级电路。
  14. 一种相控阵收发机，其特征在于，所述相控阵收发机包括多个相控阵通道，每个相控阵通道中包括串联的低噪声放大器、移相器以及如权利要求1～13任一项所述的可变增益放大器；
    所述移相器用于实现输入信号的固定相移；所述可变增益放大器用于实现所述输入信号的可变增益、且保持所述输入信号的固定相移不变。
PCT/CN2019/080704 2019-03-30 2019-03-30 一种可变增益放大器及相控阵收发机 WO2020199065A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201980094109.7A CN113728550A (zh) 2019-03-30 2019-03-30 一种可变增益放大器及相控阵收发机
PCT/CN2019/080704 WO2020199065A1 (zh) 2019-03-30 2019-03-30 一种可变增益放大器及相控阵收发机
EP19922592.1A EP3940953A4 (en) 2019-03-30 2019-03-30 VARIABLE GAIN AMPLIFIER AND PHASE CONTROL NETWORK TRANSCEIVER
US17/490,900 US20220021363A1 (en) 2019-03-30 2021-09-30 Variable Gain Amplifier And Phased Array Transceiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/080704 WO2020199065A1 (zh) 2019-03-30 2019-03-30 一种可变增益放大器及相控阵收发机

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/490,900 Continuation US20220021363A1 (en) 2019-03-30 2021-09-30 Variable Gain Amplifier And Phased Array Transceiver

Publications (1)

Publication Number Publication Date
WO2020199065A1 true WO2020199065A1 (zh) 2020-10-08

Family

ID=72664586

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/080704 WO2020199065A1 (zh) 2019-03-30 2019-03-30 一种可变增益放大器及相控阵收发机

Country Status (4)

Country Link
US (1) US20220021363A1 (zh)
EP (1) EP3940953A4 (zh)
CN (1) CN113728550A (zh)
WO (1) WO2020199065A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114499426A (zh) * 2021-12-29 2022-05-13 电子科技大学 一种基于有源交叉耦合结构的双向可变增益放大器
WO2023043489A1 (en) * 2021-09-20 2023-03-23 Kyocera International Inc. Phased-array antenna precision self-calibration

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3926825A4 (en) * 2019-03-13 2022-02-09 Mitsubishi Electric Corporation AMPLIFIER
US11967935B2 (en) * 2021-04-26 2024-04-23 Psemi Corporation Configurable phase tuned multi-gain LNA architecture
CN114567271B (zh) * 2022-02-22 2023-09-19 锐石创芯(深圳)科技股份有限公司 低噪声放大电路及射频前端模组
CN114759885B (zh) * 2022-06-16 2022-10-25 华南理工大学 超宽带可变增益放大器及无线通信设备、增益调节方法
CN115632616B (zh) * 2022-12-22 2023-04-07 成都嘉纳海威科技有限责任公司 一种可自适应增益控制的低功耗驱放芯片
CN117879517A (zh) * 2024-03-11 2024-04-12 成都通量科技有限公司 一种优化有源移相器线性度波动的可变增益放大器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502164A (zh) * 2001-03-29 2004-06-02 Gct�뵼�幫˾ 用于无线终端的可变增益低噪音放大器
CN101335504A (zh) * 2008-07-10 2008-12-31 北京大学深圳研究生院 用于幅度调制的射频功率放大器及超高频射频识别标签
CN109088604A (zh) * 2018-08-06 2018-12-25 上海华虹宏力半导体制造有限公司 一种可变增益低噪声放大器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670847B1 (en) * 2002-01-18 2003-12-30 Xilinx, Inc. Inductive amplifier with a feed forward boost
US7023272B2 (en) * 2004-04-19 2006-04-04 Texas Instruments Incorporated Multi-band low noise amplifier system
US20090251218A1 (en) * 2008-04-03 2009-10-08 Paulo Oliveira Variable Gain Amplifier
US8238867B1 (en) * 2011-02-28 2012-08-07 Silicon Laboratories Inc Low noise amplifier (LNA) suitable for use in different transmission environments and receiver using such an LNA
US9106185B2 (en) * 2013-03-11 2015-08-11 Qualcomm Incorporated Amplifiers with inductive degeneration and configurable gain and input matching
US9124228B2 (en) * 2013-04-04 2015-09-01 Qualcomm Incorporated Amplifiers with boosted or deboosted source degeneration inductance
US9923712B2 (en) * 2016-08-01 2018-03-20 Movandi Corporation Wireless receiver with axial ratio and cross-polarization calibration
US10256894B2 (en) * 2017-09-11 2019-04-09 Qualcomm Incorporated Hybrid beam former
CN107911092B (zh) * 2017-10-10 2020-11-27 天津大学 一种宽带高线性度的射频发射前端电路
CN108768312B (zh) * 2018-07-23 2024-02-20 上海亮牛半导体科技有限公司 利用可调电感和改善功率放大器线性度的电路结构及方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1502164A (zh) * 2001-03-29 2004-06-02 Gct�뵼�幫˾ 用于无线终端的可变增益低噪音放大器
CN101335504A (zh) * 2008-07-10 2008-12-31 北京大学深圳研究生院 用于幅度调制的射频功率放大器及超高频射频识别标签
CN109088604A (zh) * 2018-08-06 2018-12-25 上海华虹宏力半导体制造有限公司 一种可变增益低噪声放大器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3940953A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023043489A1 (en) * 2021-09-20 2023-03-23 Kyocera International Inc. Phased-array antenna precision self-calibration
CN114499426A (zh) * 2021-12-29 2022-05-13 电子科技大学 一种基于有源交叉耦合结构的双向可变增益放大器

Also Published As

Publication number Publication date
EP3940953A4 (en) 2022-03-09
CN113728550A (zh) 2021-11-30
EP3940953A1 (en) 2022-01-19
US20220021363A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
WO2020199065A1 (zh) 一种可变增益放大器及相控阵收发机
CN110212887B (zh) 一种射频有源移相器结构
US6888411B2 (en) Radio frequency variable gain amplifier with linearity insensitive to gain
US8482364B2 (en) Differential cross-coupled power combiner or divider
CN112332806B (zh) 一种高增益低噪声射频移相器
CN110784179B (zh) 一种双平衡fet混频器
CN107017847B (zh) 减少损失的单端混频器
US20210328565A1 (en) Variable-gain amplifier and phased array system
CN112543002B (zh) 宽带差分Doherty功率放大器及其设计方法和应用
KR102133926B1 (ko) 낮은 위상 변화를 갖는 광대역 가변 이득 증폭기
US20220006437A1 (en) Power amplifying circuit
US9602066B2 (en) Polarity-switching amplifier circuit
US7728673B2 (en) Wideband active balun using darlington pair
CN111277232B (zh) 一种基于改进型tia的超宽带放大器单元电路
CN112039449B (zh) 一种超高频可变增益放大器结构
JP2020167503A (ja) 分布型回路
US20070018727A1 (en) Variable gain amplifier and wireless communication apparatus including the same
CN114731139A (zh) 一种射频接收机
CN111800099A (zh) 适用于毫米波信号分流和组合的放大器
US8275342B2 (en) Downconversion mixer
US20220416742A1 (en) Distributed Circuit
KR101605975B1 (ko) 2단계 위상 시프터를 구비한 rf 빔포밍 시스템 장치 및 방법
US9899966B2 (en) Wideband high dynamic range low noise amplifier
US20210359654A1 (en) Drive amplifier
CN113630097B (zh) 一种差模信号相合与共模信号相消的晶体管放大器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19922592

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019922592

Country of ref document: EP

Effective date: 20211012