WO2020192340A1 - Registre à décalage, circuit d'attaque de grille et procédé d'attaque associé et dispositif d'affichage - Google Patents

Registre à décalage, circuit d'attaque de grille et procédé d'attaque associé et dispositif d'affichage Download PDF

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Publication number
WO2020192340A1
WO2020192340A1 PCT/CN2020/076669 CN2020076669W WO2020192340A1 WO 2020192340 A1 WO2020192340 A1 WO 2020192340A1 CN 2020076669 W CN2020076669 W CN 2020076669W WO 2020192340 A1 WO2020192340 A1 WO 2020192340A1
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Prior art keywords
signal
terminal
coupled
node
shift register
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PCT/CN2020/076669
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English (en)
Chinese (zh)
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刘鹏
刘白灵
李付强
王志冲
冯京
栾兴龙
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020192340A1 publication Critical patent/WO2020192340A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit and a driving method thereof, and a display device.
  • a gate driving device is usually used to provide a gate driving signal to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area.
  • the gate driving device can be formed on the array substrate of the display through an array process, that is, an array substrate line drive (Gate Driver on Array, GOA) process.
  • GOA array substrate line drive
  • This integrated process not only saves costs, but also can be achieved on both sides of the liquid crystal panel (Panel)
  • the symmetrical and beautiful design also eliminates the bonding area of the gate integrated circuit (IC) and the fan-out wiring space, so that a narrow frame design can be realized; and, This integrated process can also omit the bonding process in the gate scan line direction, thereby improving productivity and yield.
  • the embodiment of the present disclosure provides a shift register, including:
  • the input control circuit is configured to provide the signal of the first reference signal terminal to the first node in response to the effective signal of the signal input terminal;
  • the reset control circuit is configured to provide the signal of the second reference signal terminal to the first node in response to the effective signal of the reset signal terminal;
  • the first output control circuit is configured to control the signal output of the gate signal output terminal in response to the potential of the first node
  • the signal output termination circuit is configured to terminate the conduction state between the first reference signal terminal and the input control circuit in response to the effective signal of the signal output termination terminal in the partial scan mode, and terminate the second reference The conduction state between the signal terminal and the reset control circuit;
  • the signal output selection circuit is configured to output the valid signal of the selection terminal in response to the valid signal output from the gate signal output terminal when it is determined that the shift register is designated as the scanning start line in the partial scanning mode.
  • the signal is provided to the second node;
  • the signal output trigger circuit is configured to respond to the potential of the second node and provide the signal of the trigger signal terminal to all the signals in the partial scanning mode and when the shift register is designated as the scanning start line.
  • the signal output reset circuit is configured to provide the signal of the third reference signal terminal to the second node in response to the effective signal of the output reset signal terminal when it is determined that the full-screen scanning mode is restored.
  • the signal output termination circuit specifically includes: a first signal output termination circuit and a second signal output termination circuit; the first signal output termination circuit includes a first switching transistor, and The second signal output termination circuit includes a second switch transistor; wherein,
  • the gate of the first switch transistor is coupled to the signal output termination terminal, the first pole is coupled to the first reference signal terminal, and the second pole is coupled to the input control circuit;
  • the gate of the second switch transistor is coupled to the signal output termination terminal, the first pole is coupled to the second reference signal terminal, and the second pole is coupled to the reset control circuit.
  • the signal output selection circuit specifically includes: a third switch transistor; wherein,
  • the gate of the third switch transistor is coupled to the gate signal output terminal, the first pole is coupled to the signal output selection terminal, and the second pole is coupled to the second node.
  • the signal output reset circuit specifically includes: a fourth switch transistor; wherein,
  • the gate of the fourth switch transistor is coupled to the output reset signal terminal, the first pole is coupled to the third reference signal terminal, and the second pole is coupled to the second node.
  • the signal output trigger circuit specifically includes: a fifth switch transistor and a first capacitor; wherein,
  • the gate of the fifth switch transistor is coupled to the second node, the first pole is coupled to the trigger signal terminal, and the second pole is coupled to the first node;
  • the first capacitor has a first terminal coupled with the second node, and a second terminal coupled with the first node.
  • the signal output trigger circuit further includes: a sixth switch transistor; wherein,
  • the gate of the sixth switch transistor is coupled to the second terminal of the first capacitor, the first pole is coupled to the fourth reference signal terminal, and the second pole is coupled to the first node.
  • the input control circuit specifically includes: a seventh switch transistor; wherein,
  • a seventh switching transistor has its gate coupled to the signal input terminal, a first pole coupled to the second pole of the first switching transistor, and a second pole coupled to the first node.
  • the reset control circuit specifically includes: an eighth switch transistor; wherein,
  • the eighth switch transistor has its gate coupled to the reset signal terminal, the first pole is coupled to the second pole of the second switch transistor, and the second pole is coupled to the first node.
  • the above shift register further includes: a node control circuit configured to control the potential of the third node in response to the potential of the first node and the gate signal output terminal.
  • the node control circuit specifically includes: a ninth switch transistor, an eleventh switch transistor, a twelfth switch transistor, and a second capacitor; wherein,
  • a ninth switch transistor the gate and first pole of which are both coupled to the first clock signal terminal, and the second pole is coupled to the third node;
  • An eleventh switching transistor the gate of which is coupled to the first node, the first pole is coupled to the third node, and the second pole is coupled to the third reference signal terminal;
  • a twelfth switching transistor a gate of which is coupled to the gate signal output terminal, a first pole is coupled to the third node, and a second pole is coupled to the third reference signal terminal;
  • the first terminal of the second capacitor is coupled to the third node, and the second terminal is coupled to the third reference signal terminal.
  • the first output control circuit specifically includes: a thirteenth switching transistor and a third capacitor; wherein,
  • a thirteenth switching transistor the gate of which is coupled to the first node, the first pole is coupled to the second clock signal terminal, and the second pole is coupled to the gate signal output terminal;
  • the first terminal of the third capacitor is coupled to the first node, and the second terminal is coupled to the gate signal output terminal.
  • shift register further comprising: a second output control circuit configured to provide the signal of the third reference signal terminal to the gate signal output in response to the potential of the third node End and the first node.
  • the second output control circuit specifically includes: a tenth switching transistor and a fourteenth switching transistor; wherein,
  • a tenth switching transistor the gate of which is coupled to the third node, the first pole is coupled to the first node, and the second pole is coupled to the third reference signal terminal;
  • the fourteenth switching transistor has its gate coupled with the third node, a first pole coupled with the gate signal output terminal, and a second pole coupled with the third reference signal terminal.
  • shift register further includes: an initialization circuit configured to initialize the third node in response to the signal of the initialization signal terminal.
  • the initialization circuit specifically includes: a fifteenth switch transistor; wherein,
  • the gate and first pole of the fifteenth switch transistor are both coupled to the initialization signal terminal, and the second pole is coupled to the third node.
  • all switch transistors included in the shift register are N-type transistors.
  • the present disclosure also provides a gate drive circuit, including a plurality of cascaded shift registers of any of the above; wherein,
  • each stage of shift register is coupled to the signal input terminal of its adjacent next stage of shift register;
  • the gate signal output terminal of each stage of shift register is coupled to the reset signal terminal of the adjacent previous stage of shift register.
  • the present disclosure also provides a display device including the above-mentioned gate drive circuit.
  • the present disclosure also provides a driving method of the above-mentioned gate driving circuit, including:
  • FIG. 1 is a schematic diagram of a structure of a shift register provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of another structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 3 is an input and output timing diagram corresponding to the shift register shown in FIG. 2;
  • FIG. 4 is another input and output timing diagram corresponding to the shift register shown in FIG. 2;
  • FIG. 5 is an input and output timing diagram corresponding to the gate driving circuit provided by the embodiments of the disclosure.
  • FIG. 6 is another input and output timing diagram corresponding to the gate driving circuit provided by the embodiments of the disclosure.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.
  • the resolution of the traditional GOA circuit After the resolution of the traditional GOA circuit is determined, it can only scan from the first row of gate lines to the end of the last row of gate lines. Regardless of the specific actual needs of the display, all scanning and display must be performed from the start line to the end line. As the resolution of our mobile products is getting higher and higher, the power consumption also increases with the increase in resolution, resulting in a greatly reduced standby time for display products. Therefore, how to increase the standby time of a display product is a technical problem urgently needed to be solved by those skilled in the art.
  • a shift register provided by an embodiment of the present disclosure, as shown in FIG. 1, includes:
  • the input control circuit 1 which is coupled between the first node A, the signal input terminal Out N-1, and the first reference signal terminal CN, is configured to respond to the effective signal of the signal input terminal Out N-1 to set the first reference
  • the signal of the signal terminal CN is provided to the first node A;
  • the reset control circuit 2 which is coupled between the first node A, the reset signal terminal Out N+1, and the second reference signal terminal CNB, is configured to respond to the effective signal of the reset signal terminal Out N+1 to set the second reference
  • the signal of the signal terminal CNB is provided to the first node A;
  • the first output control circuit 3 which is coupled between the first node A and the gate signal output terminal Out N , is configured to control the signal output of the gate signal output terminal Out N in response to the potential of the first node A;
  • the first signal output termination circuit 4 is configured to terminate the connection between the first reference signal terminal CN and the first input control circuit 1 under the control of the signal output termination terminal CGE signal in the partial scan mode;
  • the second signal output The termination circuit 5 is configured to terminate the connection between the second reference signal terminal CNB and the second input control circuit 2 under the control of the signal output termination terminal CGE signal in the partial scan mode;
  • the signal output switching circuit includes: a signal output selection circuit 6, a signal output trigger circuit 7 and a signal output reset circuit 8; among them,
  • the signal output selection circuit 6 is configured to provide the signal of the signal output selection terminal CGI under the control of the gate signal output terminal Out N signal when it is determined that the shift register is designated as the scanning start line in the partial scanning mode To the second node B;
  • the signal output trigger circuit 7 is configured to provide the signal of the trigger signal terminal CGS to the first node under the control of the potential of the second node B in the partial scanning mode and when the shift register is designated as the scanning start line A;
  • the signal output reset circuit 8 is configured to provide the signal of the third reference signal terminal VGL to the second node B under the control of the output reset signal terminal CGR signal when it is determined to resume the full-screen scanning mode.
  • the above-mentioned shift register addeds a signal output switching circuit at the first node between the input control circuit 1 and the reset control circuit 2, wherein the signal output selection circuit 6 determines the shift register When it is designated as the scanning start line in the partial scanning mode, under the control of the gate signal output terminal Out N signal, the signal of the signal output selection terminal CGI is provided to the second node B, and the signal output trigger circuit 7 is configured as In the partial scan mode and when the shift register is designated as the scan start line, under the potential control of the second node B, the signal of the trigger signal terminal CGS is provided to the first node A instead of the input control circuit 1
  • the first node A is provided with a signal for controlling the output control circuit 3 to realize the function of any row shift register as the scanning start row.
  • a first signal output termination circuit is added between the first reference signal terminal CN and the input control circuit 1, and a second signal output termination circuit between the reset control circuit 2 and the second reference signal terminal CNB can realize any line
  • the shift register functions as the scanning end line.
  • the signal input terminal of the shift register N of the current stage may be coupled to the gate signal output terminal OUT N-1 of the shift register N-1 of the previous stage.
  • the reset signal terminal of the bit register N may be coupled to the gate signal output terminal OUT N+1 of the shift register N+1 of the next stage, or vice versa.
  • the signal of the first reference signal terminal CN is a high potential signal, and the signal of the second reference signal terminal CNB It is a low-level signal; when the reverse scan mode is adopted, the signal at the first reference signal terminal CN is a low-level signal, and the signal at the second reference signal terminal CNB is a high-level signal.
  • the signal output from the gate signal output terminal OUT N+1 of the next stage of shift register N+1 resets the current stage of shift register N; when using reverse scanning, the previous stage shifts The signal output from the gate signal output terminal OUT N-1 of the register N-1 resets the shift register N of this stage.
  • the first signal output termination circuit 4 specifically includes: a first switching transistor M1; ,
  • the gate of the first switch transistor M1 is coupled to the signal output termination terminal CGE, the first pole is coupled to the first reference signal terminal CN, and the second pole is coupled to the input control circuit 1.
  • the channel length L of the first switching transistor M1 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the first signal output termination circuit 4 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be Other structures known to those skilled in the art are not limited here.
  • the second signal output termination circuit 5 specifically includes: a second switching transistor M2; ,
  • the gate of the second switch transistor M2 is coupled to the signal output termination terminal CGE, the first pole is coupled to the second reference signal terminal CNB, and the second pole is coupled to the reset control circuit 2.
  • the channel length L of the second switching transistor M2 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the second signal output termination circuit 5 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be the present invention. Other structures known to those skilled in the art are not limited here.
  • the signal output selection circuit 6 specifically includes: a third switch transistor M3; wherein,
  • the gate of the third switch transistor M3 is coupled to the gate signal output terminal Out N , the first pole is coupled to the signal output selection terminal CGI, and the second pole is coupled to the second node B.
  • the channel length L of the third switching transistor M3 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the resolution of the traditional shift register circuit can only scan from the first row of gate lines to the end of the last row of gate lines. Regardless of the specific actual needs of the display, it must be from the start line to the end line. Perform full scan display, as our mobile products have higher resolution, power consumption also increases with the increase in resolution, resulting in a greatly reduced standby time of display products.
  • the signal output selection circuit 6 in the signal output switching circuit in the shift register can scan the third row in the full-screen scan mode through the signal output selection terminal
  • the high potential signal input by CGI charges the second node B. Due to the bootstrap effect of the first capacitor C1, the potential of the second node B remains high until the third line scan of the next frame, so that it can be switched to the second node B. Partial scan mode from 3 lines to 8th line.
  • the specific structure of the signal output selection circuit 6 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output reset circuit 8 specifically includes: a fourth switch transistor M4; wherein,
  • the fourth switch transistor M4 has its gate and the output reset signal terminal coupled to the CGR, the first pole is coupled to the third reference signal terminal VGL, and the second pole is coupled to the second node B.
  • the channel length L of the fourth switching transistor M4 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the shift register resumes the full-screen scan mode from the first line to the last line.
  • the shift of the partial scan The potential of the second node B of the register is reset, that is, the fourth switch transistor M4 is turned on under the control of the high potential signal of the output reset signal terminal CGR, and the low potential signal of the third reference signal terminal VGL is input to the second node B to ensure the first
  • the signal of the two node B is a low potential signal, which does not affect the operation of each shift register in the subsequent full-screen scan mode.
  • the specific structure of the signal output reset circuit 8 in the shift register is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output trigger circuit 7 specifically includes: a fifth switch transistor M5 and a first capacitor C1;
  • the fifth switch transistor M5 has its gate coupled to the second node B, the first pole is coupled to the trigger signal terminal CGS, and the second pole is coupled to the first node A;
  • the first capacitor C1 has a first end coupled to the second node B, and a second end coupled to the first node A.
  • the channel length L of the fifth switching transistor M5 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the first capacitor C1 can be designed to be 200f.
  • the trigger signal terminal CGS inputs a high potential signal to the first node A to charge the first node A to perform Scanning of the shift register.
  • the specific structure of the signal output trigger circuit 7 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output trigger circuit 7 may further include: a sixth switch transistor M6;
  • the sixth switch transistor M6 has its gate coupled to the second terminal of the first capacitor C1, the first pole is coupled to the fourth reference signal terminal VGH, and the second pole is coupled to the first node A; The signal of the fourth reference signal terminal VGH is provided to the first node A under the control of the node B.
  • the channel length L of the sixth switching transistor M6 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the input control circuit 1 specifically includes: a seventh switch transistor M7; wherein,
  • the gate of the seventh switch transistor M7 is coupled to the signal input terminal OUT N-1 , the first pole is coupled to the second pole of the first switch transistor M1, and the second pole is coupled to the first node A.
  • the channel length L of the seventh switching transistor M7 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the above is only an example to illustrate the specific structure of the input control circuit 1 in the shift register.
  • the specific structure of the input control circuit 1 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the reset control circuit 2 specifically includes: an eighth switch transistor M8; wherein,
  • the eighth switch transistor M8 has its gate coupled to the reset signal terminal OUT N+1 , the first pole is coupled to the second pole of the second switch transistor M2, and the second pole is coupled to the first node A.
  • the channel length L of the eighth switching transistor M8 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the reset control circuit 2 in the shift register is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the shift register may further include: a node control circuit 9 configured to respond to the first node A and the gate signal output terminal Out N
  • the second output control circuit 10 is configured to respond to the potential of the third node D and provide the signal of the third reference signal terminal VGL to the gate signal output terminal Out N and the first A node A
  • the initialization circuit 11 is configured to initialize the third node D in response to the signal of the initialization signal terminal RST.
  • the node control circuit 9 specifically includes: a ninth switch transistor M9, an eleventh switch The transistor M11, the twelfth switching transistor M12 and the second capacitor C2; among them,
  • the ninth switch transistor M9 has its gate and first pole both coupled to the first clock signal terminal CK, and the second pole is coupled to the third node D;
  • the gate of the eleventh switching transistor M11 is coupled to the first node A, the first pole is coupled to the third node D, and the second pole is coupled to the third reference signal terminal VGL;
  • the twelfth switching transistor M12 has its gate coupled to the gate signal output terminal Out N of the shift register of the current stage, the first pole is coupled to the third node D, and the second pole is coupled to the third reference signal terminal VGL ;
  • the first terminal of the second capacitor C2 is coupled to the third node D, and the second terminal is coupled to the third reference signal terminal VGL.
  • the size of the eleventh switch transistor M11 is generally set larger than that of the ninth switch transistor M9 during process preparation, so that the size of the When the potential of A is high, the eleventh switch transistor M11 provides the signal of the third reference signal terminal VGL to the third node D at a rate greater than that of the ninth switch transistor M9 under the control of the signal of the first node A.
  • the channel length L of the ninth switching transistor M9 can be designed to be 8 ⁇ m, and the channel width can be designed to be 10 ⁇ m.
  • the channel length L of the eleventh switching transistor M11 may be designed to be 8 ⁇ m, and the channel width may be designed to be 18 ⁇ m.
  • the channel length L of the twelfth switching transistor M12 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the second capacitor C2 can be designed to be 200f.
  • the above is only an example to illustrate the specific structure of the node control circuit 9 in the shift register.
  • the specific structure of the node control circuit 9 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the first output control circuit 3 specifically includes: a thirteenth switching transistor M13 and a Three capacitors C3; among them,
  • the thirteenth switching transistor M13 has its gate coupled to the first node A, the first pole is coupled to the second clock signal terminal CKB, and the second pole is coupled to the gate signal output terminal Out N of the shift register of this stage ;
  • the first terminal of the third capacitor C3 is coupled to the first node A, and the second terminal is coupled to the gate signal output terminal Out N of the shift register of this stage.
  • the channel length L of the thirteenth switching transistor M12 can be designed to be 8 ⁇ m, and the channel width can be designed to be 150 ⁇ m.
  • the third capacitor C3 can be designed to be 200f.
  • the above is only an example to illustrate the specific structure of the first output control circuit 3 in the shift register.
  • the specific structure of the first output control circuit 3 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be a technology in the art. Other structures known to the personnel are not limited here.
  • the second output control circuit 10 specifically includes: a tenth switch transistor M10 and a tenth switch transistor M10. Four-switch transistor M14; among them,
  • the tenth switch transistor M10 has its gate coupled to the third node D, the first pole is coupled to the first node A, and the second pole is coupled to the third reference signal terminal VGL;
  • the fourteenth switching transistor M14 has its gate coupled to the third node D, the first pole is coupled to the gate signal output terminal Out N of the shift register of this stage, and the second pole is coupled to the third reference signal terminal VGL .
  • the channel length L of the tenth switching transistor M10 can be designed to be 8 ⁇ m, and the channel width can be designed to be 15 ⁇ m.
  • the channel length L of the fourteenth switching transistor M14 can be designed to be 8 ⁇ m, and the channel width can be designed to be 60 ⁇ m.
  • the specific structure of the second output control circuit 10 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be technical in the art. Other structures known to the personnel are not limited here.
  • the initialization circuit 11 specifically includes: a fifteenth switching transistor M15; wherein,
  • the gate and first pole of the fifteenth switching transistor M15 are both coupled to the initialization signal terminal RST, and the second pole is coupled to the third node D.
  • the channel length L of the fifteenth switching transistor M15 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the function of the initialization circuit 11 is to initialize all the shift registers before the shift registers in the first row of the cascaded shift registers start scanning.
  • the fifteenth switch transistor M15 is high at the initialization signal terminal RST. Is turned on under the control of RST, the high potential signal of the initialization signal terminal RST is input to the third node D to charge the third node D, the fourteenth switch transistor M14 is turned on, and the low potential signal of the third reference signal terminal VGL is input to the gate signal
  • the output terminal Out N initializes the gate signal output terminal Out N so as not to affect the progressive scan of the cascaded multiple shift registers.
  • the specific structure of the initialization circuit 11 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be other structures known to those skilled in the art. It is not limited here.
  • the switching transistor mentioned in the foregoing embodiments of the present disclosure may be a thin film transistor (TFT, Thin Film Transistor), or may be a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited herein.
  • TFT Thin Film Transistor
  • MOS metal oxide semiconductor field effect transistor
  • all the switching transistors may be N-type transistors; the potential of the third reference signal terminal VGL is a low potential, and the fourth reference signal The potential of the terminal VGH is high.
  • all the switch transistors may also be P-type transistors, which is not limited herein.
  • the N-type transistor is turned on under the action of a high potential, and is turned off under the action of a low potential;
  • the P-type transistor is turned off under the action of a high potential, and is turned on under the action of a low potential.
  • the first electrode of the switching transistor mentioned in the above-mentioned embodiments of the present disclosure can be a source electrode and the second electrode can be a drain electrode, or the first electrode can be a drain electrode and the second electrode is a source electrode. distinguish.
  • a forward scan is taken as an example to describe the working process of the shift register provided in the embodiment of the present disclosure from full-screen scan to designated line scan.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • RST in Figure 3 and Figure 4 indicates that before the first row of shift registers is triggered (that is, before STV is high, STV is the initial trigger signal of the shift register), the gate signal output terminal of each shift register is initialized ,
  • double-sided driving means that the shift register on the left drives odd rows Gate lines, the shift register on the right drives the even-numbered gate lines, CKL and CKBL represent the clock signal terminals on the left, CKR and CKBR represent the clock signal terminals on the right, and the connections between CK and CKB and shift registers in different rows are mutually switched
  • CKL is connected to the second clock signal terminal CKB of the shift register connected to the gate line of the first row
  • the first clock signal terminal CK of the shift register connected to the gate line of the third row is connected
  • CKBL is connected to the first The first clock signal terminal
  • the embodiment of the present disclosure takes forward scanning as an example to illustrate the working principle of the design switching from the full-screen scanning mode to the partial scanning mode from the third line to the eighth line.
  • the next frame is the partial scan mode from line 3 to line 8, that is, the shift register in line 3 from the next frame is the starting line, and the shift register in line 8 is At the end of the line, the scanning from the shift register in the third row to the shift register in the eighth row is one cycle, and several cycles are continuously scanned according to display needs.
  • the resolution ie, partial
  • the work of the shift register that specifies the specific initial line and the end line is divided into two stages.
  • the first stage: the resolution switching trigger stage T1 is the full-screen scanning stage, which is a normal frame. Scanning (from the first line to the last line), because the next frame will start from the third line for partial scanning, so the resolution switching trigger stage T1 needs to coordinate with the signal output selection terminal CGI signal to specify the third frame of the next frame
  • the row shift register is the initial row
  • the second stage: the resolution switching display stage T2 is the partial scanning stage, which can be realized with the signal output selection terminal CGI, signal output trigger terminal CGS, signal output termination CGE and reset signal terminal CGR. Switch the resolution display, and display the start line and end line progressively according to the specified line.
  • the timing of Figure 3 is the input and output timing of the second stage shift register Out 2 and the input and output timing of the third stage shift register Out 3.
  • the timing of Figure 4 is the eighth The input and output timing of the shift register Out 8 stage and the input and output timing of the ninth stage shift register Out 9 .
  • the signal of the initialization signal terminal Rst is a high-level signal, and the other signals are low-level signals.
  • the fifteenth switch transistor M15 of each shift register is turned on and the first row is pulled up.
  • the potential of the three nodes D pulls down the potential of the first node A to reset the gate signal output terminal of the shift register.
  • each shift register scans in full screen, that is, scans step by step from the first row to the last row, and the signal at the signal output termination terminal CGE is always a high potential signal.
  • the gate signal output terminal Out 2 of the shift register in row 2 is output at a high level (the output of Out 2 in Figure 3 is a high stage)
  • the first switching transistor M1 and the seventh The switching transistor M7 is turned on to charge the first node A.
  • the signal of the first node A is a high-potential signal
  • the eleventh switching transistor M11 is turned on
  • the low-potential signal of the third reference signal terminal VGL pulls down the third
  • the potential of node D and the signal of the third node D are low potential signals.
  • the signal output selection terminal CGI will input a high-level signal when the gate signal output terminal of the shift register of the third line is a high-level signal during full-screen scan.
  • the third switch transistor M3 of the 3-row shift register is turned on, and the second node B is pulled up to a high potential.
  • the progressive scan time period after Out 3 is output, in the third row shift register
  • the signal of the second node B always remains a high potential signal.
  • the resolution switching display phase T2 starts.
  • the signal at the trigger signal terminal CGS is a high potential signal
  • the signal at the signal output termination terminal CGE is a low potential signal.
  • the second node B is raised due to the bootstrap action of the first capacitor C1, the fifth switch transistor M5 is turned on, and the sixth switch transistor M6 is also turned on, and the signal of the first node A is a high potential signal.
  • the signal of the second clock signal terminal CKB is a high-level signal.
  • the signal of the first node A further rises, the thirteenth switching transistor M13 is turned on, and Out 3 outputs a high-level signal ,
  • the twelfth switch transistor M12 is turned on, and the low potential signal of the third reference signal terminal VGL continues to pull down the signal of the third node D through the twelfth switch transistor M12.
  • the signal input at the second clock signal terminal CKB is the CKBL in FIG. 3, that is, the low potential signal
  • the potential of the first node A is restored to the high potential at the time when the output of Out 3 is low
  • the thirteenth switching transistor M13 is still on, and Out 3 outputs a low-level signal.
  • the high-potential signal output by Out 3 is input to the signal input terminal of the shift register in the fourth row, so that the subsequent shift register cascaded in the shift register in the third row outputs the signal row by row.
  • the signal of the signal output selection terminal CGI is at a high level during the output phase of Out 3 , the signal of the second node B in the shift register of the third row is always maintained at a high level during the line-by-line scanning period after Out 3 is output.
  • Out 8 outputs a high-level signal
  • the signal at the signal output trigger terminal CGS of each shift register is a high-level signal, causing the third row to shift
  • the first node in the bit register can be charged again, so that in the next frame, the shift register from row 3 is the initial scan line, that is, from row 3 to row 8, scanning for several cycles.
  • the signal at the signal output termination terminal CGE is a low level signal, so that the first line of the shift register in the 9th row
  • the switching transistor M1 is turned off and does not charge the shift register of the 9th row, that is, the scanning line ends in the 8th row.
  • a high potential signal is input to the output reset signal terminal CGR of each shift register, the fourth switch transistor is turned on, and the third reference signal terminal VGL discharges the second node B.
  • the third row of shift registers will not be used as the starting row to scan.
  • the embodiments of the present disclosure also provide a gate driving circuit, including a plurality of cascaded shift registers as provided in the embodiments of the present disclosure; wherein,
  • each stage of shift register is coupled to the signal input terminal of its adjacent next stage of shift register;
  • the gate signal output terminal of each stage of shift register is coupled to the reset signal terminal of the adjacent previous stage of shift register.
  • a frame start signal is loaded to the signal input end of the shift register of the first row to realize progressive scanning from top to bottom.
  • load the frame start signal to the signal input end of the shift register of the last row to realize progressive scanning from bottom to top.
  • embodiments of the present disclosure also provide a display device, including the gate driving circuit provided by the embodiments of the present disclosure.
  • the display device can be a display device of any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device for the implementation of the display device, reference may be made to the embodiment of the gate drive circuit described above, and the repetition is not repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a liquid crystal display device or an organic electroluminescence display device, which is not limited herein.
  • the embodiments of the present disclosure also provide a driving method of a gate driving circuit, including:
  • n and m are positive integers, and n is greater than m; that is, the gate of the m-th row shift register in the full-screen scan mode and the partial scan mode
  • the signal output terminal outputs a valid signal to the gate signal output terminal of the shift register in the n-1th row to output a valid signal
  • the valid signal is continuously input to the signal output termination terminal;
  • the following provides two embodiments to illustrate the input and output timing diagrams of the gate driving circuit provided by the embodiments of the present disclosure for switching from full-screen scanning to specified line scanning.
  • the resolution switching trigger frame T1 is a full-screen scan, and the next frame is matched with the signals output by the CGI, CGS, and CGE signal terminals of the signal output switching circuit to switch from line 3 to line 9.
  • the specific gate driving circuit please refer to the working principle of the above-mentioned shift register provided in the embodiment of the present disclosure, which will not be repeated here.
  • the resolution switching trigger frame T1 is a full-screen scan, and the next frame is matched with the signals output by the CGI, CGS, and CGE signal terminals of the signal output switching circuit to switch from the 5th line to the 12th line.
  • the specific gate driving circuit please refer to the working principle of the above-mentioned shift register provided in the embodiment of the present disclosure, which will not be repeated here.
  • the embodiment of the present disclosure provides a shift register, a gate driving circuit and a driving method thereof, and a display device.
  • a signal output switching circuit is added through the first node between the input control circuit 1 and the reset control circuit 2, wherein
  • the signal output selection circuit 6 determines that the shift register is designated as the scanning start line in the partial scanning mode, under the control of the gate signal output terminal Out N signal, it provides the signal output selection terminal CGI signal to the second
  • the signal output trigger circuit 7 is configured to provide the signal of the trigger signal terminal CGS to the trigger signal terminal CGS under the control of the potential of the second node B in the partial scan mode and when the shift register is designated as the scan start line
  • the first node A replaces the input control circuit 1 to provide the first node A with a signal for controlling the output control circuit 3 to realize the function of any row shift register as the scanning start row.
  • a first signal output termination circuit is added between the first reference signal terminal CN and the input control circuit 1, and a second signal output termination circuit between the reset control circuit 2 and the second reference signal terminal CNb can realize any line
  • the shift register functions as the scanning end line.

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Abstract

La présente invention concerne un registre à décalage, un circuit d'attaque de grille et un procédé d'attaque associé et un dispositif d'affichage. Dans le registre à décalage, un circuit de commutation de sortie de signal est ajouté de telle sorte qu'un circuit de sélection de sortie de signal (6) fournisse, lorsqu'il est déterminé que le présent registre à décalage est désigné en tant que ligne de début de balayage dans un mode de balayage local, un signal d'une borne de sélection de sortie de signal à un second nœud (B) sous la commande d'un signal d'une borne de sortie de signal de grille et un circuit de déclenchement de sortie de signal (7) fournisse, dans un mode de balayage local et lorsque le présent registre à décalage est désigné en tant que ligne de départ de balayage, un signal d'une borne de signal de déclenchement à un premier nœud (A) sous la commande potentielle du second nœud (B), de manière à remplacer un circuit de commande d'entrée afin de fournir, au premier nœud (A), un signal permettant de commander un circuit de commande de sortie, réalisant ainsi la fonction d'utilisation de n'importe quelle ligne de registre à décalage en tant que ligne de départ de balayage. De plus, un circuit de terminaison de sortie de signal est ajouté afin de réaliser la fonction d'utilisation de n'importe quelle ligne de registre à décalage en tant que ligne de fin de balayage.
PCT/CN2020/076669 2019-03-25 2020-02-25 Registre à décalage, circuit d'attaque de grille et procédé d'attaque associé et dispositif d'affichage WO2020192340A1 (fr)

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CN111798806B (zh) * 2020-06-30 2022-03-29 上海中航光电子有限公司 扫描驱动电路、显示面板及其驱动方法、显示装置
CN113763885A (zh) * 2021-09-24 2021-12-07 京东方科技集团股份有限公司 显示面板、栅极驱动电路、移位寄存单元及其驱动方法

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