WO2020192308A1 - 一种复合衬底及其制备方法和利用其制备发光元件的方法 - Google Patents

一种复合衬底及其制备方法和利用其制备发光元件的方法 Download PDF

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WO2020192308A1
WO2020192308A1 PCT/CN2020/075618 CN2020075618W WO2020192308A1 WO 2020192308 A1 WO2020192308 A1 WO 2020192308A1 CN 2020075618 W CN2020075618 W CN 2020075618W WO 2020192308 A1 WO2020192308 A1 WO 2020192308A1
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light
layer
substrate
composite substrate
emitting
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PCT/CN2020/075618
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English (en)
French (fr)
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汪玉
蔡家豪
汪琴
方斌
桂亮亮
董金矿
王珊
黄照明
邱智中
蔡吉明
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安徽三安光电有限公司
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Publication of WO2020192308A1 publication Critical patent/WO2020192308A1/zh
Priority to US17/338,901 priority Critical patent/US12021169B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Definitions

  • the invention relates to the technical field of semiconductor materials, in particular to a composite substrate, a preparation method thereof, and a method for preparing a light-emitting element using the composite substrate.
  • Semiconductor light-emitting elements are widely used in fluorescent lamps for lighting, bulb lamps, indoor and outdoor large and small pitch displays, TV backlights, mobile phone backlights, home appliance air conditioner display lights, due to their advantages of high brightness, low voltage, low energy consumption and long life. Vehicle indicator lights and other fields.
  • the LED light-emitting elements need to be laser cut during the preparation process to form individual light-emitting core particles.
  • the invisible cutting technology is to gather the translucent wavelength laser beam from the back of the substrate inside the wafer, and the substrate is separated by a specific depth. The modified layer, and then through the split, so as to separate the core particles.
  • the undercutting process due to wafer warping, there is a phenomenon that the thickness of the middle part of the source and the edge part are inconsistent.
  • the laser energy is uncontrollable. In the thin edge area, excessive energy often damages the surrounding core particles.
  • the epitaxial layer causes micro-leakage of the core particles and affects the photoelectric performance.
  • the purpose of the present invention is to provide a method for preparing a composite substrate and a method for preparing a light-emitting element using the composite substrate, which greatly reduces the damage to the light-emitting epitaxial layer by undercutting and is effective Prevent the occurrence of micro-leakage of the light-emitting element and increase its service life.
  • the present invention provides a method for preparing a composite substrate, which at least includes the following steps:
  • the substrate has at least one upper surface that is conducive to crystal deposition
  • a photoresist mask layer is formed on the upper surface of the above-mentioned substrate
  • step 5 Remove the mask pattern in step 3), and form a crisscross metal mask layer on the substrate;
  • step 6) Put the substrate in step 5) into the reaction chamber to deposit a nitride layer, and the metal mask layer will gradually vaporize with the deposition of the nitride layer to form a composite liner with a crisscross hollow structure At the bottom, the hollow structure is the first pre-cutting lane.
  • the deposition temperature of the nitride layer in the step 6) is higher than the vaporization temperature of the metal mask layer.
  • the width of the pre-filled area is 14 ⁇ m-28 ⁇ m.
  • the metal mask layer is a metal magnesium mask layer or metal sodium or metal zinc or magnesium nitride.
  • the thickness of the metal mask layer is 3 to 5 ⁇ m.
  • the reaction chamber is a MOCVD reaction chamber or a PVD reaction chamber or a PECVD reaction chamber.
  • the present invention also discloses a composite substrate, comprising a substrate and a nitride layer arranged on the substrate, characterized in that: a plurality of crisscross hollow structures are arranged at the interface between the nitride layer and the substrate , The hollow structure forms a first pre-cut path, and the first pre-cut path divides the substrate into several regions.
  • the width of the first pre-cut lane is 14-28 ⁇ m.
  • the present invention also discloses a method for preparing a light-emitting element by using the composite substrate, which at least includes the following steps:
  • the process of forming the light-emitting element includes at least the following steps:
  • the first pre-cutting lane and the second pre-cutting lane are located on the same vertical plane.
  • the formation process of the MESA pattern at least includes the following steps:
  • the light-emitting element includes a substrate, a nitride layer, a first semiconductor layer, a multiple quantum well light-emitting layer and a second semiconductor layer sequentially located on the substrate, and a first electrode located on the first semiconductor layer and a second semiconductor layer located on the second semiconductor layer.
  • the second electrode on the semiconductor layer has a recessed area at the interface between the nitride layer and the edge of the substrate.
  • the light-emitting epitaxial layer is a gallium nitride epitaxial layer or a gallium arsenide epitaxial layer or a gallium phosphide epitaxial layer.
  • a crisscross metal mask layer is formed on a substrate.
  • the nitride deposition temperature is higher than the vaporization temperature of the metal mask layer to form a composite substrate with a specific hollow structure.
  • a light-emitting epitaxial layer is formed on the composite substrate, wherein the hollow structure is a first pre-cut path, and the gap between the MESA patterns on the upper surface of the light-emitting epitaxial layer forms a second pre-cut path.
  • FIGS. 1A-1E are schematic structural diagrams of a composite substrate preparation process according to specific embodiments of the present invention.
  • Fig. 2 is a flow chart of the preparation of a light-emitting element according to a specific embodiment of the present invention.
  • FIG. 3 is a schematic top view of a structure formed in step Sb in a specific embodiment of the present invention.
  • step Sc-1 is a schematic top view of the structure formed in step Sc-1 of the specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure formed in step Sc-2 of the specific embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the structure of a light-emitting element according to a specific embodiment of the present invention.
  • the present invention provides a method for preparing a composite substrate, which at least includes the following steps:
  • S1 Provide a substrate 110, the substrate 110 has at least one upper surface that is conducive to crystal deposition.
  • the structure presented in this step refer to FIG. 1A;
  • a photoresist mask layer 120 is formed on the upper surface of the above-mentioned substrate 110.
  • FIG. 1B For the structure presented in this step, refer to FIG. 1B;
  • step S5 Remove the mask pattern 121 in step S3, and form a crisscrossed metal mask layer 130 on the substrate 110.
  • FIG. 1E For the structure presented in this step, refer to FIG. 1E;
  • step S6 Put the substrate 110 in step S5 into the reaction chamber to deposit a nitride layer 140.
  • the metal mask layer 130 gradually vaporizes with the deposition of the nitride layer 140.
  • the deposition temperature of the nitride layer 140 Higher than the vaporization temperature of the metal mask layer 130, as the nitride layer 140 is deposited, the metal mask layer 130 is gradually vaporized, leaving a horizontally and longitudinally staggered hollow structure 150 inside the nitride layer 140.
  • the hollow structure 150 is used as the first pre-cut lane for subsequent cutting of the light-emitting element, and the width of the first pre-cut lane is 3-5um.
  • a composite substrate with criss-crossed hollow structures 150 is formed.
  • the hollow structures 150 are the first pre-cut lanes. Refer to FIG. 1F for the structure presented in this step.
  • the substrate 110 may be a patterned substrate 110 or a flat substrate 110, and the material may be sapphire or silicon or silicon carbide or gallium nitride.
  • the size of the substrate 110 is 2-12 feet.
  • the present invention is basically suitable for large sizes. The beneficial effect of is more obvious.
  • a 4-inch flat sapphire growth substrate 110 is used. In fact, the larger the size of the substrate 110, more effective chips can be prepared at the same time, which is beneficial to saving production costs.
  • the size and shape of the mask pattern 121 are related to the size and shape of the preformed core particles, and the shape and size of the mask pattern 121 are basically the same as the formation and size of the preformed light-emitting element.
  • the height of the mask pattern 121 is 3 to 5 ⁇ m, preferably 3.8 ⁇ m, and the gap between adjacent mask patterns 121 is 14 ⁇ m to 28 ⁇ m.
  • the metal mask layer 130 is vapor-deposited by a metal vapor deposition method, and the thickness of the metal mask layer 130 is 3 to 5 ⁇ m.
  • the metal mask layer 130 is a metal magnesium mask layer or metal sodium or metal zinc or magnesium nitride.
  • metal Mg as the metal mask layer 130.
  • the melting point of metal magnesium is about 648° C., and a uniform metal magnesium mask layer can be formed on the substrate 110 by evaporation.
  • the vaporization temperature of magnesium is 1108° C., which is relatively low.
  • the current growth temperature of the MOCVD reaction chamber can meet its vaporization conditions, thereby forming regularly arranged hollow structures 150 in the nitride layer 140.
  • magnesium as an indispensable P-type doping impurity in the light-emitting epitaxial layer, will not cause pollution to the reaction chamber, and the vaporized magnesium vapor can be used for the growth of the P-type nitride layer 140.
  • the deposited metal mask layer 130 can be basically put into the MOCVD reaction chamber or PVD reaction chamber or PECVD reaction chamber for the deposition process of the nitride layer 140.
  • the choice of the nitride reaction chamber can be the same as the subsequent epitaxial layer.
  • the deposition chamber is the same or different.
  • the nitride layer 140 may be a GaN layer or an AlN layer or an AlGaN layer.
  • a MOCVD reaction chamber is used to deposit a GaN layer. Since the diffusion coefficient of GaN is different from the diffusion coefficient of Mg, a composite substrate with a specific hollow structure 150 is formed during the interdiffusion process.
  • the present invention also discloses a method for preparing a light-emitting element using the above-mentioned composite substrate, which at least includes the following steps:
  • the light emitting epitaxial layer includes a first semiconductor layer 300, a second semiconductor layer 400, and a multiple quantum well structure located between the first semiconductor layer 300 and the second semiconductor layer 400 Layer 500;
  • step Sb the formation process of the MESA pattern 200 includes at least the following steps:
  • step Sc the process of forming a light-emitting element includes at least the following steps:
  • a first electrode 310 is formed on the first semiconductor layer 300, and a second electrode 420 is formed on the second semiconductor layer 400. Refer to FIG. 4 for the structure formed in this step;
  • Sc-3 Use the invisible cutting process to cut the lower surface of the composite substrate along the first pre-cut path
  • FIG. 6 is a schematic diagram of the structure of the light-emitting element formed in this step.
  • the light-emitting element includes a substrate 110, a nitride layer 140 sequentially located on the substrate 110, a first semiconductor layer 300, a multiple quantum well light-emitting layer, and a second semiconductor layer 400, and the first semiconductor layer 300
  • the upper first electrode 310 and the second electrode 420 located on the second semiconductor layer 400 have a recessed area 700 at the edge interface of the nitride layer 140 and the substrate 110.
  • the recessed area 700 on the sidewall of the light-emitting element increases the light-emitting area of the sidewall on the one hand, and the recessed area 700 can also change the light-emitting angle, thereby improving the light-emitting efficiency of the light-emitting element.
  • the present invention forms a crisscross metal mask layer 130 on the substrate 110, and in the subsequent nitride deposition process, the nitride deposition temperature is higher than the vaporization temperature of the metal mask layer 130 to form a composite liner with a specific hollow structure 150
  • a light-emitting epitaxial layer is formed on the composite substrate, wherein the hollow structure 150 is a first pre-cut track, and the gap between the MESA patterns 200 on the upper surface of the light-emitting epitaxial layer forms a second pre-cut track 210.
  • the first pre-cut path hollow structure 150 due to the existence of the first pre-cut path hollow structure 150, it can avoid laser damage to the edge area of the light-emitting element, and effectively improve the epitaxial damage of the light-emitting element due to excessive laser energy.
  • the leakage caused by the layer is abnormal.

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Abstract

本发明涉及半导体材料技术领域，尤其涉及一种复合衬底的制备方法和利用其制备发光元件的方法，其通过在基板上形成纵横交错金属掩膜层，在后续氮化物沉积过程中，利用氮化物沉积温度高于金属掩膜层的气化温度而形成具有特定中空结构的复合衬底，并在该复合衬底上形成发光外延层，其中该中空结构为第一预切割道，发光外延层上表面 MESA图形之间的间隙形成第二预切割道，当激光沿着第一预切割道和第二预切割道切割时，由于第一预切割道中空结构的存在，能够避免激光对发光元件边缘区域的损伤，有效地改善发光元件因激光能量过高损伤外延层导致的漏电异常。

Description

一种复合衬底及其制备方法和利用其制备发光元件的方法 技术领域
本发明涉及半导体材料技术领域，尤其涉及一种复合衬底及其制备方法和利用其制备发光元件的方法。
背景技术
半导体发光元件因其亮度高、电压低、能耗低、寿命长等优点广泛的应用在照明用日光灯、球泡灯、户内户外大小间距显示屏、电视背光、手机背光、家电空调显示灯、车用指示灯等各个领域。
但LED发光元件在制备过程中需要经过激光切割才能形成一个个独立的发光芯粒，隐形切割技术是将半透明波长的激光束从衬底背面聚集在晶圆内部，衬底特定深度形成分隔用的改质层，再经过裂片，从而将芯粒分开。在隐切过程中，因晶圆翘曲，存在片源中间部位与边缘部位厚度不一致的现象，再加上激光能量不可控，在边缘偏薄区域常因能量过高而伤及芯粒周围的外延层，致芯粒微漏电，影响光电性能。
发明概述
技术问题
问题的解决方案
技术解决方案
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种复合衬底的制备方法和利用其制备发光元件的方法，该复合衬底大大减少了隐切对发光外延层的损伤，有效防止发光元件微漏电现在的发生，提升其使用寿命。
本发明提供一种复合衬底的制备方法，其至少包括以下步骤：
1)提供一基板，该基板至少具有一利于晶体沉积的上表面；
2)在上述基板上表面上形成一层光刻胶掩膜层；
3)采用光刻技术将所述光刻胶掩膜层分为若干个间隔排列掩膜图形，相邻掩膜图形之间具有一定的间隙，该间隙形成预填充区；
4)在上述预填充区上沉积金属掩膜层；
5)去除步骤3)中的掩膜图形，在基板上形成纵横交错的金属掩膜层；
6)将步骤5)中的基板放入反应腔室沉积一氮化物层，所述金属掩膜层随着所述氮化物层沉积的沉积逐渐气化，形成具有纵横交错的中空结构的复合衬底，所述中空结构为第一预切割道。
优选的，所述步骤6)中氮化物层的沉积温度高于金属掩膜层的气化温度。
优选的，所述预填充区的宽度为14μm～～28μm。
优选的，所述金属掩膜层为金属镁掩膜层或者金属钠或者金属锌或者氮化镁。
优选的，所述金属掩膜层的厚度为3～～5μm。
优选的，所述反应腔室为MOCVD反应室或者PVD反应室或者PECVD反应室。
本发明还公开了一种复合衬底，包括一基板和设置于该基板上的氮化物层，其特征在于：所述氮化物层与所述基板的界面处设置有若干条纵横交错的中空结构，所述中空结构形成第一预切割道，所述第一预切割道将所述基板分为若干个区域。
优选的，所述第一预切割道的宽度为14～～28μm。
本发明还公开了一种利用上述复合衬底制备发光元件的方法，其至少包括以下步骤：
a)在所述复合衬底上表面沉积发光外延层，所述发光外延层包括第一半导体层、第二半导体层和位于第一半导体层和第二半导体层之间的多量子阱结构层；
b)在所述发光外延层上制备MESA图形，相邻MESA图形之间形成的间距为第二预切割道；
c)沿第一预切割道和第二预切割道将所述复合衬底、发光外延层切割成若干个基本发光元件。
优选的，在步骤c)中，所述发光元件形成的过程至少包括以下步骤：
c-1)在第一半导体层上形成第一电极、在第二半导体层上形成第二电极；
c-2)采用隐形切割工艺沿第一预切割道在复合衬底下表面进行切割；
c-3)采用劈裂裂工艺沿第二预切割道将发光外延层劈裂，形成若干个基本发光元件。
优选的，第一预切割道与第二预切割道位于同一垂直面上。
优选的，在步骤b)中，所述MESA图形的形成过程至少包括以下步骤：
b-1)在发光外延层表面沉积透明导电层；
b-2)MESA上光阻后进行黄光开图；
b-3)ICP蚀刻出第二电极沉积平台；
b-4)去光阻，得到定义p-N结图形的晶圆。
优选的，所述发光元件包括基板、依次位于基板上的氮化物层、第一半导体层、多量子阱发光层和第二半导体层，以及位于第一半导体层上的第一电极和位于第二半导体层上的第二电极，所述氮化物层与基板边缘界面处具有一凹陷区。
优选的，所述发光外延层为氮化镓外延层或者砷化镓外延层或者磷化镓外延层。
发明的有益效果
有益效果
本发明通过在基板上形成纵横交错金属掩膜层，在后续氮化物沉积过程中，利用氮化物沉积温度高于金属掩膜层的气化温度而形成具有特定中空结构的复合衬底，并在该复合衬底上形成发光外延层，其中该中空结构为第一预切割道，发光外延层上表面MESA图形之间的间隙形成第二预切割道，当激光沿着第一预切割道和第二预切割道切割时，由于第一预切割道中空结构的存在，能够避免激光对发光元件边缘区域的损伤，有效第改善发光元件因激光能量过高损伤外延层导致的为漏电异常。
对附图的简要说明
附图说明
图1A-1E为本发明具体实施方式之复合衬底制备流程结构示意图。
图2为本发明具体实施方式之发光元件制备流程图。
图3为本发明具体实施方式之步骤Sb形成结构之俯视示意图。
图4为本发明具体实施方式之步骤Sc-1形成结构之俯视示意图。
图5为本发明具体实施方式之步骤Sc-2形成结构之结构示意图。
图6为本发明具体实施方式之发光元件的结构示意图。
发明实施例
本发明的实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1A-1E所示，本发明提供一种复合衬底的制备方法，其至少包括以下步骤：
S1：提供一基板110，该基板110至少具有一利于晶体沉积的上表面，该步骤呈现的结构参看附图1A；
S2：在上述基板110上表面上形成一层光刻胶掩膜层120，该步骤呈现的结构参看附图1B；
S3：采用光刻技术将所述光刻胶掩膜层120分为若干个间隔排列掩膜图形121，相邻掩膜图形121之间具有一定的间隙，该间隙形成预填充区122，该步骤呈现的结构参看附图1C；
S4：在上述预填充区122上沉积金属掩膜层130，该步骤呈现的结构参看附图1D；
S5：去除步骤S3中的掩膜图形121，在基板110上形成纵横交错的金属掩膜层130，该步骤呈现的结构参看附图1E；
S6：将步骤S5中的基板110放入反应腔室沉积一氮化物层140，所述金属掩膜层 130随着所述氮化物层140沉积的沉积逐渐气化，氮化物层140的沉积温度高于金属掩膜层130的气化温度，随着氮化物层140的沉积，金属掩膜层130逐步气化后而在氮化物层140内部留下横纵交错的中空结构150，该中空结构150作为后续切割发光元件的第一预切割道，第一预切割道的宽度为3～5um。
形成具有纵横交错的中空结构150的复合衬底，所述中空结构150为第一预切割道，该步骤呈现的结构参看附图1F。
在步骤S1中，基板110可以为图形化基板110或者平片基板110，材质可以为蓝宝石或者硅或者碳化硅或者氮化镓，该基板110的尺寸为2～12英尺，本发明对大尺寸基本的有益效果更明显，作为为示例，采用4英寸的蓝宝石平片生长基板110，实际上基板110尺寸越大，可同时制备更多的有效芯片，有利于节约生产成本。
在步骤S3中，掩膜图形121的尺寸、形状与预形成芯粒的尺寸、形状相关，掩膜图形121的形状、尺寸与预形成发光元件的形成、尺寸基本相同。掩膜图形121的的高度为3～5μm，优选为3.8μm，相邻掩膜图形121之间的间隙为14μm～28μm。
在步骤S4中，采用金属蒸镀法蒸镀金属掩膜层130，其厚度为3～5μm。金属掩膜层130为金属镁掩膜层或者金属钠或者金属锌或者氮化镁。作为实例，我们采用金属Mg作为金属掩膜层130，金属镁的熔点约648℃，可以采用蒸镀的方式在基板110上形成一层均匀的金属镁掩膜层。而镁的气化温度为1108℃，相对较低，当前的MOCVD反应腔室的生长温度可以满足其气化条件，从而在氮化物层140内形成规则排列的中空结构150。另一方面，镁作为发光外延层中一种必不可少的P型掺杂杂质，对反应腔体不会造成污染且气化后的镁蒸汽可用于P型氮化物层140的生长。
在步骤S6中，可以将沉积有金属掩膜层130的基本放入MOCVD反应室或者PVD反应室或者PECVD反应室进行氮化物层140的沉积工艺，氮化物反应腔室的选择可以与后续外延层沉积的腔室相同，也可以不同。例如，氮化物层140可以为GaN层或者AlN层或者AlGaN层。作为实例，采用MOCVD反应腔室沉积GaN层。由于GaN的扩散系数不同于Mg扩散系数，在相互扩散的过程即形成具有特定 中空结构150的复合衬底。形成的Mg蒸汽部分通过MOCVD尾气排出装置排出，部分未及时排出沉积在反应室腔体壁，可作为MOCVD反应强催化剂，促进GaN的生长，具有不污染反应室腔体的优势。参看附图2，本发明还公开了一种利用上述复合衬底制备发光元件的方法，其至少包括以下步骤：
Sa：在所述复合衬底上表面沉积发光外延层；发光外延层包括第一半导体层300、第二半导体层400和位于第一半导体层300和第二半导体层400之间的多量子阱结构层500；
Sb：在所述发光外延层上制备MESA图形200，相邻MESA图形200之间具有一定的间隙，该间隙形成第二预切割道210，第一预切割道与第二预切割道位于同一垂直面上，附图3是该步骤形成结构的俯视示意图；
Sc：沿第一预切割道和第二预切割道210将所述复合衬底、发光外延层切割成若干个基本发光元件。
在步骤Sb中，所述MESA图形200的形成过程至少包括以下步骤：
b-1)在发光外延层表面沉积透明导电层；
b-2)MESA上光阻后进行黄光开图；
b-3)ICP蚀刻出第二电极沉积平台4210；
b-4)去光阻，得到定义P-N结图形的晶圆。
在步骤Sc中，发光元件形成的过程至少包括以下步骤：
Sc-1：在第一半导体层300上形成第一电极310、在第二半导体层400上形成第二电极420，该步骤形成的结构参看附图4；
Sc-2：基板110背面减薄后，蒸镀DBR反射层600，该步骤形成的结构参看附图5；
Sc-3：采用隐形切割工艺沿第一预切割道在复合衬底下表面进行切割；
Sc-4：采用劈裂裂工艺沿第二预切割道210将发光外延层劈裂，形成若干个基本发光元件，附图6为该步骤形成发光元件的结构示意图。
由附图6可以看出，发光元件包括基板110、依次位于基板110上的氮化物层140、第一半导体层300、多量子阱发光层和第二半导体层400，以及位于第一半导体层300上的第一电极310和位于第二半导体层400上的第二电极420，所述氮化 物层140与基板110边缘界面处具有一凹陷区700。发光元件侧壁的凹陷区700，一方面增大了侧壁的出光面积，该凹陷区700还可以改变出光角度，进而提升发光元件的出光效率。
本发明通过在基板110上形成纵横交错金属掩膜层130，在后续氮化物沉积过程中，利用氮化物沉积温度高于金属掩膜层130的气化温度而形成具有特定中空结构150的复合衬底，并在该复合衬底上形成发光外延层，其中该中空结构150为第一预切割道，发光外延层上表面MESA图形200之间的间隙形成第二预切割道210，当激光沿着第一预切割道和第二预切割道210切割时，由于第一预切割道中空结构150的存在，能够避免激光对发光元件边缘区域的损伤，有效地改善发光元件因激光能量过高损伤外延层导致的漏电异常。
以上实施方式仅用于说明本发明，而并非用于限定本发明，本领域的技术人员，在不脱离本发明的精神和范围的情况下，可以对本发明做出各种修饰和变动，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应视权利要求书范围限定。

Claims (14)

  1. 一种复合衬底的制备方法，其特征在于，至少包括以下步骤：
    1)提供一基板，该基板至少具有一利于晶体沉积的上表面；
    2)在上述基板上表面上形成一层光刻胶掩膜层；
    3)采用光刻技术将所述光刻胶掩膜层分为若干个间隔排列掩膜图形，相邻掩膜图形之间具有一定的间隙，该间隙形成预填充区；
    4)在上述预填充区上沉积金属掩膜层；
    5)去除步骤3)中的掩膜图形，在基板上形成纵横交错的金属掩膜层；
    6)将步骤5)中的基板放入反应腔室沉积一氮化物层，所述金属掩膜层随着所述氮化物层沉积的沉积逐渐气化，形成具有纵横交错的中空结构的复合衬底，所述中空结构为第一预切割道。
  2. 根据权利要求1所述的一种复合衬底的制备方法，其特征在于：所述步骤6)中氮化物层的沉积温度高于金属掩膜层的气化温度。
  3. 根据权利要求1所述的一种复合衬底的制备方法，其特征在于：所述预填充区的宽度为14μm-28μm。
  4. 根据权利要求1所述的一种复合衬底的制备方法，其特征在于：所述金属掩膜层为金属镁掩膜层或者金属钠或者金属锌或者氮化镁。
  5. 根据权利要求1所述的一种复合衬底的制备方法，其特征在于：所述金属掩膜层的厚度为3～5μm。
  6. 根据权利要求1所述的一种复合衬底的制备方法，其特征在于：所述反应腔室为MOCVD反应室或者PVD反应室或者PECVD反应室。
  7. 一种复合衬底，包括一基板和设置于该基板上的氮化物层，其特征在于：所述氮化物层与所述基板的界面处设置有若干条纵横交错的中空结构，所述中空结构为第一预切割道，所述第一预切割道将所述基板分为若干个区域。
  8. 根据权利要求7所述的一种复合衬底，其特征在于：所述第一预切割道的宽度为14～28μm。
  9. 一种利用权利要求7-8任一所述的复合衬底制备发光元件的方法，其特征在于：包括以下步骤：
    在所述复合衬底上表面沉积发光外延层，所述发光外延层包括第一半导体层、第二半导体层和位于第一半导体层和第二半导体层之间的多量子阱结构层；
    在所述发光外延层上制备MESA图形，相邻MESA图形之间具有一定的间隙，该间隙形成第二预切割道；
    沿第一预切割道和第二预切割道将所述复合衬底、发光外延层切割成若干个基本发光元件。
  10. 根据权利要求9所述的制备发光元件的方法，其特征在于：在步骤c)中，所述发光元件形成的过程至少包括以下步骤：
    c-1)在第一半导体层上形成第一电极、在第二半导体层上形成第二电极；
    c-2)采用隐形切割工艺沿第一预切割道在复合衬底下表面进行切割；
    c-3)采用劈裂裂工艺沿第二预切割道将发光外延层劈裂，形成若干个基本发光元件。
  11. 根据权利要求9所述的制备方元件的方法，其特征在于：第一预切割道与第二预切割道位于同一垂直面上。
  12. 根据权利要求9所述的制备发光元件的方法，其特征在于：在步骤b)中，所述MESA图形的形成过程至少包括以下步骤：
    b-1)在发光外延层表面沉积透明导电层；
    b-2)MESA上光阻后进行黄光开图；
    b-3)ICP蚀刻出第二电极沉积平台；
    b-4)去光阻，得到定义P-N结图形的晶圆。
  13. 根据权利要求9所述的制备发光元件的方法，其特征在于：所述发 光元件包括基板、依次位于基板上的氮化物层、第一半导体层、多量子阱发光层和第二半导体层，以及位于第一半导体层上的第一电极和位于第二半导体层上的第二电极，所述氮化物层与基板边缘界面处具有一凹陷区。
  14. 根据权利要求9所述的制备发光元件的方法，其特征在于：所述发光外延层为氮化镓外延层或者砷化镓外延层或者磷化镓外延层。
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CN102255010A (zh) * 2011-07-13 2011-11-23 厦门市三安光电科技有限公司 一种氮化镓发光二极管的制作方法
CN106449920A (zh) * 2016-10-19 2017-02-22 华灿光电（浙江）有限公司 一种发光二极管芯片及其制造方法

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