WO2020192243A1 - 数据存储的装置、方法及可读存储介质 - Google Patents

数据存储的装置、方法及可读存储介质 Download PDF

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Publication number
WO2020192243A1
WO2020192243A1 PCT/CN2020/071113 CN2020071113W WO2020192243A1 WO 2020192243 A1 WO2020192243 A1 WO 2020192243A1 CN 2020071113 W CN2020071113 W CN 2020071113W WO 2020192243 A1 WO2020192243 A1 WO 2020192243A1
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Prior art keywords
data
buffer
transmission buffer
write
read
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PCT/CN2020/071113
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English (en)
French (fr)
Inventor
孙世博
何琼
邵金华
孙锦
段后利
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无锡海斯凯尔医学技术有限公司
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Priority to EP20777221.1A priority Critical patent/EP3951581A4/en
Priority to AU2020249862A priority patent/AU2020249862B2/en
Priority to KR1020217031961A priority patent/KR102589643B1/ko
Priority to MX2021011706A priority patent/MX2021011706A/es
Priority to JP2021557121A priority patent/JP7236172B2/ja
Priority to CA3134397A priority patent/CA3134397A1/en
Priority to BR112021019117A priority patent/BR112021019117A2/pt
Publication of WO2020192243A1 publication Critical patent/WO2020192243A1/zh
Priority to US17/481,087 priority patent/US11836098B2/en
Priority to ZA2021/07227A priority patent/ZA202107227B/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement

Definitions

  • the embodiments of the present invention relate to the technical field of big data storage, and in particular to a data storage device, method, and readable storage medium.
  • ultra-high-speed ultrasound imaging systems With the development of the Internet and the advancement of science and technology, there has been an explosive growth of data in various technological industries, forming a large amount of data. For example, in the field of ultra-high-speed ultrasound imaging technology, ultra-high-speed ultrasound imaging systems generate a large amount of data. These data need to be stored quickly during the process of mass data collection.
  • the embodiments of the present invention provide a data storage device, method, and readable storage medium, which solve the technical problems of slow storage and low storage efficiency in the prior art.
  • an embodiment of the present invention provides a data storage device, including: a processor and a memory; the processor includes: a cache scheduler, multiple transmission buffers, an interface buffer, and a memory controller;
  • Each of the transmission buffers is connected to the buffer scheduler and the interface buffer respectively, and the interface buffer is connected to the memory through the memory controller;
  • the buffer scheduler is configured to control a plurality of the transmission buffers to write data and read and send the data to the interface buffer;
  • the interface buffer is configured to receive data sent by the transmission buffer if the capacity of the data stored in the interface buffer is less than a preset capacity threshold, and if the data stored in the interface buffer is If the capacity is greater than or equal to the preset capacity threshold, stop receiving the data sent by the transmission buffer;
  • the memory controller is configured to control the memory to write data from the interface buffer and store the data.
  • the memory controller is specifically configured to control the memory to continuously write data from the interface buffer and store the data.
  • the buffer scheduler includes: an ingress scheduler and an egress scheduler;
  • the entry scheduler is used to control the transmission buffer with write permission to write data according to entry scheduling status and write token information
  • the egress scheduler is used to control the transmission buffer with read permission to read data according to the egress scheduling status and the read token information.
  • the entry scheduling state includes: an idle state and a multiple transmission buffer writing state
  • the entry scheduler is specifically configured to: if the entry scheduling state is an idle state and the write token information is a certain write token information, control to change the idle state to the certain write command
  • the transmission buffer corresponding to the card information is written in the state, and the transmission buffer is controlled to write data.
  • the entry scheduler is further configured to update the current write state of the transmission buffer to the idle state if the current write data in the transmission buffer reaches the first preset length value, and change the current The write token information is updated to another write token information.
  • the entry scheduler is specifically configured to determine the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and update the current write token information to The transmission buffer with the longest waiting time to write token information.
  • the egress scheduling status includes: interface buffer detection status, and multiple transmission buffer reading status;
  • the egress scheduler is specifically configured to: if the egress scheduling state is an interface buffer detection state and the read token information is a certain read token information, control the interface buffer detection state to jump to The read status of the transmission buffer corresponding to the certain read token information, and control the transmission buffer to read data.
  • the egress scheduler is further configured to update the current transmission buffer read status to the interface if the current data read by the transmission controller reaches the second preset length value.
  • the buffer detects the status and updates the current read token information to another read token information.
  • the egress scheduler is specifically configured to determine the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer to update the current read token information Read the token information for the transmission buffer with the longest waiting time.
  • the data is a high frame rate ultrasonic echo signal
  • the device further includes a transmitting and receiving array component
  • the processor further includes: at least one sliding window controller
  • the transmitting and receiving array component is connected with each of the sliding window controllers;
  • the transmitting and receiving array component is used to transmit ultrasonic excitation signals and receive high frame rate ultrasonic echo signals;
  • the sliding window controller is configured to filter out the signals to be stored from the high frame rate ultrasonic echo signals according to the sliding window parameters, and send the signals to be stored to the buffer scheduler under the control of the buffer scheduler The corresponding transmission buffer.
  • an embodiment of the present invention provides a data storage method, including: a buffer scheduler controls a plurality of the transmission buffers to write data and reads and sends the data to an interface buffer;
  • the interface buffer receives the data sent by the transmission buffer, if the capacity of the data stored in the interface buffer is greater than or Equal to the preset capacity threshold, the interface buffer stops receiving the data sent by the transmission buffer;
  • the memory controller controls the memory to write data from the interface buffer and store the data.
  • the memory controller controlling the memory to write data from the interface buffer and store the data specifically includes:
  • the memory controller controls the memory to continuously write data from the interface buffer and store the data.
  • the cache scheduler includes: an ingress scheduler and an egress scheduler;
  • the buffer scheduler controlling a plurality of the transmission buffers to write data and read and send the data to the interface buffer specifically includes:
  • the entry scheduler controls the transmission buffer with write permission to write data according to entry scheduling status and write token information
  • the egress scheduler controls the transmission buffer with read permission to read data according to the egress scheduling status and the read token information.
  • the entry scheduling state includes: an idle state and multiple transmission buffer write states;
  • the entry scheduler controls the transmission buffer with write permission to write data according to entry scheduling status and write token information, which specifically includes:
  • the entry scheduling state is an idle state and the write token information is a certain write token information
  • control to change the idle state to the transmission buffer write state corresponding to the certain write token information And control the transmission buffer to write data.
  • the method further includes:
  • the entry scheduler updates the current transmission buffer write state to an idle state, and updates the current write token information to another write token information.
  • the updating the current write token information to another write token information specifically includes:
  • the entry scheduler determines the transmission buffer with the longest waiting time for writing according to the waiting time of each transmission buffer, and updates the current write token information to the transmission buffer write token with the longest waiting time for writing information.
  • the egress scheduling state includes: interface buffer detection state, and multiple transmission buffer reading states;
  • the egress scheduler controls the transmission buffer with read permission to read data according to egress scheduling status and read token information, which specifically includes:
  • exit scheduling state is the interface buffer detection state and the read token information is a certain read token information
  • control to change the interface buffer detection state to the one corresponding to the certain read token information The transmission buffer reads the status and controls the transmission buffer to read data.
  • the current transmission buffer read status is updated to the interface buffer detection status, and the current read token information is updated to another read status. Token information.
  • updating the current read token information to another read token information specifically includes:
  • the egress scheduler determines the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and updates the current read token information to the transmission buffer reading token with the longest waiting time information.
  • the data is a high frame rate ultrasonic echo signal
  • the buffer scheduler controls a plurality of the transmission buffers to write the data
  • the data is read and sent to the interface buffer Before the device, it also includes:
  • Transmitting and receiving array components transmit ultrasonic excitation signals and receive high frame rate ultrasonic echo signals;
  • the sliding window controller screens out the signals to be stored from the high frame rate ultrasonic echo signals according to the sliding window parameters, and sends the signals to be stored to the corresponding transmission buffer under the control of the buffer scheduler .
  • an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the method described in any one of the second aspect.
  • Embodiments of the present invention provide a data storage device, a method, and a readable storage medium.
  • the data storage device includes: a processor and a memory; the processor includes: a buffer scheduler, multiple transmission buffers, and an interface buffer, Memory controller; each transmission buffer is connected to the buffer scheduler and the interface buffer respectively, and the interface buffer is connected to the memory through the memory controller; the buffer scheduler is used to control multiple transmission buffers to write data and The data is read out and sent to the interface buffer; the interface buffer is used to receive the data sent by the transmission buffer if the capacity of the data stored in the interface buffer is less than the preset capacity threshold, if the data stored in the interface buffer If the capacity is greater than or equal to the preset capacity threshold, stop receiving the data sent by the transmission buffer; the memory controller is used to control the memory to write data from the interface buffer and store the data. Because the buffer scheduler can schedule data in an orderly manner, the interface buffer effectively buffers the large amount of data read in the transmission buffer, avoiding the accumulation of data when the back
  • FIG. 1 is a schematic structural diagram of a data storage device provided by Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of the structure of a data storage device provided in Embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of the transition of the entry scheduling state of the entry scheduler in the data storage device provided in the second embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the transition of the egress scheduling state of the egress scheduler in the data storage device provided in the second embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a data storage device provided in Embodiment 3 of the present invention.
  • FIG. 6 is a flowchart of a data storage method provided by Embodiment 4 of the present invention.
  • FIG. 7 is a flowchart of a data storage method provided by Embodiment 5 of the present invention.
  • FIG. 8 is a flowchart of a data storage method provided by Embodiment 6 of the present invention.
  • FIG. 1 is a flowchart of a data storage device provided by Embodiment 1 of the present invention.
  • the data storage device provided in this embodiment includes a processor 101 and a memory 102.
  • the processor 101 includes: a buffer scheduler 1011, multiple transmission buffers, an interface buffer 1014, and a memory controller 1015.
  • each transmission buffer is respectively connected to the buffer scheduler 1011 and the interface buffer 1014, and the interface buffer 1014 is connected to the memory 102 through the memory controller 1015.
  • the buffer scheduler 1011 is used to control multiple transmission buffers to write data and read and send the data to the interface buffer 1014.
  • the interface buffer 1014 is used to receive the data sent by the transmission buffer if the capacity of the data stored in the interface buffer 1014 is less than the preset capacity threshold. If the capacity of the data stored in the interface buffer 1014 is greater than or equal to the preset capacity threshold Set the capacity threshold, then stop receiving the data sent by the transmission buffer.
  • the memory controller 1015 is used to control the memory 102 to write data from the interface buffer 1014 and store the data.
  • the specific type of stored data is not limited.
  • the data that needs to be stored is data that needs to be continuously generated by the data storage device in this embodiment.
  • the data can be continuously generated by the data generation unit, and the generated data can be single-frame data or multi-frame data, which is not limited in this embodiment.
  • each transmission buffer is connected to the data generation unit, and the buffer scheduler controls one transmission buffer to write data at the same time, wherein each transmission buffer can have equal write permissions, that is, After data is written in one transmission buffer, the other transmission buffer continues to write data.
  • the buffer scheduler controls a transmission buffer to read and send data to the interface buffer 1014 at the same time.
  • Each of the transmission buffers also has equal access to read data, that is, after one transmission buffer finishes reading data, the other transmission buffer continues to read data.
  • FIG. 1 two transmission buffers are included in FIG. 1, namely a first transmission buffer 1012 and a second transmission buffer 1013.
  • each transmission buffer is respectively connected to the interface buffer 1014.
  • the interface buffer 1014 is used to receive the data read by the transmission buffer with read permission, and the interface buffer 1014 receives the read data.
  • the data is read by the transmission buffer with permission, it is judged whether the capacity of the data stored by itself is less than the preset capacity threshold. If the capacity of the data stored by itself is less than the preset capacity threshold, it can be sent to the transmission buffer with read permission A read request is made so that the transmission buffer with read permission reads the data and sends the data to the interface buffer 1014.
  • a read stop request can be sent to the transmission buffer with read permission, so that the transmission buffer with read permission no longer reads data, and waits for the interface
  • the data is sent to the interface buffer 1014 again. This is to ensure that the subsequent memory 102 does not block data in the process of writing data.
  • the preset capacity threshold may be the total capacity value that the interface buffer 1014 can store, or it may be a value less than the total capacity value, which is not limited in this embodiment.
  • the memory controller 1015 controls the memory 102 to write data from the interface buffer 1014 to the memory 102, and the memory 102 stores the written data.
  • the data storage device includes: a processor 101 and a memory 102; the processor 101 includes: a cache scheduler 1011, multiple transmission buffers, an interface buffer 1014, a memory controller 1015; each transmission buffer Connected to the buffer scheduler 1011 and the interface buffer 1014 respectively, the interface buffer 1014 is connected to the memory 102 through the memory controller 1015; the buffer scheduler 1011 is used to control multiple transmission buffers to write data and read data Sent to the interface buffer 1014; the interface buffer 1014, for receiving the data sent by the transmission buffer if the capacity of the data stored in the interface buffer 1014 is less than the preset capacity threshold, if the data stored in the interface buffer 1014 If the data capacity is greater than or equal to the preset capacity threshold, stop receiving the data sent by the transmission buffer; the memory controller 1015 is used to control the memory 102 to write data from the interface buffer 1014 and store the data.
  • the interface buffer 1014 effectively buffers a large amount of data read in the transmission buffer, avoiding the accumulation of data when the back-end memory 102 performs data writing, and thus realizes data Fast storage of data to improve the efficiency of data storage.
  • Figure 2 is a schematic structural diagram of a data storage device provided in Embodiment 2 of the present invention. As shown in Figure 2, the data storage device provided in this embodiment is based on the data storage device provided in Embodiment 1 of the present invention For further refinement of the memory controller 1015 and the cache scheduler 1011, the data storage device provided in this embodiment also includes the following technical solutions.
  • the memory controller 1015 is specifically configured to control the memory to continuously write data from the interface buffer and store the data.
  • the memory controller 1015 controls the memory 102 to continuously write data from the interface buffer 1014 to the memory 102, and the memory 102 stores the written data to ensure that the interface buffer 1014 is
  • the stored data can be read out uninterruptedly, which further increases the storage speed of the data and further improves the efficiency of data storage.
  • the cache scheduler 1011 includes: an ingress scheduler 1011a and an egress scheduler 1011b.
  • the entry scheduler 1011a is used to control the write data to the transmission buffer with the write permission according to the entry scheduling status and the write token information.
  • the egress scheduler 1011b is used to control the transmission buffer with read permission to read data according to the egress scheduling status and the read token information.
  • FIG. 3 is a schematic diagram of the transition of the ingress scheduling state of the ingress scheduler 1011a in the data storage device provided in the second embodiment of the present invention.
  • the ingress scheduling state Including: idle state and multiple transmission buffer write state.
  • the idle state is the initial state of the ingress scheduler 1011a.
  • the multiple transmission buffer writing states include: a first transmission buffer writing state and a second transmission buffer writing state. Wherein, the first transmission buffer writing state indicates that the current state is the first transmission buffer 1012 writing state, and the second transmission buffer writing state indicates that the current state is the second transmission buffer 1013 writing state.
  • the write token information includes the identification of the transmission buffer, and the write token information represents information that a certain transmission buffer has the authority to write data.
  • the entry scheduler 1011a is specifically used to: if the entry scheduling state is an idle state and the write token information is a certain write token information, control the idle state to change to a certain write token Information corresponding to the transmission buffer write status, and control the transmission buffer to write data.
  • the entry scheduler 1011a is also used to update the current transmission buffer write state to an idle state, and update the current write token information to another if the current write data in the transmission buffer reaches the first preset length value.
  • One write token information is also used to update the current transmission buffer write state to an idle state, and update the current write token information to another if the current write data in the transmission buffer reaches the first preset length value.
  • the first preset length value is a preset length value of all the transmission buffers that write data each time.
  • it can be 256 bits or other values, which is not limited in this embodiment.
  • the entry scheduler 1011a is specifically configured to determine the transmission buffer with the longest waiting time for writing according to the waiting time of each transmission buffer, and update the current write token information to the longest waiting time for writing The transmission buffer writes the token information.
  • the waiting time of the transmission buffer to be written is the time interval from the time when the data is written last time to the time when the data writing starts again.
  • the entry scheduler 1011a determines the transmission buffer with the longest waiting time for writing according to the waiting time of each transmission buffer, and updates the current write token information to the longest waiting time for writing
  • the transmission buffer writes the token information, so that multiple transmission buffers have equal write permissions.
  • the waiting time for each transmission buffer to be written is the same, and the sequence of writing data into multiple transmission buffers can be predefined.
  • two transmission buffers are taken as an example for description. That is, the entry scheduling state includes: an idle state and two transmission buffer write states.
  • the entry scheduler 1011a first the entry scheduling state is in the initial state, when there is data to be written, the write token information is the first write token information, that is, the first transmission buffer 1012 has the authority to write data, then
  • the control changes the idle state to the first transmission buffer write state, and controls the first transmission buffer 1012 to write data.
  • the length of the written data is counted. If the data written in the first transmission buffer 1012 reaches the first preset length value, the first transmission buffer is written to The state is updated to the idle state, and a certain write token information is updated.
  • a certain write token information is updated, it is determined that the second transmission buffer 1013 waits for writing longer than the first transmission buffer 1012 waits for writing Time, a certain write token information is updated to the second write token information, indicating that the second transmission buffer 1013 has the authority to write data, and then the control is controlled to change from the idle state to the second transmission buffer writing state, and Control the second transmission buffer 1013 to write data. This cycle is repeated so that the two transmission buffers have equal write permissions and write data equally.
  • the transmission buffer includes: an ingress scheduler 1011a and an egress scheduler 1011b.
  • the entry scheduler 1011a is used to control the transmission buffer with the write permission to write data according to the entry scheduling status and the write token information.
  • the entry scheduling state includes: an idle state and multiple transmission buffer write states; the entry scheduler 1011a is specifically used for: if the entry scheduling state is an idle state and the write token information is a certain write token information, the control will be idle The state jumps to a transmission buffer write state corresponding to a certain write token information, and the transmission buffer is controlled to write data.
  • the entry scheduler 1011a is also used to update the current write status of the transmission buffer to an idle state, and update the current write token information to another write command if the current write data in the transmission buffer reaches the first preset length value.
  • the entry scheduler 1011a is specifically used to determine the transmission buffer with the longest waiting time for writing according to the waiting time of each transmission buffer, and to update the current write token information to the longest waiting time for writing
  • the transmission buffer writes the token information.
  • FIG. 4 is a schematic diagram of the transition of the egress scheduling state of the egress scheduler 1011b in the data storage device provided in the second embodiment of the present invention.
  • the egress scheduling state Including: interface buffer detection status, multiple transmission buffer reading status.
  • the detection state of the interface buffer 1014 is a state of detecting the interface buffer 1014. If there are two transmission buffers, the multiple transmission buffer reading states include: the first transmission buffer reading state and the second transmission Register read status. Wherein, the first transmission buffer read state indicates that the current state is a state where the first transmission buffer 1012 reads data, and the second transmission buffer read state indicates that the current state is a state where the second transmission buffer 1013 reads data.
  • the egress scheduler 1011b is specifically used to: if the egress scheduling state is the interface buffer detection state and the read token information is a certain read token information, control the interface buffer detection state to jump Read the state of the transmission buffer corresponding to a certain read token information, and control the transmission buffer to read data.
  • the egress scheduler 1011b is further configured to update the current transmission buffer read status to the interface buffer detection status if the current read data of the transmission controller reaches the second preset length value, and update the current read The token information is updated to another read token information.
  • the read token information includes the identification of the transmission buffer, and the read token information indicates information that a certain transmission buffer has the right to read data.
  • the second preset length value is a preset length value of data read by all transmission buffers each time.
  • it can be 256 bits or other values, which is not limited in this embodiment.
  • the egress scheduler 1011b is specifically configured to determine the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and update the current read token information to waiting The transmission buffer with the longest reading time reads the token information.
  • the waiting time of the transmission buffer to read is the time interval from the time after the last data read is completed to the time when the data read starts again.
  • the egress scheduler 1011b determines the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and updates the current read token information to the longest waiting time for reading
  • the transmission buffer reads the token information, which enables multiple transmission buffers to have equal read permissions.
  • two transmission buffers are used as an example for description. That is, the egress scheduling status includes: interface buffer detection status, first transmission buffer reading status, and second transmission buffer reading status. Then in the egress scheduler, the egress schedule state is in the initial state first to read data from a certain transmission buffer and transmit the data to the interface buffer 1014.
  • the egress scheduling state is the interface buffer detection state and the read token information is the first read token information, it means that the first transmission buffer 1012 has the read permission, and the egress scheduling state is controlled to jump from the interface buffer detection state to the first
  • a transmission buffer read status controls the first transmission buffer 1012 to read data.
  • the first transmission buffer 1012 reads data, the length of the read data is counted. If the data written in the first transmission buffer 1012 reaches the first preset length value, the first transmission buffer is read Update to the interface buffer detection state, and update the first read token information.
  • the first read token information is updated, it is determined that the second transmission buffer 1013 waits for a read longer than the first transmission buffer 1012 waits Reading time, the first read token information is updated to the second read token information, indicating that the second transmission buffer 1013 has the permission to read data.
  • the detection interface buffer 1014 is ready to receive data, the interface The buffer detection state jumps to the second transmission buffer reading state, and the second transmission buffer 1013 is controlled to read data. This cycle is repeated so that the two transmission buffers have equal read rights and read data equally.
  • the interface buffer 1014 when detecting whether the interface buffer 1014 is ready to receive data, it is checked whether the capacity of the data currently stored in the interface buffer 1014 plus the length of the data to be written next time is less than the preset capacity threshold. If so, the interface buffer is explained 1014 is ready to receive data. If the capacity of the currently stored data plus the length of the data to be written next is greater than the preset capacity threshold, it means that the interface buffer 1014 is not ready to receive data.
  • the buffer scheduler includes: an egress scheduler 1011b and an egress scheduler 1011b, which are used to control the transmission buffer with read permission to read data according to the egress scheduling status and read token information, and the egress
  • the scheduling status includes: interface buffer detection status, multiple transmission buffer reading status; exit scheduler 1011b, specifically used for: if the exit scheduling status is the interface buffer detection status and the read token information is a certain read token information , The detection state of the interface buffer is controlled to jump to the reading state of the transmission buffer corresponding to a certain read token information, and the transmission buffer is controlled to read data.
  • the egress scheduler 1011b is further configured to update the current transmission buffer read status to the interface buffer detection status if the current read data of the transmission controller reaches the second preset length value, and update the current read
  • the token information is updated to another read token information
  • the exit scheduler 1011b is specifically used to determine the transmission buffer with the longest waiting time for reading according to the waiting time of each transmission buffer to update the current read token information In order to wait for the transmission buffer with the longest reading time to read token information, by setting multiple exit scheduling states and writing token information, multiple transmission buffers have equal read permissions, and each transmission buffer can be quickly scheduled to perform Data reading.
  • FIG. 5 is a schematic structural diagram of a data storage device provided in Embodiment 3 of the present invention. As shown in FIG. 5, the data storage device provided in this embodiment is based on the data storage device provided in Embodiment 2 of the present invention. For high frame rate ultrasonic echo signals, the data storage device provided in this embodiment further includes: a transmitting and receiving array component 103, and the processor 101 further includes: at least one sliding window controller 1016.
  • the transmitting and receiving array component 103 is referred to as T/R array component 103 for short.
  • the T/R array component 103 is connected to each sliding window controller 1016.
  • the T/R array assembly 103 is used to transmit ultrasonic excitation signals and receive high frame rate ultrasonic echo signals.
  • the sliding window controller 1016 is used to filter out the signals to be stored from the high frame rate ultrasonic echo signals according to the sliding window parameters, and send the signals to be stored to the corresponding transmission buffer under the control of the buffer scheduler 1011.
  • the high frame rate ultrasound echo signal is the echo signal in high frame rate ultrasound imaging.
  • high frame rate ultrasound imaging has a frame rate much higher than that of traditional ultrasound imaging.
  • Using the high time resolution of high frame rate ultrasound imaging can obtain more information, but using high frame rate ultrasound echo
  • the data volume for signal imaging has greatly increased.
  • the sampling rate is 40MHz
  • the acquisition depth is 4cm
  • the acquisition channel is 128, then the data volume at this time is about 10G per second.
  • the T/R array component 103 is used to receive the high frame rate ultrasonic echo signal, and then send the high frame rate ultrasonic echo signal to the sliding window controller 1016, the sliding window controller 1016 can set the sliding window parameters, Including the start address and window length of the sliding window, which are used to screen high frame rate ultrasonic echo signals.
  • the selected high frame rate ultrasonic echo signals may include single frame or multiple frame echo signals. The unselected echo signals are discarded, the selected high frame rate ultrasound echo signals are signals to be stored, and the selected high frame rate ultrasound echo signals are sent to the corresponding transmission buffer under the control of the buffer scheduler 1011. The corresponding transmission buffer writes the selected high frame frequency ultrasonic echo signal.
  • the size of the selected high frame rate ultrasonic echo signal written depends on the maximum window length in the sliding window controller 1016. If the sliding window controller 1016 includes multiple sliding window controllers 1016, the size of the selected high frame rate ultrasonic echo signal written depends on the maximum value of the window lengths in the multiple sliding window controllers 1016.
  • the structure and function of the cache retriever, transmission buffer, interface buffer 1014, memory controller 1015, and memory 102 are the same as those in the data storage device in the second embodiment of the present invention.
  • the structures and functions of the corresponding devices are similar, so I won't repeat them here.
  • the data is a high frame rate ultrasonic echo signal.
  • the device further includes: a T/R array component 103, and the processor 101 further includes: at least one sliding window controller 1016; a T/R array component 103 is connected to each sliding window controller 1016; the T/R array component 103 is used to transmit ultrasonic excitation signals and receive high frame frequency ultrasonic echo signals; the sliding window controller 1016 is used to change the frame frequency from the high frame frequency according to the sliding window parameters
  • the signals to be stored are filtered out of the ultrasonic echo signals, and the signals to be stored are sent to the corresponding transmission buffer under the control of the buffer scheduler 1011. It can quickly collect and store high frame rate ultrasound signals, which improves the collection and storage efficiency of high frame rate ultrasound signals.
  • FIG. 6 is a flowchart of the data storage method provided by the fourth embodiment of the present invention. As shown in FIG. 6, the execution subject of the data storage method provided by this embodiment is a data storage device, then the data storage provided by this embodiment The method includes the following steps.
  • Step 601 The buffer scheduler controls multiple transmission buffers to write data and read and send the data to the interface buffer.
  • Step 602 If the capacity of the data stored in the interface buffer is less than the preset capacity threshold, the interface buffer receives the data sent by the transmission buffer, and if the capacity of the data stored in the interface buffer is greater than or equal to the preset capacity threshold , The interface buffer stops receiving the data sent by the transmission buffer.
  • Step 603 The memory controller controls the memory to write data from the interface buffer and store the data.
  • the data storage device provided in Embodiment 1 of the present invention can be used to execute the technical solution of the data transmission method in this embodiment.
  • the implementation principle and technical effect are similar, and will not be repeated here.
  • FIG. 7 is a flowchart of the data storage method provided in the fifth embodiment of the present invention.
  • the data storage method provided in this embodiment is based on the data storage method provided in the fourth embodiment of the present invention.
  • step 603 is further refined, where the cache scheduler includes: an ingress scheduler and an egress scheduler. Then, in the method for storing data provided in this embodiment, step 601 in the fourth embodiment specifically includes the following steps.
  • step 601a the portal scheduler controls the transmission buffer with write permission to write data according to the portal scheduling status and the write token information.
  • entry scheduling state includes: idle state and multiple transmission buffer write states.
  • the entry scheduler controls the writing of data to the transmission buffer with the write permission according to the entry scheduling status and the write token information, which specifically includes:
  • the entry scheduling state is the idle state and the write token information is a certain write token information
  • control to change the idle state to the transmission buffer write state corresponding to a certain write token information and control the transmission buffer writing Into the data.
  • Step 601b If the current write data in the transmission buffer reaches the first preset length value, the ingress scheduler updates the current transmission buffer write state to an idle state, and updates the current write token information to another write token information .
  • updating the current write token information to another write token information specifically includes:
  • the entry scheduler determines the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and updates the current write token information to the transmission buffer writing token information with the longest waiting time.
  • Step 601c The egress scheduler controls the transmission buffer with read permission to read data according to the egress scheduling status and the read token information.
  • the egress scheduling status includes: interface buffer detection status, and multiple transmission buffer reading status.
  • the egress scheduler controls the transmission buffer with read permission to read data according to the egress scheduling status and the read token information, which specifically includes:
  • exit scheduling state is the interface buffer detection state and the read token information is a certain read token information
  • control to change the interface buffer detection state to the transmission buffer read state corresponding to a certain read token information and Control the transmission buffer to read data.
  • Step 601d if the current data read by the transmission controller reaches the second preset length value, update the current transmission buffer reading state to the interface buffer detection state, and update the current read token information to another read token information .
  • updating the current read token information to another read token information specifically includes:
  • the egress scheduler determines the transmission buffer with the longest waiting time according to the waiting time of each transmission buffer, and updates the current read token information to the transmission buffer reading token information with the longest waiting time.
  • step 603 the memory controller controls the memory to write data from the interface buffer and store the data, specifically:
  • the memory controller controls the memory to continuously write data from the interface buffer and store the data.
  • the data transmission device provided in the second embodiment of the present invention can be used to implement the technical solution of the data transmission method in this embodiment.
  • the implementation principle and technical effect are similar, and will not be repeated here.
  • FIG. 8 is a flowchart of the data storage method provided in the sixth embodiment of the present invention.
  • the data storage method provided in this embodiment is higher than the data storage method provided in the fifth embodiment of the present invention.
  • Frame frequency ultrasonic echo signal the data storage method provided in this embodiment further includes: the T/R array component transmits an ultrasonic excitation signal and receives a high frame frequency ultrasonic echo signal, and the sliding window controller starts from high according to the sliding window parameters.
  • the data storage method provided in this embodiment includes the following steps.
  • Step 801 the transmitting and receiving array component transmits an ultrasonic excitation signal and receives a high frame rate ultrasonic echo signal.
  • the sliding window controller filters out the signals to be stored from the high frame rate ultrasonic echo signals according to the sliding window parameters, and sends the signals to be stored to the corresponding transmission buffer under the control of the buffer scheduler.
  • Step 803 The buffer scheduler controls multiple transmission buffers to write data and read and send the data to the interface buffer.
  • step 803 is the same as the implementation of steps 601a to 601d in the fifth embodiment of the present invention, and will not be repeated here.
  • Step 804 If the capacity of the data stored in the interface buffer is less than the preset capacity threshold, the interface buffer receives the data sent by the transmission buffer, and if the capacity of the data stored in the interface buffer is greater than or equal to the preset capacity threshold , The interface buffer stops receiving the data sent by the transmission buffer.
  • step 805 the memory controller controls the memory to continuously write data from the interface buffer and store the data.
  • the data storage device provided in the third embodiment of the present invention can be used to execute the technical solution of the data storage method in this embodiment.
  • the implementation principle and technical effect are similar, and will not be repeated here.
  • the seventh embodiment of the present invention also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to implement the method in any one of the first to the third embodiment of the present invention.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of modules is only a logical function division, and there may be other divisions in actual implementation, for example, multiple modules or components can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may be in electrical, mechanical or other forms.
  • the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, or in the form of hardware plus software functional modules.
  • the program code used to implement the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to the processors or controllers of general-purpose computers, special-purpose computers, or other programmable data processing devices, so that when the program codes are executed by the processor or controller, the functions specified in the flowcharts and/or block diagrams/ The operation is implemented.
  • the program code can be executed entirely on the machine, partly executed on the machine, partly executed on the machine and partly executed on the remote machine as an independent software package, or entirely executed on the remote machine or server.
  • a machine-readable medium may be a tangible medium, which may contain or store a program for use by the instruction execution system, apparatus, or device or in combination with the instruction execution system, apparatus, or device.
  • the machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • the machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing.
  • machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • RAM random access memory
  • ROM read-only memory
  • EPROM or flash memory erasable programmable read-only memory
  • CD-ROM portable compact disk read only memory
  • magnetic storage device or any suitable combination of the above.

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Abstract

一种数据存储的装置、方法及可读存储介质，该数据存储的装置，包括：处理器（101）和存储器（102）；处理器（101）包括：缓存调度器（1011），多个传输缓存器（1012,1013），接口缓存器（1014），内存控制器（1015）；每个传输缓存器（1012,1013）分别与缓存调度器（1011）和接口缓存器（1014）连接，接口缓存器（1014）通过内存控制器（1015）与存储器（102）连接；缓存调度器（1011），用于控制多个传输缓存器（1012,1013）对数据进行写入并将数据读出发送给接口缓存器（1014）；接口缓存器（1014），用于若接口缓存器（1014）中的存储的数据的容量小于预设容量阈值，则接收传输缓存器（1012,1013）发送的数据，若接口缓存器（1014）中的存储的数据的容量大于或等于预设容量阈值，则停止接收传输缓存器（1012,1013）发送的数据；内存控制器（1015），用于控制存储器（102）从接口缓存器（1014）中写入数据并对数据进行存储，能够提高数据存储的效率。

Description

数据存储的装置、方法及可读存储介质 技术领域
本发明实施例涉及大数据存储技术领域，尤其涉及一种数据存储的装置、方法及可读存储介质。
背景技术
随着互联网的发展以及科技的进步，在各个科技行业出现了数据的爆发式增长，形成了大量数据。例如在超高速超声成像技术领域，超高速超声成像系统产生了大量数据。这些数据需要在数据大量采集的过程中快速进行存储。
现有技术中并没有对大量产生的数据进行快速存储的方法，造成了存储缓慢，存储效率较低。
发明内容
本发明实施例提供一种数据存储的装置、方法及可读存储介质，解决了现有技术中存储缓慢，存储效率较低的技术问题。
第一方面，本发明实施例提供一种数据存储的装置，包括：处理器和存储器；所述处理器包括：缓存调度器，多个传输缓存器，接口缓存器，内存控制器；
每个所述传输缓存器分别与所述缓存调度器和所述接口缓存器连接，所述接口缓存器通过所述内存控制器与所述存储器连接；
所述缓存调度器，用于控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器；
所述接口缓存器，用于若所述接口缓存器中的存储的数据的容量小于预设容量阈值，则接收所述传输缓存器发送的数据，若所述接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则停止接收所述传输缓存器发送的数据；
所述内存控制器，用于控制所述存储器从所述接口缓存器中写入数据并对所述数据进行存储。
进一步地，如上所述的装置，所述内存控制器，具体用于控制所述存储器不间断地从所述接口缓存器中写入数据并对所述数据进行存储。
进一步地，如上所述的装置，所述缓存调度器，包括：入口调度器和出口调度器；
所述入口调度器，用于根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据；
所述出口调度器，用于根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
进一步地，如上所述的装置，所述入口调度状态包括：空闲状态和多个传输缓存器写入状态；
所述入口调度器，具体用于：若所述入口调度状态为空闲状态且所述写令牌信息为某一写令牌信息，则控制将所述空闲状态跳变为所述某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
进一步地，如上所述的装置，所述入口调度器，还用于若当前传输缓存器写入数据达到第一预设长度值，则将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
进一步地，如上所述的装置，所述入口调度器，具体用于根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
进一步地，如上所述的装置，所述出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态；
所述出口调度器，具体用于：若所述出口调度状态为接口缓存器检测状态且所述读令牌信息为某一读令牌信息，则控制将所述接口缓存器检测状态跳变为所述某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
进一步地，如上所述的装置，所述出口调度器，还用于若当前传输控制器读取数据达到第二预设长度值，则将所述当前传输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息。
进一步地，如上所述的装置，所述出口调度器，具体用于，根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
进一步地，如上所述的装置，所述数据为高帧频超声回波信号，所述装置还包括：发射接收阵列组件，所述处理器还包括：至少一个滑动窗控制器；
所述发射接收阵列组件与每个所述滑动窗控制器连接；
所述发射接收阵列组件，用于发射超声激励信号并接收高帧频超声回波信号；
所述滑动窗控制器，用于根据滑动窗参数从所述高帧频超声回波信号中筛选出待存储的信号，并将所述待存储的信号在所述缓存调度器的控制下发送给对应的传输缓存器。
第二方面，本发明实施例提供一种数据存储的方法，包括：缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器；
若所述接口缓存器中的存储的数据的容量小于预设容量阈值，则所述接口缓存器接收所述传输缓存器发送的数据，若所述接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则所述接口缓存器停止接收所述传输缓存器发送的数据；
所述内存控制器控制所述存储器从所述接口缓存器中写入数据并对数据进行存储。
进一步地，如上所述的方法，所述内存控制器控制所述存储器从所述接口缓存器中写入数据并对数据进行存储，具体包括：
所述内存控制器控制所述存储器不间断地从所述接口缓存器中写入数据并对所述数据进行存储。
进一步地，如上所述的方法，所述缓存调度器，包括：入口调度器和出口调度器；
所述缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器，具体包括：
所述入口调度器根据入口调度状态和写令牌信息控制拥有写入权限 的传输缓存器写入数据；
所述出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
进一步地，如上所述的方法，所述入口调度状态包括：空闲状态和多个传输缓存器写入状态；
所述入口调度器根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据，具体包括：
若所述入口调度状态为空闲状态且所述写令牌信息为某一写令牌信息，则控制将所述空闲状态跳变为所述某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
进一步地，如上所述的方法，所述控制该传输缓存器写入数据之后，还包括：
若当前传输缓存器写入数据达到第一预设长度值，则所述入口调度器将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
进一步地，如上所述的方法，所述将当前写令牌信息更新为另一写令牌信息，具体包括：
所述入口调度器根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
进一步地，如上所述的方法，所述出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态；
所述出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据，具体包括：
若所述出口调度状态为接口缓存器检测状态且所述读令牌信息为某一读令牌信息，则控制将所述接口缓存器检测状态跳变为所述某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
进一步地，如上所述的方法，所述控制该传输缓存器读取数据之后，还包括：
若当前传输控制器读取数据达到第二预设长度值，则将所述当前传 输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息。
进一步地，如上所述的方法，将所述当前读令牌信息更新为另一读令牌信息，具体包括：
所述出口调度器根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
进一步地，如上所述的方法，所述数据为高帧频超声回波信号，所述缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器之前，还包括：
发射接收阵列组件发射超声激励信号并接收高帧频超声回波信号；
滑动窗控制器根据滑动窗参数从所述高帧频超声回波信号中筛选出待存储的信号，并将所述待存储的信号在所述缓存调度器的控制下发送给对应的传输缓存器。
第三方面，本发明实施例提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行以实现第二方面任一项所述的方法。
本发明实施例提供一种数据存储的装置、方法及可读存储介质，该数据存储的装置，包括：处理器和存储器；处理器包括：缓存调度器，多个传输缓存器，接口缓存器，内存控制器；每个传输缓存器分别与缓存调度器和接口缓存器连接，接口缓存器通过内存控制器与存储器连接；缓存调度器，用于控制多个传输缓存器对数据进行写入并将数据读出发送给接口缓存器；接口缓存器，用于若接口缓存器中的存储的数据的容量小于预设容量阈值，则接收传输缓存器发送的数据，若接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则停止接收传输缓存器发送的数据；内存控制器，用于控制存储器从接口缓存器中写入数据并对数据进行存储。由于缓存调度器能够对数据进行有序的调度，接口缓存器对传输缓存器中读取的大量数据进行有效的缓存，避免后端存储器进行数据写入时数据的堆积，进而实现数据的快速存储，提高数据存储的效率。
应当理解，上述发明内容部分中所描述的内容并非旨在限定本发明的实施例的关键或重要特征，亦非用于限制本发明的范围。本发明的其它特征将通过以下的描述变得容易理解。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一提供的数据存储的装置的结构示意图；
图2为本发明实施例二提供的数据存储的装置的结构示意图；
图3为本发明实施例二提供的数据存储的装置中入口调度器的入口调度状态的跳转示意图；
图4为本发明实施例二提供的数据存储的装置中出口调度器的出口调度状态的跳转示意图；
图5为本发明实施例三提供的数据存储的装置的结构示意图；
图6为本发明实施例四提供的数据存储的方法的流程图；
图7为本发明实施例五提供的数据存储的方法的流程图；
图8为本发明实施例六提供的数据存储的方法的流程图。
附图标记
101-处理器 1011-缓存调度器 1011a-入口调度器 1011b-出口调度器 1012-第一传输缓存器 1013-第二传输缓存器 1014-接口缓存器 1015-内存控制器 1016-滑动窗控制器 102-存储器 103-发射接收阵列组件
具体实施方式
下面将参照附图更详细地描述本发明的实施例。虽然附图中显示了本发明的某些实施例，然而应当理解的是，本发明可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本发明。应当理解的是，本发明的附图 及实施例仅用于示例性作用，并非用于限制本发明的保护范围。
本发明实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明实施例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
实施例一
图1为本发明实施例一提供的数据存储的装置的流程图，如图1所示，本实施例提供的数据存储的装置包括：处理器101和存储器102。处理器101包括：缓存调度器1011，多个传输缓存器，接口缓存器1014，内存控制器1015。
其中，每个传输缓存器分别与缓存调度器1011和接口缓存器1014连接，接口缓存器1014通过内存控制器1015与存储器102连接。
具体地，本实施例中，缓存调度器1011，用于控制多个传输缓存器对数据进行写入并将数据读出发送给接口缓存器1014。接口缓存器1014，用于若接口缓存器1014中的存储的数据的容量小于预设容量阈值，则接收传输缓存器发送的数据，若接口缓存器1014中的存储的数据的容量大于或等于预设容量阈值，则停止接收传输缓存器发送的数据。内存控制器1015，用于控制存储器102从接口缓存器1014中写入数据并对数据进行存储。
本实施例中，对存储的数据的具体类型不作限定。需要存储的数据为不断生成需要采用本实施例中的数据存储的装置进行不断存储的数据。数据可由数据生成单元不断生成，生成的可以为单帧数据或多帧数据，本实施例中对此不作限定。
具体地，本实施例中，每个传输缓存器与数据生成单元连接，缓存调度器同一时间控制一个传输缓存器对数据进行写入，其中每个传输缓存器可拥有均等的写入权限，即可在一个传输缓存器写入数据后，另一传输缓存器继续写入数据。同时缓存调度器同一时间控制一个传输缓存器将数据读出发送给接口缓存器1014。其中每 个传输缓存器也拥有均等的读取数据的权限，即可在一个传输缓存器读取数据完毕后，另一传输缓存器继续读取数据。
其中，在图1中包括两个传输缓存器，分别为第一传输缓存器1012和第二传输缓存器1013。
具体地，本实施例中，每个传输缓存器分别与接口缓存器1014连接，接口缓存器1014用于接收有读取权限的传输缓存器读取的数据，在接口缓存器1014接收有读取权限的传输缓存器读取的数据时，判断自身存储的数据的容量是否小于预设容量阈值，若自身存储的数据的容量小于预设容量阈值，则可向具有读取权限的传输缓存器发送读取请求，以使有读取权限的传输缓存器读取数据并将数据发送给接口缓存器1014。若自身存储的数据的容量大于或等于预设容量阈值，则可向具有读取权限的传输缓存器发送停止读取请求，以使有读取权限的传输缓存器不再读取数据，等待接口缓存器1014中存储的数据的容量小于预设容量阈值时再次向接口缓存器1014发送数据。以保证后续的存储器102在写入数据的过程中不会发生数据的阻塞。
其中，预设容量阈值可以为接口缓存器1014能够存储的容量总值，也可以为小于容量总值的数值，本实施例中对此不作限定。
具体地，本实施例中，内存控制器1015控制存储器102从接口缓存器1014中将数据写入到存储器102中，存储器102对写入的数据进行存储。
本实施例提供的数据存储的装置，包括：处理器101和存储器102；处理器101包括：缓存调度器1011，多个传输缓存器，接口缓存器1014，内存控制器1015；每个传输缓存器分别与缓存调度器1011和接口缓存器1014连接，接口缓存器1014通过内存控制器1015与存储器102连接；缓存调度器1011，用于控制多个传输缓存器对数据进行写入并将数据读出发送给接口缓存器1014；接口缓存器1014，用于若接口缓存器1014中的存储的数据的容量小于预设容量阈值，则接收传输缓存器发送的数据，若接口缓存器1014中的存储的数据的容量大于或等于预设容量阈值，则停止接收传输缓存器发送的数据；内存控制器1015，用于控制存储器102从接口缓存器1014中写入数据并对数据进行存储。由于缓存调度器1011能够对数据进行有序的调度，接口缓存器1014对传输缓存器中读取的大量数据进行有效的缓存，避免后端存储器102进行数据写入时数据的堆积， 进而实现数据的快速存储，提高数据存储的效率。
实施例二
图2为本发明实施例二提供的数据存储的装置的结构示意图，如图2所示，本实施例提供的数据存储的装置，是在本发明实施例一提供的数据存储的装置的基础上，对内存控制器1015，缓存调度器1011的进一步细化，则本实施例提供的数据存储的装置中还包括以下技术方案。
进一步地，本实施例中，内存控制器1015，具体用于控制所述存储器不间断地从所述接口缓存器中写入数据并对所述数据进行存储。
具体地，本实施例中，内存控制器1015控制存储器102不间断地从接口缓存器1014中将数据写入到存储器102中，存储器102对写入的数据进行存储，以保证接口缓存器1014中存储的数据能够不间断地读出，进一步提高了数据的存储速度，进一步提高数据存储的效率。
进一步地，本实施例中，缓存调度器1011包括：入口调度器1011a和出口调度器1011b。
进一步地，入口调度器1011a，用于根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据。出口调度器1011b，用于根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
具体地，本实施例中，图3为本发明实施例二提供的数据存储的装置中入口调度器1011a的入口调度状态的跳转示意图，如图3所示，本实施例中，入口调度状态包括：空闲状态和多个传输缓存器写入状态。空闲状态为入口调度器1011a的初始状态。若传输缓存器为两个，则多个传输缓存器写入状态包括：第一传输缓存器写入状态和第二传输缓存器写入状态。其中，第一传输缓存器写入状态表示当前状态为第一传输缓存器1012写入状态，第二传输缓存器写入状态表示当前状态为第二传输缓存器1013写入状态。
其中，写令牌信息中包括传输缓存器的标识，写令牌信息表示某一传输缓存器具有写数据的权限的信息。
进一步地，本实施例中，入口调度器1011a，具体用于：若入口调度状态为空闲状态且写令牌信息为某一写令牌信息，则控制将空闲状态跳 变为某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
进一步地，入口调度器1011a，还用于若当前传输缓存器写入数据达到第一预设长度值，则将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
其中，第一预设长度值为预先设定的所有传输缓存器每次写入数据的长度值。如可以为256bit，或其他数值，本实施例中对此不作限定。
进一步地，入口调度器1011a，具体用于根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
其中，传输缓存器的等待写入时间为上一次写入数据完毕后的时刻到再次开始写入数据时刻的时间间隔。
具体地，本实施例中，入口调度器1011a根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息，能够使多个传输缓存器具有均等写入权限。在初始未进行数据写入时，各传输缓存器等待写入时间相同，可预先定义多个传输缓存器写入数据的顺序。本实施例中，以两个传输缓存器为例进行说明。即入口调度状态包括：空闲状态和两个传输缓存器写入状态。则在入口调度器1011a中，首先入口调度状态处于初始状态，在有数据需要写入时，写令牌信息为第一写令牌信息，即第一传输缓存器1012具有写数据的权限，则当入口调度状态为空闲状态且写令牌信息为第一写令牌信息时，则控制将空闲状态跳变为第一传输缓存器写入状态，并控制第一传输缓存器1012写入数据。在第一传输缓存器1012写入数据的过程中，对写入数据的长度进行计数，若第一传输缓存器1012写入数据达到第一预设长度值，则将第一传输缓存器写入状态更新为空闲状态，并对某一写令牌信息进行更新，在对某一写令牌信息进行更新时，确定第二传输缓存器1013等待写入时间长于第一传输缓存器1012等待写入时间，则将某一写令牌信息更新为第二写令牌信息，表示第二传输缓存器1013具有写数据的权限，则控制将空闲状态跳变为第二传输缓存器写入状态，并控制第二传输缓存器1013写入数据。如此 循环反复，使两个传输缓存器具有均等写入权限，并均等进行数据的写入。
本实施例提供的数据存储的装置中，传输缓存器包括：入口调度器1011a和出口调度器1011b。入口调度器1011a，用于根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据。入口调度状态包括：空闲状态和多个传输缓存器写入状态；入口调度器1011a，具体用于：若入口调度状态为空闲状态且写令牌信息为某一写令牌信息，则控制将空闲状态跳变为某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。入口调度器1011a，还用于若当前传输缓存器写入数据达到第一预设长度值，则将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息，入口调度器1011a，具体用于根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。通过设置多个入口调度状态及写令牌信息，使多个传输缓存器具有均等写入权限，并能够快读调度每个传输缓存器进行数据的写入。
进一步地，本实施例中，图4为本发明实施例二提供的数据存储的装置中出口调度器1011b的出口调度状态的跳转示意图，如图4所示，本实施例中，出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态。
其中，接口缓存器1014检测状态为对接口缓存器1014进行检测的状态，若传输缓存器为两个，则多个传输缓存器读取状态包括：第一传输缓存器读取状态和第二传输缓存器读取状态。其中，第一传输缓存器读取状态表示当前状态为第一传输缓存器1012读取数据的状态，第二传输缓存器读取状态表示当前状态为第二传输缓存器1013读取数据的状态。
进一步地，本实施例中，出口调度器1011b，具体用于：若出口调度状态为接口缓存器检测状态且读令牌信息为某一读令牌信息，则控制将接口缓存器检测状态跳变为某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
出口调度器1011b，还用于若当前传输控制器读取数据达到第二预设 长度值，则将所述当前传输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息。
其中，读令牌信息中包括传输缓存器的标识，读令牌信息表示某一传输缓存器具有读取数据权限的信息。
其中，第二预设长度值为预先设定的所有传输缓存器每次读取数据的长度值。如可以为256bit，或其他数值，本实施例中对此不作限定。
进一步地，本实施例中，出口调度器1011b，具体用于，根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
其中，传输缓存器的等待读取时间为上一次读取数据完毕后的时刻到再次开始读取数据时刻的时间间隔。
具体地，本实施例中，出口调度器1011b根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息，能够使多个传输缓存器拥有均等读取权限，本实施例中，以两个传输缓存器为例进行说明。即出口调度状态包括：接口缓存器检测状态，第一传输缓存器读取状态，第二传输缓存器读取状态。则在出口调度器中，首先出口调度状态处于初始状态，以从某一传输缓存器读取数据并将数据传输到接口缓存器1014中。若出口调度状态为接口缓存器检测状态且读令牌信息为第一读令牌信息，则表示第一传输缓存器1012具有读取权限，控制出口调度状态从接口缓存器检测状态跳变为第一传输缓存器读取状态，控制第一传输缓存器1012读取数据。在第一传输缓存器1012读取数据过程中，对读取的数据长度进行计数，若第一传输缓存器1012写入数据达到第一预设长度值，则将第一传输缓存器读取状态更新为接口缓存器检测状态，并对第一读令牌信息进行更新，在对第一读令牌信息进行更新时，确定第二传输缓存器1013等待读取时间长于第一传输缓存器1012等待读取时间，则将第一读令牌信息更新为第二读令牌信息，表示第二传输缓存器1013具有读取数据的权限，在检测接口缓存器1014做好接收数据准备后，将接口缓存器检测状态跳变为第二传输缓存器读取状态，控制第二传输缓存器1013读取数据。如此循环反复，使两个传输缓存器具有均等读取权 限，并均等进行数据的读取。
其中，在检测接口缓存器1014是否做好接收数据准备时，检查接口缓存器1014当前存储的数据的容量加上下次写入数据的长度后是否小于预设容量阈值，若是，则说明接口缓存器1014做好接收数据准备，若当前存储的数据的容量加上下次写入数据的长度后大于预设容量阈值，则说明接口缓存器1014没有做好接收数据准备。
本实施例提供的数据传输的装置，缓存调度器包括：出口调度器1011b，出口调度器1011b，用于根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据，出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态；出口调度器1011b，具体用于：若出口调度状态为接口缓存器检测状态且读令牌信息为某一读令牌信息，则控制将接口缓存器检测状态跳变为某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。出口调度器1011b，还用于若当前传输控制器读取数据达到第二预设长度值，则将所述当前传输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息，出口调度器1011b，具体用于，根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息，通过设置多个出口调度状态及写令牌信息，使多个传输缓存器具有均等读取权限，能够快速调度每个传输缓存器进行数据的读取。
实施例三
图5为本发明实施例三提供的数据存储的装置的结构示意图，如图5所示，本实施例提供的数据存储的装置在本发明实施例二提供的数据存储的装置的基础上，数据为高帧频超声回波信号，则本实施例提供的数据存储的装置还包括：发射接收阵列组件103，处理器101还包括：至少一个滑动窗控制器1016。
其中，发射接收阵列组件103简称为：T/R阵列组件103。
其中，T/R阵列组件103与每个滑动窗控制器1016连接。
进一步地，本实施例中，T/R阵列组件103，用于发射超声激励信号 并接收高帧频超声回波信号。滑动窗控制器1016，用于根据滑动窗参数从高帧频超声回波信号中筛选出待存储的信号，并将待存储的信号在缓存调度器1011的控制下发送给对应的传输缓存器。
其中，高帧频超声回波信号是在高帧频超声成像中的回波信号。高帧频超声成像相较于传统超声成像，帧频远高于传统超声成像的帧频，利用高帧频超声成像的高时间分辨率可以得到更多的信息，但采用高帧频超声回波信号进行成像的数据量大幅度增加，利用采用双精度采样，采样率为40MHz，采集深度为4cm，采集通道为128个，则此时的数据量约为每秒10G的数据量。
本实施例中，T/R阵列组件103用于接收高帧频超声回波信号，然后将高帧频超声回波信号发送给滑动窗控制器1016，滑动窗控制器1016能够设置滑动窗参数，包括滑动窗的起始地址和窗长，用于对高帧频超声回波信号进行筛选，选取的高帧频超声回波信号可以包括单帧或多帧回波信号。未选取的回波信号进行丢弃，选取的高帧频超声回波信号为待存储的信号，将选取的高帧频超声回波信号在缓存调度器1011的控制下发送给对应的传输缓存器。对应的传输缓存器对选取的高帧频超声回波信号进行写入。写入的选取的高帧频超声回波信号的大小取决于滑动窗控制器1016中窗长的最大值。若滑动窗控制器1016包括多个，则写入的选取的高帧频超声回波信号的大小取决于多个滑动窗控制器1016中的窗长的最大值。
本实施例中的数据的存储装置中，缓存调取器，传输缓存器，接口缓存器1014，内存控制器1015及存储器102的结构和功能与本发明实施例二中的数据的存储装置中的对应器件的结构和功能相似，在此不再一一赘述。
本实施例提供的数据存储的装置，数据为高帧频超声回波信号，装置还包括：T/R阵列组件103，处理器101还包括：至少一个滑动窗控制器1016；T/R阵列组件103与每个滑动窗控制器1016连接；T/R阵列组件103，用于发射超声激励信号并接收高帧频超声回波信号；滑动窗控制器1016，用于根据滑动窗参数从高帧频超声回波信号中筛选出待存储的信号，并将待存储的信号在缓存调度器1011的控制下发送给对应的传输 缓存器。能够对高帧频超声信号进行快速采集和存储，提高了高帧频超声信号的采集和存储效率。
实施例四
图6为本发明实施例四提供的数据存储的方法的流程图，如图6所示，本实施例提供的数据存储的方法的执行主体为数据存储的装置，则本实施例提供的数据存储的方法包括以下步骤。
步骤601，缓存调度器控制多个传输缓存器对数据进行写入并将数据读出发送给接口缓存器。
步骤602，若接口缓存器中的存储的数据的容量小于预设容量阈值，则接口缓存器接收传输缓存器发送的数据，若接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则接口缓存器停止接收传输缓存器发送的数据。
步骤603，内存控制器控制存储器从接口缓存器中写入数据并对数据进行存储。
本实施例中，采用本发明实施例一中提供的数据存储的装置可以执行本实施例中的数据传输的方法的技术方案。其实现原理和技术效果类似，此处不再一一赘述。
实施例五
图7为本发明实施例五提供的数据存储的方法的流程图，如图7所示，本实施例提供的数据存储的方法在本发明实施例四提供的数据存储的方法上，对步骤601和步骤603的进一步地细化，其中，缓存调度器，包括：入口调度器和出口调度器。则本实施例提供的数据存储的方法在实施例四中的步骤601具体包括以下步骤。
步骤601a，入口调度器根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据。
进一步地，入口调度状态包括：空闲状态和多个传输缓存器写入状态。
相应地，本实施例中，入口调度器根据入口调度状态和写令牌信息 控制向拥有写入权限的传输缓存器写入数据，具体包括：
若入口调度状态为空闲状态且写令牌信息为某一写令牌信息，则控制将空闲状态跳变为某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
步骤601b，若当前传输缓存器写入数据达到第一预设长度值，则入口调度器将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
进一步地，本实施例中，将当前写令牌信息更新为另一写令牌信息具体包括：
入口调度器根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
步骤601c，出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
进一步地，本实施例中，出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态。
相应地，本实施例中，出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据，具体包括：
若出口调度状态为接口缓存器检测状态且读令牌信息为某一读令牌信息，则控制将接口缓存器检测状态跳变为某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
步骤601d，若当前传输控制器读取数据达到第二预设长度值，则将当前传输缓存器读取状态更新为接口缓存器检测状态，将当前读令牌信息更新为另一读令牌信息。
进一步地，本实施例中，将当前读令牌信息更新为另一读令牌信息，具体包括：
出口调度器根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
进一步地，本实施例中，步骤603，内存控制器控制存储器从接口缓 存器中写入数据并对数据进行存储，具体为：
内存控制器控制存储器不间断地从接口缓存器中写入数据并对数据进行存储。
本实施例中，采用本发明实施例二中提供的数据传输的装置可以执行本实施例中的数据传输的方法的技术方案。其实现原理和技术效果类似，此处不再一一赘述。
实施例六
图8为本发明实施例六提供的数据存储的方法的流程图，如图8所示，本实施例提供的数据存储的方法在本发明实施例五提供的数据存储的方法上，数据为高帧频超声回波信号，则本实施例提供的数据存储的方法还包括：T/R阵列组件发射超声激励信号并接收高帧频超声回波信号，及滑动窗控制器根据滑动窗参数从高帧频超声回波信号中筛选出待存储的信号，并将待存储的信号在缓存调度器的控制下发送给对应的传输缓存器的步骤。则本实施例提供的数据存储的方法包括以下步骤。
步骤801，发射接收阵列组件发射超声激励信号并接收高帧频超声回波信号。
步骤802，滑动窗控制器根据滑动窗参数从高帧频超声回波信号中筛选出待存储的信号，并将待存储的信号在缓存调度器的控制下发送给对应的传输缓存器。
步骤803，缓存调度器控制多个传输缓存器对数据进行写入并将数据读出发送给接口缓存器。
本实施例中，步骤803的实现方式与本发明实施例五中的步骤601a-步骤601d的实现方式相同，在此不再一一赘述。
步骤804，若接口缓存器中的存储的数据的容量小于预设容量阈值，则接口缓存器接收传输缓存器发送的数据，若接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则接口缓存器停止接收传输缓存器发送的数据。
步骤805，内存控制器控制存储器不间断地从接口缓存器中写入数据并对数据进行存储。
本实施例中，采用本发明实施例三中提供的数据存储的装置可以执行本实施例中的数据存储的方法的技术方案。其实现原理和技术效果类似，此处不再一一赘述。
实施例七
本发明实施例七还提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行以实现如本发明实施例一至实施例三任一项的方法。
在本发明所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
用于实施本发明的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本发明的上下文中，机器可读介质可以是有形的介质，其可以包含或 存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (21)

  1. 一种数据存储的装置，其特征在于，包括：处理器和存储器；所述处理器包括：缓存调度器，多个传输缓存器，接口缓存器，内存控制器；
    每个所述传输缓存器分别与所述缓存调度器和所述接口缓存器连接，所述接口缓存器通过所述内存控制器与所述存储器连接；
    所述缓存调度器，用于控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器；
    所述接口缓存器，用于若所述接口缓存器中的存储的数据的容量小于预设容量阈值，则接收所述传输缓存器发送的数据，若所述接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则停止接收所述传输缓存器发送的数据；
    所述内存控制器，用于控制所述存储器从所述接口缓存器中写入数据并对所述数据进行存储。
  2. 根据权利要求1所述的装置，其特征在于，所述内存控制器，具体用于控制所述存储器不间断地从所述接口缓存器中写入数据并对所述数据进行存储。
  3. 根据权利要求1所述的装置，其特征在于，所述缓存调度器，包括：入口调度器和出口调度器；
    所述入口调度器，用于根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据；
    所述出口调度器，用于根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
  4. 根据权利要求3所述的装置，其特征在于，所述入口调度状态包括：空闲状态和多个传输缓存器写入状态；
    所述入口调度器，具体用于：若所述入口调度状态为空闲状态且所述写令牌信息为某一写令牌信息，则控制将所述空闲状态跳变为所述某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
  5. 根据权利要求4所述的装置，其特征在于，所述入口调度器，还 用于若当前传输缓存器写入数据达到第一预设长度值，则将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
  6. 根据权利要求5所述的装置，其特征在于，所述入口调度器，具体用于根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
  7. 根据权利要求2所述的装置，其特征在于，所述出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态；
    所述出口调度器，具体用于：若所述出口调度状态为接口缓存器检测状态且所述读令牌信息为某一读令牌信息，则控制将所述接口缓存器检测状态跳变为所述某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
  8. 根据权利要求7所述的装置，其特征在于，所述出口调度器，还用于若当前传输控制器读取数据达到第二预设长度值，则将所述当前传输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息。
  9. 根据权利要求8所述的装置，其特征在于，所述出口调度器，具体用于，根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
  10. 根据权利要求1所述的装置，其特征在于，所述数据为高帧频超声回波信号，所述装置还包括：发射接收阵列组件，所述处理器还包括：至少一个滑动窗控制器；
    所述发射接收阵列组件与每个所述滑动窗控制器连接；
    所述发射接收阵列组件，用于发射超声激励信号并接收高帧频超声回波信号；
    所述滑动窗控制器，用于根据滑动窗参数从所述高帧频超声回波信号中筛选出待存储的信号，并将所述待存储的信号在所述缓存调度器的控制下发送给对应的传输缓存器。
  11. 一种数据存储的方法，其特征在于，包括：
    缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器；
    若所述接口缓存器中的存储的数据的容量小于预设容量阈值，则所述接口缓存器接收所述传输缓存器发送的数据，若所述接口缓存器中的存储的数据的容量大于或等于预设容量阈值，则所述接口缓存器停止接收所述传输缓存器发送的数据；
    所述内存控制器控制所述存储器从所述接口缓存器中写入数据并对数据进行存储。
  12. 根据权利要求11所述的方法，其特征在于，所述内存控制器控制所述存储器从所述接口缓存器中写入数据并对数据进行存储，具体包括：
    所述内存控制器控制所述存储器不间断地从所述接口缓存器中写入数据并对所述数据进行存储。
  13. 根据权利要求11所述的方法，其特征在于，所述缓存调度器，包括：入口调度器和出口调度器；
    所述缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器，具体包括：
    所述入口调度器根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据；
    所述出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据。
  14. 根据权利要求13所述的方法，其特征在于，所述入口调度状态包括：空闲状态和多个传输缓存器写入状态；
    所述入口调度器根据入口调度状态和写令牌信息控制拥有写入权限的传输缓存器写入数据，具体包括：
    若所述入口调度状态为空闲状态且所述写令牌信息为某一写令牌信息，则控制将所述空闲状态跳变为所述某一写令牌信息对应的传输缓存器写入状态，并控制该传输缓存器写入数据。
  15. 根据权利要求14所述的方法，其特征在于，所述控制该传输缓 存器写入数据之后，还包括：
    若当前传输缓存器写入数据达到第一预设长度值，则所述入口调度器将当前传输缓存器写入状态更新为空闲状态，将当前写令牌信息更新为另一写令牌信息。
  16. 根据权利要求15所述的方法，其特征在于，所述将当前写令牌信息更新为另一写令牌信息，具体包括：
    所述入口调度器根据每个传输缓存器等待写入时间确定等待写入时间最长的传输缓存器，将所述当前写令牌信息更新为等待写入时间最长的传输缓存器写令牌信息。
  17. 根据权利要求11所述的方法，其特征在于，所述出口调度状态包括：接口缓存器检测状态，多个传输缓存器读取状态；
    所述出口调度器根据出口调度状态和读令牌信息控制拥有读取权限的传输缓存器读取数据，具体包括：
    若所述出口调度状态为接口缓存器检测状态且所述读令牌信息为某一读令牌信息，则控制将所述接口缓存器检测状态跳变为所述某一读令牌信息对应的传输缓存器读取状态，并控制该传输缓存器读取数据。
  18. 根据权利要求17所述的方法，其特征在于，所述控制该传输缓存器读取数据之后，还包括：
    若当前传输控制器读取数据达到第二预设长度值，则将所述当前传输缓存器读取状态更新为所述接口缓存器检测状态，将所述当前读令牌信息更新为另一读令牌信息。
  19. 根据权利要求18所述的方法，其特征在于，将所述当前读令牌信息更新为另一读令牌信息，具体包括：
    所述出口调度器根据每个传输缓存器等待读取时间确定等待读取时间最长的传输缓存器，将所述当前读令牌信息更新为等待读取时间最长的传输缓存器读令牌信息。
  20. 根据权利要求11所述的方法，其特征在于，所述数据为高帧频超声回波信号，所述缓存调度器控制多个所述传输缓存器对数据进行写入并将所述数据读出发送给接口缓存器之前，还包括：
    发射接收阵列组件发射超声激励信号并接收高帧频超声回波信号；
    滑动窗控制器根据滑动窗参数从所述高帧频超声回波信号中筛选出待存储的信号，并将所述待存储的信号在所述缓存调度器的控制下发送给对应的传输缓存器。
  21. 一种计算机可读存储介质，其特征在于，其上存储有计算机程序，所述计算机程序被处理器执行以实现如权利要求1-10中任一项所述的方法。
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