WO2020188807A1 - 表示装置 - Google Patents

表示装置 Download PDF

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Publication number
WO2020188807A1
WO2020188807A1 PCT/JP2019/011802 JP2019011802W WO2020188807A1 WO 2020188807 A1 WO2020188807 A1 WO 2020188807A1 JP 2019011802 W JP2019011802 W JP 2019011802W WO 2020188807 A1 WO2020188807 A1 WO 2020188807A1
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WO
WIPO (PCT)
Prior art keywords
display device
insulating film
electrode
layer
convex portion
Prior art date
Application number
PCT/JP2019/011802
Other languages
English (en)
French (fr)
Inventor
村上 晋三
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2019/011802 priority Critical patent/WO2020188807A1/ja
Priority to US17/436,650 priority patent/US20220190075A1/en
Publication of WO2020188807A1 publication Critical patent/WO2020188807A1/ja

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/124Insulating layers formed between TFT elements and OLED elements
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    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10Substrates, e.g. flexible substrates
    • H10K77/111Flexible substrates

Definitions

  • the present invention relates to a display device.
  • a self-luminous organic EL display device that uses an organic EL (electroluminescence) element has attracted attention.
  • an organic EL element various films, and the like are formed on a flexible resin substrate (hereinafter, also referred to as "flexible substrate"), and a driving IC (integrated circuit) is formed.
  • a flexible organic EL display device having a structure in which) is directly mounted has been proposed.
  • Patent Document 1 describes an image display unit and the image display on a substrate in order to eliminate the trouble of applying a protective coating to the exposed portion of the metal wiring after performing the work of connecting the drive IC to the metal wiring.
  • a display device including a drive IC for driving a plurality of electrodes constituting the unit, and a fixing member for fixing the drive IC to at least the metal wiring on the image display unit side in a connected state.
  • a display device shared with a protective cover that covers the metal wiring is disclosed.
  • the present invention has been made in view of this point, and an object of the present invention is to reduce bending of a flexible substrate when crimping an IC.
  • the display device is provided on a flexible substrate, a thin film transistor layer provided on the flexible substrate and provided with a plurality of thin film transistors, and a plurality of thin film transistor layers provided on the thin film transistor layer. It has a plurality of light emitting elements including one electrode, a plurality of functional layers, and a second electrode, and a sealing layer provided so as to cover the plurality of light emitting elements, and has a plurality of pixels and a plurality of pixel circuits.
  • a display device including a display area including the above and a frame area provided around the display area, and a plurality of input bumps into which signals are input and signals are output to the frame area.
  • An electronic component having a plurality of output bumps, a plurality of input terminal electrodes electrically connected to the plurality of input bumps via an anisotropic conductive film, and an anisotropic conductive film connected to the plurality of output bumps.
  • a terminal connection portion including a plurality of output terminal electrodes electrically connected to each other via the above is provided, and in the terminal connection portion, electrodes are provided on the plurality of input terminal electrodes and the plurality of output terminal electrodes.
  • An insulating film is provided, and the electrode insulating film is provided with an input electrode opening for exposing the plurality of input terminal electrodes and an output electrode opening for exposing the plurality of output terminal electrodes.
  • a convex portion is provided on the upper portion, and the convex portion overlaps with the electronic component in a plan view, and the plurality of input bumps and the plurality of output bumps when viewed from a direction parallel to the substrate surface of the flexible substrate. It is characterized in that it overlaps with.
  • a convex portion is provided on the input terminal electrode and the electrode insulating film provided on the output terminal electrode, and the convex portion is connected to an electronic component (IC) in a plan view. Since they are superimposed and overlapped with the input bumps and output bumps of the IC when viewed from a direction parallel to the substrate surface of the flexible substrate, the bending of the flexible substrate when the IC is crimped can be reduced.
  • IC electronic component
  • FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
  • FIG. 2 is a side view showing a schematic configuration of an organic EL display device according to the first embodiment of the present invention.
  • FIG. 3 is a plan view of a display area of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a display area of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 5 is an equivalent circuit diagram showing a pixel circuit of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.
  • FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
  • FIG. 2 is a side view showing a schematic configuration of an organic EL display
  • FIG. 7 is a bottom view of an IC constituting the organic EL display device according to the first embodiment of the present invention.
  • FIG. 8 is a plan view showing a terminal connection portion of the frame region of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 9 is an enlarged cross-sectional view showing a terminal connection portion of the frame region of the organic EL display device according to the first embodiment of the present invention along the IX-IX line in FIG. 10 (a) and 10 (b) are terminals in the frame region of the organic EL display device according to the first embodiment of the present invention as viewed from the directions Y1 in FIG. 9 and the direction Y2 in FIG. 9, respectively. It is the schematic which shows the connection part.
  • FIG. 10 (a) and 10 (b) are terminals in the frame region of the organic EL display device according to the first embodiment of the present invention as viewed from the directions Y1 in FIG. 9 and the direction Y2 in FIG. 9, respectively. It is the schematic which shows the connection
  • FIG. 11 is an enlarged cross-sectional view for explaining the thickness of the convex portion of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 12 is an enlarged cross-sectional view showing a modified example of the terminal connection portion of the frame region of the organic EL display device according to the first embodiment of the present invention, and is a view corresponding to FIG.
  • FIG. 13 is a plan view showing a terminal connection portion of the frame region of the organic EL display device according to the second embodiment of the present invention, and is a view corresponding to FIG.
  • FIG. 14 is a plan view showing a terminal connection portion of the frame region of the organic EL display device according to the third embodiment of the present invention, and is a view corresponding to FIG. FIG.
  • FIG. 15 is an enlarged cross-sectional view showing a terminal connection portion of the frame region of the organic EL display device according to the third embodiment of the present invention along the XV-XV line in FIG. 14, and is a view corresponding to FIG. Is.
  • FIG. 16 is a plan view showing a terminal connection portion of the frame region of the organic EL display device according to the fourth embodiment of the present invention, and is a view corresponding to FIG.
  • FIG. 17 is an enlarged cross-sectional view showing a terminal connection portion of the frame region of the organic EL display device according to the fourth embodiment of the present invention along the line XVII-XVII in FIG. 16, and is a view corresponding to FIG. Is.
  • FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 50a of the present embodiment.
  • FIG. 2 is a side view showing a schematic configuration of the organic EL display device 50a.
  • FIG. 3 is a plan view of the display area D of the organic EL display device 50a.
  • FIG. 4 is a cross-sectional view of the display area D of the organic EL display device 50a.
  • FIG. 5 is an equivalent circuit diagram showing the pixel circuit C of the organic EL display device 50a.
  • FIG. 6 is a cross-sectional view showing the organic EL layer 23 constituting the organic EL display device 50a.
  • FIG. 7 is a bottom view of the IC 46 constituting the organic EL display device 50a.
  • FIG. 8 is a plan view showing a terminal connection portion J of the frame region F of the organic EL display device 50a.
  • FIG. 9 is an enlarged cross-sectional view showing a terminal connection portion J of the frame region F of the organic EL display device 50a along the IX-IX line in FIG.
  • FIG. 10 (a) and 10 (b) are outlines showing the terminal connection portion J of the frame region F of the organic EL display device 50a as viewed from the directions Y1 in FIG. 9 and the direction Y2 in FIG. 9, respectively. It is a figure.
  • FIG. 11 is an enlarged cross-sectional view for explaining the thickness of the convex portion 43a of the organic EL display device 50a.
  • FIG. 12 is an enlarged cross-sectional view showing a modified example of the terminal connection portion J of the frame region F of the organic EL display device 50a, and is a view corresponding to FIG.
  • the organic EL display device 50a includes a display area D for displaying an image provided in a rectangular shape and a frame area F provided in a frame shape around the display area D. It has.
  • the rectangular display area D is illustrated, but the rectangular shape includes, for example, a shape in which the sides are arcuate, a shape in which the corners are arcuate, and a part of the sides.
  • a substantially rectangular shape such as a shape with a notch is also included.
  • a plurality of sub-pixels p are arranged in a matrix in the display area D. Further, in the display area D, as shown in FIG. 3, for example, a sub-pixel pr having a red light emitting region Lr for displaying red, and a sub pixel pg having a green light emitting region Lg for displaying green, And sub-pixels pb having a blue light emitting region Lb for displaying blue are provided so as to be adjacent to each other.
  • one pixel P is composed of three adjacent sub-pixels pr, pb, and pb having a red light emitting region Lr, a green light emitting region Lg, and a blue light emitting region Lb.
  • the external terminal portion T is provided so as to extend in the direction X extending in the lateral direction in the drawing. Further, in the frame area F, as shown in FIGS. 1 and 2, a terminal connecting portion J is provided between the display area D and the external terminal portion T so as to extend in the direction X.
  • the direction X parallel to the substrate surface of the resin substrate layer 10 described later and the direction X perpendicular to the direction X and parallel to the substrate surface of the resin substrate layer 10 A direction Y and a direction X and a direction Z perpendicular to the direction Y are defined.
  • the organic EL display device 50a is provided on the resin substrate layer 10 provided as a flexible substrate and a plurality of thin film transistors (TFTs) in the display region D.
  • TFTs thin film transistors
  • Thin film transistor provided on the thin film transistor layer 20
  • an organic EL element 25 provided on the thin film transistor layer 20 as a light emitting element constituting the display region D
  • a seal provided so as to cover the organic EL element 25. It includes a layer 29.
  • a film layer 60 is provided on the back surface of the resin substrate layer 10 (the right surface in FIG. 2 and the lower surface in FIG. 4).
  • the resin substrate layer 10 is made of, for example, a polyimide resin or the like.
  • the thin film transistor layer 20 includes a base coat film 11 provided on the resin substrate layer 10 and a first TFT 9a provided on the base coat film 11 as a pixel circuit C (see FIG. 5) for each sub-pixel p.
  • the second TFT 9b and the capacitor 9c, and the flattening film 19 for the TFT provided on each of the first TFT 9a, each second TFT 9b and each capacitor 9c are provided.
  • a plurality of pixel circuits C are arranged in a matrix corresponding to the plurality of sub-pixels p. Further, as shown in FIGS.
  • the thin film transistor layer 20 is provided with a plurality of gate lines 14 so as to extend in parallel with each other in the lateral direction in the drawing. Further, as shown in FIGS. 3 and 5, the thin film transistor layer 20 is provided with a plurality of source lines 18f so as to extend parallel to each other in the vertical direction in the drawing. Further, as shown in FIGS. 3 and 5, the thin film transistor layer 20 is provided with a plurality of power lines 18g so as to extend in parallel with each other in the vertical direction in the drawing. As shown in FIG. 3, each power supply line 18g is provided so as to be adjacent to each source line 18f.
  • the base coat film 11 is composed of, for example, a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f at each sub-pixel p. Further, as shown in FIG. 4, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and the like, which are sequentially provided on the base coat film 11. A source electrode 18a and a drain electrode 18b are provided.
  • the semiconductor layer 12a is provided in an island shape on the base coat film 11 by, for example, a polysilicon film, and has a channel region, a source region, and a drain region. Further, as shown in FIG.
  • the gate insulating film 13 is provided so as to cover the semiconductor layer 12a. Further, as shown in FIG. 4, the gate electrode 14a is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. Further, the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order so as to cover the gate electrode 14a as shown in FIG. Further, as shown in FIG. 4, the source electrode 18a and the drain electrode 18b are provided on the second interlayer insulating film 17 so as to be separated from each other. Further, as shown in FIG.
  • the source electrode 18a and the drain electrode 18b are provided through the contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. It is electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively.
  • the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are composed of, for example, a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride. ..
  • the second TFT 9b is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel p.
  • the second TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, and the like, which are sequentially provided on the base coat film 11. It includes a source electrode 18c and a drain electrode 18d.
  • the semiconductor layer 12b is provided in an island shape on the base coat film 11 by, for example, a polysilicon film, and has a channel region, a source region, and a drain region. Further, as shown in FIG.
  • the gate insulating film 13 is provided so as to cover the semiconductor layer 12b. Further, as shown in FIG. 4, the gate electrode 14b is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. Further, the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order so as to cover the gate electrode 14b as shown in FIG. Further, as shown in FIG. 4, the source electrode 18c and the drain electrode 18d are provided on the second interlayer insulating film 17 so as to be separated from each other. Further, as shown in FIG.
  • the source electrode 18c and the drain electrode 18d are provided through the contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. It is electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively.
  • the top gate type first TFT 9a and the second TFT 9b are illustrated, but the first TFT 9a and the second TFT 9b may be a bottom gate type TFT.
  • the capacitor 9c is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel p.
  • the capacitor 9c is provided so as to cover the lower conductive layer 14c formed of the same material as the gate electrodes 14a and 14b in the same layer and the lower conductive layer 14c.
  • a film 15 and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c are provided.
  • the upper conductive layer 16 is electrically connected to the power supply line 18g via a contact hole formed in the second interlayer insulating film 17.
  • the flattening film 19 is made of an organic resin material such as a polyimide resin.
  • the organic EL element 25 includes a plurality of first electrodes 21 provided in order on the flattening film 19, an edge cover 22, and a plurality of organic EL layers 23 provided as functional layers. It includes a second electrode 24.
  • the plurality of first electrodes 21 are provided in a matrix on the flattening film 19 so as to correspond to the plurality of sub-pixels p. Further, as shown in FIG. 4, each first electrode 21 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the flattening film 19. There is. Further, the first electrode 21 has a function of injecting holes into the organic EL layer 23. Further, the first electrode 21 is more preferably formed of a material having a large work function in order to improve the hole injection efficiency into the organic EL layer 23.
  • examples of the material constituting the first electrode 21 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), and gold (Au). , Titanium (Ti), Ruthenium (Ru), Manganese (Mn), Indium (In), Ytterbium (Yb), Lithium fluoride (LiF), Platinum (Pt), Palladium (Pd), Molybdenum (Mo), Iridium ( Examples include metal materials such as Ir) and tin (Sn). Further, the material constituting the first electrode 21 may be, for example, an alloy such as astatine (At) / oxidized astatine (AtO 2 ).
  • the material constituting the first electrode 21 is, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). There may be. Further, the first electrode 21 may be formed by laminating a plurality of layers made of the above materials. Examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the edge cover 22 is provided in a grid pattern so as to cover the peripheral edge of each first electrode 21.
  • the material constituting the edge cover 22 include positive photosensitive resins such as polyimide resin, acrylic resin, polysiloxane resin, and novolak resin.
  • a part of the surface of the edge cover 22 is an island-shaped pixel photo spacer that protrudes upward in the drawing.
  • each organic EL layer 23 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection, which are sequentially provided on the first electrode 21. It has layer 5.
  • the hole injection layer 1 is also called an anode buffer layer, and has a function of bringing the energy levels of the first electrode 21 and the organic EL layer 23 closer to each other and improving the hole injection efficiency from the first electrode 21 to the organic EL layer 23.
  • Examples include hydrazone derivatives and stillben derivatives.
  • the hole transport layer 2 has a function of improving the hole transport efficiency from the first electrode 21 to the organic EL layer 23.
  • examples of the material constituting the hole transport layer 2 include a porphyrin derivative, an aromatic tertiary amine compound, a styrylamine derivative, polyvinylcarbazole, a poly-p-phenylene vinylene, a polysilane, a triazole derivative, and an oxadiazole.
  • Derivatives imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stillben derivatives, hydride amorphous silicon, Examples thereof include hydride amorphous silicon carbide, zinc sulfide, and zinc selenium.
  • the light emitting layer 3 When a voltage is applied by the first electrode 21 and the second electrode 24, the light emitting layer 3 is injected with holes and electrons from the first electrode 21 and the second electrode 24, respectively, and the holes and electrons are recombined. It is an area.
  • the light emitting layer 3 is formed of a material having high luminous efficiency. Examples of the material constituting the light emitting layer 3 include a metal oxinoid compound [8-hydroxyquinolin metal complex], a naphthalene derivative, an anthracene derivative, a diphenylethylene derivative, a vinylacetone derivative, a triphenylamine derivative, a butadiene derivative, and a coumarin derivative.
  • the electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3.
  • the material constituting the electron transport layer 4 for example, as an organic compound, an oxadiazole derivative, a triazole derivative, a benzoquinone derivative, a naphthoquinone derivative, an anthraquinone derivative, a tetracyanoanthracinodimethane derivative, a diphenoquinone derivative, and a fluorenone derivative , Cyrol derivatives, metal oxinoid compounds and the like.
  • the electron injection layer 5 has a function of bringing the energy levels of the second electrode 24 and the organic EL layer 23 closer to each other and improving the efficiency of injecting electrons from the second electrode 24 into the organic EL layer 23.
  • the drive voltage of the organic EL element 25 can be lowered.
  • the electron injection layer 5 is also called a cathode buffer layer.
  • examples of the material constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), and barium fluoride. Examples thereof include inorganic alkaline compounds such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), strontium oxide (SrO) and the like.
  • the second electrode 24 is provided so as to cover each organic EL layer 23 and the edge cover 22. Further, the second electrode 24 has a function of injecting electrons into the organic EL layer 23. Further, the second electrode 24 is more preferably made of a material having a small work function in order to improve the efficiency of electron injection into the organic EL layer 23.
  • the material constituting the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), and gold (Au).
  • the second electrode 24 is, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), asstatin (At) / oxidized asstatin (AtO 2).
  • the second electrode 24 may be formed of, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). .. Further, the second electrode 24 may be formed by laminating a plurality of layers made of the above materials.
  • Examples of materials having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), and sodium.
  • (Na) / potassium (K) lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al) And so on.
  • the sealing layer 29 includes a first inorganic insulating film 26 provided so as to cover the second electrode 24, an organic film 27 provided on the first inorganic insulating film 26, and an organic film. It is provided with a second inorganic insulating film 28 provided so as to cover 27, and has a function of protecting the organic EL layer 23 from moisture, oxygen, and the like.
  • the first inorganic insulating film 26 and the second inorganic insulating film 28 are nitrided, for example, such as silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and trisilicon tetranitride (Si 3 N 4 ).
  • the organic film 27 is made of an organic material such as an acrylic resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.
  • the film layer 60 is attached to the surface of the resin substrate layer 10 opposite to the surface on which the thin film transistor layer 20 is provided, for example, via an adhesive layer 61. Further, the film layer 60 is arranged in the entire display area D and the frame area F.
  • the film layer 60 is made of, for example, a plastic film made of polyethylene terephthalate (PET) resin or the like.
  • a plurality of external terminal electrodes 30 are arranged in the external terminal portion T of the frame region F.
  • the external terminal electrode 30 is for inputting a signal from the outside, and is electrically connected to each electrode such as FPC (Flexible printed circuits) (not shown) via ACF, for example.
  • FPC Flexible printed circuits
  • the organic EL display device 50a is provided with an IC 46 provided as an electronic component and a back surface (IC 46) of the resin substrate layer 10 in the terminal connection portion J of the frame region F.
  • IC 46 an electronic component
  • a film layer 60 provided on the surface opposite to the surface
  • the IC 46 is, for example, a drive IC for supplying a drive signal to each pixel circuit C, and is crimp-connected to the terminal connection portion J as shown in FIGS. 1 and 2.
  • a plurality of input bumps 47 to which signals are input and a plurality of output bumps 48 to which signals are output are respectively on the back surface of the IC 46 (the surface mounted on the terminal connection portion J). They are placed apart.
  • the back surface of the IC 46 is provided with an input bump area R47 surrounding all of the plurality of input bumps 47 and an output bump area R48 surrounding all of the plurality of output bumps 48.
  • FIG. 7 the back surface of the IC 46 is provided with an input bump area R47 surrounding all of the plurality of input bumps 47 and an output bump area R48 surrounding all of the plurality of output bumps 48.
  • bump area R47, R48 the input bump 47 and the output bump are located in the center of the back surface of the IC46.
  • 48 (hereinafter, also referred to as “bump 47, 48”) is not arranged.
  • the input bumps 47 are arranged in a row along one side edge in the longitudinal direction of the IC 46 (direction X in FIG. 7), and the output bumps 48 are staggered in two rows along the other side edge in a plan view. It is arranged in. Further, the output bumps 48 have a smaller area and a larger number than the input bumps 47. Further, the bumps 47 and 48 are formed in a rectangular shape in a plan view.
  • a first inorganic insulating film 31 provided in order on the resin substrate layer 10 and a plurality of first routing wires 32 are provided in the terminal connection portion J.
  • a plurality of second routing wires 33, a second inorganic insulating film 34, a plurality of input terminal electrodes 35 and a plurality of output terminal electrodes 36, an electrode insulating film 37 provided as an insulating film, and a convex portion 43a are provided. ing.
  • the first inorganic insulating film 31 is a moisture-proof film provided on the resin substrate layer 10, and is formed in the same layer as the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the like.
  • a plurality of the first routing wiring 32 and the second routing wiring 33 (hereinafter, also referred to as “route wiring 32, 33”) are provided on the first inorganic insulating film 31, respectively. .. These routing wires 32 and 33 are formed in the same layer as the gate electrode 14a, the upper conductive layer 16, and the like, respectively.
  • each first routing wiring 32 is electrically connected to each output terminal electrode 36, and is configured to input a signal to each pixel circuit C.
  • each of the second routing wires 33 is electrically connected to each of the external terminal electrodes 30 and each of the input terminal electrodes 35. That is, each external terminal electrode 30 and each input terminal electrode 35 are electrically connected via the second routing wiring 33.
  • the second inorganic insulating film 34 is provided on the first inorganic insulating film 31, the first routing wiring 32, and the second routing wiring 33.
  • the second inorganic insulating film 34 has a first wiring opening 38 that overlaps with each output bump 48 and exposes each first routing wiring 32.
  • a second wiring opening 39 that overlaps with each input bump 47 and exposes the second routing wiring 33 is formed. Then, in the first wiring opening 38, each output terminal electrode 36 and each exposed first routing wiring 32 are in contact with each other, and in the second wiring opening 39, each input terminal electrode 35 and each exposed second routing wiring 33 are in contact with each other. Is in contact with.
  • the second inorganic insulating film 34 is formed in the same layer as the first interlayer insulating film 15, the second interlayer insulating film 17, and the like.
  • the first inorganic insulating film 31 is composed of the base coat film 11 and the gate insulating film 13 and the second inorganic insulating film 34 is the first interlayer insulating film. It is composed of a film 15 and a second interlayer insulating film 17.
  • the routing wires 32 and 33 are composed of the upper conductive layer 16
  • the first inorganic insulating film 31 is composed of the base coat film 11, the gate insulating film 13, and the first interlayer insulating film 15, and is composed of the second inorganic insulating film.
  • the film 34 is composed of a second interlayer insulating film 17.
  • each input terminal electrode 35 is placed on the second routing wiring 33 exposed from the second wiring opening 39 and the second inorganic material so as to overlap each input bump 47 in a plan view. It is provided on the peripheral edge of the insulating film 34.
  • each output terminal electrode 36 is placed on the first routing wiring 32 exposed from the first wiring opening 38 and on the peripheral edge of the second inorganic insulating film 34 so as to overlap each output bump 48 in a plan view. It is provided.
  • each input terminal electrode 35 is formed in a plurality of rectangular shapes in a plan view corresponding to each input bump 47, and the output terminal electrode 36 is formed on each output bump 48. Correspondingly, they are formed in a plurality of rectangular shapes in a plan view. Further, the input terminal electrodes 35 are arranged in a row along one side edge of the terminal connection portion J, and the output terminal electrodes 36 are arranged in two rows in a staggered manner along the other side edge in a plan view. ing. Further, the output terminal electrodes 36 have a smaller area and a larger number than the input terminal electrodes 35. In FIG. 8, the illustration of the IC 46 is simplified, and the bumps 47 and 48 of the IC 46 are omitted.
  • terminal electrodes 35, 36 between the input terminal electrode 35 and the output terminal electrode 36 (hereinafter, also referred to as “terminal electrodes 35, 36”), in other words, the central portion of the terminal connection portion J corresponding to the central portion of the IC 46. Is provided with an inter-electrode region r in which the terminal electrodes 35 and 36 are not arranged.
  • each input terminal electrode 35 is electrically connected to each input bump 47 via ACF 49
  • each output terminal electrode 36 is electrically connected to each output bump 48 via ACF 49.
  • These terminal electrodes 35 and 36 are formed in the same layer with the same material as the source wire 18f, respectively.
  • the electrode insulating film 37 is provided on the terminal electrodes 35 and 36 and the second inorganic insulating film 34 so as to cover the peripheral edges of the terminal electrodes 35 and 36. That is, the electrode insulating film 37 is an edge cover and flattening film of the terminal electrodes 35 and 36.
  • the electrode insulating film 37 is composed of a single-layer film or a laminated film of an organic insulating film, and is formed of, for example, the same material as the flattening film 19.
  • the electrode insulating film 37 has an input electrode opening 40 that exposes all of the input terminal electrodes 35 and an output electrode opening that exposes all of the output terminal electrodes 36. Each of the portions 41 is formed.
  • the input electrode opening 40 is formed in a rectangular shape in a plan view along the direction X in which the terminal connection portion J extends so as to surround the entire input terminal electrode 35.
  • the output electrode opening 41 is formed in a rectangular shape in a plan view along the direction X so as to surround the entire output terminal electrode 36.
  • These two input electrode openings 40 and output electrode openings 41 (hereinafter, also referred to as “electrode openings 40, 41”) are formed at both ends of the inter-electrode region r in the direction Y, respectively, as shown in FIG. There is. In other words, the electrode openings 40 and 41 are formed so as to correspond to the bump regions R47 and R48, respectively.
  • the planar shapes of the electrode openings 40 and 41 are not limited to the rectangular shape shown in the figure, but may be, for example, a polygonal shape, a trapezoidal shape, an elliptical shape, or the like.
  • the input electrode opening 40 is formed so that the dimension Y 40 of the opening edge is larger than the dimension Y 35 of the input terminal electrode 35, and the output electrode opening 40 is formed.
  • 41 is formed so that its dimension Y 41 is larger than the dimension Y 36 of the output terminal electrode 36. This is to prevent the bumps 47 and 48 and the convex portion 43a, which will be described later, from overlapping with each other in a plan view even if the IC46 is displaced in the direction Y when the IC46 is crimped to the terminal connection portion J. is there.
  • FIG. 9 when a plurality of output terminal electrodes 36 are arranged in the output electrode opening 41 along the direction Y (two in FIG.
  • the dimension Y 41 of the output electrode opening 41 is it may be adjusted to be larger than the dimension of the dimension Y 36 and multiple partial sum of the output terminal electrode 36.
  • the size Y 41 dimension Y 40, and an output electrode opening 41 of the input electrode opening 40, the electrode opening 40 and 41 is adjusted to be smaller than the outer edge of the IC 46.
  • a convex portion 43a is provided on the electrode insulating film 37 so as to project in the direction of the IC 46.
  • the convex portion 43a is composed of a single-layer film or a laminated film of an organic insulating film, and is formed in the same layer with, for example, the same material as the edge cover 22.
  • the convex portion 43a is provided along the periphery of the input electrode opening 40 so as to surround the input electrode opening 40, and the output electrode opening 41 is provided so as to surround the output electrode opening 41. It is provided along the periphery of 41.
  • the convex portion 43a is provided along the periphery of the input bump region R47 and is provided along the periphery of the output bump 48.
  • the convex portion 43a is formed in a frame shape in a plan view corresponding to the contour (outer peripheral edge portion) of the IC 46 surrounding all of the bumps 47 and 48.
  • the convex portion 43a is flat along the direction X in which the terminal connection portion J extends between the input electrode opening 40 and the output electrode opening 41 (that is, the inter-electrode region r). It is provided in a band shape visually. In other words, the convex portion 43a is provided so as to correspond between the input bump region R47 and the output bump region R48 (that is, the central portion of the IC 46).
  • the convex portion 43a overlaps with the IC46 via the IC46 and the ACF49 at the end portion (outer peripheral edge portion) and the central portion of the IC46 in a plan view. Further, as shown in FIGS. 9 and 10, the convex portion 43a is superimposed on the bumps 47 and 48 when viewed from a direction parallel to the substrate surface of the resin substrate layer 10.
  • the directions parallel to the substrate surface of the resin substrate layer 10 are, for example, in FIGS. 9 and 10, the direction parallel to the direction X, the direction parallel to the direction Y (directions Y1, Y2, etc.), the direction X, and the direction. Includes all directions, such as directions parallel to the direction inclined to Y. In other words, the convex portion 43a does not overlap with the bumps 47 and 48 in a plan view.
  • the convex portion 43a is arranged along the outer peripheral edge portion of the IC 46 so as not to overlap with the bumps 47 and 48 while overlapping with the IC 46 in a plan view, the IC 46 is attached to the terminal connecting portion J.
  • the bottom surface portion along the outer peripheral edge portion of the IC 46 and the convex portion 43a come into contact with each other via the conductive particles 49a of the ACF 49.
  • the bending of the resin substrate layer 10 and the film layer 60 along the outer peripheral edge of the IC 46 is reduced.
  • the convex portion 43a is arranged corresponding to the central portion of the IC 46 so as not to overlap with the bumps 47 and 48 while overlapping with the IC 46 in a plan view, the IC 46 is crimped to the terminal connecting portion J. Occasionally, the bottom surface portion and the convex portion 43a in the central portion of the IC 46 come into contact with each other via the conductive particles 49a. As a result, the bending of the resin substrate layer 10 and the film layer 60 corresponding to the central portion of the IC 46 is reduced.
  • the first inorganic insulating film 31, the second inorganic insulating film 34, and the electrodes provided on the resin substrate layer 10 are reduced.
  • the stress applied to the inorganic insulating layer such as the insulating film 37 and the metal layer such as the routing wires 32 and 33 and the terminal electrodes 35 and 36 is reduced.
  • the coefficient of linear expansion of the film layer 60 is larger than the coefficient of linear expansion of the resin substrate layer 10, so that when the IC 46 is crimped to the terminal connection portion J, the film layer 60 is compared with the resin substrate layer 10. Inflate. Therefore, in the organic EL display device in which the convex portion 43a is not provided, after the IC46 is crimped, the adhesion force of the resin substrate layer 10, the adhesive layer 61, and the film layer 60 corresponding to the outer peripheral edge portion and the central portion of the IC46 is increased. The weakest layers may peel off.
  • the difference in stress applied to the resin substrate layer 10 and the film layer 60 under the resin substrate layer 10 may cause peeling at the adhesive layer 61 between the resin substrate layer 10 and the film layer 60 as a boundary.
  • the organic EL display device 50a since the area of contact between the bottom surface of the IC 46 and the convex portion 43a is large via the conductive particles 49a of the ACF 49, the bending of the resin substrate layer 10 and the film layer 60 is reduced, and as a result, the bending is reduced. , The difference in stress becomes small, and peeling between the layers after crimping the IC46 is suppressed.
  • the terminal electrodes 35 and 36 may be deformed into a concave shape in a cross-sectional view after the IC46 is crimped.
  • the mechanical connectivity between the outer peripheral edges and the central portions of the bumps 47 and 48 and the conductive particles 49a may be weakened, and the electrical connectivity may be lowered.
  • the convex portion 43a is provided corresponding to both the outer peripheral portion and the central portion of the IC 46, the bending of the resin substrate layer 10 is reduced, and the resin substrate layer 10
  • the terminal electrodes 35 and 36 on the upper layer are less likely to be deformed into a concave shape in a cross-sectional view. As a result, mechanical connectivity is maintained and deterioration of electrical connectivity is suppressed.
  • the convex portion 43a is provided corresponding to only one of the outer peripheral edge portion and the central portion of the IC 46, the bending of the resin substrate layer 10 is reduced, but since the resin substrate layer 10 is flexible, the IC 46 When the convex portion 43a is provided corresponding to both the outer peripheral portion and the central portion, the bending of the resin substrate layer 10 can be further reduced, and the effects of mechanical connectivity and electrical connectivity are enhanced.
  • the thickness (dimension in the direction Z) Ze of the convex portion 43a is the thickness Zc of the second inorganic insulating film 34, the thickness Za of the terminal electrodes 35 and 36, and the thickness Zd of the electrode insulating film 37. Therefore, it may be determined that the convex portion 43a abuts on the bottom surface of the IC 46 via the conductive particles 49a.
  • the height (dimension in the Z direction) is Zf
  • the height between the bottom surface of the IC46 at the IC end (convex 43a side) g and the surface of the electrode layer between the routing wires 32 and 33 is Zg. It may be determined so that the value of the step ⁇ between the height Zf of the panel electrode portion f and the height Zg of the IC end portion g shown in the above is small.
  • the height Zb of the bumps 47 and 48 is, for example, about 7 ⁇ m.
  • the particle size of the conductive particles 49a is, for example, about 2 to 4 ⁇ m.
  • the organic EL display device 50a described above turns on the first TFT 9a by inputting a gate signal to the first TFT 9a via the gate line 14 in each sub-pixel p, and turns on the first TFT 9a, and the gate electrode of the second TFT 9b via the source line 18f.
  • a data signal to the 14b and the capacitor 9c and supplying a current from the power supply line 18g corresponding to the gate voltage of the second TFT 9b to the organic EL layer 23
  • the light emitting layer 3 of the organic EL layer 23 emits light, and the image It is configured to display.
  • the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the light emitting layer 3 emits light until the gate signal of the next frame is input. Be maintained.
  • the method for manufacturing the organic EL display device 50a of the present embodiment includes a resin substrate layer forming step, a thin film transistor layer forming step, an organic EL element forming step, a sealing layer forming step, an external terminal portion forming step, and a terminal connecting portion forming step. And a film pasting process is provided.
  • the resin substrate layer 10 is formed by applying a non-photosensitive polyimide resin on a support substrate (not shown) such as a glass substrate, and then prebaking and post-baking the coated film.
  • a base coat film 11, a first TFT 9a, a second TFT 9b, a capacitor 9c, and a flattening film 19 are formed on the resin substrate layer 10 formed in the resin substrate layer forming step by, for example, using a well-known method to form a thin film transistor.
  • the layer 20 is formed.
  • the first electrode 21, the edge cover 22, and the organic EL layer 23 are used on the flattening film 19 of the thin film transistor layer 20 formed in the thin film transistor layer forming step.
  • the layer 2, the light emitting layer 3, the electron transport layer 4, the electron injection layer 5) and the second electrode 24 are formed to form the organic EL element 25.
  • an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is plasma-enhanced on the surface of the substrate on which the organic EL element 25 formed in the organic EL element forming step is formed, using a mask.
  • the first inorganic insulating film 26 is formed by forming a film by the CVD method.
  • an organic resin material such as an acrylic resin is formed on the surface of the substrate on which the first inorganic insulating film 26 is formed by, for example, an inkjet method to form the organic film 27.
  • an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed on the substrate on which the organic film 27 is formed by a plasma CVD method using a mask to form a second film.
  • the sealing layer 29 is formed by forming the inorganic insulating film 28.
  • the external terminal portion T is formed by forming the external terminal electrode 30 on the second interlayer insulating film 17 at the end of the frame region F by using a well-known method.
  • the first inorganic insulating film 31, the routing wiring 32, 33, and the second inorganic insulating film 34 are used on the resin substrate layer 10 by a well-known method.
  • the terminal connection portion J is formed by forming the terminal electrodes 35 and 36, the electrode insulating film 37, and the convex portion 43a.
  • the first inorganic insulating film 31, the routing wiring 32, 33, the second inorganic insulating film 34, the terminal electrodes 35, 36, and the electrode insulating film 37 are the gates of the base coat film 11 and the first TFT 9a in the thin film transistor layer forming step.
  • the insulating film 13, the gate electrode 14a, the first interlayer insulating film 15, the second interlayer insulating film 17, the source electrode 18a, the flattening film 19, and the like may be formed at the same time. Further, the convex portion 43a may be formed at the same time as the edge cover 22 is formed in the organic EL element forming step.
  • the first wiring opening 38 and the second wiring opening 38 are formed in the second inorganic insulating film 34 by dry etching. Form 39. After that, the terminal electrodes 35 and 36 are formed so as to fill the first wiring opening 38 and the second wiring opening 39.
  • all of the terminal electrodes 35 and 36 are formed by forming the electrode openings 40 and 41 in the electrode insulating film 37 by dry etching. While exposing, the edge covers of the terminal electrodes 35 and 36 are formed.
  • a convex portion 43a is formed on the electrode insulating film 37 along the periphery of the electrode openings 40 and 41.
  • the thickness of the convex portion 43a may be adjusted by performing gray tone processing or the like on the photomask side so that the electrode insulating film 37 is not scraped by etching after the convex portion 43a is patterned.
  • the resin substrate layer 10 is irradiated with laser light from the support substrate side to support the resin substrate layer 10 from the surface opposite to the surface on which the thin film transistor layer 20 is provided. To peel off. Subsequently, the film layer 60 is attached to the surface of the resin substrate layer 10 from which the support substrate has been peeled off via the adhesive layer 61.
  • the organic EL display device 50a of the present embodiment can be manufactured.
  • the convex portion may be formed by thickening the electrode insulating film 37 without providing the convex portion 43a on the electrode insulating film 37. ..
  • the terminal connection forming step the terminal electrodes 35 and 36 are exposed by etching and an edge cover thereof is formed, and the periphery thereof is dug shallowly by performing gray tone processing, halftone processing, or the like, and the electrodes.
  • a step is provided on the insulating film 37.
  • the convex portion can be formed by the thickened electrode insulating film 37.
  • the organic EL display device 50a of the present embodiment As described above, according to the organic EL display device 50a of the present embodiment, the following effects can be obtained.
  • the convex portion 43a overlaps with the IC 46 in a plan view and overlaps with the bumps 47 and 48 when viewed from a direction parallel to the substrate surface of the resin substrate layer 10, the IC 46 is crimped to the terminal connection portion J. At this time, the bottom surface of the IC 46 and the convex portion 43a come into contact with each other via the conductive particles 49a of the ACF 49. As a result, the bending of the resin substrate layer 10 and the film layer 60 when the IC 46 is crimped to the terminal connection portion J is reduced.
  • the convex portion 43a is arranged so as to correspond to the outer peripheral edge portion and the central portion of the IC 46, the stress applied to the resin substrate layer 10 and the film layer 60 after crimping the IC 46 is reduced, and the difference in stress is reduced. Becomes smaller. As a result, peeling of the adhesive layer 61 between the resin substrate layer 10 and the film layer 60 as a boundary is suppressed.
  • the terminal electrodes 35 and 36 after crimping the IC46 are less likely to be deformed into a concave shape in a cross-sectional view. As a result, mechanical connectivity is maintained and deterioration of electrical connectivity is suppressed.
  • FIG. 13 is a plan view showing a terminal connection portion J of the frame region F of the organic EL display device 50b of the present embodiment, and is a view corresponding to FIG. Since the overall configuration of the organic EL display device 50b including the display area D and the frame area F other than the terminal connection portion J is the same as that of the first embodiment described above, detailed description thereof will be omitted here. .. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
  • the organic EL display device 50b is characterized in that a plurality of convex portions 43b are provided in an island shape (columnar shape) in a plan view.
  • the illustration of the IC 46 is simplified, and the bumps 47 and 48 of the IC 46 are omitted.
  • the convex portion 43b is a columnar body having any one shape of a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, and a rhombic shape, or a shape obtained by combining these shapes in a plan view.
  • the fluidity of the thermosetting resin 49b of ACF49 hereinafter referred to as “resin fluidity” when the IC46 is crimped to the terminal connection portion J is improved.
  • the mechanical connectivity between the bumps 47, 48 or the terminal electrodes 35, 36 and the conductive particles 49a is maintained.
  • the size, shape, number, position, etc. of the convex portions 43b are not particularly limited, and it is determined that the bending of the resin substrate layer 10 and the film layer 60 when the IC 46 is crimped to the terminal connecting portion J is reduced. do it.
  • the shape of the convex portion 43b along the end portion of the IC 46 and the shape of the convex portion 43b corresponding to the central portion of the IC 46 may be the same or different.
  • the positions of the convex portions 43b may be equidistant or random.
  • the inter-electrode region r is located at a position corresponding to the central portion of the IC 46 from the viewpoint of improving the resin fluidity of the ACF 49 when the IC 46 is crimped to the terminal connecting portion J. It is preferable that the bumps 47 and 48 are arranged so as to extend in the direction in which the bumps 47 and 48 are arranged (direction Y in FIG. 13).
  • the convex portion 43b is arranged corresponding to the outer peripheral edge portion and the central portion of the IC 46. Then, as shown in FIG. 13, the convex portion 43b overlaps with the IC 46 at the outer peripheral edge portion and the central portion of the IC 46 in a plan view, and the bump 47 is viewed from a direction parallel to the substrate surface of the resin substrate layer 10. , 48 are superimposed.
  • the convex portion 43b overlaps the bumps 47 and 48 when viewed from parallel to the direction parallel to the direction X, the direction parallel to the direction Y, and the direction inclined in the direction X and the direction Y.
  • the convex portion 43b is, for example, an inorganic insulating film or a metal material (more specifically, the same as the first electrode 21) in addition to a single-layer film or a laminated film of an organic insulating film. It may be formed of a single-layer film or a laminated film of the same material), or may be formed of a laminated material in which these organic insulating film, inorganic insulating film, and metal material are combined. This is because if the convex portions 43b are independent columnar bodies, cracks are unlikely to occur in the convex portions 43b even if the resin substrate layer 10 and the film layer 60 are bent when the IC 46 is crimped to the terminal connecting portion J. Because.
  • the organic EL display device 50b can be manufactured by changing the pattern shape of the convex portion 43a in the manufacturing method of the organic EL display device 50a of the first embodiment described above.
  • the following effects can be obtained in addition to the effects (1) to (5) above.
  • FIG. 14 is a plan view showing a terminal connection portion J of the frame region F of the organic EL display device 50c of the present embodiment, and is a view corresponding to FIG.
  • FIG. 15 is an enlarged cross-sectional view showing a terminal connection portion J of the frame region F of the organic EL display device 50c along the XV-XV line in FIG. 14, and is a view corresponding to FIG. Since the overall configuration of the organic EL display device 50c including the display area D and the frame area F other than the terminal connection portion J is the same as that of the first embodiment described above, detailed description thereof will be omitted here. .. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
  • the convex portions 43c are provided in a plurality of islands in a plan view.
  • the convex portions 43c are provided between a plurality of projecting portions 43ca (four in FIGS. 14 and 15) having upper surfaces in contact with the surface of the IC 46 and a plurality of projecting portions (four in FIGS. 14 and 15) and two adjacent projecting portions (FIGS. 14 and 15).
  • FIG. 15 it is characterized in that it is provided with three) groove portions 43 cc.
  • the illustration of the IC 46 is simplified, and the bumps 47 and 48 of the IC 46 are omitted.
  • the protruding portion 43ca and the groove portion 43cc are provided along the direction (direction X) in which the terminal connecting portion J extends.
  • the protruding portion (top) 43ca is in direct contact with the outer peripheral edge portion and the bottom surface portion in the central portion of the IC 46, so that when the IC 46 is crimped to the terminal connecting portion J, the resin substrate layer is formed. The deflection of 10 and the film layer 60 is reduced. Since the convex portion 43c is composed of a single-layer film or a laminated film of an organic insulating film and has flexibility, the protruding portion 43ca is in contact with the bottom surface of the IC 46 when the IC 46 is crimped to the terminal connection portion J. However, the residual stress can be absorbed and the stress is reduced.
  • the dimension of the groove portion 43cc (the separation dimension (pitch) of the two adjacent protruding portions 43ca) is larger than the particle diameter of the conductive particles 49a.
  • the direction, size, shape, number, position, etc. of the protruding portion 43ca and the groove portion 43cc are not particularly limited, and the bending of the resin substrate layer 10 and the film layer 60 when the IC 46 is crimped to the terminal connecting portion J is reduced. It should be decided to be done.
  • the directions of the protruding portion 43ca and the groove portion 43cc are not limited to the direction X, and may be any direction parallel to the substrate surface of the resin substrate layer 10.
  • the direction of the protruding portion 43ca and the groove portion 43cc may be changed for each arrangement position of the convex portion 43c, or the pitch thereof may be changed.
  • the shape of the groove portion 43cc may be any structure as long as the conductive particles 49a flow into the groove portion 43cc when the IC46 is crimped to the terminal connection portion J, and may be, for example, a grid-like groove.
  • the convex portion 43c is arranged corresponding to the outer peripheral portion and the central portion of the IC 46. Then, as shown in FIGS. 14 and 15, the convex portion 43c overlaps with the IC 46 at the outer peripheral edge portion and the central portion of the IC 46 in a plan view, and is viewed from a direction parallel to the substrate surface of the resin substrate layer 10. It overlaps with bumps 47 and 48.
  • the convex portion 43c overlaps the bumps 47 and 48 when viewed from a direction parallel to the direction Y, a direction parallel to the direction X and a direction inclined in the direction Y.
  • the convex portion 43c is not superimposed on the bumps 47 and 48 when viewed from a direction parallel to the direction X, but may be superimposed.
  • the organic EL display device 50c can be manufactured by changing the pattern shape of the convex portion 43a in the manufacturing method of the organic EL display device 50a of the first embodiment described above.
  • the following effects can be obtained in addition to the effects (1) to (7) above.
  • the convex portions 43c are provided in a plurality of islands in a plan view, and have a dimension larger than the particle diameter of the conductive particles 49a between the protruding portion 43ca directly in contact with the bottom surface of the IC 46 and the adjacent protruding portions 43ca. Since the groove portion 43cc is provided, when the IC46 is crimped to the terminal connection portion J, the conductive particles 49a enter the groove portion 43cc and the protruding portion 43ca directly contacts the bottom surface of the IC46. As a result, the bending of the resin substrate layer 10 and the film layer 60 when the IC 46 is crimped to the terminal connection portion J is reduced.
  • FIG. 16 is a plan view showing a terminal connection portion J of the frame region F of the organic EL display device 50d of the present embodiment, and is a view corresponding to FIG.
  • FIG. 17 is an enlarged cross-sectional view showing a terminal connection portion J of the frame region F of the organic EL display device 50d along the line XVII-XVII in FIG. 16, which corresponds to FIG. Since the overall configuration of the organic EL display device 50d including the display area D and the frame area F other than the terminal connection portion J is the same as that of the first embodiment described above, detailed description thereof will be omitted here. .. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
  • the organic EL display device 50d is provided on the third inorganic insulating film 44 provided between the second inorganic insulating film 34 and the electrode insulating film 37, and on the terminal electrodes 35 and 36. It is characterized in that it further includes the transparent electrode 45.
  • the illustration of the IC 46 is simplified, and the bumps 47 and 48 of the IC 46 are omitted.
  • the third inorganic insulating film 44 is provided on the terminal electrodes 35 and 36 and the second inorganic insulating film 34 so as to cover the peripheral edges of the terminal electrodes 35 and 36. That is, the third inorganic insulating film 44 is an edge cover and flattening film of the terminal electrodes 35 and 36.
  • the third inorganic insulating film 44 is formed of a single-layer or laminated film of the inorganic insulating film.
  • the transparent electrode 45 is provided on the third inorganic insulating film 44 and the terminal electrodes 35 and 36 so as to cover the peripheral edge of the third inorganic insulating film 44.
  • the transparent electrode 45 is a protective film for preventing corrosion of the terminal electrodes 35 and 36.
  • the transparent electrode 45 is formed of, for example, ITO, IZO, or the like.
  • the electrode insulating film 37 and the convex portion 43d are sequentially placed on the third inorganic insulating film 44 so as to correspond to the outer peripheral edge portion and the central portion of the IC 46. It is provided.
  • the organic EL display device 50d forms the third inorganic insulating film 44 after forming the terminal electrodes 35 and 36 in the terminal connection portion forming step in the method for manufacturing the organic EL display device 50a of the first embodiment. After that, the transparent electrode 45, the electrode insulating film 37, and the convex portion 43d may be formed. The thickness of the convex portion 43d may be determined in consideration of the thickness of the third inorganic insulating film 44.
  • the electrode insulating film 37 is not arranged on the third inorganic insulating film 44 between the adjacent output bumps 48, but the electrode insulating film 37 is arranged. It may have been done. However, from the viewpoint of ensuring the resin fluidity of the ACF 49 when the IC 46 is crimped to the terminal connection portion J, it is preferable that the electrode insulating film 37 is not arranged between the output bumps 48.
  • the following effects can be obtained in addition to the effects (1) to (5) above.
  • the convex portion is arranged so as to correspond to the outer peripheral edge portion and the central portion of the IC, but it may be arranged along at least one of the outer peripheral edge portion and the central portion of the IC. It is preferable that the convex portion is arranged at least along the outer edge portion of the IC.
  • the convex portion is arranged corresponding to the outer peripheral edge portion and the central portion of the IC, but is not limited thereto, and for example, a space is provided between adjacent output bumps, adjacent input bumps, and the like. If there is a vacant region, a convex portion may be provided on the resin substrate layer corresponding to the region in order to reduce the deflection of the resin substrate layer corresponding to the region.
  • the convex portion may be a combination of the convex portions applied to the first to fourth embodiments.
  • the convex portions corresponding to the central portion of the IC may be provided in a plurality of islands in a plan view as in the second or third embodiment.
  • the convex portion along the outer peripheral edge portion of the IC has a frame shape in a plan view corresponding to the outer peripheral edge portion of the IC, as in the first or fourth embodiment. It may be provided in.
  • the electrode insulating film is composed of a single-layer film or a laminated film of an organic insulating film, but an edge cover of the input / output terminal electrode is formed by the inorganic insulating film, and the edge cover is placed on the edge cover. It may be composed of a laminated film of an inorganic insulating film and an organic insulating film in which the same material as is laminated in the same layer.
  • the convex portion may not be provided on the electrode insulating film as in the first embodiment, but may be formed by thickening the electrode insulating film.
  • an organic EL layer having a five-layer laminated structure of a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer has been exemplified, but the organic EL layer may be, for example, hole injection. It may have a three-layer laminated structure of a layer / hole transport layer, a light emitting layer, and an electron transport layer / electron injection layer.
  • an organic EL display device in which the first electrode is used as an anode and the second electrode is used as a cathode is illustrated, but in the present invention, the laminated structure of the organic EL layer is inverted and the first electrode is used as a cathode.
  • the present invention can also be applied to an organic EL display device using the second electrode as an anode.
  • the organic EL display device has been described as an example of the display device, but the present invention is not limited to the organic EL display device, and any flexible display device can be applied.
  • it can be applied to a flexible display device provided with a QLED (Quantum-dot light emission diode) or the like, which is a light emitting element using a quantum dot-containing layer.
  • QLED Quantum-dot light emission diode
  • the present invention is useful for flexible display devices.

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Abstract

上記額縁領域(F)には、複数の入力バンプ(47)と複数の出力バンプ(48)とを有するIC(46)、及び複数の入力端子電極(35)と複数の出力端子電極(36)とを備えた端子接続部(J)が設けられ、端子接続部(J)において、入力端子電極(35)及び出力端子電極(36)上には電極絶縁膜(37)が設けられ、電極絶縁膜(37)上には凸部(43a)が設けられ、凸部(43a)は、平面視でIC(46)と重畳し、且つ樹脂基板層(10)の基板表面に平行な方向(X,Y)から見て入力バンプ(47)及び出力バンプ(48)と重畳している。

Description

表示装置
 本発明は、表示装置に関するものである。
 近年、液晶表示装置に代わる表示装置として、有機EL(electroluminescence:エレクトロルミネッセンス)素子を用いた自発光型の有機EL表示装置が注目されている。この有機EL表示装置では、可撓性を有する樹脂基板(以下「フレキシブル基板」ともいう)上に、有機EL素子や種々のフィルム等が形成されていると共に、駆動用IC(integrated circuit:集積回路)が直接に実装された構造を有するフレキシブルな有機EL表示装置が提案されている。
 例えば、特許文献1には、駆動用ICを金属配線に接続する作業を行った後に、金属配線の露出部に保護コーティングを行う手間をなくすために、基板上に画像表示部と、前記画像表示部を構成する複数の電極を駆動するための駆動用ICとを備えた表示装置であって、前記駆動用ICを少なくとも前記画像表示部側の金属配線と接続状態に固定するための固定部材を、該金属配線を被覆する保護カバーと共用した表示装置が開示されている。
特開2003-223112号公報
 ところで、フレキシブルな有機EL表示装置では、フレキシブル基板にACF(anisotropic conductive film:異方性導電膜)を介してICを圧着するときに、熱と荷重を加えてボンディングするため、該フレキシブル基板に撓みが生じるという問題を発生することがあった。
 本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、ICを圧着するときのフレキシブル基板の撓みを低減することにある。
 上記目的を達成するために、本発明に係る表示装置は、フレキシブル基板と、上記フレキシブル基板上に設けられ、複数の薄膜トランジスタが設けられた薄膜トランジスタ層と、上記薄膜トランジスタ層上に設けられ、複数の第1電極、複数の機能層、及び第2電極を備えた複数の発光素子と、上記複数の発光素子を覆うように設けられた封止層と、を有し、複数の画素と複数の画素回路とを備えた表示領域、及び上記表示領域の周囲に設けられた額縁領域を備えた表示装置であって、上記額縁領域には、信号が入力される複数の入力バンプと、信号が出力される複数の出力バンプとを有する電子部品、及び上記複数の入力バンプに異方性導電膜を介してそれぞれ電気的に接続された複数の入力端子電極と、上記複数の出力バンプに異方性導電膜を介してそれぞれ電気的に接続された複数の出力端子電極とを備えた端子接続部が設けられ、上記端子接続部において、上記複数の入力端子電極及び上記複数の出力端子電極上には、電極絶縁膜が設けられ、上記電極絶縁膜には、上記複数の入力端子電極を露出させる入力電極開口部と、上記複数の出力端子電極を露出させる出力電極開口部とが設けられ、上記電極絶縁膜上には、凸部が設けられ、上記凸部は、平面視で上記電子部品と重畳し、且つ上記フレキシブル基板の基板表面に平行な方向から見て上記複数の入力バンプ及び上記複数の出力バンプと重畳していることを特徴とする。
 本発明によれば、端子接続部において、入力端子電極及び出力端子電極上に設けられた電極絶縁膜上には、凸部が設けられ、この凸部は、平面視で電子部品(IC)と重畳し、且つフレキシブル基板の基板表面に平行な方向から見てICの入力バンプ及び出力バンプと重畳しているため、ICを圧着するときのフレキシブル基板の撓みを低減することができる。
図1は、本発明の第1の実施形態に係る有機EL表示装置の概略構成を示す平面図である。 図2は、本発明の第1の実施形態に係る有機EL表示装置の概略構成を示す側面図である。 図3は、本発明の第1の実施形態に係る有機EL表示装置の表示領域の平面図である。 図4は、本発明の第1の実施形態に係る有機EL表示装置の表示領域の断面図である。 図5は、本発明の第1の実施形態に係る有機EL表示装置の画素回路を示す等価回路図である。 図6は、本発明の第1の実施形態に係る有機EL表示装置を構成する有機EL層を示す断面図である。 図7は、本発明の第1の実施形態に係る有機EL表示装置を構成するICの底面図である。 図8は、本発明の第1の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す平面図である。 図9は、図8中のIX-IX線に沿った本発明の第1の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す拡大断面図である。 図10(a)及び図10(b)は、それぞれ図9中の方向Y1及び図9中の方向Y2方向から見た本発明の第1の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す概略図である。 図11は、本発明の第1の実施形態に係る有機EL表示装置の凸部の厚みを説明するための拡大断面図である。 図12は、本発明の第1の実施形態に係る有機EL表示装置の額縁領域の端子接続部の変形例を示す拡大断面図であり、図9に相当する図である。 図13は、本発明の第2の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す平面図であり、図8に相当する図である。 図14は、本発明の第3の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す平面図であり、図8に相当する図である。 図15は、図14中のXV-XV線に沿った本発明の第3の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す拡大断面図であり、図9に相当する図である。 図16は、本発明の第4の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す平面図であり、図8に相当する図である。 図17は、図16中のXVII-XVII線に沿った本発明の第4の実施形態に係る有機EL表示装置の額縁領域の端子接続部を示す拡大断面図であり、図9に相当する図である。
 以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。
 《第1の実施形態》
 図1~図12は、本発明に係る表示装置の第1の実施形態を示している。なお、以下の各実施形態では、発光素子を備えた表示装置として、有機EL素子を備えた有機EL表示装置を例示する。ここで、図1は、本実施形態の有機EL表示装置50aの概略構成を示す平面図である。また、図2は、有機EL表示装置50aの概略構成を示す側面図である。また、図3は、有機EL表示装置50aの表示領域Dの平面図である。また、図4は、有機EL表示装置50aの表示領域Dの断面図である。また、図5は、有機EL表示装置50aの画素回路Cを示す等価回路図である。また、図6は、有機EL表示装置50aを構成する有機EL層23を示す断面図である。また、図7は、有機EL表示装置50aを構成するIC46の底面図である。また、図8は、有機EL表示装置50aの額縁領域Fの端子接続部Jを示す平面図である。また、図9は、図8中のIX-IX線に沿った有機EL表示装置50aの額縁領域Fの端子接続部Jを示す拡大断面図である。また、図10(a)及び図10(b)は、それぞれ図9中の方向Y1及び図9中の方向Y2方向から見た有機EL表示装置50aの額縁領域Fの端子接続部Jを示す概略図である。また、図11は、有機EL表示装置50aの凸部43aの厚みを説明するための拡大断面図である。また、図12は、有機EL表示装置50aの額縁領域Fの端子接続部Jの変形例を示す拡大断面図であり、図9に相当する図である。
 有機EL表示装置50aは、図1及び図2に示すように、例えば、矩形状に設けられた画像表示を行う表示領域Dと、表示領域Dの周囲に枠状に設けられた額縁領域Fとを備えている。なお、本実施形態では、矩形状の表示領域Dを例示したが、この矩形状には、例えば、辺が円弧状になった形状、角部が円弧状になった形状、辺の一部に切り欠きがある形状等の略矩形状も含まれている。
 表示領域Dには、図3に示すように、複数のサブ画素pがマトリクス状に配列されている。また、表示領域Dでは、図3に示すように、例えば、赤色の表示を行うための赤色発光領域Lrを有するサブ画素pr、緑色の表示を行うための緑色発光領域Lgを有するサブ画素pg、及び青色の表示を行うための青色発光領域Lbを有するサブ画素pbが互いに隣り合うように設けられている。なお、表示領域Dでは、例えば、赤色発光領域Lr、緑色発光領域Lg及び青色発光領域Lbを有する隣り合う3つのサブ画素pr,pb,pbにより、1つの画素Pが構成されている。
 額縁領域Fの図1中下側端部には、外部端子部Tが図中横方向に延びる方向Xに延びるように設けられている。また、額縁領域Fにおいて、図1及び図2に示すように、表示領域D及び外部端子部Tの間には、端子接続部Jが方向Xに延びるように設けられている。なお、有機EL表示装置50aでは、図1及び図2に示すように、後述する樹脂基板層10の基板表面に平行な方向Xと、方向Xに垂直で且つ樹脂基板層10の基板表面に平行な方向Yと、方向X及び方向Yに垂直な方向Zとが規定されている。
 また、有機EL表示装置50aは、図2及び図4に示すように、表示領域Dにおいて、フレキシブル基板として設けられた樹脂基板層10と、樹脂基板層10上に設けられ、複数の薄膜トランジスタ(TFT:thin film transistor)が設けられた薄膜トランジスタ層20と、薄膜トランジスタ層20上に表示領域Dを構成する発光素子として設けられた有機EL素子25と、有機EL素子25を覆うように設けられた封止層29とを備えている。また、樹脂基板層10の裏面(図2では右側表面、図4では下側表面)には、フィルム層60が設けられている。
 樹脂基板層10は、例えば、ポリイミド樹脂等により構成されている。
 薄膜トランジスタ層20は、図4に示すように、樹脂基板層10上に設けられたベースコート膜11と、ベースコート膜11上にサブ画素p毎に画素回路C(図5参照)として設けられた第1TFT9a、第2TFT9b及びキャパシタ9cと、各第1TFT9a、各第2TFT9b及び各キャパシタ9c上に設けられたTFT用の平坦化膜19とを備えている。ここで、薄膜トランジスタ層20には、複数のサブ画素pに対応して、複数の画素回路Cがマトリクス状に配列されている。また、薄膜トランジスタ層20には、図3及び図5に示すように、図中横方向に互いに平行に延びるように複数のゲート線14が設けられている。また、薄膜トランジスタ層20には、図3及び図5に示すように、図中縦方向に互いに平行に延びるように複数のソース線18fが設けられている。また、薄膜トランジスタ層20には、図3及び図5に示すように、図中縦方向に互いに平行に延びるように複数の電源線18gが設けられている。なお、各電源線18gは、図3に示すように、各ソース線18fと隣り合うように設けられている。
 ベースコート膜11は、例えば、窒化シリコン、酸化シリコン、酸窒化シリコン等の無機絶縁膜の単層膜又は積層膜により構成されている。
 第1TFT9aは、図5に示すように、各サブ画素pにおいて、対応するゲート線14及びソース線18fに電気的に接続されている。また、第1TFT9aは、図4に示すように、ベースコート膜11上に順に設けられた半導体層12a、ゲート絶縁膜13、ゲート電極14a、第1層間絶縁膜15、第2層間絶縁膜17、並びにソース電極18a及びドレイン電極18bを備えている。ここで、半導体層12aは、例えば、ポリシリコン膜により、図4に示すように、ベースコート膜11上に島状に設けられ、チャネル領域、ソース領域及びドレイン領域を有している。また、ゲート絶縁膜13は、図4に示すように、半導体層12aを覆うように設けられている。また、ゲート電極14aは、図4に示すように、ゲート絶縁膜13上に半導体層12aのチャネル領域と重なるように設けられている。また、第1層間絶縁膜15及び第2層間絶縁膜17は、図4に示すように、ゲート電極14aを覆うように順に設けられている。また、ソース電極18a及びドレイン電極18bは、図4に示すように、第2層間絶縁膜17上に互いに離間するように設けられている。また、ソース電極18a及びドレイン電極18bは、図4に示すように、ゲート絶縁膜13、第1層間絶縁膜15及び第2層間絶縁膜17の積層膜に形成された各コンタクトホールを介して、半導体層12aのソース領域及びドレイン領域にそれぞれ電気的に接続されている。なお、ゲート絶縁膜13、第1層間絶縁膜15及び第2層間絶縁膜17は、例えば、窒化シリコン、酸化シリコン、酸窒化シリコン等の無機絶縁膜の単層膜又は積層膜により構成されている。
 第2TFT9bは、図5に示すように、各サブ画素pにおいて、対応する第1TFT9a及び電源線18gに電気的に接続されている。また、第2TFT9bは、図4に示すように、ベースコート膜11上に順に設けられた半導体層12b、ゲート絶縁膜13、ゲート電極14b、第1層間絶縁膜15、第2層間絶縁膜17、並びにソース電極18c及びドレイン電極18dを備えている。ここで、半導体層12bは、例えば、ポリシリコン膜により、図4に示すように、ベースコート膜11上に島状に設けられ、チャネル領域、ソース領域及びドレイン領域を有している。また、ゲート絶縁膜13は、図4に示すように、半導体層12bを覆うように設けられている。また、ゲート電極14bは、図4に示すように、ゲート絶縁膜13上に半導体層12bのチャネル領域と重なるように設けられている。また、第1層間絶縁膜15及び第2層間絶縁膜17は、図4に示すように、ゲート電極14bを覆うように順に設けられている。また、ソース電極18c及びドレイン電極18dは、図4に示すように、第2層間絶縁膜17上に互いに離間するように設けられている。また、ソース電極18c及びドレイン電極18dは、図4に示すように、ゲート絶縁膜13、第1層間絶縁膜15及び第2層間絶縁膜17の積層膜に形成された各コンタクトホールを介して、半導体層12bのソース領域及びドレイン領域にそれぞれ電気的に接続されている。
 なお、本実施形態では、トップゲート型の第1TFT9a及び第2TFT9bを例示したが、第1TFT9a及び第2TFT9bは、ボトムゲート型のTFTであってもよい。
 キャパシタ9cは、図5に示すように、各サブ画素pにおいて、対応する第1TFT9a及び電源線18gに電気的に接続されている。ここで、キャパシタ9cは、図4に示すように、ゲート電極14a及び14bと同一材料により同一層に形成された下部導電層14cと、下部導電層14cを覆うように設けられた第1層間絶縁膜15と、第1層間絶縁膜15上に下部導電層14cと重なるように設けられた上部導電層16とを備えている。なお、上部導電層16は、図4に示すように、第2層間絶縁膜17に形成されたコンタクトホールを介して電源線18gに電気的に接続されている。
 平坦化膜19は、例えば、ポリイミド樹脂等の有機樹脂材料により構成されている。
 有機EL素子25は、図4に示すように、平坦化膜19上に順に設けられた複数の第1電極21と、エッジカバー22と、機能層として設けられた複数の有機EL層23と、第2電極24とを備えている。
 複数の第1電極21は、図4に示すように、複数のサブ画素pに対応するように、平坦化膜19上にマトリクス状に設けられている。また、各第1電極21は、図4に示すように、平坦化膜19に形成されたコンタクトホールを介して、各第2TFT9bのドレイン電極18d(又はソース電極18c)に電気的に接続されている。また、第1電極21は、有機EL層23にホール(正孔)を注入する機能を有している。また、第1電極21は、有機EL層23への正孔注入効率を向上させるために、仕事関数の大きな材料で形成するのがより好ましい。ここで、第1電極21を構成する材料としては、例えば、銀(Ag)、アルミニウム(Al)、バナジウム(V)、コバルト(Co)、ニッケル(Ni)、タングステン(W)、金(Au)、チタン(Ti)、ルテニウム(Ru)、マンガン(Mn)、インジウム(In)、イッテルビウム(Yb)、フッ化リチウム(LiF)、白金(Pt)、パラジウム(Pd)、モリブデン(Mo)、イリジウム(Ir)、スズ(Sn)等の金属材料が挙げられる。また、第1電極21を構成する材料は、例えば、アスタチン(At)/酸化アスタチン(AtO)等の合金であっても構わない。さらに、第1電極21を構成する材料は、例えば、酸化スズ(SnO)、酸化亜鉛(ZnO)、インジウムスズ酸化物(ITO)、インジウム亜鉛酸化物(IZO)のような導電性酸化物等であってもよい。また、第1電極21は、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数の大きな化合物材料としては、例えば、インジウムスズ酸化物(ITO)やインジウム亜鉛酸化物(IZO)等が挙げられる。
 エッジカバー22は、図4に示すように、各第1電極21の周縁部を覆うように格子状に設けられている。ここで、エッジカバー22を構成する材料としては、例えば、ポリイミド樹脂、アクリル樹脂、ポリシロキサン樹脂、ノボラック樹脂等のポジ型の感光性樹脂が挙げられる。また、エッジカバー22の表面の一部は、図4に示すように、図中上方に突出して、島状に設けられた画素フォトスペーサになっている。
 複数の有機EL層23は、図4に示すように、各第1電極21上に配置され、複数のサブ画素pに対応するように、マトリクス状に設けられている。ここで、各有機EL層23は、図6に示すように、第1電極21上に順に設けられた正孔注入層1、正孔輸送層2、発光層3、電子輸送層4及び電子注入層5を備えている。
 正孔注入層1は、陽極バッファ層とも呼ばれ、第1電極21と有機EL層23とのエネルギーレベルを近づけ、第1電極21から有機EL層23への正孔注入効率を改善する機能を有している。ここで、正孔注入層1を構成する材料としては、例えば、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、フェニレンジアミン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体等が挙げられる。
 正孔輸送層2は、第1電極21から有機EL層23への正孔の輸送効率を向上させる機能を有している。ここで、正孔輸送層2を構成する材料としては、例えば、ポルフィリン誘導体、芳香族第三級アミン化合物、スチリルアミン誘導体、ポリビニルカルバゾール、ポリ-p-フェニレンビニレン、ポリシラン、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、ピラゾロン誘導体、フェニレンジアミン誘導体、アリールアミン誘導体、アミン置換カルコン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体、水素化アモルファスシリコン、水素化アモルファス炭化シリコン、硫化亜鉛、セレン化亜鉛等が挙げられる。
 発光層3は、第1電極21及び第2電極24による電圧印加の際に、第1電極21及び第2電極24から正孔及び電子がそれぞれ注入されると共に、正孔及び電子が再結合する領域である。ここで、発光層3は、発光効率が高い材料により形成されている。そして、発光層3を構成する材料としては、例えば、金属オキシノイド化合物[8-ヒドロキシキノリン金属錯体]、ナフタレン誘導体、アントラセン誘導体、ジフェニルエチレン誘導体、ビニルアセトン誘導体、トリフェニルアミン誘導体、ブタジエン誘導体、クマリン誘導体、ベンズオキサゾール誘導体、オキサジアゾール誘導体、オキサゾール誘導体、ベンズイミダゾール誘導体、チアジアゾール誘導体、ベンズチアゾール誘導体、スチリル誘導体、スチリルアミン誘導体、ビススチリルベンゼン誘導体、トリススチリルベンゼン誘導体、ペリレン誘導体、ペリノン誘導体、アミノピレン誘導体、ピリジン誘導体、ローダミン誘導体、アクイジン誘導体、フェノキサゾン、キナクリドン誘導体、ルブレン、ポリ-p-フェニレンビニレン、ポリシラン等が挙げられる。
 電子輸送層4は、電子を発光層3まで効率良く移動させる機能を有している。ここで、電子輸送層4を構成する材料としては、例えば、有機化合物として、オキサジアゾール誘導体、トリアゾール誘導体、ベンゾキノン誘導体、ナフトキノン誘導体、アントラキノン誘導体、テトラシアノアントラキノジメタン誘導体、ジフェノキノン誘導体、フルオレノン誘導体、シロール誘導体、金属オキシノイド化合物等が挙げられる。
 電子注入層5は、第2電極24と有機EL層23とのエネルギーレベルを近づけ、第2電極24から有機EL層23へ電子が注入される効率を向上させる機能を有し、この機能により、有機EL素子25の駆動電圧を下げることができる。なお、電子注入層5は、陰極バッファ層とも呼ばれる。ここで、電子注入層5を構成する材料としては、例えば、フッ化リチウム(LiF)、フッ化マグネシウム(MgF)、フッ化カルシウム(CaF)、フッ化ストロンチウム(SrF)、フッ化バリウム(BaF)のような無機アルカリ化合物、酸化アルミニウム(Al)、酸化ストロンチウム(SrO)等が挙げられる。
 第2電極24は、図4に示すように、各有機EL層23及びエッジカバー22を覆うように設けられている。また、第2電極24は、有機EL層23に電子を注入する機能を有している。また、第2電極24は、有機EL層23への電子注入効率を向上させるために、仕事関数の小さな材料で構成するのがより好ましい。ここで、第2電極24を構成する材料としては、例えば、銀(Ag)、アルミニウム(Al)、バナジウム(V)、コバルト(Co)、ニッケル(Ni)、タングステン(W)、金(Au)、カルシウム(Ca)、チタン(Ti)、イットリウム(Y)、ナトリウム(Na)、ルテニウム(Ru)、マンガン(Mn)、インジウム(In)、マグネシウム(Mg)、リチウム(Li)、イッテルビウム(Yb)、フッ化リチウム(LiF)等が挙げられる。また、第2電極24は、例えば、マグネシウム(Mg)/銅(Cu)、マグネシウム(Mg)/銀(Ag)、ナトリウム(Na)/カリウム(K)、アスタチン(At)/酸化アスタチン(AtO)、リチウム(Li)/アルミニウム(Al)、リチウム(Li)/カルシウム(Ca)/アルミニウム(Al)、フッ化リチウム(LiF)/カルシウム(Ca)/アルミニウム(Al)等の合金により形成されていてもよい。また、第2電極24は、例えば、酸化スズ(SnO)、酸化亜鉛(ZnO)、インジウムスズ酸化物(ITO)、インジウム亜鉛酸化物(IZO)等の導電性酸化物により形成されていてもよい。また、第2電極24は、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数が小さい材料としては、例えば、マグネシウム(Mg)、リチウム(Li)、フッ化リチウム(LiF)、マグネシウム(Mg)/銅(Cu)、マグネシウム(Mg)/銀(Ag)、ナトリウム(Na)/カリウム(K)、リチウム(Li)/アルミニウム(Al)、リチウム(Li)/カルシウム(Ca)/アルミニウム(Al)、フッ化リチウム(LiF)/カルシウム(Ca)/アルミニウム(Al)等が挙げられる。
 封止層29は、図4に示すように、第2電極24を覆うように設けられた第1無機絶縁膜26と、第1無機絶縁膜26上に設けられた有機膜27と、有機膜27を覆うように設けられた第2無機絶縁膜28とを備え、有機EL層23を水分や酸素等から保護する機能を有している。ここで、第1無機絶縁膜26及び第2無機絶縁膜28は、例えば、酸化シリコン(SiO)や酸化アルミニウム(Al)、四窒化三ケイ素(Si)のような窒化シリコン(SiNx(xは正数))、炭窒化ケイ素(SiCN)等の無機材料により構成されている。また、有機膜27は、例えば、アクリル樹脂、ポリ尿素樹脂、パリレン樹脂、ポリイミド樹脂、ポリアミド樹脂等の有機材料により構成されている。
 フィルム層60は、図2及び図4に示すように、樹脂基板層10の薄膜トランジスタ層20が設けられた面とは反対側の表面に、例えば、接着層61を介して貼り付けられている。また、フィルム層60は、表示領域D及び額縁領域F全体に配置されている。なお、フィルム層60は、例えば、ポリエチレンテレフタレート(PET)樹脂等からなるプラスチックフィルムにより構成されている。
 また、有機EL表示装置50aでは、図1に示すように、額縁領域Fの外部端子部Tに、複数の外部端子電極30が配列されている。この外部端子電極30は、外部から信号を入力するためのものであり、例えば、ACFを介してFPC(Flexible printed circuits)(不図示)等の各電極と電気的に接続されている。
 また、有機EL表示装置50aは、図1及び図2に示すように、額縁領域Fの端子接続部Jにおいて、電子部品として設けられたIC46と、樹脂基板層10の裏面(IC46が設けられた面とは反対側の表面)に設けられたフィルム層60とを備えている。
 IC46は、例えば、各画素回路Cに駆動信号を供給するための駆動用ICであり、図1及び図2に示すように、端子接続部Jに圧着接続されている。このIC46の裏面(端子接続部Jに実装される面)には、図7に示すように、信号が入力される複数の入力バンプ47と、信号が出力される複数の出力バンプ48とがそれぞれ離間して配置されている。そして、IC46の裏面には、図7に示すように、複数の入力バンプ47の全部を囲む入力バンプ領域R47、及び複数の出力バンプ48の全部を囲む出力バンプ領域R48がそれぞれ設けられている。なお、図7に示すように、入力バンプ領域R47及び出力バンプ領域R48(以下「バンプ領域R47,R48」ともいう)の間、換言するとIC46の裏面の中央部には、入力バンプ47及び出力バンプ48(以下「バンプ47,48」ともいう)が配置されていない。
 入力バンプ47は、IC46の長手方向(図7では方向X)における一方の側縁に沿って1列に配列され、出力バンプ48は、他方の側縁に沿って2列に平面視で千鳥状に配列されている。また、出力バンプ48は、入力バンプ47に比して、面積が小さく、数が多くなっている。また、バンプ47,48は、平面視で矩形状に形成されている。
 また、有機EL表示装置50aは、図9及び図11に示すように、端子接続部Jにおいて、樹脂基板層10上に順に設けられた第1無機絶縁膜31と、複数の第1引き回し配線32及び複数の第2引き回し配線33と、第2無機絶縁膜34と、複数の入力端子電極35及び複数の出力端子電極36と、絶縁膜として設けられた電極絶縁膜37と、凸部43aを備えている。
 第1無機絶縁膜31は、樹脂基板層10上に設けられた防湿膜であり、ベースコート膜11、ゲート絶縁膜13、第1層間絶縁膜15等と同一材料により同一層に形成されている。
 第1引き回し配線32及び第2引き回し配線33(以下「引き回し配線32,33」ともいう)は、図9及び図11に示すように、それぞれ第1無機絶縁膜31上に複数に設けられている。これら引き回し配線32,33は、ゲート電極14a、上部導電層16等と同一材料により同一層にそれぞれ形成されている。
 また、各第1引き回し配線32は、各出力端子電極36に電気的に接続され、各画素回路Cに信号を入力するように構成されている。一方、各第2引き回し配線33は、各外部端子電極30及び各入力端子電極35にそれぞれ電気的に接続されている。即ち、各外部端子電極30と各入力端子電極35とは、各第2引き回し配線33を介して電気的に接続されている。
 第2無機絶縁膜34は、図9及び図11に示すように、第1無機絶縁膜31上、第1引き回し配線32、及び第2引き回し配線33上に設けられている。
 また、図9及び図11に示すように、第2無機絶縁膜34には、平面視において、各出力バンプ48と重畳し、各第1引き回し配線32を露出させる第1配線開口部38と、各入力バンプ47と重畳し、第2引き回し配線33を露出させる第2配線開口部39とがそれぞれ形成されている。そして、第1配線開口部38において、各出力端子電極36と露出した各第1引き回し配線32とが接し、第2配線開口部39において、各入力端子電極35と露出した各第2引き回し配線33とが接している。
 なお、第2無機絶縁膜34は、第1層間絶縁膜15、第2層間絶縁膜17等と同一材料により同一層に形成されている。
 ここで、引き回し配線32,33がゲート電極14aにより構成されているときは、第1無機絶縁膜31はベースコート膜11及びゲート絶縁膜13により構成され、第2無機絶縁膜34は第1層間絶縁膜15及び第2層間絶縁膜17により構成される。一方、引き回し配線32,33が上部導電層16により構成されているときは、第1無機絶縁膜31はベースコート膜11、ゲート絶縁膜13及び第1層間絶縁膜15により構成され、第2無機絶縁膜34は第2層間絶縁膜17により構成される。
 各入力端子電極35は、図9及び図11に示すように、平面視で各入力バンプ47と重畳するように、第2配線開口部39から露出した第2引き回し配線33上、及び第2無機絶縁膜34の周縁部上に設けられている。一方、各出力端子電極36は、平面視で各出力バンプ48と重畳するように、第1配線開口部38から露出した第1引き回し配線32上、及び第2無機絶縁膜34の周縁部上に設けられている。
 より具体的には、図8に示すように、各入力端子電極35は、各入力バンプ47に対応して平面視で矩形状に複数に形成され、出力端子電極36は、各出力バンプ48に対応して平面視で矩形状に複数に形成されている。また、入力端子電極35は、端子接続部Jの一方の側縁に沿って1列に配列され、出力端子電極36は、他方の側縁に沿って平面視で2列の千鳥状に配列されている。また、出力端子電極36は、入力端子電極35に比して、面積が小さく、数が多くなっている。なお、図8では、IC46の図示が簡略化され、IC46のバンプ47,48が省略されている。
 一方、図8に示すように、入力端子電極35及び出力端子電極36(以下「端子電極35,36」ともいう)の間、換言すると、IC46の中央部に対応する端子接続部Jの中央部には、端子電極35,36が配列されていない電極間領域rが設けられている。
 また、各入力端子電極35は、各入力バンプ47にACF49を介して電気的に接続され、各出力端子電極36は、各出力バンプ48にACF49を介して電気的に接続されている。これら端子電極35,36は、それぞれソース線18fと同一材料により同一層に形成されている。
 電極絶縁膜37は、図9及び図11に示すように、端子電極35,36の周縁部を覆うように、端子電極35,36及び第2無機絶縁膜34上に設けられている。即ち、電極絶縁膜37は、端子電極35,36のエッジカバー且つ平坦化膜である。この電極絶縁膜37は、有機絶縁膜の単層膜又は積層膜により構成され、例えば、平坦化膜19と同一材料により形成されている。
 また、電極絶縁膜37には、図8、図9及び図11に示すように、入力端子電極35の全部を露出させる入力電極開口部40と、出力端子電極36の全てを露出させる出力電極開口部41とがそれぞれ形成されている。
 入力電極開口部40は、入力端子電極35の全部を囲むように、端子接続部Jが延びる方向Xに沿って平面視で矩形状に形成されている。出力電極開口部41は、出力端子電極36の全部を囲むように、方向Xに沿って平面視で矩形状に形成されている。これら2つの入力電極開口部40及び出力電極開口部41(以下「電極開口部40,41」ともいう)は、図8に示すように、電極間領域rの方向Yの両端にそれぞれ形成されている。換言すると、電極開口部40,41は、それぞれバンプ領域R47,R48に対応するように形成されている。なお、電極開口部40,41の平面形状は、図示した矩形状だけでなく、例えば、多角形状、台形状、楕円形状等でもよい。
 また、図9に示すように、方向Yにおいて、入力電極開口部40は、その開口縁部の寸法Y40が入力端子電極35の寸法Y35よりも大きくなるように形成され、出力電極開口部41は、その寸法Y41が出力端子電極36の寸法Y36よりも大きくなるように形成されている。これは、IC46を端子接続部Jに圧着するときに方向YにIC46の位置ずれが生じたとしても、平面視で、バンプ47,48と後述する凸部43aとが重畳しないようにするためである。なお、例えば、図9に示すように、出力電極開口部41に出力端子電極36が方向Yに沿って複数(図9では2つ)配置される場合、出力電極開口部41の寸法Y41は、出力端子電極36の寸法Y36を複数分加算した寸法よりも大きくなるように調整すればよい。但し、入力電極開口部40の寸法Y40、及び出力電極開口部41の寸法Y41は、電極開口部40,41がIC46の外側縁部よりも小さくなるように調整する。
 ここで、有機EL表示装置50aでは、図9及び図11に示すように、電極絶縁膜37上に、IC46の方向に向かって突出するように、凸部43aが設けられている。この凸部43aは、有機絶縁膜の単層膜又は積層膜により構成され、例えば、エッジカバー22と同一材料により同一層に形成されている。
 凸部43aは、図8に示すように、入力電極開口部40を囲むように入力電極開口部40の周囲に沿って設けられていると共に、出力電極開口部41を囲むように出力電極開口部41の周囲に沿って設けられている。換言すると、凸部43aは、入力バンプ領域R47の周囲に沿って設けられていると共に、出力バンプ48の周囲に沿って設けられている。このように、凸部43aは、バンプ47,48の全部を囲むIC46の輪郭(外周縁部)に対応した平面視で枠状に構成されている。
 また、凸部43aは、図8に示すように、入力電極開口部40と出力電極開口部41との間(即ち、電極間領域r)に、端子接続部Jが延びる方向Xに沿って平面視で帯状に設けられている。換言すると、凸部43aは、入力バンプ領域R47及び出力バンプ領域R48の間(即ち、IC46の中央部)に対応するように設けられている。
 ここで、凸部43aは、図8及び図9に示すように、平面視で、IC46の端部(外周縁部)及び中央部において、IC46とACF49を介して重畳している。また、凸部43aは、図9及び図10に示すように、樹脂基板層10の基板表面に平行な方向から見て、バンプ47,48と重畳している。なお、樹脂基板層10の基板表面に平行な方向とは、例えば、図9及び図10において、方向Xに平行な方向、方向Y(方向Y1、Y2等)に平行な方向、方向X及び方向Yに傾斜する方向に平行な方向等の全ての方向を含む。換言すると、凸部43aは、平面視でバンプ47,48と重畳していない。
 このように、凸部43aは、平面視において、IC46と重畳する一方、バンプ47,48と重畳しないように、IC46の外周縁部に沿って配置されているため、IC46を端子接続部Jに圧着するときに、ACF49の導電性粒子49aを介してIC46の外周縁部に沿う底面部と凸部43aとが接する。その結果、IC46の外周縁部に沿う樹脂基板層10及びフィルム層60の撓みが低減される。
 また、凸部43aは、平面視において、IC46と重畳する一方、バンプ47,48と重畳しないように、IC46の中央部に対応して配置されているため、IC46を端子接続部Jに圧着するときに、該導電性粒子49aを介してIC46の中央部における底面部と凸部43aとが接する。その結果、IC46の中央部に対応する樹脂基板層10及びフィルム層60の撓みが低減される。
 そして、IC46を端子接続部Jに圧着するときの樹脂基板層10の撓みが低減される結果、該樹脂基板層10上に設けられた第1無機絶縁膜31、第2無機絶縁膜34、電極絶縁膜37等の無機絶縁層や、引き回し配線32,33、端子電極35,36等の金属層にかかる応力が低減される。
 また、一般に、フィルム層60の線膨張係数は、樹脂基板層10の線膨張係数よりも大きいため、IC46を端子接続部Jに圧着するときに、樹脂基板層10に比してフィルム層60が膨張する。そのため、凸部43aが設けられていない有機EL表示装置では、IC46の圧着後に、IC46の外周縁部及び中央部に対応する樹脂基板層10、接着層61、及びフィルム層60のうち、密着力が最も弱い層間が剥離することがある。より具体的には、樹脂基板層10とその下層のフィルム層60にかかる応力の差によって樹脂基板層10とフィルム層60との間にある接着層61を境界とした剥離が生じることがある。それに対し、有機EL表示装置50aでは、ACF49の導電性粒子49aを介してIC46の底面と凸部43aとの接する面積が多いため、樹脂基板層10及びフィルム層60の撓みが低減され、その結果、上記応力の差が小さくなり、IC46の圧着後の上記層間の剥離が抑制される。
 また、凸部43aが設けられていない有機EL表示装置では、IC46の圧着後に、端子電極35,36が断面視で凹型に変形することがある。この場合、バンプ47,48の外周縁部及び中央部と、導電性粒子49aとの機械的接続性が弱くなり、電気的接続性が低下するおそれがある。これに対し、有機EL表示装置50aでは、IC46の外周縁部及び中央部の双方に対応して凸部43aが設けられているため、樹脂基板層10の撓みが低減され、樹脂基板層10の上層にある端子電極35,36が断面視で凹型に変形し難くなる。これにより、機械的接続性が維持され、電気的接続性の低下が抑制される。但し、IC46の外周縁部及び中央部のいずれか一方にのみ対応して凸部43aを設けても樹脂基板層10の撓みは低減されるが、樹脂基板層10がフレキシブルであるため、IC46の外周縁部及び中央部の双方に対応して凸部43aを設けたほうが、樹脂基板層10の撓みをより一層低減でき、機械的接続性及び電気的接続性の効果が高くなる。
 なお、図11に示すように、凸部43aの厚み(方向Zの寸法)Zeは、第2無機絶縁膜34の厚みZc、端子電極35,36の厚みZa、及び電極絶縁膜37の厚みZdに応じて、IC46の底面に導電性粒子49aを介して凸部43aが当たるように決定すればよい。
 より具体的には、図11に示すように、導電性粒子49aの粒子径を除く、パネル電極部(バンプ47,48側)fのIC46の底面と引き回し配線32,33との電極層表面間の高さ(Z方向の寸法)をZf、IC端部(凸部43a側)gのIC46の底面と引き回し配線32,33との電極層表面間の高さをZgとすると、以下の数式1に示す、パネル電極部fの高さZfと、IC端部gの高さZgとの段差Δの値が小さくなるように決定すればよい。なお、バンプ47,48の高さZbは、例えば、7μm程度である。また、導電性粒子49aの粒子径は、例えば、2~4μm程度である。
 [数1]
 Δ=Zf-Zg(なお、式中、Zf=Za+Zb、Zg=Zc+Zd+Zeである。)
 上述した有機EL表示装置50aは、各サブ画素pにおいて、ゲート線14を介して第1TFT9aにゲート信号を入力することにより、第1TFT9aをオン状態にし、ソース線18fを介して第2TFT9bのゲート電極14b及びキャパシタ9cにデータ信号を書き込み、第2TFT9bのゲート電圧に応じた電源線18gからの電流が有機EL層23に供給されることにより、有機EL層23の発光層3が発光して、画像表示を行うように構成されている。なお、有機EL表示装置50aでは、第1TFT9aがオフ状態になっても、第2TFT9bのゲート電圧がキャパシタ9cによって保持されるので、次のフレームのゲート信号が入力されるまで発光層3による発光が維持される。
 次に、本実施形態の有機EL表示装置50aの製造方法について説明する。本実施形態の有機EL表示装置50aの製造方法は、樹脂基板層形成工程と、薄膜トランジスタ層形成工程、有機EL素子形成工程、封止層形成工程、外部端子部形成工程、端子接続部形成工程、及びフィルム貼付工程を備える。
 <樹脂基板層形成工程>
 例えば、ガラス基板等の支持基板(不図示)上に、非感光性のポリイミド樹脂を塗布した後、その塗布膜に対して、プリベーク及びポストベークを行うことにより、樹脂基板層10を形成する。
 <薄膜トランジスタ層形成工程>
 上記樹脂基板層形成工程で形成された樹脂基板層10上に、例えば、周知の方法を用いて、ベースコート膜11、第1TFT9a、第2TFT9b、キャパシタ9c、及び平坦化膜19を形成して、薄膜トランジスタ層20を形成する。
 <有機EL素子形成工程>
 上記薄膜トランジスタ層形成工程で形成された薄膜トランジスタ層20の平坦化膜19上に、周知の方法を用いて、第1電極21、エッジカバー22、有機EL層23(正孔注入層1、正孔輸送層2、発光層3、電子輸送層4、電子注入層5)及び第2電極24を形成して、有機EL素子25を形成する。
 <封止層形成工程>
 まず、上記有機EL素子形成工程で形成された有機EL素子25が形成された基板表面に、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマCVD法により成膜して、第1無機絶縁膜26を形成する。
 続いて、第1無機絶縁膜26が形成された基板表面に、例えば、インクジェット法により、アクリル樹脂等の有機樹脂材料を成膜して、有機膜27を形成する。
 さらに、有機膜27が形成された基板に対して、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマCVD法により成膜して、第2無機絶縁膜28を形成することにより、封止層29を形成する。
 <外部端子部形成工程>
 額縁領域Fの端部における第2層間絶縁膜17上に、周知の方法を用いて、外部端子電極30を形成することにより、外部端子部Tを形成する。
 <端子接続部形成工程>
 表示領域D及び外部端子部Tの間における額縁領域Fにおいて、樹脂基板層10上に、周知の方法を用いて、第1無機絶縁膜31、引き回し配線32,33、第2無機絶縁膜34、端子電極35,36、電極絶縁膜37、及び凸部43aを形成することにより、端子接続部Jを形成する。なお、第1無機絶縁膜31、引き回し配線32,33、第2無機絶縁膜34、端子電極35,36、及び電極絶縁膜37は、上記薄膜トランジスタ層形成工程で、ベースコート膜11、第1TFT9aのゲート絶縁膜13、ゲート電極14a、第1層間絶縁膜15、第2層間絶縁膜17、ソース電極18a、平坦化膜19等を形成するときに同時に形成すればよい。また、凸部43aは、上記有機EL素子形成工程で、エッジカバー22を形成するときに同時に形成すればよい。
 より具体的には、第2無機絶縁膜34を形成した後、端子電極35,36を形成する前に、ドライエッチングにより第2無機絶縁膜34に第1配線開口部38及び第2配線開口部39を形成する。その後、これら第1配線開口部38及び第2配線開口部39を埋めるように端子電極35,36を形成する。
 続いて、電極絶縁膜37を形成した後、凸部43aを形成する前に、ドライエッチングにより、電極絶縁膜37に電極開口部40,41を形成することにより、端子電極35,36の全てを露出させると共に、端子電極35,36のエッジカバーを形成する。
 最後に、電極開口部40,41の周囲に沿う電極絶縁膜37上に凸部43aを形成する。なお、凸部43aは、凸部43aのパターニング後のエッチングにより、電極絶縁膜37が削れないように、フォトマスク側でグレートーン加工等を行い、厚みを調整すればよい。
 <フィルム貼付工程>
 上記樹脂基板層形成工程の後に、樹脂基板層10に対して支持基板側からレーザー光を照射することにより、樹脂基板層10の薄膜トランジスタ層20が設けられた面とは反対側の表面から支持基板を剥離する。続いて、支持基板を剥離した樹脂基板層10の表面に接着層61を介して、フィルム層60を貼り付ける。
 以上のようにして、本実施形態の有機EL表示装置50aを製造することができる。
 なお、有機EL表示装置50aでは、凸部は、図12に示すように、電極絶縁膜37上に凸部43aを設けず、電極絶縁膜37を厚膜化することにより構成されていてもよい。この場合、上記端子接続部形成工程において、エッチングにより、端子電極35,36を露出させると共にそのエッジカバーを形成し、その周辺をグレートーン加工やハーフトーン加工等を施すことにより浅めに掘り、電極絶縁膜37に段差を設ける。一方、IC46の外周縁部及び中央部に対応する電極絶縁膜37はエッチングされないように残すことで、厚膜化された電極絶縁膜37により凸部を構成することができる。
 以上説明したように、本実施形態の有機EL表示装置50aによれば、以下の効果を得ることができる。
 (1)凸部43aは、平面視でIC46と重畳し、且つ樹脂基板層10の基板表面に平行な方向から見てバンプ47,48と重畳しているため、IC46を端子接続部Jに圧着するときに、ACF49の導電性粒子49aを介してIC46の底面と凸部43aとが接する。これにより、IC46を端子接続部Jに圧着するときの樹脂基板層10及びフィルム層60の撓みが低減される。
 (2)IC46を端子接続部Jに圧着するときの樹脂基板層10の撓みが低減される結果、該樹脂基板層10上に設けられた無機絶縁層や金属層にかかる応力が低減されるる。これにより、無機絶縁層のクラックの発生や、金属層からなる各電極、各配線の断線が抑制される。
 (3)凸部43aは、IC46の外周縁部及び中央部に対応して配置されているため、IC46の圧着後の樹脂基板層10及びフィルム層60にかかる応力が低減され、該応力の差が小さくなる。これにより、樹脂基板層10とフィルム層60との間にある接着層61を境界とした剥離が抑制される。
 (4)IC46の圧着後の樹脂基板層10にかかる応力が低減される結果、IC46の圧着後の端子電極35,36が断面視で凹型に変形し難くなる。これにより、機械的接続性が維持され、電気的接続性の低下が抑制される。
 (5)無機絶縁層のクラックの発生や、金属層からなる各電極、各配線の断線が抑制される結果、有機EL表示装置50aの封止性能、電気的特性及び耐環境性能の劣化が抑制される。これにより、有機EL表示装置50aの寿命低下等の問題を防ぐことができる。
 《第2の実施形態》
 次に、本発明の第2の実施形態について説明する。図13は、本実施形態の有機EL表示装置50bの額縁領域Fの端子接続部Jを示す平面図であり、図8に相当する図である。なお、端子接続部J以外の表示領域D及び額縁領域F等を含む有機EL表示装置50bの全体構成は、上述の第1の実施形態の場合と同じであるため、ここでは詳しい説明を省略する。また、上記第1の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。
 有機EL表示装置50bでは、図13に示すように、凸部43bは、平面視で島状(柱状)に複数に設けられている点に特徴がある。なお、図13では、IC46の図示が簡略化され、IC46のバンプ47,48が省略されている。
 換言すると、凸部43bは、平面視で、矩形状、多角形状、円形状、楕円形状、及び菱形状の何れか1つの形状、又はこれらの形状を組み合わせた形状を有する柱状体である。これにより、IC46を端子接続部Jに圧着するときのACF49の熱硬化性樹脂49bの流動性(以下「樹脂流動性」という)が向上される。その結果、バンプ47,48、又は端子電極35,36と、導電性粒子49aとの機械的接続性が維持される。
 なお、凸部43bの大きさ、形状、数、位置等は、特に限定されず、IC46を端子接続部Jに圧着するときの樹脂基板層10及びフィルム層60の撓みが低減されるように決定すればよい。例えば、IC46の端部に沿う凸部43bの形状と、IC46の中央部に対応する凸部43bの形状とは、同じであってもよく、異なっていてもよい。また、各凸部43bの位置は、等間隔でもよく、ランダムでもよい。なお、凸部43bの形状が矩形状の場合、IC46を端子接続部Jに圧着するときのACF49の樹脂流動性を向上する観点から、IC46の中央部に対応する位置には、電極間領域rを介してバンプ47,48が配置される方向(図13では方向Y)に延びるように配置されていることが好ましい。
 また、凸部43bは、図13に示すように、IC46の外周縁部及び中央部に対応して配置されている。そして、凸部43bは、図13に示すように、平面視で、IC46の外周縁部及び中央部において、IC46と重畳し、且つ樹脂基板層10の基板表面に平行な方向から見てバンプ47,48と重畳している。
 より具体的には、凸部43bは、バンプ47,48と、方向Xに平行な方向、方向Yに平行な方向、方向X及び方向Yに傾斜する方向に平行から見て重畳している。
 ここで、凸部43bは、各々独立した柱状体の場合、有機絶縁膜の単層膜又は積層膜の他、例えば、無機絶縁膜又は金属材料(より具体的には、第1電極21と同一材料で同一層)の単層膜又は積層膜により形成されていてもよく、これら有機絶縁膜、無機絶縁膜、及び金属材料を組み合わせた積層材料により形成されていてもよい。これは、凸部43bが各々独立した柱状体であれば、IC46を端子接続部Jに圧着するときに、樹脂基板層10及びフィルム層60が撓んでも、凸部43bにクラックが発生し難いからである。
 有機EL表示装置50bは、上述の第1の実施形態の有機EL表示装置50aの製造方法において、凸部43aのパターン形状を変更することにより、製造することができる。
 以上に説明した有機EL表示装置50bによれば、上記(1)~(5)の効果に加えて、以下の効果を得ることができる。
 (6)凸部43bは、平面視で島状に複数に設けられているため、IC46を端子接続部Jに圧着するときのACF49の樹脂流動性が向上される。これにより、IC46を端子接続部Jに圧着するときの樹脂基板層10及びフィルム層60の撓みがより一層低減される。
 (7)導電性粒子49aと、バンプ47,48、又は端子電極35,36との機械的接続性が維持されるため、電気的接続性の低下が抑制される。
 《第3の実施形態》
 次に、本発明の第3の実施形態について説明する。図14は、本実施形態の有機EL表示装置50cの額縁領域Fの端子接続部Jを示す平面図であり、図8に相当する図である。また、図15は、図14中のXV-XV線に沿った有機EL表示装置50cの額縁領域Fの端子接続部Jを示す拡大断面図であり、図9に相当する図である。
なお、端子接続部J以外の表示領域D及び額縁領域F等を含む有機EL表示装置50cの全体構成は、上述の第1の実施形態の場合と同じであるため、ここでは詳しい説明を省略する。また、上記第1の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。
 有機EL表示装置50cでは、図14及び図15に示すように、上記第2の実施形態と同様に、凸部43cが平面視で島状に複数に設けられている。そして、凸部43cは、IC46の表面に接する上面を各々有する複数(図14及び図15では4つ)の突出部分43caと、隣り合う2つの突出部分の間に設けられた複数(図14及び図15では3つ)の溝部43cbとを備える点に特徴がある。なお、図14では、IC46の図示が簡略化され、IC46のバンプ47,48が省略されている。
 突出部分43ca、及び溝部43cbは、図14に示すように、端子接続部Jが延びる方向(方向X)に沿って設けられている。
 また、突出部分(頂部)43caは、図15に示すように、直接IC46の外周縁部及び中央部における底面部に接しているため、IC46を端子接続部Jに圧着するときに、樹脂基板層10及びフィルム層60の撓みが低減される。なお、凸部43cは、有機絶縁膜の単層膜又は積層膜により構成され、可撓性を有するため、IC46を端子接続部Jに圧着するときに、IC46の底面に突出部分43caが接していても残留応力を吸収することができ、該応力が低減される。
 ここで、溝部43cbの寸法(隣り合う2つの突出部分43caの離間寸法(ピッチ))は、導電性粒子49aの粒子径よりも大きくなっている。これにより、IC46を端子接続部Jに圧着するときに、導電性粒子49aが流動して溝部43cb内に入ることができる。
 なお、突出部分43ca及び溝部43cbの方向、大きさ、形状、数、位置等は、特に限定されず、IC46を端子接続部Jに圧着するときの樹脂基板層10及びフィルム層60の撓みが低減されるように決定すればよい。例えば、突出部分43ca及び溝部43cbの方向は、方向Xに限定されず、樹脂基板層10の基板表面に平行な方向であればよい。また、突出部分43ca及び溝部43cbは、凸部43cの配置位置毎に、その方向を変えてもよいし、そのピッチを変えてもよい。また、溝部43cbの形状は、IC46を端子接続部Jに圧着するときに導電性粒子49aが流動して溝部43cbの中に入る構造であればよく、例えば、格子状の溝でもよい。
 また、凸部43cは、図14に示すように、IC46の外周縁部及び中央部に対応して配置されている。そして、凸部43cは、図14及び図15に示すように、平面視で、IC46の外周縁部及び中央部において、IC46と重畳し、且つ樹脂基板層10の基板表面に平行な方向から見てバンプ47,48と重畳している。
 より具体的には、凸部43cは、バンプ47,48と、方向Yに平行な方向、方向X及び方向Yに傾斜する方向に平行な方向から見て重畳している。なお、凸部43cは、バンプ47,48と、方向Xに平行な方向から見て重畳していないが、重畳してもよい。
 有機EL表示装置50cは、上述の第1の実施形態の有機EL表示装置50aの製造方法において、凸部43aのパターン形状を変更することにより、製造することができる。
 以上に説明した有機EL表示装置50cによれば、上記(1)~(7)の効果に加えて、以下の効果を得ることができる。
 (8)凸部43cは、平面視で島状に複数に設けられ、直接IC46の底面に接する突出部分43caと、隣り合う突出部分43caの間に導電性粒子49aの粒子径よりも大きい寸法を有する溝部43cbとが設けられているため、IC46を端子接続部Jに圧着するときに、導電性粒子49aが溝部43cb内に入ると共に、突出部分43caが直接IC46の底面に接する。これにより、IC46を端子接続部Jに圧着するときの樹脂基板層10及びフィルム層60の撓みが低減される。
 《第4の実施形態》
 次に、本発明の第4の実施形態について説明する。図16は、本実施形態の有機EL表示装置50dの額縁領域Fの端子接続部Jを示す平面図であり、図8に相当する図である。また、図17は、図16中のXVII-XVII線に沿った有機EL表示装置50dの額縁領域Fの端子接続部Jを示す拡大断面図であり、図9に相当する図である。なお、端子接続部J以外の表示領域D及び額縁領域F等を含む有機EL表示装置50dの全体構成は、上述の第1の実施形態の場合と同じであるため、ここでは詳しい説明を省略する。また、上記第1の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。
 有機EL表示装置50dは、図16及び図17に示すように、第2無機絶縁膜34及び電極絶縁膜37の間に設けられた第3無機絶縁膜44と、端子電極35,36上に設けられた透明電極45とをさらに備える点に特徴がある。なお、図16では、IC46の図示が簡略化され、IC46のバンプ47,48が省略されている。
 第3無機絶縁膜44は、図17に示すように、端子電極35,36の周縁部を覆うように、端子電極35,36及び第2無機絶縁膜34上に設けられている。即ち、第3無機絶縁膜44は、端子電極35,36のエッジカバー且つ平坦化膜である。なお、第3無機絶縁膜44は、無機絶縁膜の単層膜又は積層膜により形成されている。
 透明電極45は、図17に示すように、第3無機絶縁膜44の周縁部を覆うように、第3無機絶縁膜44及び端子電極35,36上に設けられている。この透明電極45は、端子電極35,36の腐食等を防止するための保護膜である。なお、透明電極45は、例えば、ITO、IZO等により形成されている。
 また、有機EL表示装置50dでは、図16に示すように、IC46の外周縁部及び中央部に対応するように、第3無機絶縁膜44上に、電極絶縁膜37、及び凸部43dが順に設けられている。
 有機EL表示装置50dは、上述の第1の実施形態の有機EL表示装置50aの製造方法における上記端子接続部形成工程において、端子電極35,36を形成した後に第3無機絶縁膜44を形成し、その後に透明電極45、電極絶縁膜37、及び凸部43dを形成すればよい。なお、凸部43dの厚みは、第3無機絶縁膜44の厚みを考慮して決定すればよい。
 なお、有機EL表示装置50dでは、図17に示すように、隣り合う出力バンプ48間の第3無機絶縁膜44上には、電極絶縁膜37が配置されていないが、電極絶縁膜37が配置されていてもよい。但し、IC46を端子接続部Jに圧着するときのACF49の樹脂流動性を確保する観点から、出力バンプ48間に電極絶縁膜37が配置されていないほうが好ましい。
 以上に説明した有機EL表示装置50dによれば、上記(1)~(5)の効果に加えて、以下の効果を得ることができる。
 (9)端子電極35,36は、第3無機絶縁膜44及び透明電極45により覆われているため、端子電極35,36の腐食等が抑制される。これにより、有機EL表示装置50dの電気的特性及び耐環境性能の劣化がより一層抑制される。
 《その他の実施形態》
 上記各実施形態では、凸部は、ICの外形縁部及び中央部に対応して配置されているが、ICの外形縁部及び中央部の少なくとも一方に沿って配置されていればよい。なお、凸部は、少なくともICの外形縁部に沿って配置されていることが好ましい。
 上記各実施形態では、凸部は、ICの外形縁部及び中央部に対応して配置されているが、それに限定されず、例えば、隣り合う出力バンプ間や、隣り合う入力バンプ間等にスペースの空いた領域があれば、該領域に対応する樹脂基板層の撓みを低減するために、該領域に対応する樹脂基板層上に凸部が設けられていてもよい。
 上記各実施形態では、凸部は、上記第1~第4の実施形態に適用される凸部をそれぞれ組み合わせたものであってもよい。例えば、上記第1及び第4の実施形態において、ICの中央部に対応する凸部は、上記第2又は第3の実施形態と同様に、平面視で島状に複数に設けられていてもよい。また、上記第2又は第3の実施形態において、ICの外形縁部に沿う凸部は、上記第1又は第4の実施形態と同様に、ICの外周縁部に対応した平面視で枠状に設けられていてもよい。
 上記各実施形態では、電極絶縁膜は、有機絶縁膜の単層膜又は積層膜により構成されているが、無機絶縁膜により入出力端子電極のエッジカバーを形成し、該エッジカバー上にエッジカバーと同一材料が同一層に積層された、無機絶縁膜と有機絶縁膜との積層膜により構成されていてもよい。
 上記第2~第4の実施形態では、凸部は、上記第1の実施形態と同様に、電極絶縁膜上に設けず、電極絶縁膜を厚膜化することにより構成されていてもよい。
 上記各実施形態では、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層の5層積層構造の有機EL層を例示したが、有機EL層は、例えば、正孔注入層兼正孔輸送層、発光層、及び電子輸送層兼電子注入層の3層積層構造であってもよい。
 また、上記各実施形態では、第1電極を陽極とし、第2電極を陰極とした有機EL表示装置を例示したが、本発明は、有機EL層の積層構造を反転させ、第1電極を陰極とし、第2電極を陽極とした有機EL表示装置にも適用することができる。
 また、上記各実施形態では、表示装置として有機EL表示装置を例に挙げて説明したが、本発明は、有機EL表示装置に限定されず、フレキシブルな表示装置であれば適用可能である。例えば、量子ドット含有層を用いた発光素子であるQLED(Quantum-dot light emitting diode)等を備えたフレキシブルな表示装置に適用することができる。
 以上説明したように、本発明は、フレキシブルな表示装置について有用である。
C     画素回路
D     表示領域
F     額縁領域
J     端子接続部
P     画素
R47   入力バンプ領域(入力バンプの全部を囲む領域)
R48   出力バンプ領域(出力バンプの全部を囲む領域)
r     電極間領域
T     外部端子部
X,Y   樹脂基板層の基板表面に平行な方向
9a    第1TFT(薄膜トランジスタ)
9b    第2TFT(薄膜トランジスタ)
10    樹脂基板層(フレキシブル基板)
20    薄膜トランジスタ層
21    第1電極
22    エッジカバー
23    有機EL層(機能層)
24    第2電極
25    有機EL素子(有機エレクトロルミネッセンス素子)(発光素子)
29    封止層
30    外部端子電極 
31    第1無機絶縁膜 
32    第1引き回し配線
33    第2引き回し配線
34    第2無機絶縁膜 
35    入力端子電極 
36    出力端子電極 
37    電極絶縁膜 
38    第1配線開口部 
39    第2配線開口部 
40    入力電極開口部 
41    出力電極開口部 
43a,43b,43c,43d  凸部 
43ca  突出部分 
43cb  溝部 
44    第3無機絶縁膜 
45   透明電極 
46   IC(電子部品)
47   入力バンプ 
48   出力バンプ 
49   ACF 
49a  導電性粒子 
49b  熱硬化性樹脂 
50a,50b,50c,50d  有機EL表示装置 
60   フィルム層 
61   接着層

Claims (22)

  1.  フレキシブル基板と、
     上記フレキシブル基板上に設けられ、複数の薄膜トランジスタが設けられた薄膜トランジスタ層と、
     上記薄膜トランジスタ層上に設けられ、複数の第1電極、複数の機能層、及び第2電極を備えた複数の発光素子と、
     上記複数の発光素子を覆うように設けられた封止層と、を有し、
     複数の画素と複数の画素回路とを備えた表示領域、及び
     上記表示領域の周囲に設けられた額縁領域を備えた表示装置であって、
     上記額縁領域には、信号が入力される複数の入力バンプと、信号が出力される複数の出力バンプとを有する電子部品、及び
     上記複数の入力バンプに異方性導電膜を介してそれぞれ電気的に接続された複数の入力端子電極と、上記複数の出力バンプに異方性導電膜を介してそれぞれ電気的に接続された複数の出力端子電極とを備えた端子接続部が設けられ、
     上記端子接続部において、上記複数の入力端子電極及び上記複数の出力端子電極上には、電極絶縁膜が設けられ、
     上記電極絶縁膜には、上記複数の入力端子電極を露出させる入力電極開口部と、上記複数の出力端子電極を露出させる出力電極開口部とが設けられ、
     上記電極絶縁膜上には、凸部が設けられ、
     上記凸部は、平面視で上記電子部品と重畳し、且つ上記フレキシブル基板の基板表面に平行な方向から見て上記複数の入力バンプ及び上記複数の出力バンプと重畳していることを特徴とする表示装置。
  2.  請求項1に記載された表示装置において、
     上記凸部は、上記入力電極開口部を囲むように設けられていることを特徴とする表示装置。
  3.  請求項1又は2に記載された表示装置において、
     上記凸部は、上記出力電極開口部を囲むように設けられていることを特徴とする表示装置。
  4.  請求項1~3の何れか1つに記載された表示装置において、
     上記凸部は、上記入力電極開口部と上記出力電極開口部との間に設けられていることを特徴とする表示装置。
  5.  請求項1~4の何れか1つに記載された表示装置において、
     上記凸部は、平面視で上記電子部品の端部と重畳していることを特徴とする表示装置。
  6.  請求項1~5の何れか1つに記載された表示装置において、
     上記凸部は、上記複数の入力バンプ又は上記複数の出力バンプの全部を囲む領域の周囲に設けられていることを特徴とする表示装置。
  7.  請求項1~6の何れか1つに記載された表示装置において、
     上記凸部は、平面視で、異方性導電膜を介して上記電子部品と重畳していることを特徴とする表示装置。
  8.  請求項1~7の何れか1つに記載された表示装置において、
     上記凸部は、上記電子部品の底面に接していることを特徴とする表示装置。
  9.  請求項1~8の何れか1つに記載された表示装置において、
     上記凸部は、平面視で島状に複数に設けられていることを特徴とする表示装置。
  10.  請求項9に記載された表示装置において、
     島状の上記各凸部は、平面視で上記電子部品の端部と重畳していることを特徴とする表示装置。
  11.  請求項1~10の何れか1つに記載された表示装置において、
     上記凸部は、無機絶縁膜により形成されていることを特徴とする表示装置。
  12.  請求項1~10の何れか1つに記載された表示装置において、
     上記凸部は、有機絶縁膜により形成されていることを特徴とする表示装置。
  13.  請求項12に記載された表示装置において、
     上記凸部は、エッジカバーと同一材料により同一層に形成されていることを特徴とする表示装置。
  14.  請求項1~10の何れか1つに記載された表示装置において、
     上記凸部は、金属材料により形成されていることを特徴とする表示装置。
  15.  請求項14に記載された表示装置において、
     上記凸部は、上記複数の第1電極と同一材料により同一層に形成されていることを特徴とする表示装置。
  16.  請求項1~10の何れか1つに記載された表示装置において、
     上記凸部は、積層材料により形成されていることを特徴とする表示装置。
  17.  請求項1~16の何れか1つに記載された表示装置において、
     上記額縁領域の端部には、外部から信号が入力される複数の外部端子電極が配列された外部端子部が設けられ、
     上記各外部端子電極は、上記各入力端子電極に電気的に接続されていることを特徴とする表示装置。
  18.  請求項17に記載された表示装置において、
     上記フレキシブル基板上には、該フレキシブル基板からみて、第1無機絶縁膜、複数の第1引き回し配線及び複数の第2引き回し配線、第2無機絶縁膜、並びに上記複数の入力端子電極及び上記複数の出力端子電極が順に設けられ、
     上記各第1引き回し配線は、上記各出力端子電極に電気的に接続されて、上記各画素回路に信号を入力し、
     上記各第2引き回し配線を介して、上記各外部端子電極と上記各入力端子電極とが電気的に接続されていることを特徴とする表示装置。
  19.  請求項18に記載された表示装置において、
     上記第2無機絶縁膜には、平面視で上記複数の出力バンプと重畳するように、上記複数の第1引き回し配線を露出させる第1配線開口部が設けられ、
     上記第1配線開口部において、上記各第1引き回し配線と上記各出力端子電極とが接していることを特徴とする表示装置。
  20.  請求項18又は19に記載された表示装置において、
     上記第2無機絶縁膜には、平面視で上記複数の入力バンプと重畳するように、上記複数の第2引き回し配線を露出させる第2配線開口部が設けられ、
     上記第2配線開口部において、上記各第2引き回し配線と上記各入力端子電極とが接していることを特徴とする表示装置。
  21.  請求項1~20の何れか1つに記載された表示装置において、
     上記フレキシブル基板の裏面には、接着層が設けられ、
     上記接着層を介して、フィルム層が設けられていることを特徴とする表示装置。
  22.  請求項1~21の何れか1つに記載された表示装置において、
     上記各発光素子は、有機エレクトロルミネッセンス素子であることを特徴とする表示装置。
PCT/JP2019/011802 2019-03-20 2019-03-20 表示装置 WO2020188807A1 (ja)

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US11997889B2 (en) * 2018-03-30 2024-05-28 Sharp Kabushiki Kaisha Display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130053280A (ko) * 2011-11-15 2013-05-23 엘지디스플레이 주식회사 씨오지 타입 플렉서블 유기발광소자
US20150163911A1 (en) * 2013-12-10 2015-06-11 Samsung Display Co., Ltd. Flexible display device and method of manufacturing the same
US20160211279A1 (en) * 2015-01-15 2016-07-21 Samsung Display Co., Ltd. Flexible display and method of manufacturing the same
JP2017219844A (ja) * 2016-06-03 2017-12-14 三星ディスプレイ株式會社Samsung Display Co.,Ltd. 表示装置
WO2019038884A1 (ja) * 2017-08-24 2019-02-28 シャープ株式会社 表示装置
JP2019036426A (ja) * 2017-08-10 2019-03-07 株式会社Joled 有機el表示パネルの製造方法及び有機el表示パネル

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100737896B1 (ko) * 2001-02-07 2007-07-10 삼성전자주식회사 어레이 기판과, 액정표시장치 및 그 제조방법
CN102203841B (zh) * 2008-11-26 2014-01-22 夏普株式会社 显示装置
RU2465656C1 (ru) * 2008-12-05 2012-10-27 Шарп Кабусики Кайся Подложка для устройства отображения и устройство отображения
US9595544B2 (en) * 2012-08-30 2017-03-14 Sharp Kabushiki Kiasha Thin film transistor substrate and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130053280A (ko) * 2011-11-15 2013-05-23 엘지디스플레이 주식회사 씨오지 타입 플렉서블 유기발광소자
US20150163911A1 (en) * 2013-12-10 2015-06-11 Samsung Display Co., Ltd. Flexible display device and method of manufacturing the same
US20160211279A1 (en) * 2015-01-15 2016-07-21 Samsung Display Co., Ltd. Flexible display and method of manufacturing the same
JP2017219844A (ja) * 2016-06-03 2017-12-14 三星ディスプレイ株式會社Samsung Display Co.,Ltd. 表示装置
JP2019036426A (ja) * 2017-08-10 2019-03-07 株式会社Joled 有機el表示パネルの製造方法及び有機el表示パネル
WO2019038884A1 (ja) * 2017-08-24 2019-02-28 シャープ株式会社 表示装置

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