WO2020177258A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

Info

Publication number
WO2020177258A1
WO2020177258A1 PCT/CN2019/095265 CN2019095265W WO2020177258A1 WO 2020177258 A1 WO2020177258 A1 WO 2020177258A1 CN 2019095265 W CN2019095265 W CN 2019095265W WO 2020177258 A1 WO2020177258 A1 WO 2020177258A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
potential
node
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/095265
Other languages
English (en)
French (fr)
Inventor
蔡玉莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020177258A1 publication Critical patent/WO2020177258A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • This application relates to the field of display technology, in particular to a pixel drive circuit and a display panel.
  • OLED(Organic Light The Emitting Diode (organic light emitting diode) display panel has the advantages of high brightness, wide viewing angle, fast response speed, low power consumption, etc., and has been widely used in the field of high-performance displays.
  • the pixels are arranged in a matrix with multiple rows and multiple columns.
  • Each pixel is usually composed of two transistors and one capacitor, commonly known as 2T1C circuit.
  • the transistor has the problem of threshold voltage drift.
  • OLED pixel drive circuit needs corresponding compensation structure.
  • the compensation structure of the OLED pixel driving circuit is relatively complicated, which occupies a large area when designing a layout, which is not conducive to the design of a high PPI (Pixels Per Inch, pixel density) display panel.
  • the purpose of the embodiments of the present application is to provide a pixel driving circuit and a display panel, which can solve the technical problem that the compensation structure of the existing pixel driving circuit is relatively complicated and a large area is occupied when designing the layout.
  • the embodiment of the present application provides a pixel driving circuit, the drain of which is electrically connected to the first node;
  • the anode terminal of the light emitting device is electrically connected to the first power signal, and the cathode terminal of the light emitting device is electrically connected to the second node;
  • the first terminal of the second capacitor is electrically connected to the first node
  • a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second power signal;
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor; the light emitting device is an organic light emitting diode.
  • the combination of the control signal, the data signal, and the second power signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the data signal includes The first reference low potential, the second reference low potential, and the display high potential, the potential value of the first reference low potential is less than the potential value of the second reference low potential, and the potential value of the second reference low potential is less than all
  • the display shows a high potential;
  • the second power signal includes a second power low potential and a second power high potential.
  • the potential value of the high potential of the second power source is greater than the potential value of the first power source signal and the potential value of the turn-on voltage of the light-emitting device.
  • the control signal in the threshold voltage acquisition phase, the control signal is at a high potential, and the data signal jumps from the first reference low potential to the second reference low potential,
  • the second power signal is a high potential of the second power source.
  • the control signal in the data voltage acquisition phase, is a high potential, the data signal is the display high potential, and the second power signal is the second power source High potential.
  • the control signal in the light-emitting phase, the control signal is at a low potential, the data signal jumps from the display high potential to the first reference low potential, and the second The power signal jumps from the high potential of the second power source to the low potential of the second power source.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • An embodiment of the present application also provides a pixel driving circuit, including: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a second power signal;
  • the gate of the second transistor is electrically connected to the control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the second capacitor of the second capacitor. end;
  • the gate of the third transistor is electrically connected to the control signal, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the first node.
  • the anode terminal of the light emitting device is electrically connected to the first power signal, and the cathode terminal of the light emitting device is electrically connected to the second node;
  • the first terminal of the second capacitor is electrically connected to the first node
  • the first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the second power signal.
  • the combination of the control signal, the data signal, and the second power signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the data signal includes The first reference low potential, the second reference low potential, and the display high potential, the potential value of the first reference low potential is less than the potential value of the second reference low potential, and the potential value of the second reference low potential is less than all
  • the display shows a high potential;
  • the second power signal includes a second power low potential and a second power high potential.
  • the potential value of the high potential of the second power source is greater than the potential value of the first power source signal and the potential value of the turn-on voltage of the light-emitting device.
  • the control signal in the threshold voltage acquisition phase, the control signal is at a high potential, and the data signal jumps from the first reference low potential to the second reference low potential,
  • the second power signal is a high potential of the second power source.
  • the control signal in the data voltage acquisition phase, is a high potential, the data signal is the display high potential, and the second power signal is the second power source High potential.
  • the control signal in the light-emitting phase, the control signal is at a low potential, the data signal jumps from the display high potential to the first reference low potential, and the second The power signal jumps from the high potential of the second power source to the low potential of the second power source.
  • the first transistor, the second transistor, and the third transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light-emitting device is an organic light-emitting diode.
  • An embodiment of the present application further provides a display panel including a pixel driving circuit, the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light emitting device;
  • the gate of the first transistor is electrically connected to a first node, the source of the first transistor is electrically connected to a second node, and the drain of the first transistor is electrically connected to a second power signal;
  • the gate of the second transistor is electrically connected to the control signal, the source of the second transistor is electrically connected to the data signal, and the drain of the second transistor is electrically connected to the second capacitor of the second capacitor. end;
  • the gate of the third transistor is electrically connected to the control signal, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the first node.
  • the anode terminal of the light emitting device is electrically connected to the first power signal, and the cathode terminal of the light emitting device is electrically connected to the second node;
  • the first terminal of the second capacitor is electrically connected to the first node
  • the first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the second power signal.
  • the combination of the control signal, the data signal, and the second power signal sequentially corresponds to a threshold voltage acquisition phase, a data voltage acquisition phase, and a light-emitting phase;
  • the data signal includes a first A reference low potential, a second reference low potential, and a display high potential, the potential value of the first reference low potential is less than the potential value of the second reference low potential, and the potential value of the second reference low potential is less than the potential value of the second reference low potential Displays the potential value of the high potential;
  • the second power signal includes the second power low potential and the second power high potential.
  • the current flowing through the light emitting device is independent of the threshold voltage of the first transistor.
  • the light emitting device is an organic light emitting diode.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 3T2C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a timing diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the threshold voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a path of the pixel driving circuit provided by the application embodiment in the data voltage acquisition phase under the driving timing shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase under the driving timing shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • the pixel driving circuit provided by the embodiment of the present application includes: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and a light-emitting device OLED. It can be an organic light emitting diode. That is, the embodiment of the present application adopts the pixel driving circuit of the 3T2C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and uses fewer components, the structure is simple and stable, and the cost is saved.
  • the first transistor T1 in the pixel driving circuit is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the first node a, the source of the first transistor T1 is electrically connected to the second node b, and the drain of the first transistor T1 is electrically connected to the second power signal VSS .
  • the gate of the second transistor T2 is electrically connected to the control signal S, the source of the second transistor T2 is electrically connected to the data signal D, and the drain of the second transistor T2 is electrically connected to the second end of the second capacitor C2.
  • the gate of the third transistor T3 is electrically connected to the control signal S, the source of the third transistor T3 is electrically connected to the second node b, and the drain of the third transistor T3 is electrically connected to the first node a.
  • the anode terminal of the light emitting device OLED is electrically connected to the first power signal Vdd, and the cathode terminal of the light emitting device OLED is electrically connected to the second node b.
  • the first terminal of the second capacitor C2 is electrically connected to the first node a.
  • the first terminal of the first capacitor C1 is electrically connected to the first node a, and the second terminal of the first capacitor C1 is electrically connected to the second power signal VSS.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 2 is a timing diagram of the pixel driving circuit provided by an embodiment of the application.
  • the combination of the control signal S, the data signal D, and the second power signal VSS sequentially corresponds to the threshold voltage acquisition phase t1, the data voltage acquisition phase t2, and the light-emitting phase t3.
  • the data signal D includes a first reference low potential, a second reference low potential, and a display high potential.
  • the potential value of the first reference low potential is less than the potential value of the second reference low potential
  • the potential value of the second reference low potential is less than the display The potential value of the high potential.
  • the second power signal VSS includes a second power low potential Vsl and a second power high potential Vsh.
  • the potential value of the second power high potential Vsh is greater than the potential value of the first power signal Vdd and the potential value of the turn-on voltage of the light emitting device OLED.
  • the first power signal Vdd is a constant voltage and high potential signal, that is, the potential value of the first power signal Vdd is always unchanged.
  • the control signal S is at a high level
  • the data signal D jumps from the first reference low level to the second reference low level
  • the second power signal VSS is the second power high level Vsh .
  • the control signal S is a high potential
  • the data signal D is a display high potential
  • the second power signal VSS is a second power high potential Vsh.
  • the control signal S is at a low level
  • the data signal D jumps from a display high level to a first reference low level
  • the second power signal VSS jumps from a second power high level Vsh to a first reference level.
  • the second power supply is low potential Vsl.
  • FIG. 3 is a schematic diagram of the path of the threshold voltage obtaining stage t1 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the control signal S is at a high potential, and the second transistor T2 and the third transistor T3 are turned on.
  • the data signal D is the first reference low potential. That is, the first reference low potential of the data signal D is output to the second end of the second capacitor C2.
  • the first power signal Vdd is output to the first node a via the light emitting device OLED and the third transistor T3. Subsequently, the data signal D jumps from the first reference low potential to the second reference low potential.
  • the potential of the first node a also changes accordingly.
  • the first transistor T1 is turned on and the first node a is discharged. Until the first transistor T1 is turned off.
  • the second power signal VSS is the second power high potential Vsh, and the potential value of the second power high potential Vsh is greater than the potential value of the first power signal Vdd and the turn-on voltage of the light emitting device OLED At this time, the light-emitting device OLED does not emit light.
  • FIG. 4 is a schematic diagram of the data voltage acquisition phase t2 of the pixel driving circuit provided by the application embodiment in the driving sequence shown in FIG. 2.
  • the control signal S is at a high level
  • the second transistor T2 and the third transistor T3 are turned on
  • the data signal D jumps from the second reference low level to the display high level. Due to the capacitive coupling effect, the first node a also changes accordingly.
  • the second power signal VSS is the second power high potential Vsh, and the potential value of the second power high potential Vsh is greater than the potential value of the first power signal Vdd and the turn-on voltage of the light emitting device OLED At this time, the light-emitting device OLED does not emit light.
  • Vsh Vsh
  • Vdata is the display high potential of the data signal D
  • Vb is the second reference low potential of the power signal
  • C1 is the capacitance value of the first capacitor C1
  • C2 is the capacitance value of the second capacitor C2.
  • FIG. 5 is a schematic diagram of the path of the pixel driving circuit provided by the application embodiment in the light-emitting phase t3 under the driving timing shown in FIG. 2.
  • the control signal S is at a low level
  • the second transistor T2 and the third transistor T3 are turned off, and the data signal D fails to be output to the second terminal of the second capacitor C2. Due to the storage effect of the first capacitor C1 and the second capacitor C2, the voltage difference between the potential of the first node a and the potential of the drain of the first transistor T1 remains unchanged.
  • the second power signal VSS jumps from the second power high potential Vsh to the second power low potential Vsl. At this time, the light-emitting device OLED emits light.
  • I OLED 1/2Cox( ⁇ W/L)(Vgs1-Vth) 2 , where I OLED is the current flowing through the light-emitting device OLED, ⁇ is the carrier mobility of the first transistor T1, W and L are the first The width and length of the channel of the transistor T1, Vg1s is the voltage difference between the gate and the drain of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.
  • I OLED 1/2Cox( ⁇ W/L)(V gs -Vth) 2
  • the current of the light-emitting device OLED has nothing to do with the threshold voltage of the first transistor T1, and the compensation function is realized.
  • the light emitting device OLED emits light, and the current flowing through the light emitting device OLED has nothing to do with the threshold voltage of the first transistor T1.
  • the embodiment of the application itself also provides a display panel, which includes the above-mentioned pixel driving circuit.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • the pixel driving circuit please refer to the above description of the pixel driving circuit, which will not be repeated here.
  • the pixel drive circuit and the display panel provided by the embodiments of the present application use a pixel drive circuit with a 3T2C structure to effectively compensate the threshold voltage of the drive transistor in each pixel.
  • the compensation structure of the pixel drive circuit is relatively simple, so that the design is not No need to take up a lot of area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请实施例提供的像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
 背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。其中，在OLED显示器面板中，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个晶体管与一个电容构成，俗称2T1C电路，但晶体管存在阈值电压漂移的问题，因此，OLED像素驱动电路需要相应的补偿结构。目前，OLED像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积，不利于高PPI(Pixels Per Inch，像素密度)显示面板的设计。
 技术问题
本申请实施例的目的在于提供一种像素驱动电路及显示面板，能够解决现有的像素驱动电路的补偿结构较为复杂，在设计布局时占用大量面积的技术问题。
 技术解决方案
本申请实施例提供一种像素驱动电路，的漏极电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
所述第二电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号；
流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
在本申请所述的像素驱动电路中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
在本申请所述的像素驱动电路中，所述第二电源高电位的电位值大于所述第一电源信号的电位值与所述发光器件的开启电压的电位值。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述控制信号为高电位，所述数据信号由所述第一参考低电位跳变至所述第二参考低电位，所述第二电源信号为所述第二电源高电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述控制信号为高电位，所述数据信号为所述显示高电位，所述第二电源信号为所述第二电源高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述控制信号为低电位，所述数据信号由所述显示高电位跳变至所述第一参考低电位，所述第二电源信号由所述第二电源高电位跳变至所述第二电源低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
本申请实施例还提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第二电源信号；
所述第二晶体管的栅极电性连接于控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第二电容的第二端；
所述第三晶体管的栅极电性连接于所述控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
所述第二电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号。
在本申请所述的像素驱动电路中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
在本申请所述的像素驱动电路中，所述第二电源高电位的电位值大于所述第一电源信号的电位值与所述发光器件的开启电压的电位值。
在本申请所述的像素驱动电路中，在所述阈值电压获取阶段，所述控制信号为高电位，所述数据信号由所述第一参考低电位跳变至所述第二参考低电位，所述第二电源信号为所述第二电源高电位。
在本申请所述的像素驱动电路中，在所述数据电压获取阶段，所述控制信号为高电位，所述数据信号为所述显示高电位，所述第二电源信号为所述第二电源高电位。
在本申请所述的像素驱动电路中，在所述发光阶段，所述控制信号为低电位，所述数据信号由所述显示高电位跳变至所述第一参考低电位，所述第二电源信号由所述第二电源高电位跳变至所述第二电源低电位。
在本申请所述的像素驱动电路中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在本申请所述的像素驱动电路中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的像素驱动电路中，所述发光器件为有机发光二极管。
本申请实施例还提供一种显示面板，包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第二电源信号；
所述第二晶体管的栅极电性连接于控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第二电容的第二端；
所述第三晶体管的栅极电性连接于所述控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述第一节点；
所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
所述第二电容的第一端电性连接于所述第一节点；
所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号。
在本申请所述的显示面板中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
在本申请所述的显示面板中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
在本申请所述的显示面板中，所述发光器件为有机发光二极管。
 有益效果
本申请实施例提供的像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的时序图；
图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段的通路示意图；
图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段的通路示意图；
图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段的通路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的像素驱动电路的结构示意图。如图1所示，本申请实施例提供的像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1、第二电容C2以及发光器件OLED，发光器件OLED可以为有机发光二极管。也即，本申请实施例采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，用了较少的元器件，结构简单稳定，节约了成本。该像素驱动电路中的第一晶体管T1为驱动晶体管。
其中，第一晶体管T1的栅极电性连接于第一节点a，第一晶体管T1的源极电性连接于第二节点b，第一晶体管T1的漏极电性连接于第二电源信号VSS。第二晶体管T2的栅极电性连接于控制信号S，第二晶体管T2的源极电性连接于数据信号D，第二晶体管T2的漏极电性连接于第二电容C2的第二端。第三晶体管T3的栅极电性连接于控制信号S，第三晶体管T3的源极电性连接于第二节点b，第三晶体管T3的漏极电性连接于第一节点a。发光器件OLED的阳极端电性连接于第一电源信号Vdd，发光器件OLED的阴极端电性连接于第二节点b。第二电容C2的第一端电性连接于第一节点a。第一电容C1的第一端电性连接于第一节点a，第一电容C1的第二端电性连接于第二电源信号VSS。
在一些实施例中，第一晶体管T1、第二晶体管T2以及第三晶体管T3均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图2，图2为本申请实施例提供的像素驱动电路的时序图。如图2所示，控制信号S、数据信号D以及第二电源信号VSS相组合先后对应于阈值电压获取阶段t1、数据电压获取阶段t2以及发光阶段t3。其中，数据信号D包括第一参考低电位、第二参考低电位以及显示高电位，第一参考低电位的电位值小于第二参考低电位的电位值，第二参考低电位的电位值小于显示高电位的电位值。第二电源信号VSS包括第二电源低电位Vsl以及第二电源高电位Vsh。第二电源高电位Vsh的电位值大于第一电源信号Vdd的电位值与发光器件OLED的开启电压的电位值。在本申请实施例中，第一电源信号Vdd为一恒压高电位信号，也即，第一电源信号Vdd的电位值始终不变。
在一些实施例中，在阈值电压获取阶段t1，控制信号S为高电位，数据信号D由第一参考低电位跳变至第二参考低电位，第二电源信号VSS为第二电源高电位Vsh。
在一些实施例中，在数据电压获取阶段t2，控制信号S为高电位，数据信号D为显示高电位，第二电源信号VSS为第二电源高电位Vsh。
在一些实施例中，在发光阶段t3，控制信号S为低电位，数据信号D由显示高电位跳变至第一参考低电位，第二电源信号VSS由第二电源高电位Vsh跳变至第二电源低电位Vsl。
具体的，请参阅图3，图3为申请实施例提供的像素驱动电路在图2所示的驱动时序下的阈值电压获取阶段t1的通路示意图。首先，结合图2、图3所示，在阈值电压获取阶段t1，控制信号S为高电位，第二晶体管T2以及第三晶体管T3打开。刚开始，数据信号D为第一参考低电位。也即，数据信号D的第一参考低电位输出至第二电容C2的第二端。第一电源信号Vdd经发光器件OLED和第三晶体管T3输出至第一节点a。随后，数据信号D由第一参考低电位跳变至第二参考低电位，由于电容耦合效应，第一节点a的电位也相应发生变化，此时，第一晶体管T1打开，第一节点a放电至第一晶体管T1关闭。与此同时，在阈值电压获取阶段t1，第二电源信号VSS为第二电源高电位Vsh，且第二电源高电位Vsh的电位值大于第一电源信号Vdd的电位值与发光器件OLED的开启电压的电位值，此时，发光器件OLED不发光。
在该阈值电压获取阶段t1，第一节点a的电位和第一晶体管T1的漏极的电位可以根据以下公式进行设置：V g=Vsh+Vth，V s=Vsh，其中，V g为第一节点a的电位，V s为第一晶体管T1的漏极的电位，Vth为第一晶体管T1的阈值电压，Vsh为第二电源信号VSS的第二电源高电位Vsh。
接着，请参阅图4，图4为申请实施例提供的像素驱动电路在图2所示的驱动时序下的数据电压获取阶段t2的通路示意图。结合图2、图4所示，在数据电压获取阶段t2，控制信号S为高电位，第二晶体管T2以及第三晶体管T3打开，数据信号D由第二参考低电位跳变至显示高电位，由于电容耦合效应，第一节点a也相应发生变化。与此同时，在数据电压获取阶段t2，第二电源信号VSS为第二电源高电位Vsh，且第二电源高电位Vsh的电位值大于第一电源信号Vdd的电位值与发光器件OLED的开启电压的电位值，此时，发光器件OLED不发光。
在该数据电压获取阶段t2，第一节点a的电位和第一晶体管T1的漏极的电位可以根据以下公式进行设置：V g=Vsh+Vth+（Vdata-Vb）C2/（C1+C2），V s=Vsh，其中，V g为第一节点a的电位，V s为第一晶体管T1的漏极的电位，Vth为第一晶体管T1的阈值电压，Vsh为第二电源信号VSS的第二电源高电位Vsh，Vdata为数据信号D的显示高电位，Vb为电源信号的第二参考低电位，C1为第一电容C1的电容值，C2为第二电容C2的电容值。
最后，请参阅图5，图5为申请实施例提供的像素驱动电路在图2所示的驱动时序下的发光阶段t3的通路示意图。结合图2、图5所示，在发光阶段t3，控制信号S为低电位，第二晶体管T2以及第三晶体管T3关闭，数据信号D未能输出至第二电容C2的第二端。由于第一电容C1和第二电容C2的存储作用，第一节点a的电位与第一晶体管T1的漏极的电位之间的压差保持不变。与此同时，在发光阶段t3，第二电源信号VSS由第二电源高电位Vsh跳变至第二电源低电位Vsl，此时，发光器件OLED发光。
在该发光阶段t3，第一节点a与第一晶体管T1的漏极之间的压差可根据以下公式获得：V gs=Vth+（Vdata-Vb）C2/（C1+C2），其中，V g为第一节点a的电位，V s为第一晶体管T1的漏极的电位，Vth为第一晶体管T1的阈值电压，Vdata为数据信号D的显示高电位，Vb为电源信号的第二参考低电位，C1为第一电容C1的电容值，C2为第二电容C2的电容值。
进一步地，计算流经发光器件OLED的电流的公式为：
I OLED＝1/2Cox(μW/L)(Vgs1－Vth) 2，其中I OLED为流经发光器件OLED的电流，μ为第一晶体管T1的载流子迁移率，W和L分别为第一晶体管T1的沟道的宽度和长度，Vg1s为第一晶体管T1的栅极与漏极极之间的压差、Vth为第一晶体管T1的阈值电压。在本申请实施例中，第一晶体管T1的栅极与漏极极之间的压差等于第一节点a的电位与第二晶体管T2的漏极的电位之间的压差。将第一节点a的电位与第一晶体管T1的漏极的电位之间的压差V gs=Vth+（Vdata-Vb）C2/（C1+C2）代入上式，即有：
I OLED＝1/2Cox(μW/L)(V gs-Vth) 2
＝1/2Cox(μW/L)(（Vdata-Vb）C2/（C1+C2）) 2
由此可见，发光器件OLED的电流与第一晶体管T1的阈值电压无关，实现了补偿功能。发光器件OLED发光，且流经发光器件OLED的电流与第一晶体管T1的阈值电压无关。
本身申请实施例还提供一种显示面板，其包括以上所述的像素驱动电路，具体可参照以上对该像素驱动电路的描述，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，采用3T2C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，该像素驱动电路的补偿结构较为简单，从而在设计时并不需要占用大量面积。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第二电源信号；
    所述第二晶体管的栅极电性连接于控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第二电容的第二端；
    所述第三晶体管的栅极电性连接于所述控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
    所述第二电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号；
    流经所述发光器件的电流与所述第一晶体管的阈值电压无关；所述发光器件为有机发光二极管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第二电源高电位的电位值大于所述第一电源信号的电位值与所述发光器件的开启电压的电位值。
  4. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述控制信号为高电位，所述数据信号由所述第一参考低电位跳变至所述第二参考低电位，所述第二电源信号为所述第二电源高电位。
  5. 根据权利要求2所述的像素驱动电路，其中，在所述数据电压获取阶段，所述控制信号为高电位，所述数据信号为所述显示高电位，所述第二电源信号为所述第二电源高电位。
  6. 根据权利要求2所述的像素驱动电路，其中，在所述发光阶段，所述控制信号为低电位，所述数据信号由所述显示高电位跳变至所述第一参考低电位，所述第二电源信号由所述第二电源高电位跳变至所述第二电源低电位。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  8. 一种像素驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第二电源信号；
    所述第二晶体管的栅极电性连接于控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第二电容的第二端；
    所述第三晶体管的栅极电性连接于所述控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
    所述第二电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号。
  9. 根据权利要求8所述的像素驱动电路，其中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第二电源高电位的电位值大于所述第一电源信号的电位值与所述发光器件的开启电压的电位值。
  11. 根据权利要求9所述的像素驱动电路，其中，在所述阈值电压获取阶段，所述控制信号为高电位，所述数据信号由所述第一参考低电位跳变至所述第二参考低电位，所述第二电源信号为所述第二电源高电位。
  12. 根据权利要求9所述的像素驱动电路，其中，在所述数据电压获取阶段，所述控制信号为高电位，所述数据信号为所述显示高电位，所述第二电源信号为所述第二电源高电位。
  13. 根据权利要求9所述的像素驱动电路，其中，在所述发光阶段，所述控制信号为低电位，所述数据信号由所述显示高电位跳变至所述第一参考低电位，所述第二电源信号由所述第二电源高电位跳变至所述第二电源低电位。
  14. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管以及所述第三晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  15. 根据权利要求8所述的像素驱动电路，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  16. 根据权利要求8所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  17. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容以及发光器件；
    所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的源极电性连接于第二节点，所述第一晶体管的漏极电性连接于第二电源信号；
    所述第二晶体管的栅极电性连接于控制信号，所述第二晶体管的源极电性连接于数据信号，所述第二晶体管的漏极电性连接于所述第二电容的第二端；
    所述第三晶体管的栅极电性连接于所述控制信号，所述第三晶体管的源极电性连接于所述第二节点，所述第三晶体管的漏极电性连接于所述第一节点；
    所述发光器件的阳极端电性连接于第一电源信号，所述发光器件的阴极端电性连接于所述第二节点；
    所述第二电容的第一端电性连接于所述第一节点；
    所述第一电容的第一端电性连接于所述第一节点，所述第一电容的第二端电性连接于所述第二电源信号。
  18. 根据权利要求17所述的显示面板，其中，所述控制信号、所述数据信号以及所述第二电源信号相组合先后对应于阈值电压获取阶段、数据电压获取阶段以及发光阶段；所述数据信号包括第一参考低电位、第二参考低电位以及显示高电位，所述第一参考低电位的电位值小于所述第二参考低电位的电位值，所述第二参考低电位的电位值小于所述显示高电位的电位值；所述第二电源信号包括第二电源低电位以及第二电源高电位。
  19. 根据权利要求17所述的显示面板，其中，流经所述发光器件的电流与所述第一晶体管的阈值电压无关。
  20. 根据权利要求17所述的显示面板，其中，所述发光器件为有机发光二极管。
PCT/CN2019/095265 2019-03-07 2019-07-09 像素驱动电路及显示面板 Ceased WO2020177258A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910173068.2A CN109801595A (zh) 2019-03-07 2019-03-07 像素驱动电路及显示面板
CN201910173068.2 2019-03-07

Publications (1)

Publication Number Publication Date
WO2020177258A1 true WO2020177258A1 (zh) 2020-09-10

Family

ID=66561714

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/095265 Ceased WO2020177258A1 (zh) 2019-03-07 2019-07-09 像素驱动电路及显示面板

Country Status (2)

Country Link
CN (1) CN109801595A (zh)
WO (1) WO2020177258A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801595A (zh) * 2019-03-07 2019-05-24 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN110189705B (zh) * 2019-06-19 2021-02-05 京东方科技集团股份有限公司 像素电路、显示面板和显示设备
CN114708825A (zh) * 2022-04-22 2022-07-05 Tcl华星光电技术有限公司 像素电路及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859539A (zh) * 2010-04-16 2010-10-13 友达光电股份有限公司 电流驱动元件的驱动电路以及驱动方法
US20160148565A1 (en) * 2014-11-21 2016-05-26 Samsung Display Co., Ltd. Pixel circuit and organic light-emitting display device including the same
CN106847188A (zh) * 2017-03-31 2017-06-13 昆山国显光电有限公司 像素电路及其驱动方法、显示面板与显示装置
CN106935197A (zh) * 2017-04-07 2017-07-07 京东方科技集团股份有限公司 像素补偿电路、驱动方法、有机发光显示面板及显示装置
CN108335671A (zh) * 2018-02-28 2018-07-27 深圳市华星光电技术有限公司 Amoled像素驱动电路及驱动方法
CN109801595A (zh) * 2019-03-07 2019-05-24 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110013693A (ko) * 2009-08-03 2011-02-10 삼성모바일디스플레이주식회사 유기 전계발광 표시장치 및 그의 구동방법
TWI425479B (zh) * 2009-09-01 2014-02-01 Univ Nat Taiwan Science Tech 畫素及其驅動方法與照明裝置
CN103117041A (zh) * 2013-01-31 2013-05-22 华南理工大学 有源有机电致发光显示器的像素电路及其编程方法
CN103545343A (zh) * 2013-10-28 2014-01-29 深圳丹邦投资集团有限公司 高精度电压编程像素电路及oled显示器
CN103700346B (zh) * 2013-12-27 2016-08-31 合肥京东方光电科技有限公司 像素驱动电路、阵列基板、显示装置和像素驱动方法
CN103927984B (zh) * 2014-04-01 2017-07-28 深圳市华星光电技术有限公司 一种oled显示器的像素驱动电路及其驱动方法
CN104821150B (zh) * 2015-04-24 2018-01-16 北京大学深圳研究生院 像素电路及其驱动方法和显示装置
KR102661651B1 (ko) * 2017-02-06 2024-04-30 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치 및 화소

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859539A (zh) * 2010-04-16 2010-10-13 友达光电股份有限公司 电流驱动元件的驱动电路以及驱动方法
US20160148565A1 (en) * 2014-11-21 2016-05-26 Samsung Display Co., Ltd. Pixel circuit and organic light-emitting display device including the same
CN106847188A (zh) * 2017-03-31 2017-06-13 昆山国显光电有限公司 像素电路及其驱动方法、显示面板与显示装置
CN106935197A (zh) * 2017-04-07 2017-07-07 京东方科技集团股份有限公司 像素补偿电路、驱动方法、有机发光显示面板及显示装置
CN108335671A (zh) * 2018-02-28 2018-07-27 深圳市华星光电技术有限公司 Amoled像素驱动电路及驱动方法
CN109801595A (zh) * 2019-03-07 2019-05-24 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板

Also Published As

Publication number Publication date
CN109801595A (zh) 2019-05-24

Similar Documents

Publication Publication Date Title
US11361712B2 (en) Pixel circuit, driving method thereof, and display device
WO2023005597A1 (zh) 像素驱动电路及显示面板
CN109785797B (zh) 一种amoled像素电路
CN114155813B (zh) 像素电路、像素电路的驱动方法和显示面板
US11410600B2 (en) Pixel driving circuit and method, display apparatus
CN113571009B (zh) 发光器件驱动电路、背光模组以及显示面板
CN111312160B (zh) 像素驱动电路及显示面板
WO2016119304A1 (zh) Amoled像素驱动电路及像素驱动方法
CN106067291A (zh) 一种像素驱动电路及其驱动方法、显示装置
WO2021174616A1 (zh) 像素驱动电路及显示面板
CN108389551B (zh) 一种像素电路及其驱动方法、显示装置
WO2016119305A1 (zh) Amoled像素驱动电路及像素驱动方法
CN102930821A (zh) 一种像素电路及其驱动方法、显示装置
WO2021012430A1 (zh) 像素驱动电路及显示面板
WO2022226727A1 (zh) 像素电路、像素驱动方法和显示装置
WO2023115665A1 (zh) 发光器件驱动电路及显示面板
WO2022170700A1 (zh) 像素驱动电路及显示面板
WO2019227989A1 (zh) 像素驱动电路及方法、显示装置
CN104537984B (zh) 一种像素电路及其驱动方法
WO2023226083A1 (zh) 像素驱动电路、像素驱动方法和显示面板
CN114038405A (zh) 发光器件驱动电路、背光模组以及显示面板
WO2020177258A1 (zh) 像素驱动电路及显示面板
CN104680968B (zh) 像素电路及其显示装置和一种像素电路驱动方法
WO2020206857A1 (zh) 像素驱动电路及显示面板
CN108335666B (zh) 一种补偿驱动管阈值电压漂移的硅基oled像素电路及其方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19917950

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19917950

Country of ref document: EP

Kind code of ref document: A1