WO2020177098A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2020177098A1
WO2020177098A1 PCT/CN2019/077180 CN2019077180W WO2020177098A1 WO 2020177098 A1 WO2020177098 A1 WO 2020177098A1 CN 2019077180 W CN2019077180 W CN 2019077180W WO 2020177098 A1 WO2020177098 A1 WO 2020177098A1
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WIPO (PCT)
Prior art keywords
pattern
patterns
basic
substrate
semiconductor structure
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PCT/CN2019/077180
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English (en)
French (fr)
Inventor
陆斌
沈健
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深圳市汇顶科技股份有限公司
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Priority to EP19917826.0A priority Critical patent/EP3758065A4/en
Priority to CN201980000338.8A priority patent/CN111902934B/zh
Priority to PCT/CN2019/077180 priority patent/WO2020177098A1/zh
Publication of WO2020177098A1 publication Critical patent/WO2020177098A1/zh
Priority to US17/022,240 priority patent/US20210005706A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors

Definitions

  • This application relates to the field of semiconductors, and more specifically, to a semiconductor structure and a manufacturing method thereof.
  • energy storage devices for example, batteries, capacitors, etc.
  • sensors, etc. are widely used in modern electronic systems, it is necessary to fabricate structures with high surface area and low footprint to increase energy density, sensing area, etc.
  • Plasma etching technology is a widely used method to increase the surface area of trenches with high aspect ratio.
  • processing high aspect ratio structures has greater process difficulty. To put it simply, as the etching progresses to a certain depth, on the one hand, it is difficult for the reactive substances participating in the etching to continue to enter the bottom of the trench, and on the other hand, the products formed by the reaction are difficult to diffuse out from the bottom of the trench. The smaller the trench opening, the greater the trench depth, and the more serious this phenomenon is. Therefore, using the existing etching technology to fabricate a higher aspect ratio structure easily leads to process problems such as low etching efficiency, poor etching uniformity, and poor repeatability.
  • the present application provides a semiconductor structure and a manufacturing method thereof, which can manufacture a non-linear trench structure, and can increase the surface area of the trench structure without increasing the aspect ratio and maintaining the same floor area.
  • a semiconductor structure including:
  • the substrate includes an upper surface and a lower surface arranged oppositely;
  • At least one trench structure is disposed on the substrate and formed downward from the upper surface;
  • the projection of the groove structure on the upper surface forms a first pattern of a curve type or a zigzag type, and the first pattern includes n second patterns adjacent to each other, and the n second patterns are odd
  • the second patterns of bits are the same, and the second patterns of even-numbered bits are the same, and n is a positive integer.
  • the at least one curved or broken line trench structure provided in the substrate can maintain the footprint without increasing the aspect ratio.
  • the area is constant, the surface area of the trench structure is increased.
  • the second pattern with odd bits can be rotated to obtain the second pattern with even bits, or the second pattern with even bits can be rotated to obtain the second pattern with odd bits.
  • the semiconductor structure is used to prepare a structure with a high surface area and a low footprint.
  • the semiconductor structure is used to prepare energy storage devices and/or sensors, wherein the energy storage devices and/or sensors include at least one conductive layer and at least one conductive layer disposed in the trench structure.
  • the energy storage devices and/or sensors include at least one conductive layer and at least one conductive layer disposed in the trench structure.
  • a dielectric layer is used to prepare energy storage devices and/or sensors, wherein the energy storage devices and/or sensors include at least one conductive layer and at least one conductive layer disposed in the trench structure.
  • a dielectric layer is used to prepare energy storage devices and/or sensors, wherein the energy storage devices and/or sensors include at least one conductive layer and at least one conductive layer disposed in the trench structure.
  • a dielectric layer is used to prepare energy storage devices and/or sensors, wherein the energy storage devices and/or sensors include at least one conductive layer and at least one conductive layer disposed in the trench structure.
  • the semiconductor structure of the embodiment of the present application when the semiconductor structure of the embodiment of the present application is applied to an energy storage device and/or sensor, the energy density of the energy storage device can be increased, and the sensing area of the sensor can be increased.
  • a method for manufacturing a semiconductor structure including:
  • the substrate comprising an upper surface and a lower surface which are arranged oppositely;
  • At least one trench structure is etched on the substrate based on the first pattern of the curve type or the zigzag type, and the trench structure enters the substrate downward from the upper surface, wherein the first pattern It includes n second patterns adjacent to each other, in the n second patterns, odd-digit second patterns are the same, and even-digit second patterns are the same, and n is a positive integer.
  • the curved or broken line trench structure can be etched on the substrate based on the first pattern of the curve type or the broken line type, which can maintain the floor area without increasing the aspect ratio. Under the same condition, increase the surface area of the trench structure.
  • the method before etching the at least one trench structure, the method further includes:
  • the linear groove pattern is divided into n rectangular patterns adjacent to each other, wherein the rectangular pattern has a first long side and a second long side with a length of L/n in the first direction, and the rectangle The pattern has two wide sides with a width W in the second direction, and the first direction is perpendicular to the second direction;
  • the odd-numbered rectangular patterns among the n rectangular patterns are divided into two first sub-patterns according to a first dividing line, and the two first sub-patterns respectively include the first long side and the second A long side, and the first dividing line connects two end points of the first long side;
  • N1 is a positive integer
  • N2 is a positive integer
  • the N1 first basic patterns and the N2 second basic patterns are combined to form the first pattern, and the sum of N1 and N2 is n.
  • the area of the first pattern is exactly the same as the original linear groove pattern, so the floor area remains unchanged.
  • the perimeter of the first pattern is larger than the linear groove pattern, and the perimeter multiplied by the depth equals the surface area, so the surface area is increased.
  • the method before etching the at least one trench structure, the method further includes:
  • the removing sharp corners at both ends of the first pattern includes:
  • the first dividing line and/or the second dividing line are at least one curve and/or at least one polyline.
  • the first dividing line and the second dividing line are symmetric about the axis of the linear groove pattern as a symmetry axis.
  • the first basic pattern can be rotated to obtain the second basic pattern, or the second basic pattern can be rotated to obtain the first basic pattern.
  • the etching at least one trench structure on the substrate based on the first pattern based on the curve or the broken line includes:
  • the at least one trench structure is etched on the substrate by using Deep Reactive Ion Etch (DRIE).
  • DRIE Deep Reactive Ion Etch
  • FIG. 1 and 2 show schematic diagrams of a semiconductor structure 100 according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a first pattern 121 according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a semiconductor structure 100 according to an embodiment of the present application.
  • FIG. 5 shows a schematic flowchart of a method 200 for manufacturing a semiconductor structure according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a manufacturing method of a semiconductor structure according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another method of manufacturing a semiconductor structure according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another method for manufacturing a semiconductor structure according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of yet another method for manufacturing a semiconductor structure according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of yet another method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of yet another method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 1 and 2 show schematic diagrams of a semiconductor structure 100 according to an embodiment of the present application.
  • FIG. 1 is a three-dimensional view of a semiconductor structure 100
  • FIG. 2 is a first pattern 121 formed by projection of at least one trench structure 120 in the semiconductor structure 100 on the upper surface of the substrate 110.
  • the semiconductor structure 100 includes a substrate 110 and at least one trench structure 120.
  • the substrate 110 includes an upper surface and a lower surface disposed oppositely.
  • the at least one trench structure 120 is disposed on the substrate 110 and formed downward from the upper surface.
  • the projection of the groove structure 120 on the upper surface forms a first pattern 121 of a curve type or a fold line type.
  • the first pattern 121 includes n second patterns 122 adjacent to each other, so In the n second patterns 122, the odd-digit second patterns 122 are the same, and the even-digit second patterns 122 are the same, and n is a positive integer.
  • the groove structure 120 is a non-linear groove.
  • n 10
  • the second patterns 122 numbered 1, 3, 5, 7 and 9 are the same
  • the second patterns numbered 2, 4, 6, 8 and 10 are the same.
  • the two patterns 122 are the same. It should be noted that the number of the second pattern 122 is assigned for a better understanding of the solution, and this application is not limited thereto.
  • the trench structure 120 is used to prepare a device. (For example, an energy storage device), it is possible to avoid the formation of an area where the electric field is too concentrated at the sharp corners, thereby ensuring the performance of the prepared device.
  • the sharp corners at both ends of the groove structure 120 may not be removed.
  • the odd-digit second pattern 122 can be rotated to obtain the even-digit second pattern 122, or the even-digit second pattern 122 can be rotated to obtain the odd-digit second pattern 122.
  • the number 2 second pattern 122 can be rotated to obtain the number 3 second pattern 122, of course, the number 3 second pattern 122 can also be rotated to obtain the number 2 second pattern 122.
  • the first patterns 121 in different trench structures 120 in the at least one trench structure 120 may be the same or different.
  • the first pattern 121 may be one or more of the three patterns a, b, and c shown in FIG. 3.
  • the first pattern 121 may also be other regular or irregular patterns, which is not limited in this application.
  • the semiconductor structure 100 may be as shown in FIG. 4, where in FIG. 4, A is at least one trench structure 120 in the semiconductor structure 100 according to the embodiment of the present application.
  • a perspective view of B is a top view of at least one trench structure 120 in the semiconductor structure 100 according to an embodiment of the application, and in FIG. 4, the x direction represents the width direction of the trench 120, and the y direction represents the length of the trench 120 The direction, the z direction indicates the depth direction of the trench 120.
  • the semiconductor structure 100 shown in FIG. 4 includes three trench structures 120, and the three trench structures 120 are disposed on the substrate 110 and are formed downward from the upper surface of the substrate 110. The projection of the groove structure 120 on the upper surface of the substrate 110 forms a curved first pattern 121.
  • the semiconductor structure 100 is applied to a structure with a high surface area and a low footprint.
  • at least one trench structure 120 is etched on the substrate 110 by deep reactive ion etching, which can be achieved without increasing the aspect ratio and maintaining the same footprint.
  • Increase the surface area of the trench structure 120 for example, increase the surface area by more than 50%.
  • the semiconductor structure 100 is used to prepare an energy storage device and/or sensor, wherein the energy storage device and/or sensor includes at least one conductive layer and at least one dielectric disposed in the trench structure 120 Layer, and the at least one conductive layer and the at least one dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other.
  • a dielectric layer and a conductive layer are alternately deposited in the trench structure 120 to form an energy storage device.
  • a dielectric layer and a conductive layer are alternately deposited in the trench structure 120 to form a capacitor.
  • the dielectric layer deposited in the trench structure 120 may include at least one of the following: a silicon dioxide layer, a silicon nitride layer, an aluminum oxide (Al 2 O 3 ) layer, an oxide layer Zirconium (ZrO 2 ) layer, hafnium oxide (HfO 2 ) layer, titanium oxide (TiO 2 ) layer, yttrium oxide (Y 2 O 3 ) layer, lanthanum oxide (La 2 O 3 ) layer, hafnium silicate (HfSiO 4 ) Layers, lanthanum aluminate (LaAlO 3 ) layer, lanthanum lutetium oxide (LaLuO 3 ) layer, barium titanate (BaTiO3) layer, strontium titanate (SrTiO 3 ) layer, barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) layer, lead zirconate titanate (PbZr x Ti
  • the specific insulating material and dielectric layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer may also include some other material layers with high dielectric constant characteristics, which is not limited in the embodiment of the present application.
  • the conductive layer deposited in the trench structure 120 includes at least one of the following: a heavily doped polysilicon layer, a carbon-based material layer, a metal layer, and a titanium nitride layer.
  • the specific conductive material can be heavily doped polysilicon, carbon-based materials, or various metals such as aluminum, tungsten, and copper, or compounds with low resistivity such as titanium nitride (TiN) and tantalum nitride (TaN), or It is a combination of the above-mentioned conductive materials.
  • the dielectric layer deposited in the trench structure 120 may be a stack of silicon dioxide/alumina/silicon dioxide (SiO 2 /Al 2 O 3 /SiO 2 ) containing materials with high dielectric constant, so that Improve capacitance density.
  • the substrate 110 may be an n-type or p-type heavily doped low-resistivity silicon wafer.
  • High-resistivity wafers can also be used, but after the trench structure 120 is fabricated, the upper surface (front) of the substrate 110 and the surface of the trench structure 120 need to be doped to form a heavily doped low-resistivity conductive layer .
  • At least one trench structure provided in the substrate is a curved or broken line trench structure.
  • the depth and width may not be increased. Increase the surface area of the trench structure while maintaining the same floor area.
  • FIG. 5 is a schematic flowchart of the method for fabricating a semiconductor structure according to an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or modifications of each operation in FIG. 5.
  • FIG. 5 shows a schematic flowchart of a method 200 for manufacturing a semiconductor structure according to an embodiment of the present application. As shown in FIG. 5, the manufacturing method 200 of the semiconductor structure includes:
  • the second A pattern includes n second patterns adjacent to each other, in the n second patterns, the odd-digit second patterns are the same, and the even-digit second patterns are the same, and n is a positive integer.
  • At least one trench structure 120 is etched on the substrate 110 based on the first pattern 121 of a curve type or a broken line type to prepare the semiconductor structure 100 as shown in FIG. 1.
  • the method 200 further includes:
  • the first pattern is prepared.
  • the first pattern can be prepared through the following steps:
  • Step 1 Provide a linear groove pattern with a length L and a width W, where L and W are positive numbers.
  • the linear groove pattern 21 has a certain length L and width W, wherein the x direction may be the width direction of the linear groove pattern 21, and the y direction may be the linear groove pattern.
  • Step 2 Divide the linear groove pattern into n rectangular patterns adjacent to each other, where n is a positive integer, wherein the rectangular pattern has a first long side with a length of L/n in the first direction and The second long side, the rectangular pattern has two wide sides with a width W in a second direction, and the first direction is perpendicular to the second direction.
  • the linear groove pattern 21 as shown in a in FIG. 6 is divided into 10 rectangular patterns 22 adjacent to each other, as shown in b in FIG. 6, and the rectangular pattern 22 includes the first in the y direction.
  • a long side S1 and a second long side S2 the length of the first long side S1 and the second long side S2 is L/n
  • the rectangular pattern 22 has two wide sides with a width W along the x direction, that is, the first The direction is the y direction, and the second direction is the x direction.
  • the 10 rectangular patterns 22 are numbered, and they are recorded as 1 to 10, respectively.
  • first long side S1 and the second long side S2 are formed by two end points and a straight line connecting the two end points.
  • the linear groove pattern 21 is divided into ten rectangular patterns 22 of 1 ⁇ m ⁇ 0.8 ⁇ m.
  • Step 3 Divide the odd-numbered rectangular pattern among the n rectangular patterns into two first sub-patterns according to a first dividing line, and the two first sub-patterns respectively include the first long side and the first sub-pattern.
  • the second long side, and the first dividing line connects two end points of the first long side.
  • the odd-numbered (numbered 1, 3, 5, 7 and 9) rectangular patterns 22 of the 10 rectangular patterns 22 shown in b in FIG. 6 are divided into first sub-patterns according to the first dividing line 23 22A and the first sub-pattern 22B.
  • the first sub-pattern 22A includes a first long side S1
  • the first sub-pattern 22B includes a second long side S2.
  • the first dividing line 23 connects the two end points of the first long side S1, as shown in FIG. As shown in c in 6.
  • Step 4 overlapping the long sides of the two first sub-patterns to form N1 first basic patterns, where N1 is a positive integer.
  • Step 5 Divide the even-numbered rectangular pattern in the n rectangular patterns into two second sub-patterns according to a second dividing line, the two second sub-patterns respectively including the first long side and the The second long side, and the second dividing line connects two end points of the second long side.
  • the even-numbered (numbered 2, 4, 6, 8 and 10) rectangular patterns 22 of the 10 rectangular patterns 22 shown in b in FIG. 6 are divided into second sub-patterns according to the second dividing line 25 22C and the second sub-pattern 22D, the second sub-pattern 22C includes the first long side S1, the second sub-pattern 22D includes the second long side S2, and the second dividing line 25 connects the two end points of the second long side S2, as shown in the figure As shown in c in 6.
  • Step 6 overlapping the long sides of the two second sub-patterns to form N2 second basic patterns, where N2 is a positive integer.
  • Step 7 combining the N1 first basic patterns and the N2 second basic patterns to form a first pattern 121, and the sum of N1 and N2 is n.
  • the N1 first basic patterns and the N2 second basic patterns are alternately combined. That is, a first basic pattern can only be combined with a second basic pattern, but cannot be combined with other first basic patterns. Similarly, a second basic pattern can only be combined with the first basic pattern, but cannot be combined with other second basic patterns combination.
  • first basic patterns 24 and the five second basic patterns 26 shown in d in FIG. 6 are combined to form a first pattern 121, as shown in e in FIG. 6.
  • the five first basic patterns 24 and the five second basic patterns 26 may be randomly combined.
  • the first basic pattern 24 numbered 1 is combined with the second basic pattern 26 numbered 6, the second basic pattern 26 numbered 6 is combined with the first basic pattern 24 numbered 3, and the first basic pattern numbered 3 is combined.
  • the basic pattern 24 is combined with the second basic pattern 26 numbered 2
  • the second basic pattern 26 numbered is combined with the first basic pattern 24 numbered 5
  • the first basic pattern 24 numbered 5 is combined with the 8th basic pattern numbered.
  • Two basic patterns 26 are combined, the second basic pattern 26 numbered 8 is combined with the first basic pattern 24 numbered 7, the first basic pattern 24 numbered 7 is combined with the second basic pattern 26 numbered 10,
  • the second basic pattern 26 numbered 10 is combined with the first basic pattern 24 numbered 9, and the first basic pattern 24 numbered 9 is combined with the second basic pattern 26 numbered 4.
  • the five first basic patterns 24 and the five second basic patterns 26 may be combined in a certain order.
  • the first basic pattern 24 numbered 1 is combined with the second basic pattern 26 numbered 2
  • the second basic pattern 26 numbered 2 is combined with the first basic pattern 24 numbered 3
  • the first basic pattern numbered 3 is combined.
  • the basic pattern 24 is combined with the second basic pattern 26 numbered 4
  • the second basic pattern 26 numbered 4 is combined with the first basic pattern 24 numbered 5
  • the first basic pattern 24 numbered 5 is combined with the 6th basic pattern numbered.
  • Combine the two basic patterns 26, the second basic pattern 26 numbered 6 is combined with the first basic pattern 24 numbered 7 and the first basic pattern 24 numbered 7 is combined with the second basic pattern 26 numbered 8
  • the second basic pattern 26 numbered 8 is combined with the first basic pattern 24 numbered 9, and the first basic pattern 24 numbered 9 is combined with the second basic pattern 26 numbered 10.
  • the number of the first basic pattern 24 is the number of the corresponding rectangular pattern 22.
  • the rectangular pattern 22 with the number 1 is divided and combined to form the first basic pattern 24 with the number 1, and the rectangular pattern 22 with the number 3.
  • the first basic pattern 24 numbered 3 is formed by division and combination
  • the first basic pattern 24 numbered 5 is formed by division and combination of the rectangular pattern 22 numbered
  • the first basic pattern number 5 is formed by the rectangular pattern 22 numbered by division and combination.
  • the first basic pattern 24 numbered 7 and the rectangular pattern 22 numbered 9 are divided and combined to form the first basic pattern 24 numbered 9.
  • the number of the second basic pattern 26 is the number of the corresponding rectangular pattern 22.
  • the rectangular pattern 22 with the number 2 is divided and combined to form the second basic pattern 26 with the number 2 and the rectangular pattern with the number 4 22
  • the second basic pattern 26 numbered 4 is formed by division and combination
  • the second basic pattern 26 numbered 6 is formed by division and combination of the rectangular pattern 22 numbered
  • the rectangular pattern 22 numbered 8 is formed by division and combination
  • the second basic pattern 26 numbered 8 and the rectangular pattern 22 numbered 10 are divided and combined to form the second basic pattern 26 numbered 10.
  • first basic pattern 24 and the second basic pattern 26 can be combined along an edge in the x direction.
  • the at least one trench structure 120 may be etched on the substrate 110 based on the first pattern 121 and using deep reactive ion etching.
  • a layer of photoresist is spin-coated on the upper surface (front side) of the substrate 110, and exposed and developed to form an etching pattern window that is not covered with the photoresist.
  • at least one trench structure 120 is formed in the substrate 110 by deep reactive ion etching. The trench structure 120 extends downward from the upper surface of the substrate 110, and the depth of the trench structure 120 is less than the thickness of the substrate 110.
  • the execution order of the above steps 3 and 4 can be interchanged with the above steps 5 and 6, that is, the odd-numbered rectangular pattern can be processed first to form N1 first basic patterns, or the even-numbered bit can be processed first.
  • the rectangular patterns are processed to form N2 second basic patterns.
  • the area of the first pattern 121 is exactly the same as the original linear groove pattern 21, so the floor area remains unchanged.
  • the perimeter of the first pattern 121 is larger than the linear groove pattern 21, and the perimeter multiplied by the depth equals the surface area, so the surface area is increased.
  • the perimeter of the first pattern 121 is approximately 1.57 times that of the linear groove pattern 21, and the surface area of the groove structure 120 thus obtained can also be increased by 57%.
  • a non-linear groove pattern can be formed based on the linear groove pattern, so that a non-linear groove structure can be etched on the substrate based on the non-linear groove pattern. Without increasing the aspect ratio and maintaining the same footprint, the surface area of the trench structure is increased.
  • the method 200 further includes:
  • the sharp corners less than 90 degrees at both ends of the first pattern 121 are removed.
  • the first pattern 121 when using the first pattern 121 to prepare a device (for example, an energy storage device), it is possible to avoid the formation of an area where the electric field is too concentrated at the sharp corners. Therefore, the performance of the prepared device is guaranteed.
  • a device for example, an energy storage device
  • the sharp corners at both ends of the first pattern 121 can be removed by cutting, erasing, or the like.
  • the sharp corners at both ends of the first pattern 121 can also be removed in other ways, which is not limited in this application.
  • the first dividing line 23 and/or the second dividing line 25 are at least one curve and/or at least one broken line.
  • the first dividing line 23 and the second dividing line 25 are a fold line, and the non-linear groove pattern shown in FIG. 7 is formed based on the manufacturing method 200 of the semiconductor structure ( The first pattern).
  • the first dividing line 23 and the second dividing line 25 are a curve, and the non-linear groove pattern shown in FIG. 8 is formed based on the manufacturing method 200 of the semiconductor structure. (The first pattern).
  • the first dividing line 23 and the second dividing line 25 are also a curved line, and a non-linear trench as shown in FIG. 9 is formed based on the manufacturing method 200 of the semiconductor structure.
  • Pattern first pattern
  • the first dividing line 23 and the second dividing line 25 are also a curve, and a non-linear trench as shown in FIG. 10 is formed based on the manufacturing method 200 of the above semiconductor structure.
  • Pattern first pattern
  • the first dividing line 23 and the second dividing line 25 are also multiple fold lines, and a non-linear groove as shown in FIG. 11 is formed based on the manufacturing method 200 of the above semiconductor structure.
  • Slot pattern first pattern
  • the first dividing line 23 and the second dividing line 25 are formed by the linear groove pattern.
  • the axis is symmetrical; the first basic pattern 24 can be rotated to obtain the second basic pattern 26, or the second basic pattern 26 can be rotated to obtain the first basic pattern 24.
  • the first dividing line 23 and the second dividing line 25 may also be different.
  • the first dividing line 23 is a broken line
  • the second dividing line 25 is a curve.
  • a non-linear groove pattern can be formed based on the linear groove pattern, so that a non-linear groove structure can be etched on the substrate based on the non-linear groove pattern. Without increasing the aspect ratio and maintaining the same footprint, the surface area of the trench structure is increased.
  • At least one insulating layer and at least one conductive layer may be alternately deposited in the at least one trench structure 120 to prepare a capacitor.
  • silicon dioxide is deposited (grown) on the upper surface of the substrate 110 and the inner surface of the at least one trench structure 120 as an insulating layer.
  • silicon dioxide or silicon nitride is grown by physical vapor deposition (PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD).
  • a high dielectric constant material film such as Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , La 2 O 3 , HfSiO 4 , is grown through an atomic layer deposition (ALD) process , LaAlO 3 , BaTiO 3 , SrTiO 3 , LaLuO 3 , BST, PZT, CCTO.
  • ALD atomic layer deposition
  • the material of the insulating layer includes silicon oxide, silicon nitride, metal oxide, metal nitride, etc., such as silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, Zirconium oxide, zinc oxide, titanium oxide, yttrium oxide, lanthanum oxide, hafnium silicate, lanthanum aluminate, lanthanum lutetium, barium titanate, strontium titanate, barium strontium titanate, copper calcium titanate, lead zirconate titanate, etc. .
  • the insulating layer can be one layer, or two or more layers. The specific material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the deposition method of the conductive layer includes ALD, PVD, organic metal chemical vapor deposition, evaporation, electroplating, and the like.
  • the conductive material of the conductive layer can be heavily doped polysilicon, carbon-based materials, or various metals such as aluminum, tungsten, copper, etc., or low-resistivity compounds such as titanium nitride, or a combination of the above-mentioned conductive materials .
  • the conductive layer may include at least one of the following: a heavily doped polysilicon layer, a carbon-based material layer, a metal layer, and a titanium nitride layer.

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Abstract

本申请提供一种半导体结构及其制作方法，能够制作非直线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构表面积。该半导体结构包括：衬底，包括相对设置的上表面和下表面；至少一个沟槽结构，设置于所述衬底，并自所述上表面向下形成；其中，所述沟槽结构在所述上表面的投影形成曲线型或者折线型的第一图案，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体领域，并且更具体地，涉及一种半导体结构及其制作方法。
背景技术
随着储能器件(例如，电池、电容等)、传感器等大量应用于现代电子系统，需要制作高表面积、低占地面积(footprint)的结构，用于提高能量密度、感应面积等。
在衬底上利用等离子刻蚀技术加工制作高深宽比的沟槽是一种被广泛采用的提高表面积的方法。然而，由于等离子刻蚀技术的特点，加工高深宽比的结构具有较大的工艺难度。简单来说，随着刻蚀进行到一定深度，一方面参与刻蚀的反应活性物质难以持续进入沟槽底部，另一方面反应生成的产物也很难从沟槽底部扩散出去。沟槽开口越小，沟槽深度越大，此类现象越严重。因此，利用现有刻蚀技术制作更高深宽比结构容易导致刻蚀效率低、刻蚀一致性差、可重复性差等工艺问题。另外，除去上述刻蚀本身的问题，在更高深宽比结构上进行后续工艺的难度也相应加大。随之引起的一系列良率、产出、成本等问题，难以解决。因此，如何制作高表面积、低占地面积的结构，为一个亟待解决的技术问题。
发明内容
本申请提供一种半导体结构及其制作方法，能够制作非直线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构表面积。
第一方面，提供了一种半导体结构，包括：
衬底，包括相对设置的上表面和下表面；
至少一个沟槽结构，设置于所述衬底，并自所述上表面向下形成；
其中，所述沟槽结构在所述上表面的投影形成曲线型或者折线型的第一图案，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。
因此，本申请实施例提供的半导体结构中，相对于直线型的沟槽结构，设置于衬底内的曲线型或者折线型的至少一个沟槽结构可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构表面积。
在一些可能的实现方式中，奇数位的第二图案能够通过旋转得到偶数位的第二图案，或者，偶数位的第二图案能够通过旋转得到奇数位的第二图案。
在一些可能的实现方式中，所述半导体结构用于制备高表面积、低占地面积的结构。
在一些可能的实现方式中，所述半导体结构用于制备储能器件和/或传感器，其中，所述储能器件和/或传感器包括设置于所述沟槽结构内的至少一个导电层和至少一个电介质层。
因此，在本申请实施例的半导体结构的应用于储能器件和/或传感器时，可以提高储能器件的能量密度，以及提高传感器的感应面积。
第二方面，提供了一种半导体结构的制作方法，包括：
提供衬底，所述衬底包括相对设置的上表面和下表面；
基于曲线型或者折线型的第一图案，在所述衬底上刻蚀至少一个沟槽结构，所述沟槽结构自所述上表面向下进入所述衬底，其中，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。
因此，在本申请实施例中，可以基于曲线型或者折线型的第一图案，在衬底上刻蚀曲线型或者折线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构的表面积。
在一些可能的实现方式中，在刻蚀所述至少一个沟槽结构之前，所述方法还包括：
提供长度为L且宽度为W的直线型沟槽图案，L和W为正数；
将所述直线型沟槽图案分割为彼此相邻的n个矩形图案，其中，所述矩形图案在第一方向上具有长度为L/n的第一长边和第二长边，所述矩形图案在第二方向上具有宽度为W的两个宽边，所述第一方向与所述第二方向垂直；
将所述n个矩形图案中奇数位的所述矩形图案按照第一分割线分割为两个第一子图案，所述两个第一子图案分别包括所述第一长边和所述第二长边，且所述第一分割线连接所述第一长边的两个端点；
将所述两个第一子图案的长边重合，以形成N1个第一基础图案，N1为正整数；
将所述n个矩形图案中偶数位的所述矩形图案按照第二分割线分割为两个第二子图案，所述两个第二子图案分别包括所述第一长边和所述第二长边，且所述第二分割线连接所述第二长边的两个端点；
将所述两个第二子图案的长边重合，以形成N2个第二基础图案，N2为正整数；
将所述N1个第一基础图案和所述N2个第二基础图案进行组合，以形成所述第一图案，N1与N2的和为n。
需要说明的是，第一图案的面积与原始的直线形沟槽图案完全一致，因此占地面积不变。第一图案的周长大于直线形沟槽图案，周长乘以深度等于表面积，因此表面积增大。
在一些可能的实现方式中，在刻蚀所述至少一个沟槽结构之前，所述方法还包括：
去除所述第一图案中首尾两端的尖角。
需要说明的是，去除所述第一图案中首尾两端的尖角，在利用所述第一图案制备器件(例如，储能器件)时，可以避免在尖角处形成电场过于集中的区域，从而，保证所制备的器件的性能。
在一些可能的实现方式中，所述去除所述第一图案中首尾两端的尖角，包括：
去除所述第一图案中首尾两端的小于90度的尖角。
在一些可能的实现方式中，所述第一分割线和/或所述第二分割线为至少一条曲线和/或至少一条折线。
在一些可能的实现方式中，所述第一分割线和所述第二分割线以所述直线型沟槽图案的轴线为对称轴对称。
在一些可能的实现方式中，所述第一基础图案能够通过旋转得到所述第二基础图案，或者，所述第二基础图案能够通过旋转得到所述第一基础图案。
在一些可能的实现方式中，所述基于曲线型或者折线型的第一图案，在所述衬底上刻蚀至少一个沟槽结构，包括：
基于所述第一图案，利用深反应离子刻蚀(Deep Reactive Ion Etch，DRIE)在所述衬底上刻蚀所述至少一个沟槽结构。
附图说明
图1和图2示出了本申请一个实施例的半导体结构100的示意图。
图3是根据本申请实施例的一种第一图案121的示意图。
图4是根据本申请实施例的半导体结构100的示意图。
图5示出了根据本申请实施例的半导体结构的制作方法200的示意性流程图。
图6是本申请实施例的一种半导体结构的制作方法的示意图。
图7是本申请实施例的另一种半导体结构的制作方法的示意图。
图8是本申请实施例的另一种半导体结构的制作方法的示意图。
图9是本申请实施例的再一种半导体结构的制作方法的示意图。
图10是本申请实施例的再一种半导体结构的制作方法的示意图。
图11是本申请实施例的再一种半导体结构的制作方法的示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1和图2示出了本申请一个实施例的半导体结构100的示意图。
图1为半导体结构100的三维视图，图2为半导体结构100中至少一个沟槽结构120在衬底110的上表面的投影形成的第一图案121。
如图1所示，半导体结构100包括衬底110和至少一个沟槽结构120。
所述衬底110包括相对设置的上表面和下表面。
所述至少一个沟槽结构120，设置于所述衬底110，并自所述上表面向下形成。
如图2所示，所述沟槽结构120在所述上表面的投影形成曲线型或者折线型的第一图案121，所述第一图案121包括彼此相邻的n个第二图案122，所述n个第二图案122中奇数位的第二图案122相同，且偶数位的第二图案122相同，n为正整数。
也就是说，在本申请实施例中，所述沟槽结构120为非直线型的沟槽。
具体地，如图2所示，n为10，编号1,3,5,7和9(奇数位)的第二图案122相同，编号2,4,6,8和10(偶数位)的第二图案122相同。需要说明的是，第二图案122的编号是为了更好理解方案而被赋予的，本申请对此并不限定。
需要说明的是，编号1的第二图案122和编号10的第二图案122中去除了尖角，去除所述沟槽结构120中首尾两端的尖角，在利用所述沟槽结构120制备器件(例如，储能器件)时，可以避免在尖角处形成电场过于集中的区域，从而，保证所制备的器件的性能。
当然，在本申请实施例中，也可以不用去除所述沟槽结构120中首尾两端的尖角。
可选地，奇数位的第二图案122能够通过旋转得到偶数位的第二图案122，或者，偶数位的第二图案122能够通过旋转得到奇数位的第二图案122。例如，如图2所示，编号2的第二图案122能够通过旋转得到编号3的第二图案122，当然，编号3的第二图案122也能够通过旋转得到编号2的第二图案122。
可选地，在本申请一个实施例中，所述至少一个沟槽结构120中不同的沟槽结构120中的所述第一图案121可以相同，也可以不同。
例如，所述第一图案121可以是如图3所示的a、b、c三种图案中的一种或者多种。当然，所述第一图案121还可以是其他规则或者不规则图案，本申请对此不作限定。
可选地，在本申请一个实施例中，所述半导体结构100可以如图4所示，其中，在图4中，A为本申请实施例所述的半导体结构100中至少一个沟槽结构120的透视图，B为本申请实施例所述的半导体结构100中至少一个沟槽结构120的俯视图，且在图4中，x方向表示沟槽120的宽度方向，y方向表示沟槽120的长度方向，z方向表示沟槽120的深度方向。在如图4所示的所述半导体结构100中包括3个沟槽结构120，且这3个沟槽结构120设置于衬底110，并自所述衬底110的上表面向下形成，沟槽结构120在衬底110的上表面的投影形成曲线型的第一图案121。
可选地，在本申请一个实施例中，所述半导体结构100应用于高表面积、低占地面积的结构。例如，基于非直线型的第一图案121，利用深反应离子刻蚀在衬底110上刻蚀出至少一个沟槽结构120，可以在不增加深宽比且维持占地面积不变的情况下，提升沟槽结构120的表面积，如提升50％以上的表面积。
可选地，所述半导体结构100用于制备储能器件和/或传感器，其中，所述储能器件和/或传感器包括设置于所述沟槽结构120内的至少一个导电层 和至少一个电介质层，且所述至少一个导电层和所述至少一个电介质层形成导电层与电介质层彼此相邻的结构。
例如，在沟槽结构120内交替沉积电介质层和导电层，以形成储能器件。
可选地，作为一个示例，在沟槽结构120内交替沉积电介质层和导电层，以形成电容器。
需要说明的是，在该示例中，在沟槽结构120内沉积的电介质层可以包括以下中的至少一层：二氧化硅层、氮化硅层、氧化铝(Al 2O 3)层、氧化锆(ZrO 2)层、氧化铪(HfO 2)层、氧化钛(TiO 2)层，氧化钇(Y 2O 3)层，氧化镧(La 2O 3)层，硅酸铪(HfSiO 4)层，铝酸镧(LaAlO 3)层，镥酸镧(LaLuO 3)层，钛酸钡(BaTiO3)层，钛酸锶(SrTiO 3)层，钛酸锶钡(Ba xSr 1-xTiO 3，BST)层，锆钛酸铅(PbZr xTi 1-xO 3，PZT)层、和钛酸铜钙(CaCu 3Ti 4O 12，CCTO)层。具体绝缘材料和电介质层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，电介质层还可以包括一些其他具有高介电常数特性的材料层，本申请实施例对此不作限定。在沟槽结构120内沉积的导电层包括以下至少一层：重掺杂多晶硅层、碳基材料层、金属层和氮化钛层。具体导电材料可以是重掺杂多晶硅，碳基材料，或者是铝、钨、铜等各类金属，也可以是氮化钛(TiN)、氮化钽(TaN)等低电阻率的化合物，或者是上述几种导电材料的组合。
在沟槽结构120内沉积的电介质层可以是二氧化硅/氧化铝/二氧化硅(SiO 2/Al 2O 3/SiO 2)这种含有高介电常数的材料的叠层，从而，可以提高电容密度。
可选地，在本申请一个实施例中，该衬底110可以是n型或p型重掺杂的低电阻率硅晶圆。也可以选用高电阻率晶圆，但在制作好该沟槽结构120之后，需要对衬底110上表面(正面)以及该沟槽结构120表面掺杂，形成重掺杂的低电阻率导电层。
因此，本申请实施例提供的半导体结构中，设置于衬底内的至少一个沟槽结构为曲线型或者折线型的沟槽结构，相对于直线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构表面积。
以下，结合图5至图11，详细介绍本申请实施例的半导体结构的制作方法。
应理解，图5是本申请实施例的半导体结构的制作方法的示意性流程图， 但这些步骤或操作仅是示例，本申请实施例还可以执行其他操作或者图5中的各个操作的变形。
图5示出了根据本申请实施例的半导体结构的制作方法200的示意性流程图。如图5所示，该半导体结构的制作方法200包括：
S210，提供衬底，所述衬底包括相对设置的上表面和下表面；
S220，基于曲线型或者折线型的第一图案，在所述衬底上刻蚀至少一个沟槽结构，所述沟槽结构自所述上表面向下进入所述衬底，其中，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。
具体地，基于曲线型或者折线型的第一图案121，在衬底110上刻蚀至少一个沟槽结构120，以制备如图1所示的半导体结构100。
可选地，在刻蚀所述至少一个沟槽结构之前，所述方法200还包括：
制备所述第一图案。
具体地，可以通过如下步骤制备所述第一图案：
步骤1，提供长度为L且宽度为W的直线型沟槽图案，L和W为正数。
具体地，如图6中的a所示，直线型沟槽图案21具有一定的长度L和宽度W，其中，x方向可以是直线型沟槽图案21的宽度方向，y方向可以是直线型沟槽图案21的长度方向。
步骤2，将所述直线型沟槽图案分割为彼此相邻的n个矩形图案，n为正整数，其中，所述矩形图案在第一方向上具有长度为L/n的第一长边和第二长边，所述矩形图案在第二方向上具有宽度为W的两个宽边，所述第一方向与所述第二方向垂直。
具体地，将如图6中的a所示的直线型沟槽图案21分割为彼此相邻的10个矩形图案22，如图6中的b所示，并且矩形图案22沿着y方向包括第一长边S1和第二长边S2，第一长边S1和第二长边S2的长度为L/n，矩形图案22沿着x方向上具有宽度为W的两个宽边，即第一方向为y方向，第二方向为x方向。如图6中的b所示，按形成这10个矩形图案22的顺序，对10个矩形图案22编号，分别记为1至10。
需要说明的是，第一长边S1和第二长边S2由两个端点以及连接两个端点的直线段形成。
应理解，具体分割为彼此相邻的几个矩形图案22可以根据实际需求进 行确定，例如，可以根据直线型沟槽图案21的长度L确定。
假设直线型沟槽图案21的长度L和宽度W分别为10微米和0.8微米，则将直线型沟槽图案21分割为10个1微米×0.8微米的矩形图案22。
步骤3，将所述n个矩形图案中奇数位的所述矩形图案按照第一分割线分割为两个第一子图案，所述两个第一子图案分别包括所述第一长边和所述第二长边，且所述第一分割线连接所述第一长边的两个端点。
具体地，将如图6中的b所示的10个矩形图案22中奇数位(编号为1,3,5,7和9)的矩形图案22按照第一分割线23分割为第一子图案22A和第一子图案22B，第一子图案22A包括第一长边S1，第一子图案22B包括第二长边S2，第一分割线23连接第一长边S1的两个端点，如图6中的c所示。
步骤4，将所述两个第一子图案的长边重合，以形成N1个第一基础图案，N1为正整数。
具体地，将如图6中的c所示的第一子图案22A所包括的第一长边S1与第一子图案22B所包括的第二长边S2重合，以形成5个第一基础图案24，即N1＝5，如图6中的d所示。
步骤5，将所述n个矩形图案中偶数位的所述矩形图案按照第二分割线分割为两个第二子图案，所述两个第二子图案分别包括所述第一长边和所述第二长边，且所述第二分割线连接所述第二长边的两个端点。
具体地，将如图6中的b所示的10个矩形图案22中偶数位(编号为2,4,6,8和10)的矩形图案22按照第二分割线25分割为第二子图案22C和第二子图案22D，第二子图案22C包括第一长边S1，第二子图案22D包括第二长边S2，第二分割线25连接第二长边S2的两个端点，如图6中的c所示。
步骤6，将所述两个第二子图案的长边重合，以形成N2个第二基础图案，N2为正整数。
具体地，将如图6中的c所示的第二子图案22C所包括的第一长边S1与第二子图案22D所包括的第二长边S2重合，以形成5个第二基础图案26，即N2＝5，如图6中的d所示。
步骤7，将所述N1个第一基础图案和所述N2个第二基础图案进行组合，以形成第一图案121，N1与N2的和为n。
可选地，所述N1个第一基础图案和所述N2个第二基础图案交替组合。即一个第一基础图案仅与第二基础图案组合，而不能与其他的第一基础图案组合，同理，一个第二基础图案仅与第一基础图案组合，而不能与其他的第二基础图案组合。
具体地，将如图6中的d所示的5个第一基础图案24和5个第二基础图案26进行组合，以形成第一图案121，如图6中的e所示。
可选地，5个第一基础图案24和5个第二基础图案26可以是随机组合。
例如，编号为1的第一基础图案24与编号为6第二基础图案26进行组合，编号为6的第二基础图案26与编号为3第一基础图案24进行组合，编号为3的第一基础图案24与编号为2第二基础图案26进行组合，编号为2的第二基础图案26与编号为5第一基础图案24进行组合，编号为5的第一基础图案24与编号为8第二基础图案26进行组合，编号为8的第二基础图案26与编号为7第一基础图案24进行组合，编号为7的第一基础图案24与编号为10第二基础图案26进行组合，编号为10的第二基础图案26与编号为9第一基础图案24进行组合，编号为9的第一基础图案24与编号为4第二基础图案26进行组合。
可选地，5个第一基础图案24和5个第二基础图案26可以是按照一定的顺序进行组合。
例如，编号为1的第一基础图案24与编号为2第二基础图案26进行组合，编号为2的第二基础图案26与编号为3第一基础图案24进行组合，编号为3的第一基础图案24与编号为4第二基础图案26进行组合，编号为4的第二基础图案26与编号为5第一基础图案24进行组合，编号为5的第一基础图案24与编号为6第二基础图案26进行组合，编号为6的第二基础图案26与编号为7第一基础图案24进行组合，编号为7的第一基础图案24与编号为8第二基础图案26进行组合，编号为8的第二基础图案26与编号为9第一基础图案24进行组合，编号为9的第一基础图案24与编号为10第二基础图案26进行组合。
应理解，第一基础图案24的编号为其对应的矩形图案22的编号，例如编号为1的矩形图案22通过分割、组合形成编号为1的第一基础图案24，编号为3的矩形图案22通过分割、组合形成编号为3的第一基础图案24，编号为5的矩形图案22通过分割、组合形成编号为5的第一基础图案24， 编号为7的矩形图案22通过分割、组合形成编号为7的第一基础图案24，编号为9的矩形图案22通过分割、组合形成编号为9的第一基础图案24。同理，第二基础图案26的编号为其对应的矩形图案22的编号，例如，编号为2的矩形图案22通过分割、组合形成编号为2的第二基础图案26，编号为4的矩形图案22通过分割、组合形成编号为4的第二基础图案26，编号为6的矩形图案22通过分割、组合形成编号为6的第二基础图案26，编号为8的矩形图案22通过分割、组合形成编号为8的第二基础图案26，编号为10的矩形图案22通过分割、组合形成编号为10的第二基础图案26。
需要说明的是，第一基础图案24与第二基础图案26可以沿x方向上的边进行组合。
可选地，可以基于所述第一图案121，且利用深反应离子刻蚀在衬底110上刻蚀所述至少一个沟槽结构120。
具体地，首先，基于该第一图案121，在衬底110上表面(正面)旋涂一层光刻胶，并曝光、显影，形成未覆盖光刻胶的刻蚀图形窗口。接着，通过深反应离子刻蚀，在衬底110中制作至少一个沟槽结构120。该沟槽结构120自该衬底110的上表面向下延伸，且该沟槽结构120的深度小于该衬底110的厚度。
应理解，在刻蚀出该至少一个沟槽结构120之后，去除光刻胶。
需要说明的是，上述步骤3和4的执行顺序与上述步骤5和6可以互换，即可以先对奇数位的矩形图案进行处理，以形成N1个第一基础图案，也可以先对偶数位的矩形图案进行处理，以形成N2个第二基础图案。
在上述半导体结构的制作方法200中，第一图案121的面积与原始的直线形沟槽图案21完全一致，因此占地面积不变。第一图案121的周长大于直线形沟槽图案21，周长乘以深度等于表面积，因此表面积增大。例如，第一图案121的周长约是直线形沟槽图案21的1.57倍，由此得到的沟槽结构120的表面积也因此可以增大57％。
因此，在本申请实施例中，可以根据直线型沟槽图案，形成非直线型沟槽图案，从而基于非直线型沟槽图案，在衬底上刻蚀非直线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构的表面积。
可选地，在刻蚀所述至少一个沟槽结构120之前，所述方法200还包括：
去除所述第一图案121中首尾两端的尖角。
具体地，将如图6中的e所示的第一图案121中首尾两端的尖角去除，如图6中的f所示。
例如，去除所述第一图案121中首尾两端的小于90度的尖角。
需要说明的是，去除所述第一图案121中首尾两端的尖角，在利用所述第一图案121制备器件(例如，储能器件)时，可以避免在尖角处形成电场过于集中的区域，从而，保证所制备的器件的性能。
还需要说明的是，可以通过裁剪、擦除等方式去除所述第一图案121中首尾两端的尖角。当然，也可以通过其他方式去除所述第一图案121中首尾两端的尖角，本申请对此不作限定。
在一些可能的实现方式中，所述第一分割线23和/或所述第二分割线25为至少一条曲线和/或至少一条折线。
例如，如图7所示，所述第一分割线23和所述第二分割线25为一条折线，并基于上述半导体结构的制作方法200形成如图7所示的非直线型沟槽图案(第一图案)。
又例如，如图8所示，所述第一分割线23和所述第二分割线25为一条曲线，并基于上述半导体结构的制作方法200形成如图8所示的非直线型沟槽图案(第一图案)。
又例如，如图9所示，所述第一分割线23和所述第二分割线25也为一条曲线，并基于上述半导体结构的制作方法200形成如图9所示的非直线型沟槽图案(第一图案)。
再例如，如图10所示，所述第一分割线23和所述第二分割线25也为一条曲线，并基于上述半导体结构的制作方法200形成如图10所示的非直线型沟槽图案(第一图案)。
再例如，如图11所示，所述第一分割线23和所述第二分割线25也为多条折线，并基于上述半导体结构的制作方法200形成如图11所示的非直线型沟槽图案(第一图案)。
需要说明的是，在上述图7至图11所示的非直线型沟槽图案的形成过程中，所述第一分割线23和所述第二分割线25以所述直线型沟槽图案的轴线为对称轴对称；所述第一基础图案24能够通过旋转得到所述第二基础图案26，或者，所述第二基础图案26能够通过旋转得到所述第一基础图案24。 当然，所述第一分割线23与所述第二分割线25也可以不同，例如，所述第一分割线23为一条折线，所述第二分割线25为一条曲线。
因此，在本申请实施例中，可以根据直线型沟槽图案，形成非直线型沟槽图案，从而基于非直线型沟槽图案，在衬底上刻蚀非直线型的沟槽结构，可以在不增大深宽比且维持占地面积不变的情况下，提升沟槽结构的表面积。
可选地，作为一个示例，可以在所述至少一个沟槽结构120内交替沉积至少一个绝缘层和至少一个导电层，以制备电容器。
例如，通过热氧化的方式，在衬底110的上表面和该至少一个沟槽结构120内表面沉积(生长)二氧化硅，作为绝缘层。再例如，通过物理气相沉积(Physical Vapor Deposition，PVD)或化学气相沉积(Chemical Vapor Deposition，CVD)生长二氧化硅或氮化硅。再例如，通过原子层沉积(Atomic layer deposition，ALD)工艺生长高介电常数材料薄膜，例如Al 2O 3，HfO 2，ZrO 2，TiO 2，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，BaTiO 3，SrTiO 3，LaLuO 3，BST，PZT，CCTO。
需要说明的是，绝缘层的材料包括硅的氧化物，硅的氮化物，金属的氧化物，金属的氮化物等，例如二氧化硅，氮化硅，氧化铝，氮化铝，氧化铪，氧化锆，氧化锌，氧化钛，氧化钇，氧化镧，硅酸铪，铝酸镧，镥酸镧，钛酸钡，钛酸锶，钛酸锶钡，钛酸铜钙，锆钛酸铅等。绝缘层可以是一层，也可以是两层或多层。具体材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。
又例如，导电层的沉积方法包括ALD、PVD、有机金属化学气相沉积、蒸镀、电镀等。导电层的导电材料可以是重掺杂多晶硅，碳基材料，或者是铝、钨、铜等各类金属，也可以是氮化钛等低电阻率的化合物，或者是上述几种导电材料的组合。导电层可以包括以下至少一层：重掺杂多晶硅层、碳基材料层、金属层和氮化钛层。
本领域普通技术人员可以意识到，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特 征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。
此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所申请的内容。

Claims (13)

  1. 一种半导体结构，其特征在于，包括：
    衬底，包括相对设置的上表面和下表面；
    至少一个沟槽结构，设置于所述衬底，并自所述上表面向下形成；
    其中，所述沟槽结构在所述上表面的投影形成曲线型或者折线型的第一图案，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。
  2. 根据权利要求1所述的半导体结构，其特征在于，奇数位的第二图案能够通过旋转得到偶数位的第二图案，或者，偶数位的第二图案能够通过旋转得到奇数位的第二图案。
  3. 根据权利要求1或2所述的半导体结构，其特征在于，所述至少一个沟槽结构中不同的沟槽结构中的所述第一图案相同或者不同。
  4. 根据权利要求1至3中任一项所述的半导体结构，其特征在于，所述半导体结构用于制备高表面积、低占地面积的结构。
  5. 根据权利要求1至4中任一项所述的半导体结构，其特征在于，所述半导体结构用于制备储能器件和/或传感器，其中，所述储能器件和/或传感器包括设置于所述沟槽结构内的至少一个导电层和至少一个电介质层，且所述至少一个导电层和所述至少一个电介质层形成导电层与电介质层彼此相邻的结构。
  6. 一种半导体结构的制作方法，其特征在于，包括：
    提供衬底，所述衬底包括相对设置的上表面和下表面；
    基于曲线型或者折线型的第一图案，在所述衬底上刻蚀至少一个沟槽结构，所述沟槽结构自所述上表面向下进入所述衬底，其中，所述第一图案包括彼此相邻的n个第二图案，所述n个第二图案中奇数位的第二图案相同，且偶数位的第二图案相同，n为正整数。
  7. 根据权利要求6所述的制作方法，其特征在于，在刻蚀所述至少一个沟槽结构之前，所述方法还包括：
    提供长度为L且宽度为W的直线型沟槽图案，L和W为正数；
    将所述直线型沟槽图案分割为彼此相邻的n个矩形图案，其中，所述矩形图案在第一方向上具有长度为L/n的第一长边和第二长边，所述矩形图案在第二方向上具有宽度为W的两个宽边，所述第一方向与所述第二方向垂 直；
    将所述n个矩形图案中奇数位的所述矩形图案按照第一分割线分割为两个第一子图案，所述两个第一子图案分别包括所述第一长边和所述第二长边，且所述第一分割线连接所述第一长边的两个端点；
    将所述两个第一子图案的长边重合，以形成N1个第一基础图案，N1为正整数；
    将所述n个矩形图案中偶数位的所述矩形图案按照第二分割线分割为两个第二子图案，所述两个第二子图案分别包括所述第一长边和所述第二长边，且所述第二分割线连接所述第二长边的两个端点；
    将所述两个第二子图案的长边重合，以形成N2个第二基础图案，N2为正整数；
    将所述N1个第一基础图案和所述N2个第二基础图案进行组合，以形成所述第一图案，N1与N2的和为n。
  8. 根据权利要求7所述的制作方法，其特征在于，在刻蚀所述至少一个沟槽结构之前，所述方法还包括：
    去除所述第一图案中首尾两端的尖角。
  9. 根据权利要求8所述的制作方法，其特征在于，所述去除所述第一图案中首尾两端的尖角，包括：
    去除所述第一图案中首尾两端的小于90度的尖角。
  10. 根据权利要求7至9中任一项所述的制作方法，其特征在于，所述第一分割线和/或所述第二分割线为至少一条曲线和/或至少一条折线。
  11. 根据权利要求7至10中任一项所述的制作方法，其特征在于，所述第一分割线和所述第二分割线以所述直线型沟槽图案的轴线为对称轴对称。
  12. 根据权利要求11所述的制作方法，其特征在于，所述第一基础图案能够通过旋转得到所述第二基础图案，或者，所述第二基础图案能够通过旋转得到所述第一基础图案。
  13. 根据权利要求6至12中任一项所述的制作方法，其特征在于，所述基于曲线型或者折线型的第一图案，在所述衬底上刻蚀至少一个沟槽结构，包括：
    基于所述第一图案，利用深反应离子刻蚀在所述衬底上刻蚀所述至少一 个沟槽结构。
PCT/CN2019/077180 2019-03-06 2019-03-06 半导体结构及其制作方法 WO2020177098A1 (zh)

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