WO2020172959A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2020172959A1
WO2020172959A1 PCT/CN2019/082419 CN2019082419W WO2020172959A1 WO 2020172959 A1 WO2020172959 A1 WO 2020172959A1 CN 2019082419 W CN2019082419 W CN 2019082419W WO 2020172959 A1 WO2020172959 A1 WO 2020172959A1
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layer
source
drain electrodes
gate insulating
array substrate
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French (fr)
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吴伟
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the invention relates to the field of display, in particular to an array substrate, a manufacturing method thereof, and a display device.
  • Liquid Crystal Display has many advantages such as thin body, power saving, and no radiation, and has been widely used, such as: mobile phones, personal digital assistants (PDA), digital cameras, computer screens or notebooks Computer screen, etc.
  • PDA personal digital assistants
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • OLED organic electroluminescence display
  • the operating temperature is wide, the volume is light and thin, the response speed is fast, and it is easy to achieve color display and large screen display, easy to achieve matching with integrated circuit driver, easy to achieve flexible display and other advantages, so it has broad application prospects.
  • OLED can be divided into passive matrix OLED (Passive Matrix Organic Light-Emitting Diode, PMOLED for short) and Active Matrix OLED (Active Matrix Organic Light-Emitting Diode, AMOLED for short) two categories, namely direct addressing and thin film transistor matrix addressing.
  • PMOLED Passive Matrix Organic Light-Emitting Diode
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • AMOLED has pixels arranged in an array, is an active display type, has high luminous efficiency, and is generally used as a high-definition large-size display device.
  • Thin Film Transistor is currently the main driving element in liquid crystal display devices and active matrix OLED display devices, and is directly related to the development direction of high-performance flat panel display devices.
  • Thin film transistors have a variety of structures, and there are also a variety of materials for preparing thin film transistors with corresponding structures.
  • Amorphous silicon (a-Si) is a relatively common material.
  • Indium gallium zinc oxide Indium Gallium Metal oxide materials represented by Zinc Oxide (IGZO for short) have a mobility of more than 10 cm2/(Vs), and the preparation of corresponding thin film transistors has good compatibility with the existing a-Si semiconductor-driven production line. It quickly became the focus of research and development in the display field.
  • IGZO TFT Compared with traditional a-Si TFT, IGZO TFT has the following advantages:
  • the resolution of the IGZO TFT display backplane can be a-Si More than twice that of TFT, the carrier concentration in the IGZO material is high, and the mobility is large, which can reduce the volume of TFT and ensure the improvement of resolution;
  • the leakage current is less than 1pA; the driving frequency is reduced from the original 30-50Hz to 2-5Hz. Through special technology, it can even reach 1Hz. Although the number of TFT driving is reduced, the alignment of the liquid crystal molecules can still be maintained.
  • the high mobility of the IGZO semiconductor material enables a smaller size TFT to provide sufficient charging capacity and a higher capacitance value, and it improves the LCD panel
  • IGZO as the semiconductor active layer of the TFT generally adopts an etching barrier type. Due to the existence of an etching barrier layer (Etch Stop Layer, ESL), the etching process of the source and drain electrodes, the etching barrier layer can effectively protect IGZO from being exposed to Influence, to ensure that TFT has excellent semiconductor characteristics.
  • ESL etch Stop Layer
  • the preparation process of ESL-type IGZO TFT is more complicated and requires six yellow light processes, which is not conducive to reducing costs. Therefore, the industry generally pursues back channel etching with fewer photomask processes, lower costs, and a high degree of lean device.
  • Back Channel Etch, BCE Back Channel Etch
  • the purpose of the present invention is to provide an array substrate, a manufacturing method thereof, and a display device to solve the problem of oxidation and other damage to the source and drain electrodes caused by the protective layer in the prior art, thereby resulting in the combination between the protective layer and the source and drain electrode layers
  • the force difference promotes problems such as the deterioration of the stability of the indium gallium zinc oxide thin film transistor.
  • the present invention provides an array substrate, which includes a gate insulating layer, an active layer, source and drain electrodes, a first protective layer, and a second protective layer.
  • the active layer and the source and drain electrodes are both provided on the gate insulating layer, and the source and drain electrodes are connected to the active layer.
  • the first protective layer is provided on the gate insulating layer and the active layer.
  • the second protection layer is provided on the source and drain electrodes and the first protection layer.
  • the array substrate further includes a base, a gate, and a pixel electrode.
  • the gate is provided on the substrate, and the gate insulating layer is provided on the substrate and covers the gate.
  • the pixel electrode is arranged on the second protection layer and connected to the source and drain electrodes.
  • the present invention also provides a manufacturing method of the array substrate as described above, which includes the following steps:
  • the gate insulating layer is formed.
  • An active layer is formed on the gate insulating layer.
  • Source and drain electrodes are formed on the gate insulating layer, the source and drain electrodes are provided with a photoresist layer, and the source and drain electrodes are connected to the active layer.
  • a first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer.
  • a second protection layer is formed on the first protection layer and the source and drain electrodes.
  • the step of forming the source and drain electrodes includes: depositing a metal layer on the active layer, coating a photoresist layer on the metal layer, patterning the photoresist layer, and then wet Method etching etches the metal layer to form the source and drain electrodes, and excess photoresist layers remain on the source and drain electrodes.
  • the step of removing the photoresist layer and the first protective layer on the photoresist layer includes: removing the photoresist layer and the photoresist layer on the source and drain electrodes by a liquid phase lift-off method The first protective layer is peeled off.
  • a gate is formed on the substrate.
  • Forming a pixel electrode forming a pixel electrode on the second protective layer, and the pixel electrode is connected to the source and drain electrodes.
  • the gate insulating layer is formed.
  • An active layer and source and drain electrodes are formed on the gate insulating layer, and the source and drain electrodes are provided with a photoresist layer.
  • a first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer.
  • a second protection layer is formed on the first protection layer and the source and drain electrodes.
  • a metal oxide layer is formed on the gate insulating layer.
  • a metal layer is deposited on the metal oxide layer.
  • the step of removing the photoresist layer and the first protective layer on the photoresist layer includes: removing the photoresist layer and the photoresist layer on the source and drain electrodes by a liquid phase lift-off method The first protective layer is peeled off.
  • a gate is formed on the substrate.
  • Forming a pixel electrode forming a pixel electrode on the second protective layer, and the pixel electrode is connected to the source and drain electrodes.
  • the present invention also provides a display device, which includes the above-mentioned array substrate.
  • the array substrate includes a gate insulating layer, an active layer, source and drain electrodes, a first protective layer, and a second protective layer.
  • the active layer and the source and drain electrodes are both provided on the gate insulating layer, and the source and drain electrodes are connected to the active layer.
  • the first protective layer is provided on the gate insulating layer and the active layer.
  • the second protection layer is provided on the source and drain electrodes and the first protection layer.
  • the array substrate further includes a base, a gate, and a pixel electrode.
  • the gate is provided on the substrate, and the gate insulating layer is provided on the substrate and covers the gate.
  • the pixel electrode is arranged on the second protection layer and connected to the source and drain electrodes.
  • the array substrate provided in the present invention realizes two functions of passivating the active layer and covering the protective metal layer by depositing two protective layers.
  • the active layer is passivated by the first protective layer, and the source and drain electrodes are covered and protected by the second protective layer.
  • the present invention also provides a manufacturing method of the array substrate. In the manufacturing method, there is no need to use oxygen plasma bombardment to passivate the active layer, and only two protective layers need to be deposited separately without causing damage to the source and drain electrodes. Damage such as oxidation increases the bonding force between the protective layer and the source and drain electrode layers, so that problems such as bulging and falling off will not occur, improving the production yield and stability of the product, and enhancing the user experience.
  • FIG. 1 is a schematic diagram of a layered structure of an array substrate in Embodiment 1 or 2 of the present invention
  • FIG. 2 is a schematic flow chart of the manufacturing method of the array substrate in Embodiment 1 of the present invention.
  • FIG. 3 is a schematic flowchart of a manufacturing method of an array substrate in Embodiment 2 of the invention.
  • the part When some part is described as being “on” another part, the part may be directly placed on the other part; there may also be an intermediate part on which the part is placed, And the middle part is placed on another part.
  • a component When a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is indirectly “mounted to” or “connected to” through an intermediate component To" another part.
  • an embodiment of the present invention provides an array substrate 100.
  • the array substrate 100 includes a gate insulating layer 3, an active layer 4, source and drain electrodes 5, a first protective layer 6 and a second protective layer. 7.
  • the gate insulating layer 3 may be made of silicon oxide, silicon nitride, aluminum oxide and other materials.
  • the active layer 4 and the source and drain electrodes 5 are provided on the gate insulating layer 3, and the source and drain electrodes 5 are located at both ends of the active layer 4 and are connected to the active layer 4 .
  • the material of the active layer 4 is metal oxide, and the metal oxide is indium gallium zinc oxide.
  • the source and drain electrodes 5 are made of metal, and the metal is aluminum or copper.
  • the first protective layer 6 is provided on the gate insulating layer 3 and the active layer 4 to passivate and protect the active layer 4.
  • the second protection layer 7 is disposed on the source and drain electrodes 5 and the first protection layer 6 to cover and protect the source and drain electrodes 5.
  • the array substrate 100 further includes a base 1, a gate 2 and a pixel electrode 8.
  • the substrate 1 may be a glass substrate 1, a flexible substrate 1, and the like.
  • the gate 2 is provided on the substrate 1, the gate insulating layer 3 is provided on the substrate 1 and covers the gate 2, and the gate 2 may be molybdenum, aluminum, copper, silver, etc. Any one type of metal or an alloy of two or more types.
  • the pixel electrode 8 is disposed on the second protection layer 7 and connected to the source and drain electrodes 5.
  • the manufacturing method is as shown in FIG. 2.
  • the specific manufacturing steps include:
  • a substrate 1 is provided.
  • the substrate 1 may be a glass substrate 1, a flexible substrate 1, etc.
  • Step S102) Forming a gate 2 A gate 2 is formed on the substrate 1.
  • the material of the gate 2 can be any one or a combination of two or more of molybdenum, aluminum, copper, silver, etc. Alloy.
  • Step S103) forming a gate insulating layer 3 a gate insulating layer 3 is formed on the base, while the gate insulating layer 3 covers the gate 2, and the material of the gate insulating layer 3 can be It is silicon oxide, silicon nitride, aluminum oxide, etc.
  • Step S105) forming source and drain electrodes 5 deposit a metal layer on the gate insulating layer 3, and the metal layer simultaneously covers the active layer 4.
  • the material of the metal layer may be one of aluminum or copper.
  • a photoresist layer is coated on the metal layer, and the photoresist layer is patterned by exposure and development.
  • the photoresist layer is an insulating material.
  • the metal layer is etched by wet etching to form the source and drain electrodes 5.
  • the source and drain electrodes 5 are located at both ends of the active layer 4 and are connected to the active layer 4. An excess photoresist layer remains on the source and drain electrodes 5.
  • Step S106) forming a first protective layer 6 depositing a first protective layer 6 on the gate insulating layer 3, the active layer 4 and the photoresist layer by a chemical vapor deposition method.
  • Step S107) Remove the photoresist layer and the first protective layer 6 on the photoresist layer: remove the photoresist layer on the source and drain electrodes 5 and the photoresist layer on the photoresist layer by a liquid phase lift-off method.
  • the first protective layer 6 is peeled off.
  • Step S108) forming a second protective layer 7 forming a second protective layer 7: forming a second protective layer 7 on the first protective layer 6 and the source and drain electrodes 5 by chemical vapor deposition, and then patterning the second protective layer 7 .
  • Step S109) forming a pixel electrode 8 forming a pixel electrode 8 on the second protection layer 7, and the pixel electrode 8 is connected to the source and drain electrodes 5.
  • An embodiment of the present invention also provides a display device (not shown), and the display device includes the array substrate 100 described above.
  • the display device may be any product or component with a display function, such as a display, a mobile phone, a tablet computer, a notebook computer, and a television.
  • an array substrate 100 and a manufacturing method thereof are provided.
  • Two protective layers are deposited on the array substrate 100, wherein the active layer 4 is passivated by the first protective layer 6 and the source and drain electrodes 5 are covered and protected by the second protective layer 7.
  • the active layer 4 is passivated by the first protective layer 6 and the source and drain electrodes 5 are covered and protected by the second protective layer 7.
  • oxygen plasma bombardment to passivate the active layer 4
  • only two protective layers are deposited separately, which will not cause damage to the source and drain electrodes 5 such as oxidation, and increase the protective layer and the source and drain electrodes 5
  • the bonding force between the layers prevents problems such as bulging and falling off, improves the production yield and stability of the product, and enhances the user experience.
  • an embodiment of the present invention provides an array substrate 100.
  • the array substrate 100 includes a gate insulating layer 3, an active layer 4, source and drain electrodes 5, a first protective layer 6 and a second protective layer. 7.
  • the gate insulating layer 3 may be made of silicon oxide, silicon nitride, aluminum oxide and other materials.
  • the active layer 4 and the source and drain electrodes 5 are provided on the gate insulating layer 3, and the source and drain electrodes 5 are located at both ends of the active layer 4 and are connected to the active layer 4 .
  • the material of the active layer 4 is metal oxide, and the metal oxide is indium gallium zinc oxide.
  • the source and drain electrodes 5 are made of metal, and the metal is aluminum or copper.
  • the first protective layer 6 is provided on the gate insulating layer 3 and the active layer 4 to passivate and protect the active layer 4.
  • the second protection layer 7 is disposed on the source and drain electrodes 5 and the first protection layer 6 to cover and protect the source and drain electrodes 5.
  • the array substrate 100 further includes a base 1, a gate 2 and a pixel electrode 8.
  • the substrate 1 may be a glass substrate 1, a flexible substrate 1, and the like.
  • the gate 2 is provided on the substrate 1, the gate insulating layer 3 is provided on the substrate 1 and covers the gate 2, and the gate 2 may be molybdenum, aluminum, copper, silver, etc. Any one type of metal or an alloy of two or more types.
  • the pixel electrode 8 is disposed on the second protection layer 7 and connected to the source and drain electrodes 5.
  • the substrate 1 may be a glass substrate 1, a flexible substrate 1, and the like.
  • Step S202) forming a gate 2 forming a gate 2 on the substrate 1.
  • the material of the gate 2 can be any one or a combination of two or more of molybdenum, aluminum, copper, silver, etc. Alloy.
  • Step S203) forming a gate insulating layer 3 forming a gate insulating layer 3 on the substrate 1, while the gate insulating layer 3 covers the gate 2, and the material of the gate insulating layer 3 It can be silicon oxide, silicon nitride, aluminum oxide, etc.
  • Step S204) forming the active layer 4 and the source and drain electrodes 5 deposit a metal oxide layer on the gate insulating layer 3, and the metal oxide is indium gallium zinc oxide.
  • a metal layer is deposited on the metal oxide layer, and the metal can be one of aluminum or copper.
  • a photoresist layer is coated on the metal layer, and the photoresist layer is patterned by exposure and development. The photoresist layer is an insulating material.
  • the metal oxide layer and the metal layer are patterned under a photomask process, the metal oxide layer forms the active layer 4, and the metal layer forms the source and drain electrodes 5.
  • the source and drain electrodes 5 are located at both ends of the active layer 4 and are connected to the active layer 4. An excess photoresist layer remains on the source and drain electrodes 5.
  • Step S205) forming a first protective layer 6 depositing a first protective layer 6 on the gate insulating layer 3, the active layer 4 and the photoresist layer by a chemical vapor deposition method.
  • Step S206) Remove the photoresist layer and the first protection layer 6 on the photoresist layer: remove the photoresist layer on the source and drain electrodes 5 and the photoresist layer on the photoresist layer by a liquid phase lift-off method.
  • the first protective layer 6 is peeled off.
  • Step S208) forming a pixel electrode 8 forming a pixel electrode 8 on the second protection layer 7, and the pixel electrode 8 is connected to the source and drain electrodes 5.
  • the metal oxide layer and the metal layer are simultaneously etched under a photomask process through a halftone mask method, and the active layer 4 and the source leakage are generated simultaneously Pole 5, compared with the manufacturing method in Example 1, the preparation steps are reduced, and the preparation process is simpler.
  • An embodiment of the present invention also provides a display device (not shown), and the display device includes the array substrate 100 described above.
  • the display device may be any product or component with a display function, such as a display, a mobile phone, a tablet computer, a notebook computer, and a television.
  • an array substrate 100 and a manufacturing method thereof are provided.
  • Two protective layers are deposited on the array substrate 100, wherein the active layer 4 is passivated by the first protective layer 6 and the source and drain electrodes 5 are covered and protected by the second protective layer 7.
  • the active layer 4 is passivated by the first protective layer 6 and the source and drain electrodes 5 are covered and protected by the second protective layer 7.
  • oxygen plasma bombardment to passivate the active layer 4
  • only two protective layers are deposited separately, which will not cause damage to the source and drain electrodes 5 such as oxidation, and increase the protective layer and the source and drain electrodes 5.
  • the bonding force between the layers prevents problems such as bulging and falling off, improves the production yield and stability of the product, and enhances the user experience.

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Abstract

本发明提供了一种阵列基板及其制作方法、显示装置。所述阵列基板包括栅极绝缘层、有源层、源漏电极、第一保护层以及第二保护层。所述有源层和所述源漏电极均设于所述栅极绝缘层上，所述源漏电极连接至所述有源层。所述第一保护层设于所述栅极绝缘层和所述有源层上。所述第二保护层设于所述源漏电极和所述第一保护层上。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明涉及显示领域，特别是一种阵列基板及其制作方法、显示装置。
 背景技术
液晶显示装置（Liquid Crystal Display，简称LCD）具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本电脑屏幕等。
有机发光二极管（Organic Light-Emitting Diode，简称OLED）显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED（Passive Matrix Organic Light-Emitting Diode，简称PMOLED）和有源矩阵型OLED（Active Matrix Organic Light-Emitting Diode，简称AMOLED）两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管（Thin Film Transistor，简称TFT）是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅（a-Si）材料是比较常见的一种。
随着液晶显示装置和OLED显示装置向着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/（Vs）左右的迁移率已经无法满足要求，以铟镓锌氧化物（Indium Gallium Zinc Oxide ，简称IGZO）为代表的金属氧化物材料具备超过10cm2/（Vs）以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡型，由于有刻蚀阻挡层（Etch Stop Layer，ESL）存在，源漏电极的蚀刻过程，刻蚀阻挡层可以有效的保护IGZO不受到影响，保证TFT具有优异的半导体特性。但是ESL型的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求光罩工艺更少、成本更低、器件精益化程度高的背沟道蚀刻（Back Channel Etch，BCE）型的IGZO TFT的开发。
但现有技术中的BCE型IGZO TFT因为背沟道受到蚀刻等工艺的损伤，需要在后续的保护层的沉积过程中利用氧等离子体轰击将背沟道钝化，而这一工艺同时会对IGZO TFT中原材料为金属的源漏电极造成氧化等损伤，从而导致保护层与源漏电极层之间的结合力差，出现膜层鼓包脱落等问题，促使IGZO TFT的稳定性变差。
 技术问题
本发明的目的是提供一种阵列基板及其制作方法和显示装置，以解决现有技术中因保护层而对源漏电极造成氧化等损伤，从而导致保护层与源漏电极层之间的结合力差，促使铟镓锌氧化物薄膜晶体管的稳定性变差等问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，其包括栅极绝缘层、有源层、源漏电极、第一保护层以及第二保护层。所述有源层和所述源漏电极均设于所述栅极绝缘层上，所述源漏电极连接至所述有源层。所述第一保护层设于所述栅极绝缘层和所述有源层上。所述第二保护层设于所述源漏电极和所述第一保护层上。
进一步地，所述阵列基板还包括基底、栅极以及像素电极。所述栅极设于所述基底上，所述栅极绝缘层设于所述基底上，且覆盖所述栅极。所述像素电极设于所述第二保护层上，并与所述源漏电极连接。
本发明还提供一种如上所述的阵列基板的制作方法，其包括以下步骤：
形成栅极绝缘层。
形成有源层于所述栅极绝缘层上。
形成源漏电极于所述栅极绝缘层上，所述源漏电极上具有光阻层，且所述源漏电极连接至所述有源层。
形成第一保护层于所述栅极绝缘层、所述有源层和所述光阻层上。
去除所述光阻层以及光阻层上的所述第一保护层。
形成第二保护层于所述第一保护层和所述源漏电极上。
进一步地，在形成源漏电极步骤中包括：在所述有源层上沉积一金属层，在所述金属层上涂布一光阻层，并将所述光阻层图案化，然后通过湿法蚀刻将所述金属层蚀刻，形成所述源漏电极，所述源漏电极上残留有多余的光阻层。
进一步地，在去除所述光阻层以及光阻层上的所述第一保护层步骤中包括：通过液相剥离法将所述源漏电极上的所述光阻层以及所述光阻层上的所述第一保护层剥离。
进一步地，在所述制备栅极绝缘层步骤前还包括以下步骤：
提供一基底。在所述基底上形成栅极。
在形成第二保护层步骤后还包括以下步骤：
形成像素电极：在所述第二保护层上形成像素电极，且所述像素电极与所述源漏电极连接。
本发明还提供另一种如上所述的阵列基板的制作方法，其包括以下步骤：
形成栅极绝缘层。
形成有源层和源漏电极于所述栅极绝缘层上，所述源漏电极上具有光阻层。
形成第一保护层于所述栅极绝缘层、所述有源层和所述光阻层上。
去除所述光阻层以及光阻层上的所述第一保护层。
形成第二保护层于所述第一保护层和所述源漏电极上。
进一步地，在形成有源层和源漏电极步骤中包括：
在所述栅极绝缘层形成一金属氧化物层。
在所述金属氧化物层上沉积一金属层。
在所述金属层上涂布一光阻层，并将所述光阻层图案化，然后通过半色调掩膜法同时将所述金属氧化物层和所述金属层图案化，形成所述有源层和所述源漏电极，所述源漏电极上残留有多余的光阻层。
进一步地，在去除所述光阻层以及光阻层上的所述第一保护层步骤中包括：通过液相剥离法将所述源漏电极上的所述光阻层以及所述光阻层上的所述第一保护层剥离。
进一步地，在所述制备栅极绝缘层步骤前还包括一下步骤：
提供一基底。在所述基底上形成栅极。
在形成第二保护层步骤后还包括以下步骤：
形成像素电极：在所述第二保护层上形成像素电极，且所述像素电极与所述源漏电极连接。
本发明还提供一种显示装置，其包括如上所述的阵列基板。
进一步地，所述阵列基板包括栅极绝缘层、有源层、源漏电极、第一保护层以及第二保护层。所述有源层和所述源漏电极均设于所述栅极绝缘层上，所述源漏电极连接至所述有源层。所述第一保护层设于所述栅极绝缘层和所述有源层上。所述第二保护层设于所述源漏电极和所述第一保护层上。
进一步地，所述阵列基板还包括基底、栅极以及像素电极。所述栅极设于所述基底上，所述栅极绝缘层设于所述基底上，且覆盖所述栅极。所述像素电极设于所述第二保护层上，并与所述源漏电极连接。
 有益效果
本发明的优点是：本发明中提供的一种阵列基板，其通过沉积两层保护层分别实现钝化有源层和覆盖保护金属层两种功能。其中，通过第一保护层实现钝化有源层，再通过第二保护层实现覆盖保护源漏电极。在本发明中还提供了所述阵列基板的制作方法，在其制作方法中无需利用氧等离子体轰击使其有源层钝化，只需分别沉积两层保护层，不会对源漏电极造成氧化等损伤，增加了保护层与源漏电极层之间的结合力，从而不会出现鼓包脱落等问题，提高产品的生产良率以及稳定性，提升用户体验感。
 附图说明
图1为本发明实施例1或2中阵列基板的层状结构示意图；
图2为本发明实施例1中阵列基板制作方法的流程示意图；
图3为本发明实施例2中阵列基板制作方法的流程示意图。
图中部件表示如下：
阵列基板                   100；
基底                            1；栅极                            2；
栅极绝缘层     3；有源层                       4；
源漏电极                   5；第一保护层              6；
第二保护层     7；像素电极                   8。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选实施例，证明本发明可以实施，所述发明实施例可以向本领域中的技术人员完整介绍本发明，使其技术内容更加清楚和便于理解。本发明可以通过许多不同形式的发明实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。附图所示的每一部件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。为了使图示更清晰，附图中有些地方适当夸大了部件的厚度。
此外，以下各发明实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定发明实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
当某些部件被描述为“在”另一部件“上”时，所述部件可以直接置于所述另一部件上；也可以存在一中间部件，所述部件置于所述中间部件上，且所述中间部件置于另一部件上。当一个部件被描述为“安装至”或“连接至”另一部件时，二者可以理解为直接“安装”或“连接”，或者一个部件通过一中间部件间接“安装至”、或“连接至”另一个部件。
实施例1
如图1所示，本发明实施例中提供一种阵列基板100，所述阵列基板100包括栅极绝缘层3、有源层4、源漏电极5、第一保护层6以及第二保护层7。
所述栅极绝缘层3可以为氧化硅、氮化硅、氧化铝等材料。所述有源层4和所述源漏电极5设于所述栅极绝缘层3上，并且所述源漏电极5位于所述有源层4的两端并与所述有源层4连接。其中，所述有源层4的材料为金属氧化物，所述金属氧化物为铟镓锌氧化物。所述源漏电极5的原材料为金属，所述金属为铝或铜。所述第一保护层6设于所述栅极绝缘层3和所述有源层4上，用于钝化并保护所述有源层4。所述第二保护层7设于所述源漏电极5和所述第一保护层6上，用于覆盖保护所述源漏电极5。
所述阵列基板100还包括基底1、栅极2以及像素电极8。所述基底1可以为玻璃基底1、柔性基底1等。所述栅极2设于所述基底1上，所述栅极绝缘层3设于所述基底1上且覆盖所述栅极2，所述栅极2可以为钼、铝、铜、银等中的任一种金属或两种以上的组成的合金。所述像素电极8设于所述第二保护层7上，并与所述源漏电极5连接。
本发明实施中还提供一种如上所述的阵列基板100的制作方法，所述制作方法的流程如图2所示，具体制作步骤包括：
步骤S101）提供一基底1，所述基底1可以为玻璃基底1、柔性基底1等。
步骤S102）形成栅极2：在所述基底1上形成一栅极2，所述栅极2的材料可以为钼、铝、铜、银等中的任意一种金属或两种以上组合而成的合金。
步骤S103）形成栅极绝缘层3：在所述基地上形成一栅极绝缘层3，同时所述栅极绝缘层3覆盖在所述栅极2上，所述栅极绝缘层3的材料可以为氧化硅、氮化硅、氧化铝等。
步骤S104）形成有源层4上：在所述栅极绝缘层3上沉积一金属氧化物层，所述金属氧化物层的材料为铟镓锌氧化物。然后将所述金属氧化物图案化，形成所述有源层4。
步骤S105）形成源漏电极5：在所述栅极绝缘层3上沉积一金属层，所述金属层同时覆盖在所述有源层4上。所述金属层的材料可以为铝或铜中的一种。然后在所述金属层上涂布一光阻层，并通过曝光、显影将所述光阻层图案化，所述光阻层为绝缘材料。最后通过湿法蚀刻将所述金属层蚀刻，形成所述源漏电极5。所述源漏电极5位于所述有源层4的两端，并与所述有源层4连接。所述源漏电极5上残留有多余的光阻层。
步骤S106）形成第一保护层6：通过化学气相沉积法在所述栅极绝缘层3、所述有源层4和所述光阻层上沉积一第一保护层6。
步骤S107）去除所述光阻层以及光阻层上的所述第一保护层6：通过液相剥离法将所述源漏电极5上的所述光阻层以及所述光阻层上的第一保护层6剥离。
步骤S108）形成第二保护层7：通过化学气相沉积法在所述第一保护层6和所述源漏电极5上形成一第二保护层7，然后将所述第二保护层7图案化。
步骤S109）形成像素电极8：在所述第二保护层7上形成像素电极8，且所述像素电极8与所述源漏电极5连接。
本发明实施例中还提供一种显示装置（图未示），所述显示装置包括以上所述的阵列基板100。所述显示装置可以为显示器、手机、平板电脑、笔记本电脑、电视机等任何具有显示功能的产品或者部件。
在本发明实施例中，提供了一种阵列基板100以及其制作方法。所述阵列基板100上沉积了两层保护层，其中，通过第一保护层6实现钝化有源层4，再通过第二保护层7实现覆盖保护源漏电极5。在其制作方法中无需利用氧等离子体轰击使其有源层4钝化，只需分别沉积两层保护层，不会对源漏电极5造成氧化等损伤，增加了保护层与源漏电极5层之间的结合力，从而不会出现鼓包脱落等问题，提高产品的生产良率以及稳定性，提升用户体验感。
实施例2
如图1所示，本发明实施例中提供一种阵列基板100，所述阵列基板100包括栅极绝缘层3、有源层4、源漏电极5、第一保护层6以及第二保护层7。
所述栅极绝缘层3可以为氧化硅、氮化硅、氧化铝等材料。所述有源层4和所述源漏电极5设于所述栅极绝缘层3上，并且所述源漏电极5位于所述有源层4的两端并与所述有源层4连接。其中，所述有源层4的材料为金属氧化物，所述金属氧化物为铟镓锌氧化物。所述源漏电极5的原材料为金属，所述金属为铝或铜。所述第一保护层6设于所述栅极绝缘层3和所述有源层4上，用于钝化并保护所述有源层4。所述第二保护层7设于所述源漏电极5和所述第一保护层6上，用于覆盖保护所述源漏电极5。
所述阵列基板100还包括基底1、栅极2以及像素电极8。所述基底1可以为玻璃基底1、柔性基底1等。所述栅极2设于所述基底1上，所述栅极绝缘层3设于所述基底1上且覆盖所述栅极2，所述栅极2可以为钼、铝、铜、银等中的任一种金属或两种以上的组成的合金。所述像素电极8设于所述第二保护层7上，并与所述源漏电极5连接。
本发明实施中还提供一种如上所述的阵列基板100的制作方法，所述制作方法的流程如图3所示，具体制作步骤包括：
步骤S201）提供一基底1，所述基底1可以为玻璃基底1、柔性基底1等。
步骤S202）形成栅极2：在所述基底1上形成一栅极2，所述栅极2的材料可以为钼、铝、铜、银等中的任意一种金属或两种以上组合而成的合金。
步骤S203）形成栅极绝缘层3：在所述基底1上形成一栅极绝缘层3，同时所述栅极绝缘层3覆盖在所述栅极2上，所述栅极绝缘层3的材料可以为氧化硅、氮化硅、氧化铝等。
步骤S204）形成有源层4和源漏电极5：在所述栅极绝缘层3上沉积一金属氧化物层，所述金属氧化物为铟镓锌氧化物。再在所述金属氧化物层上沉积一金属层，所述金属可以为铝或铜中的一种。然后在所述金属层上涂布一光阻层，并通过曝光、显影将所述光阻层图案化，所述光阻层为绝缘材料。最后通过半色调掩膜法（Half-tone Mask）在一道光罩程序下将所述金属氧化物层和所述金属层图案化，所述金属氧化物层形成所述有源层4，所述金属层形成所述源漏电极5。所述源漏电极5位于所述有源层4的两端，并与所述有源层4连接。所述源漏电极5上残留有多余的光阻层。
步骤S205）形成第一保护层6：通过化学气相沉积法在所述栅极绝缘层3、所述有源层4和所述光阻层上沉积一第一保护层6。
步骤S206）去除所述光阻层以及光阻层上的所述第一保护层6：通过液相剥离法将所述源漏电极5上的所述光阻层以及所述光阻层上的第一保护层6剥离。
步骤S207）形成第二保护层7：通过化学气相沉积法在所述第一保护层6和所述源漏电极5上形成一第二保护层7，然后将所述第二保护层7图案化。
步骤S208）形成像素电极8：在所述第二保护层7上形成像素电极8，且所述像素电极8与所述源漏电极5连接。
本发明实施例中提供的制作方法，通过半色调掩膜法在一道光罩程序下将所述金属氧化物层和所述金属层同时蚀刻，同时产生所述有源层4和所述源漏电极5，与实施例1中的制作方法相比较减少了制备步骤，制备流程更加简单。
本发明实施例中还提供一种显示装置（图未示），所述显示装置包括以上所述的阵列基板100。所述显示装置可以为显示器、手机、平板电脑、笔记本电脑、电视机等任何具有显示功能的产品或者部件。
在本发明实施例中，提供了一种阵列基板100以及其制作方法。所述阵列基板100上沉积了两层保护层，其中，通过第一保护层6实现钝化有源层4，再通过第二保护层7实现覆盖保护源漏电极5。在其制作方法中无需利用氧等离子体轰击使其有源层4钝化，只需分别沉积两层保护层，不会对源漏电极5造成氧化等损伤，增加了保护层与源漏电极5层之间的结合力，从而不会出现鼓包脱落等问题，提高产品的生产良率以及稳定性，提升用户体验感。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (13)

  1. 一种阵列基板，其包括：
    栅极绝缘层；
    有源层和源漏电极，设于所述栅极绝缘层上，所述源漏电极连接至所述有源层；
    第一保护层，设于所述栅极绝缘层和所述有源层上；以及
    第二保护层，设于所述源漏电极和所述第一保护层上。
  2. 如权利要求1所述的阵列基板，其还包括：
    基底；以及
    栅极，设于所述基底上，所述栅极绝缘层设于所述基底上且覆盖所述栅极；
    像素电极，设于所述第二保护层上，并与所述源漏电极连接。
  3. 一种如权利要求1所述的阵列基板的制作方法，其包括以下步骤：
    形成栅极绝缘层；
    形成有源层于所述栅极绝缘层上；
    形成源漏电极于所述栅极绝缘层上，所述源漏电极上具有光阻层，且所述源漏电极连接至所述有源层；
    形成第一保护层于所述栅极绝缘层、所述有源层和所述光阻层上；
    去除所述光阻层以及光阻层上的所述第一保护层；
    形成第二保护层于所述第一保护层和所述源漏电极上。
  4. 如权利要求3所述的阵列基板的制作方法，其中，在形成源漏电极步骤中包括：在所述有源层上沉积一金属层，在所述金属层上涂布一光阻层，并将所述光阻层图案化，然后通过湿法蚀刻将所述金属层蚀刻，形成所述源漏电极，所述源漏电极上残留有多余的光阻层。
  5. 如权利要求3所述的阵列基板的制作方法，其中，在去除所述光阻层以及光阻层上的所述第一保护层步骤中包括：通过液相剥离法将所述源漏电极上的所述光阻层以及所述光阻层上的所述第一保护层剥离。
  6. 如权利要求3所述的阵列基板的制作方法，其中，
    在所述制备栅极绝缘层步骤前还包括以下步骤：
    提供一基底；
    在所述基底上形成栅极；
    在形成第二保护层步骤后还包括以下步骤：
    在所述第二保护层上形成像素电极，且所述像素电极与所述源漏电极连接。
  7. 一种如权利要求1所述的阵列基板的制作方法，其包括以下步骤：
    形成栅极绝缘层；
    形成有源层和源漏电极于所述栅极绝缘层上，所述源漏电极上具有光阻层；
    形成第一保护层于所述栅极绝缘层、所述有源层和所述光阻层上；
    去除所述光阻层以及光阻层上的所述第一保护层；
    形成第二保护层于所述第一保护层和所述源漏电极上。
  8. 如权利要求7所述的阵列基板的制作方法，其中，
    在形成有源层和源漏电极步骤中包括：
    在所述栅极绝缘层形成一金属氧化物层；
    在所述金属氧化物层上沉积一金属层；
    在所述金属层上涂布一光阻层，并将所述光阻层图案化，然后通过半色调掩膜法同时将所述金属氧化物层和所述金属层图案化，形成所述有源层和所述源漏电极，所述源漏电极上残留有多余的光阻层。
  9. 如权利要求7所述的阵列基板的制作方法，其中，在去除所述光阻层以及光阻层上的所述第一保护层步骤中包括：通过液相剥离法将所述源漏电极上的所述光阻层以及所述光阻层上的所述第一保护层剥离。
  10.    如权利要求7所述的阵列基板的制作方法，其中，
    在所述制备栅极绝缘层步骤前还包括一下步骤：
    提供一基底；
    在所述基底上形成栅极；
    在形成第二保护层步骤后还包括以下步骤：
    在所述第二保护层上形成像素电极，且所述像素电极与所述源漏电极连接。
  11.    一种显示装置，其包括如权利要求1所述的阵列基板。
  12.    如权利要求11所述的显示装置，所述阵列基板包括：
    栅极绝缘层；
    有源层和源漏电极，设于所述栅极绝缘层上，所述源漏电极连接至所述有源层；
    第一保护层，设于所述栅极绝缘层和所述有源层上；以及
    第二保护层，设于所述源漏电极和所述第一保护层上。
  13.    如权利要求12所述的显示装置，所述阵列基板还包括：
    基底；以及
    栅极，设于所述基底上，所述栅极绝缘层设于所述基底上且覆盖所述栅极；
    像素电极，设于所述第二保护层上，并与所述源漏电极连接。
PCT/CN2019/082419 2019-02-26 2019-04-12 阵列基板及其制作方法、显示装置 Ceased WO2020172959A1 (zh)

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