WO2020155970A1 - 驱动电路和显示面板 - Google Patents

驱动电路和显示面板 Download PDF

Info

Publication number
WO2020155970A1
WO2020155970A1 PCT/CN2019/128751 CN2019128751W WO2020155970A1 WO 2020155970 A1 WO2020155970 A1 WO 2020155970A1 CN 2019128751 W CN2019128751 W CN 2019128751W WO 2020155970 A1 WO2020155970 A1 WO 2020155970A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
conductive film
additional conductive
area
out area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/128751
Other languages
English (en)
French (fr)
Inventor
刘忠念
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/420,134 priority Critical patent/US12276887B2/en
Publication of WO2020155970A1 publication Critical patent/WO2020155970A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This application relates to the field of display technology, and in particular to a driving circuit and a display panel.
  • a liquid crystal display usually includes at least two drive chip connections that transmit gate drive signals. Two adjacent gate drive chips are also connected by substrate wiring (Wire on Array, WOA). Each gate driving chip is respectively connected to a set of fan-out lines on the substrate, and is connected to each scan line through the fan-out lines.
  • the resistance value of the fan-out line connected to the next gate drive chip will be larger than the resistance value of the fan-out line connected to the previous gate drive chip, so that the signal between adjacent gate drive chips Inconsistent transmission causes uneven brightness of the display panel, and the display quality of the display panel is reduced.
  • the present application discloses a driving circuit, which includes: a driving circuit board; a plurality of gate driving chips connected to the driving circuit board; a connecting line connecting the driving circuit board and the gate driving chip is configured to transmit Signal to the gate driving chip; a fan-out line connected between the gate driving chip and the gate line of the display panel, and the fan-out line connected to the same gate driving chip forms a fan-out Area, the fan-out areas are arranged according to the transmission direction of the signal; and the additional conductive film provided in the fan-out area, the area of the additional conductive film provided in each fan-out area is different, according to the signal In the transmission direction, the total area of the additional conductive film overlapping with the fan-out line of each fan-out area decreases one by one.
  • the application also discloses a driving circuit, which includes a driving circuit board; a plurality of gate driving chips connected to the driving circuit board; a connecting line connecting the driving circuit board and the gate driving chip is configured to transmit Signal to the gate driving chip; a fan-out line connected between the gate driving chip and the gate line of the display panel, and the fan-out line connected to the same gate driving chip forms a fan-out Area, the fan-out areas are arranged according to the transmission direction of the signal; and an additional conductive film arranged on the first fan-out area to the penultimate fan-out area according to the signal transmission direction The area of the additional conductive film provided in each fan-out area is different.
  • the total area of the additional conductive film overlapping with the fan-out line of each fan-out area is one by one
  • the additional conductive film is set corresponding to each of the fan-out lines, and the additional conductive film provided in the same fan-out area has the same overlapping area with each of the fan-out lines; the additional conductive film is made of indium oxide Tin conductive film and metal conductive film are combined.
  • the application also discloses a display panel.
  • the display panel includes a plurality of gate lines and a driving circuit for driving the gate lines;
  • the driving circuit includes a driving circuit board; and a plurality of gates connected to the driving circuit board A pole drive chip; a connection line connecting the drive circuit board and the gate drive chip, configured to transmit signals to the gate drive chip; connected to the gate drive chip and the gate line of the display panel
  • the fan-out lines connected to the same gate drive chip form a fan-out area, the fan-out areas are arranged in line according to the signal transmission direction; and the fan-out areas are arranged in the fan-out area
  • Additional conductive film the area of the additional conductive film provided in each fan-out area is different, according to the signal transmission direction, the additional conductive film overlaps the fan-out line of each fan-out area The total area decreases one by one.
  • each fan-out area is connected by a connecting line, the connecting line itself has a certain resistance, which will have a certain impact on the signal transmission.
  • C an additional conductive film is added in the fan-out area to form a compensation capacitor to increase the time constant of the signal delay in the front fan-out area, so that the signal delay time constant of each fan-out area is equal, so that each The signal of the fan-out zone is output synchronously.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a fan-out area in an embodiment of the present application
  • FIG. 3 is a schematic diagram of an additional conductive film provided in a fan-out area according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of an additional conductive film provided in a fan-out area according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of an additional conductive film provided in a fan-out area according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a display device according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise specified, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features; “plurality” means two or more.
  • the term “comprising” and any variations thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • the signal is transmitted from the source driver chip 310, enters the fan-out line 341 through the connecting line 330, and then enters the active area (AA) in the display panel 100.
  • a display panel 100 including a substrate, multiple sets of gate lines 500, and a driving circuit 700 for driving the gate lines 500.
  • the driving circuit 700 includes a driving circuit board 600.
  • a plurality of source driving chips 310 arranged on the first side 380 of the substrate are connected to the driving circuit board 600; a plurality of gate driving chips 320 arranged on the second side 390 of the substrate are connected to the source driving chip 310 Or on the driving circuit board 600;
  • the connecting line 330 connecting the driving circuit board 600 and the gate driving chip 320 is configured to transmit signals to the gate driving chip 320; connecting the gate driving chip 320 and the gate line 500 of the display panel 100
  • the fan-out line 341, the fan-out line 341 connected to the same gate driving chip 320 forms a fan-out area 340, the fan-out areas 340 are arranged according to the signal transmission direction; and the additional conductive film 350 disposed in the fan-out area 340, each The area of the additional conductive film 350 provided in
  • the total area of the additional conductive film 350 overlapping the fan-out line 341 of each fan-out area 340 decreases one by one.
  • each C W value is calculated.
  • the only variable is C F.
  • Controlling the C F value of each fan-out area 340 can make each is equal to the signal fan-out region 340 of the delay of the time constant [tau], means for controlling the C F value is used to line the fan by adding additional conductive film 350,341 to form a capacitor, control of the additional conductive film 350 and the fan-out lines overlapping area 341 is controlled CF
  • the value of each fan-out area 340 is output synchronously, so that the grid line 500 charges the pixels uniformly, and the screen display is more uniform.
  • the substrate is the array substrate 300, the first side 380 and the second side 390 are two adjacent sides of the array substrate 300 that are perpendicular to each other, and the additional conductive film 350 is in a suspended state and is not connected to other components.
  • a display panel 100 includes a color filter substrate 200 and an array substrate 300.
  • the color filter substrate 200 includes a glass substrate 210, The resist 220 and the first conductive film 230, the color resist 220 is arranged on the glass substrate 210, and the first conductive film 230 is arranged on the color resist 220;
  • the array substrate 300 includes a source driver chip 310, a gate driver chip 320, and connecting wires 330, fan-out line 341, additional conductive film 350, insulating layer 360 and passivation layer 370;
  • the source driver chip 310 is connected to the gate driver chip 320 through the connection line 330, and the gate driver chips 320 on the same side are also connected
  • the line 330 is connected, and the fan-out line 341 connected to the same gate driving chip 320 forms a fan-out area 340.
  • the fan-out areas 340 are arranged in accordance with the signal transmission direction. Each fan-out area 340 is provided with an additional conductive film 350. The area of the additional conductive film 350 provided in the fan-out area 340 is different. According to the signal transmission direction, the total area of the additional conductive film 350 overlapping the fan-out line 341 of each fan-out area 340 decreases one by one. The film 350 is used to increase the compensation capacitance of different sizes.
  • S is the distance between the additional conductive film 350 and the fan-out line 341
  • the facing area by controlling the facing area S of the additional conductive film 350 and the fan-out line 341, different compensation capacitors C are obtained. Specifically, the facing area S of the additional conductive film 350 and the fan-out line 341 is from the first fan-out area After 340, it decreases one by one, and the supplementary capacitor C also decreases one by one from the first fan-out area 340.
  • the fan-out line 341 will cause a signal delay due to the resistance of the connecting line 330. From the calculation formula of the time constant formula ⁇ , the signal delay time constant ⁇ is affected by the resistance R and The influence of capacitance C. Because of the influence of the resistance of the connecting line 330 between each gate driving chip 320, the signal of each fan-out area 340 will be delayed. An additional conductive film 350 is provided in the fan-out area 340 to form a capacitor with the fan-out line 341 C; The length of the connecting line 330 connected to each fan-out area 340 is different, and the size of the influencing resistance R is also different.
  • each fan-out area 340 is provided with an additional conductive film 350 of different area to make the time constant ⁇ of each fan-out area 340 consistent, so that the signal is output at the same time, so that the grid line 500 charges the pixels uniformly, and the screen displays More uniform.
  • the length of the fan-out line 341 covering the part of the additional conductive film 350 is L F11
  • the length of the fan-out line 341 that does not cover the part of the additional conductive film 350 is L F12
  • L F11 + L F12 L F1
  • the capacitance of the fan-out line 341 of the film 350 includes the capacitance between the fan-out line 341 and the additional conductive film 350, and the capacitance between the fan-out line 341 and the first conductive film 230 on the color filter substrate 200 side:
  • C F11 ⁇ 0 ⁇ P ⁇ S F11 /d 2 + ⁇ 0 ⁇ L ⁇ S F11 /d 1
  • S F11 W F1 ⁇ L F11
  • ⁇ P is the dielectric constant of the insulating layer 360 and the passivation layer 370, d 2 It is the sum of the thickness of the insulating layer 360 and the passivation layer 370. Since
  • the time constant of the signal delay of a certain fan-out line 341 in the second fan-out area 340 can be calculated.
  • the only variable is the phase
  • the C value variable caused by the different lengths of the fan-out lines 341 of the two adjacent fan-out regions 340 that cover the additional conductive film 350 can be obtained by the above formula. Control the signal delay of adjacent COF traces.
  • the coverage area of the additional conductive film 350 on the first fan-out area 340 is set to be the largest, and then decreases one by one in order, so that the compensation capacitance value of each fan-out area 340 decreases sequentially, so that the signal of each fan-out area 340
  • the time constants of the delay are equal, so that the signal is output synchronously, so that the grid line 500 charges the pixels uniformly, and the screen display is more uniform.
  • the additional conductive film 350 is disposed on the first fan-out area 340 to the penultimate fan-out area 340, and the last fan-out area 340 is not provided with the additional conductive film 350.
  • the array substrate 300 includes an insulating layer 360 and a passivation layer 370.
  • the insulating layer 360 is disposed on the fan-out line 341, and the passivation layer 370 is disposed on the insulating layer 360.
  • the conductive film 350 is disposed on the passivation layer 370 corresponding to each fan-out line 341, and the additional conductive film 350 disposed in the same fan-out area 340 overlaps with each fan-out line 341 in the same area.
  • the additional conductive film 350 arranged in the same fan-out area 340 overlaps with each fan-out line 341 in the same area, so that the compensation capacitance added to each fan-out line 341 of the same fan-out area 340 is equal, and each fan-out line 341 has the same signal
  • the time constant of the delay is also equal, so that the signal of each fan-out line 341 of the same fan-out area 340 is output synchronously, so that the grid line 500 charges the pixels uniformly, and the screen display is more uniform.
  • the additional conductive film 350 is formed by combining the indium tin oxide conductive film 351 and the metal conductive film 352, and the positions of the two are not limited.
  • the additional conductive film 350 can also be disposed at the bottom of the fan-out area 340 or other positions; the additional conductive film 350 can also be an indium tin oxide conductive film 351 or a metal conductive film 352 alone.
  • the start boundary line and the end boundary line of the additional conductive film 350 provided in each fan-out area 340 are parallel and parallel to the second side 390 of the array substrate 300, and the start boundary line is parallel to The vertical distance between the end boundary lines is L.
  • the effective area of the additional conductive film 350 is increased or decreased by controlling the value of the distance L, which is convenient for production.
  • one fan-out area 340 is correspondingly provided with a whole additional conductive film 350, and the additional conductive film 350 has a trapezoidal shape.
  • a whole piece of additional conductive film 350 is directly covered, saving part of the process of processing the additional conductive film 350.
  • the shape of the additional conductive film 350 is set to a trapezoid, which reduces the ineffective area of the additional conductive film 350 and saves materials.
  • the additional conductive film 350 may also have other shapes, such as a triangle, a rectangle, an ellipse, and so on.
  • a display device 400 As shown in FIG. 6, as another embodiment of the present application, a display device 400 is disclosed.
  • the display device 400 includes the above-mentioned display panel 100, and the display panel 100 includes a gate line 500 and a driving circuit 700.
  • the technical solution of the present application can be widely used in various display panels, such as twisted nematic (TN) display panels, in-plane switching (IPS) display panels, and vertical alignment (Vertical Alignment, VA) display panels.
  • Display panels Multi-Domain Vertical Alignment (MVA) display panels, of course, can also be other types of display panels, such as Organic Light-Emitting Diode (OLED) display panels, either Apply the above scheme.
  • TN twisted nematic
  • IPS in-plane switching
  • VA Vertical Alignment
  • Display panels Multi-Domain Vertical Alignment (MVA) display panels, of course, can also be other types of display panels, such as Organic Light-Emitting Diode (OLED) display panels, either Apply the above scheme.
  • OLED Organic Light-Emitting Diode

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

公开了一种驱动电路和显示面板。驱动电路包括驱动电路板(600)；连接到驱动电路板(600)的栅极驱动芯片(320)；连接驱动电路板(600)与栅极驱动芯片(320)的连接线(330)；连接于栅极驱动芯片(320)与显示面板(100)的栅线(500)之间的扇出线(341)，与一个栅极驱动芯片(320)连接的扇出线(341)形成一个扇出区(340)；以及设置于扇出区(340)的附加导电膜(350)。

Description

驱动电路和显示面板
本申请要求于2019年01月30日提交中国专利局，申请号为CN201910089137.1，申请名称为“一种驱动电路、显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技进步，具有省电、无幅射、体积小、低耗电量、平面直角、高分辨率、画质稳定等多项优势的液晶显示器，尤其是现今各式信息产品如：手机、笔记本电脑、数字相机、液晶屏幕等产品越来越普及，也使得液晶显示器的需求量大大提升。液晶显示器中通常包括至少两个传输栅极驱动信号的驱动芯片连接。相邻的两个栅极驱动芯片之间也通过基板走线(Wire on Array，WOA)连接。每个栅极驱动芯片分别与基板上的一组扇出线相连，并通过扇出线连接至各条扫描线。
由于基板走线具有一定阻值，所以后一个栅极驱动芯片相连的扇出线的阻值会比前一个栅极驱动芯片相连的扇出线的阻值大，使得相邻栅极驱动芯片之间信号传输不一致，使得显示面板亮度不均匀，显示面板的显示品质降低。
发明内容
本申请公开了一种驱动电路，包括：驱动电路板；连接到所述驱动电路板的多个栅极驱动芯片；连接所述驱动电路板与所述栅极驱动芯片的连接线，设置为传输信号给所述栅极驱动芯片；连接于所述栅极驱动芯片与所述显示面板的栅线之间的扇出线，与同一个所述栅极驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及设置于所述扇出区的附加导电膜，每个所述扇出区设置的附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减。
本申请还公开了一种驱动电路，包括驱动电路板；连接到所述驱动电路板的多个栅极驱动芯片；连接所述驱动电路板与所述栅极驱动芯片的连接线，设置为传输信号给所述栅极驱动芯片；连接于所述栅极驱动芯片与所述显示面板的栅线之间的扇出线，与同一个所述栅极 驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及按照所述信号的传输方向设置于第一个所述扇出区至倒数第二个所述扇出区上的附加导电膜，每个所述扇出区设置的所述附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减；所述附加导电膜对应每条所述扇出线设置，同一所述扇出区内设置的所述附加导电膜与每条所述扇出线重叠的面积相同；所述附加导电膜由氧化铟锡导电膜与金属导电膜结合而成。
本申请还公开了一种显示面板，所述显示面板包括多条栅线，以及驱动所述栅线的驱动电路；所述驱动电路包括驱动电路板；连接到所述驱动电路板的多个栅极驱动芯片；连接所述驱动电路板与所述栅极驱动芯片的连接线，设置为传输信号给所述栅极驱动芯片；连接于所述栅极驱动芯片与所述显示面板的栅线之间的扇出线，与同一个所述栅极驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及设置于所述扇出区的附加导电膜，每个所述扇出区设置的所述附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减。
由于每个扇出区之间是通过连接线连接的，连接线本身带有一定的电阻，就会对信号的传输产生一定的影响，根据信号延迟的时间常数τ＝RC，R为电阻，C为电容，本申请在扇出区增加附加导电膜来形成一个补偿电容，来增大前面扇出区的信号延迟的时间常数，使各个扇出区的信号延迟的时间常数相等，从而使每个扇出区的信号同步输出。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种阵列基板的结构的示意图；
图2是本申请的一实施例的扇出区的剖面结构的示意图；
图3是本申请的一实施例的一个扇出区设置附加导电膜的示意图；
图4是本申请的另一实施例的一个扇出区设置附加导电膜的示意图；
图5是本申请的另一实施例的一个扇出区设置附加导电膜的示意图；
图6是本申请的一实施例的一种显示装置的示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体 实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
如图1所示，信号从源极驱动芯片310传入，经过连接线330进入扇出线341，然后再进入显示面板100内的显示区域(Active Area，AA)。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1所示，作为本申请的一实施例，公开了一种显示面板100，包括基板、多组栅线500和驱动栅线500的驱动电路700，所述驱动电路700包括驱动电路板600；设置在基板的第一边380的多个源极驱动芯片310，连接于驱动电路板600上；设置在基板的第二边390的多个栅极驱动芯片320，连接于源极驱动芯片310或驱动电路板600上；连接驱动电路板600与栅极驱动芯片320的连接线330，设置为传输信号给栅极驱动芯片320；连接于栅极驱动芯片320与显示面板100的栅线500的扇出线341，与同一个栅极驱动芯片320连接的扇出线341形成一个扇出区340，扇出区340按照信号的传输方向排列设置；以及设置于扇出区340的附加导电膜350，每个扇出区340设置的附加导电膜350的面积不同，按信号的传输方向，附加导电膜350与每个扇出区340的扇出线341重叠的总面积逐个递减，附加导电膜350仅设置在第一个扇出区340至倒数第二个扇出区340上，最后一个扇出区不进行设置，每个扇出区340中设置的附加导电膜350的起始界线和结束界线平行，且与基板的第二边390平行；对于有N个扇出区340的显示面板100，信号延迟的时间常数τ1＝τ2＝τ3…＝τN，即为：(R W1+R F1)(C W1+C F1)＝(R W1+R W2+R F2)(C W1+C W2+C F2)＝(R W1+R W2+R W3+R F3)(C W1+C W2+C W3+C F3)＝…＝(R W1+R W2+R W3+…R WN+ R FN)(C W1+C W2+C W3+…+C WN+C FN)。
在上述的计算公式中，所有的R值都能通过计算得出，各个C W的值是计算得出，唯一的变量就为C F，控制各个扇出区340的C F值就能使各个扇出区340的信号延迟的时间常数τ相等，控制C F值的手段是通过增设附加导电膜350来与扇出线341形成一个电容，控制附加导电膜350与扇出线341的重叠面积来控制CF值的大小，来使得各个扇出区340的信号同步输出，使栅线500给画素充电均匀，画面显示更均匀。
其中，基板为阵列基板300，第一边380和第二边390为阵列基板300的两个相互垂直的相邻边，附加导电膜350为悬空状态的，不与其他元器件连接。
当然，所有所述扇出区均对应设置所述附加导电膜也是可行的。
如图1和图2所示，作为本申请的另一实施例，公开了一种显示面板100，显示面板100包括彩膜基板200和阵列基板300，彩膜基板200包括玻璃衬底210、色阻220和第一导电膜230，色阻220设置在玻璃衬底210上，第一导电膜230设置在色阻220上；阵列基板300包括源极驱动芯片310、栅极驱动芯片320、连接线330、扇出线341、附加导电膜350、绝缘层360和钝化层370；源极驱动芯片310通过连接线330与栅极驱动芯片320连接，同一侧的栅极驱动芯片320之间也以连接线330连接，与同一个栅极驱动芯片320连接的扇出线341形成一个扇出区340，扇出区340按照信号的传输方向排列设置，每个扇出区340对应设置附加导电膜350，不同的扇出区340设置的附加导电膜350的面积不同，按信号的传输方向，附加导电膜350与每个扇出区340的扇出线341重叠的总面积逐个递减，通过增加不同面积的附加导电膜350来增加不同大小的补偿电容。
其中，扇出线341信号延迟的时间常数τ的计算公式为：τ＝RC，其中，R为电阻，C为电容，电容C的计算公式
Figure PCTCN2019128751-appb-000001
其中，ε为介质介电电常数，S为两极板正对面积，π为圆周率，k为静电力常量，d为两极板间垂直距离，此方案中S为附加导电膜350与扇出线341的正对面积，通过控制附加导电膜350与扇出线341的正对面积S来得到不同的补偿电容C，具体的，附加导电膜350与扇出线341的正对面积S从第一个扇出区340往后逐个递减，补充电容C也是从第一个扇出区340往后逐个递减。
在栅极驱动芯片320之间的信号传输过程中，扇出线341会因为连接线330的电阻而产生信号延迟，从时间常数公式τ的计算公式来看，信号延迟的时间常数τ受电阻R和电容C的影响。因为每个栅极驱动芯片320之间连接线330的电阻的影响，每个扇出区340的信号会产生延迟，在扇出区340设置一层附加导电膜350，与扇出线341形成一个电容C；连接线330连接到每个扇出区340的长度不同，产生影响的电阻R大小也不同，由电容C的计算公式来看，通过控制附加导电膜350与扇出线341的正对面积S来控制电容的大小，每个扇出区340设置不同面积的附加导电膜350，来使各个扇出区340的时间常数τ一致，使信 号同时输出，使栅线500给画素充电均匀，画面显示更均匀。
具体的，对于第一个扇出区340的某一条扇出线341，其信号延迟的时间常数τ1＝(R W1+R F1)(C W1+C F1)，其中，连接线330按照信号的传输方向排列，Rw1、Cw1分别为第一条连接线330的电阻和电容，R F1、C F1分别为第一个扇出区340中扇出线341的电阻和电容；对于第一条连接线330的电阻R w1＝Rs×L w1/W w1，其中L W1、W W1分别为第一条连接线330的长度和宽度；同理可得第一个扇出区340的电阻R F1＝Rs×L F1/W F1。对于没有附加导电膜350覆盖的连接线330，其电容Cw1是连接线330与彩膜基板200的第一导电膜230形成的，电容：C w1＝ε 0·ε L·S w1/d 1，其中ε 0为绝对介电常数，ε L为液晶的相对介电常数，SW1为连接线330的面积，d1为液晶盒的厚度，介于3-4um之间。对于扇出线341，假设覆盖附加导电膜350部分的扇出线341长度为L F11，没有覆盖附加导电膜350部分的扇出线341长度为L F12，L F11+L F12＝L F1，对于覆盖附加导电膜350部分的扇出线341的电容，包括扇出线341与附加导电膜350之间的电容、扇出线341与彩膜基板200侧的第一导电膜230之间电容两部分：C F11＝ε 0·ε P·S F11/d 2+ε 0·ε L·S F11/d 1,S F11＝W F1·L F11，其中ε P为绝缘层360和钝化层370的介电常数，d 2为绝缘层360和钝化层370的厚度之和。由于ε P≈ε L，而d 1≥d 2，因此在粗略计算中，电容C F11计算公式中的第二项可以忽略。
对于没有覆盖附加导电膜350的扇出线341部分，其电容只包括扇出线341与彩膜基板200侧的第一导电膜230的电容：C F12＝ε 0·ε L·S F12/d 1，其中S F12＝W F1·L F12，W F1为扇出区340的宽度。因此扇出区340的电容包括覆盖附加导电膜350与不覆盖附加导电膜350部分导线的电容之和：C F1＝C F11+C F12。同理，可以计算得到第二个扇出区340某一条扇出线341信号延迟的时间常数，在一个显示面板100的设计中，不同栅极驱动芯片320对应的扇出线341的设计相同，所以R F1＝R F2，不同之处在于，第二个扇出区340引入了第二根连接线330产生影响的计算部分，第二个扇出区340的信号延迟的时间常数为：τ 2＝(R W1+R W2+R F2)(C W1+C W2+C F2)。每个扇出区的之间的信号延迟的时间常数相同，使τ 1＝τ 2，即(R W1+R F1)(C W1+C F1)＝(R W1+R W2+R F2)(C W1+C W2+C F2)，在上述的所有参数中，所有R值都可以通过带入已有的参数计算得出，连接线330的C值也可以计算得出，唯一的变量在于相邻两个扇出区340的覆盖附加导电膜350部分的扇出线341长度不同导致的C值变量，通过上式可以得到相邻扇出区340各自覆盖附加导电膜350的长度的关系，从而精确控制相邻COF走线的信号延迟。另外从上式可以得出，R W1+R F1＜R W1+R W2+R F2，欲使等式成立，则C W1+C F1＞C W1+C W2+C F2，即C F1＞C F2， 所以第一个扇出区340上方覆盖的附加导电膜350的面积要大于第二个扇出区340的附加导电膜350的面积。为了进一步提升显示效果，每个所述扇出区中的每条所述扇出线的信号延迟的时间常数相同。
对于设置有N个所述扇出区340的所述显示面板100，所述信号延迟的时间常数τ 1＝τ 2＝τ 3…＝τ N，即(R W1+R F1)(C W1+C F1)＝(R W1+R W2+R F2)(C W1+C W2+C F2)＝(R W1+R W2+R W3+R F3)(C W1+C W2+C W3+C F3)＝…＝(R W1+R W2+R W3+…+R WN+R FN)(C W1+C W2+C W3+…+C WN+C FN)；可以得出R W1+R F1＜R W1+R W2+R F2＜R W1+R W2+R W3+R F2＜R W1+R W2+R W3+…+R WN+R F2，因此C W1+C F1＞C W1+C W2+C F2＞C W1+C W2+C W3+C F2＞C W1+C W2+C W3+…+C WN+C F2，即C F1＞C F2＞C F3＞…＞C FN。
第一个扇出区340上的附加导电膜350的覆盖面积设置为最大，往后按顺序逐个递减，使各个扇出区340的补偿电容值按顺序逐个递减，使得各个扇出区340的信号延迟的时间常数相等，从而使信号同步输出，使栅线500给画素充电均匀，画面显示更均匀。
在一实施例中，按照信号的传输方向，附加导电膜350设置于第一个扇出区340至倒数第二个扇出区340上，最后一个扇出区340不设置附加导电膜350。以最后一个扇出区340的信号延迟的时间常数为基准来计算前面的扇出区340的信号延迟的时间常数，使第一个扇出区340到倒数第二个扇出区340的信号延迟的时间常数都等于最后一个扇出区340的信号延迟的时间常数，这样在最后一个扇出区340就不用设置附加导电膜350，节省工序和材料。
如图2和图3所示，在一实施例中，阵列基板300包括绝缘层360和钝化层370，绝缘层360设置在扇出线341上，钝化层370设置在绝缘层360上，附加导电膜350对应每条扇出线341设置在钝化层370上，同一扇出区340内设置的附加导电膜350与每条扇出线341重叠的面积相同。在同一扇出区340内设置的附加导电膜350与每条扇出线341重叠的面积相同，这样同一个扇出区340的每条扇出线341上增加的补偿电容相等，每条扇出线341信号延迟的时间常数也相等，使得同一个扇出区340的每条扇出线341的信号同步输出，使栅线500给画素充电均匀，画面显示更均匀。
具体的，附加导电膜350由氧化铟锡导电膜351与金属导电膜352结合而成，两者位置不做限定。
当然，附加导电膜350也可以设置在扇出区340的底部或其他位置；附加导电膜350也可单独为氧化铟锡导电膜351或金属导电膜352。
如图4所述，在一实施例中，每个扇出区340中设置的附加导电膜350的起始界线和结 束界线平行，且与阵列基板300的第二边390平行，起始界线和结束界线之间的竖直距离为L。在制作的过程中，通过控制距离L的值来使附加导电膜350的有效面积增大或减小，方便生产。
如图5所示，在一实施例中，一个扇出区340对应设置一整块的附加导电膜350，附加导电膜350的形状为梯形。直接一整块附加导电膜350进行覆盖，节省了部分对附加导电膜350进行处理的工序，将附加导电膜350的形状设置为梯形，减小附加导电膜350的无效面积，节省材料。当然，附加导电膜350也可以为其他形状，例如三角形、矩形、椭圆形等。
如图6所示，作为本申请的另一实施例，公开了一种显示装置400，显示装置400包括上述的显示面板100，所述显示面板100包括栅线500和驱动电路700。
本申请的技术方案可以广泛用于各种显示面板，如扭曲向列型(Twisted Nematic，TN)显示面板、平面转换型(In-Plane Switching，IPS)显示面板、垂直配向型(Vertical Alignment，VA)显示面板、多象限垂直配向型(Multi-Domain Vertical Alignment，MVA)显示面板，当然，也可以是其他类型的显示面板，如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，均可适用上述方案。
以上内容是结合具体的可选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种驱动电路，包括：
    驱动电路板；
    多个栅极驱动芯片，连接到所述驱动电路板；
    连接线，连接所述驱动电路板与所述栅极驱动芯片，设置为传输信号给所述栅极驱动芯片；
    扇出线，连接于所述栅极驱动芯片与所述显示面板的栅线之间，与同一个所述栅极驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及
    附加导电膜，设置于所述扇出区，每个所述扇出区设置的所述附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减。
  2. 如权利要求1所述的一种驱动电路，其中，每个所述扇出区中设置的所述附加导电膜的起始界线和结束界线平行。
  3. 如权利要求1所述的一种驱动电路，其中，按照所述信号的传输方向，所述附加导电膜设置于第一个所述扇出区至倒数第二个所述扇出区上。
  4. 如权利要求1所述的一种驱动电路，其中，所有所述扇出区均对应设置所述附加导电膜。
  5. 如权利要求1所述的一种驱动电路，其中，所述附加导电膜对应每条所述扇出线设置，同一所述扇出区内设置的所述附加导电膜与每条所述扇出线重叠的面积相同。
  6. 如权利要求2所述的一种驱动电路，其中，一个所述扇出区对应设置一整块的所述附加导电膜。
  7. 如权利要求6所述的一种驱动电路，其中，所述附加导电膜为梯形。
  8. 如权利要求6所述的一种驱动电路，其中，所述附加导电膜为三角形。
  9. 如权利要求6所述的一种驱动电路，其中，所述附加导电膜为矩形。
  10. 如权利要求6所述的一种驱动电路，其中，所述附加导电膜为椭圆形。
  11. 如权利要求1所述的一种驱动电路，其中，每个所述扇出区之间的信号延迟的时间常数相同。
  12. 如权利要求11所述的一种驱动电路，其中，所述扇出区的信号延迟的时间常数为：
    τ＝(R W+R F)(C W+C F)；
    其中，R W和C W为一个所述扇出区连接的所述连接线的电阻和电容，R F和C F为一个所述扇出区的电阻和电容。
  13. 如权利要求1所述的一种驱动电路，其中，每个所述扇出区中的每条所述扇出线的信号延迟的时间常数相同。
  14. 如权利要求1所述的一种驱动电路，其中，所述附加导电膜为氧化铟锡导电膜。
  15. 如权利要求1所述的一种驱动电路，其中，所述附加导电膜为金属导电膜。
  16. 如权利要求1所述的一种驱动电路，其中，所述附加导电膜由氧化铟锡导电膜与金属导电膜结合而成。
  17. 一种驱动电路，包括：
    驱动电路板；
    多个栅极驱动芯片，连接到所述驱动电路板；
    连接线，连接所述驱动电路板与所述栅极驱动芯片，设置为传输信号给所述栅极驱动芯片；
    扇出线，连接于所述栅极驱动芯片与所述显示面板的栅线之间，与同一个所述栅极驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及
    附加导电膜，按照所述信号的传输方向设置于第一个所述扇出区至倒数第二个所述扇出区上，每个所述扇出区设置的所述附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减；
    所述附加导电膜对应每条所述扇出线设置，同一所述扇出区内设置的所述附加导电膜与每条所述扇出线重叠的面积相同；所述附加导电膜由氧化铟锡导电膜与金属导电膜结合而成。
  18. 一种显示面板，包括多条栅线，以及驱动所述栅线的驱动电路；
    所述驱动电路包括：
    驱动电路板；
    多个栅极驱动芯片，连接到所述驱动电路板；
    连接线，连接所述驱动电路板与所述栅极驱动芯片，设置为传输信号给所述栅极驱动芯片；
    扇出线，连接于所述栅极驱动芯片与所述显示面板的栅线之间，与同一个所述栅极驱动芯片连接的所述扇出线形成一个扇出区，所述扇出区按照所述信号的传输方向排列设置；以及
    附加导电膜，设置于所述扇出区，每个所述扇出区设置的所述附加导电膜的面积不同，按所述信号的传输方向，所述附加导电膜与每个所述扇出区的所述扇出线重叠的总面积逐个递减。
  19. 如权利要求18所述的一种显示面板，其中，按照所述信号的传输方向，所述附加导电膜设置于第一个所述扇出区至倒数第二个所述扇出区上；所述附加导电膜对应每条所述扇出线设置，同一所述扇出区内设置的所述附加导电膜与每条所述扇出线重叠的面积相同；每个所述扇出区之间的信号延迟的时间常数相同。
PCT/CN2019/128751 2019-01-30 2019-12-26 驱动电路和显示面板 Ceased WO2020155970A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/420,134 US12276887B2 (en) 2019-01-30 2019-12-26 Driver circuit and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910089137.1A CN109658891B (zh) 2019-01-30 2019-01-30 一种驱动电路、显示面板和显示装置
CN201910089137.1 2019-01-30

Publications (1)

Publication Number Publication Date
WO2020155970A1 true WO2020155970A1 (zh) 2020-08-06

Family

ID=66122424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/128751 Ceased WO2020155970A1 (zh) 2019-01-30 2019-12-26 驱动电路和显示面板

Country Status (3)

Country Link
US (1) US12276887B2 (zh)
CN (1) CN109658891B (zh)
WO (1) WO2020155970A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109658891B (zh) * 2019-01-30 2020-08-18 惠科股份有限公司 一种驱动电路、显示面板和显示装置
CN110286532B (zh) * 2019-07-19 2022-04-22 昆山国显光电有限公司 阵列基板和显示面板
CN114155804B (zh) * 2021-12-16 2023-09-19 合肥维信诺科技有限公司 显示面板和显示装置
CN114185209B (zh) * 2022-02-17 2022-05-27 成都中电熊猫显示科技有限公司 阵列基板、显示面板和显示装置
CN117203579A (zh) 2022-02-24 2023-12-08 京东方科技集团股份有限公司 显示基板和显示装置
CN120636340B (zh) * 2025-06-26 2026-03-17 长沙惠科光电有限公司 驱动电路、驱动方法和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007328346A (ja) * 2006-06-08 2007-12-20 Samsung Electronics Co Ltd 薄膜トランジスタ基板及びこれを含む液晶表示板
US20120306826A1 (en) * 2011-06-03 2012-12-06 Renesas Electronics Corporation Data driver for panel display apparatuses
CN103309107A (zh) * 2013-05-13 2013-09-18 深圳市华星光电技术有限公司 阵列基板的扇出线结构及显示面板
CN109658891A (zh) * 2019-01-30 2019-04-19 惠科股份有限公司 一种驱动电路、显示面板和显示装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100831235B1 (ko) * 2002-06-07 2008-05-22 삼성전자주식회사 박막 트랜지스터 기판
US6842200B1 (en) * 2003-06-18 2005-01-11 Hannstar Display Corporation Liquid crystal panel having compensation capacitors for balancing RC delay effect
US8310442B2 (en) * 2005-02-23 2012-11-13 Pixtronix, Inc. Circuits for controlling display apparatus
US8619054B2 (en) * 2006-05-31 2013-12-31 Atmel Corporation Two dimensional position sensor
KR101249246B1 (ko) * 2006-06-27 2013-04-01 삼성디스플레이 주식회사 표시 기판 및 이를 구비한 표시 장치
TWI395007B (zh) * 2009-09-30 2013-05-01 Au Optronics Corp 扇出線路以及顯示面板
KR20140068592A (ko) * 2012-11-28 2014-06-09 삼성디스플레이 주식회사 표시장치
KR102458683B1 (ko) * 2015-08-13 2022-10-26 삼성디스플레이 주식회사 어레이 기판
CN105204248A (zh) * 2015-10-10 2015-12-30 重庆京东方光电科技有限公司 一种阵列基板及显示装置
CN106205540B (zh) * 2016-08-31 2019-02-01 深圳市华星光电技术有限公司 改善显示亮度均一性的液晶显示面板与液晶显示器
US20180218191A1 (en) * 2017-01-31 2018-08-02 Synaptics Incorporated Outside of active area finger-print sensor
CN106896592B (zh) * 2017-02-14 2020-05-22 深圳市华星光电技术有限公司 液晶显示面板及显示装置
KR102427667B1 (ko) * 2017-09-26 2022-08-02 삼성디스플레이 주식회사 디스플레이 장치
KR102352312B1 (ko) * 2017-09-29 2022-01-19 삼성디스플레이 주식회사 표시 장치
TWI697141B (zh) * 2018-12-11 2020-06-21 友達光電股份有限公司 元件基板
KR102691314B1 (ko) * 2019-01-16 2024-08-05 삼성전기주식회사 기판 배선 쇼트 검출 장치 및 방법
CN111081750B (zh) * 2019-12-31 2022-05-17 厦门天马微电子有限公司 一种显示面板和显示装置
CN111323949A (zh) * 2020-04-15 2020-06-23 昆山国显光电有限公司 阵列基板及显示面板
CN111933674B (zh) * 2020-08-18 2024-06-11 京东方科技集团股份有限公司 显示基板和显示装置
WO2023115239A1 (zh) * 2021-12-20 2023-06-29 京东方科技集团股份有限公司 显示面板和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007328346A (ja) * 2006-06-08 2007-12-20 Samsung Electronics Co Ltd 薄膜トランジスタ基板及びこれを含む液晶表示板
US20120306826A1 (en) * 2011-06-03 2012-12-06 Renesas Electronics Corporation Data driver for panel display apparatuses
CN103309107A (zh) * 2013-05-13 2013-09-18 深圳市华星光电技术有限公司 阵列基板的扇出线结构及显示面板
CN109658891A (zh) * 2019-01-30 2019-04-19 惠科股份有限公司 一种驱动电路、显示面板和显示装置

Also Published As

Publication number Publication date
CN109658891A (zh) 2019-04-19
US12276887B2 (en) 2025-04-15
US20220082878A1 (en) 2022-03-17
CN109658891B (zh) 2020-08-18

Similar Documents

Publication Publication Date Title
WO2020155970A1 (zh) 驱动电路和显示面板
US12222612B2 (en) Array substrate, display panel, and display apparatus
US9570021B2 (en) Array substrate, flexible display device and electronic device
CN102411242B (zh) 像素结构及其驱动方法
US11264407B2 (en) Array substrate
JP6472066B2 (ja) 電気容量分圧式低い色ずれ画素回路
US9864246B2 (en) Array substrate and display device
US20180292693A1 (en) A display panel and an array substrate thereof
CN105824161B (zh) 一种液晶显示面板及液晶显示装置
US10394099B2 (en) Liquid crystal display panel with multiple sub-common electrodes and display device
WO2019205467A1 (zh) Tft阵列基板及显示装置
CN106449652B (zh) 阵列基板及其制造方法、显示面板和显示设备
WO2016095316A1 (zh) 一种液晶显示面板及其制造方法
CN107678590B (zh) 一种触控显示面板及其驱动方法
JP2012242497A (ja) 液晶表示装置
WO2016145978A1 (zh) 阵列基板及其制作方法以及显示装置
WO2019184039A1 (zh) 阵列基板及显示面板
TWI489185B (zh) 顯示面板
US10963114B1 (en) Touch display panel
CN103412447A (zh) 一种液晶显示面板和显示装置
US20200176480A1 (en) Display panel and display device
US8610854B2 (en) Liquid crystal display panel and pixel electrode thereof
WO2018176809A1 (zh) 阵列基板及其制作方法、显示装置
WO2022116199A1 (zh) 显示面板及电子设备
WO2013152515A1 (zh) 液晶显示装置及其显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19913921

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19913921

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.01.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 19913921

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 17420134

Country of ref document: US