WO2020155390A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020155390A1
WO2020155390A1 PCT/CN2019/082283 CN2019082283W WO2020155390A1 WO 2020155390 A1 WO2020155390 A1 WO 2020155390A1 CN 2019082283 W CN2019082283 W CN 2019082283W WO 2020155390 A1 WO2020155390 A1 WO 2020155390A1
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Prior art keywords
layer
substrate
voltage signal
lead
display panel
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PCT/CN2019/082283
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English (en)
French (fr)
Inventor
熊锐
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/493,498 priority Critical patent/US11069764B2/en
Publication of WO2020155390A1 publication Critical patent/WO2020155390A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • This application relates to a display technology, in particular to a display panel and a display device.
  • Figure 1 is a schematic diagram of the structure of a narrow-frame display panel in the prior art.
  • 100' is a substrate; 101' is a GOA driving circuit unit; 102' is an organic flat layer; 103' is an anode; 104' is Pixel definition layer; 105' is the cathode; 106' is the first inorganic layer of the packaging structure layer; 107' is the organic layer of the packaging structure layer; 108' is the second inorganic layer of the packaging structure layer; 109' is the source/drain metal
  • the film layer, namely the VSS signal wiring, 110' is the second retaining wall.
  • the distance from the second inorganic layer 108' to the edge of the second retaining wall 110' is L.
  • the larger the value of L, the first inorganic layer 106' and the second inorganic layer 108' in the encapsulation structure layer The larger the contact area with the film layer of the substrate 100'; the larger the contact area, the greater the bonding force between the package structure layer and the substrate 100', and peeling is less likely to occur.
  • the value of L′ needs to be compressed, so that Peelinng between the packaging structure layer and the substrate 100′ is likely to occur, and at the same time, poor edge packaging is likely to occur.
  • the embodiments of the present application provide a display panel and a display device to solve the technical problem that when the frame width of the existing narrow frame display panel is compressed, the bonding force between the packaging structure layer and the substrate is weak, which leads to poor edge packaging.
  • An embodiment of the present application provides a display panel including a display area and a frame area located on both sides of the display area, wherein the frame area includes a substrate and a substrate layer, voltage signal wiring, A flat layer, lead wires and a package structure layer, the package structure layer extends to the outside of the flat layer and is connected to the substrate;
  • the display area includes the substrate and the driving circuit unit, the flat layer and the anode which are sequentially arranged on the substrate, and the lead wires extend outward from one side of the anode and are connected to the voltage Signal routing;
  • the overlapping length of the overlapping portion of the lead wire and the voltage signal wire is greater than the length of the orthographic projection of the overlapping portion on the substrate;
  • the substrate layer is provided with a plurality of trenches, and the voltage signal wiring is formed on the substrate layer, so that the voltage signal wiring is in a concave-convex structure;
  • the display area further includes a pixel definition layer, a cathode, and the packaging structure layer disposed on the anode;
  • the encapsulation structure layer corresponding to the display area includes a first inorganic layer, an organic layer, and a second inorganic layer disposed on the cathode.
  • the lead wires are in the shape of a concave-convex structure, and the voltage signal wires are concave-convex lap fit.
  • the encapsulation structure layer includes a first inorganic layer disposed on the lead wire, and the overlapping area of the first inorganic layer and the lead wire is a concave-convex structure that matches with each other .
  • the substrate layer is an insulating organic layer or an insulating inorganic layer.
  • the voltage signal wiring is a VSS wiring or a VDD wiring.
  • An embodiment of the present application provides a display panel, which includes a display area and a frame area located on both sides of the display area, wherein the frame area includes a substrate, a substrate layer and voltage signal traces sequentially disposed on the substrate , A flat layer, lead wires and a packaging structure layer, the packaging structure layer extends to the outside of the flat layer and is connected to the substrate;
  • the display area includes the substrate and the driving circuit unit, the flat layer and the anode which are sequentially arranged on the substrate, and the lead wires extend outward from one side of the anode and are connected to the voltage Signal routing;
  • the overlapping length of the overlapping portion of the lead wire and the voltage signal wire is greater than the length of the orthographic projection of the overlapping portion on the substrate.
  • the substrate layer is provided with a plurality of trenches, and the voltage signal wiring is formed on the substrate layer, so that the voltage signal wiring is in a concave-convex structure.
  • the lead wires are in the shape of a concave-convex structure, and the voltage signal wires are concave-convex lap fit.
  • the encapsulation structure layer includes a first inorganic layer disposed on the lead wire, and the overlapping area of the first inorganic layer and the lead wire is a concave-convex structure that matches with each other .
  • the frame area further includes a first retaining wall and a second retaining wall disposed at the end of the lead-out wire, the first retaining wall is close to the display area, and the second retaining wall is far away from the display area.
  • the substrate layer is an insulating organic layer or an insulating inorganic layer.
  • the voltage signal wiring is a VSS wiring or a VDD wiring.
  • the display area further includes a pixel definition layer, a cathode, and the packaging structure layer disposed on the anode;
  • the encapsulation structure layer corresponding to the display area includes a first inorganic layer, an organic layer, and a second inorganic layer disposed on the cathode.
  • the present application also relates to a display device, which includes a display panel, the display panel includes a display area and a frame area located on both sides of the display area, wherein the frame area includes a substrate and is sequentially arranged on the substrate A substrate layer, voltage signal traces, a flat layer, lead-out traces, and a packaging structure layer, the packaging structure layer extends to the outside of the flat layer and is connected to the substrate;
  • the display area includes the substrate and the driving circuit unit, the flat layer and the anode which are sequentially arranged on the substrate, and the lead wires extend outward from one side of the anode and are connected to the voltage Signal routing;
  • the overlapping length of the overlapping portion of the lead wire and the voltage signal wire is greater than the length of the orthographic projection of the overlapping portion on the substrate.
  • the substrate layer is provided with a plurality of trenches, and the voltage signal wiring is formed on the substrate layer, so that the voltage signal wiring is in a concave-convex structure.
  • the lead wires are in the shape of a concave-convex structure, and the voltage signal wires are concave-convex lap fit.
  • the encapsulation structure layer includes a first inorganic layer disposed on the lead wire, and the overlapping area of the first inorganic layer and the lead wire is a concave-convex structure that matches with each other .
  • the substrate layer is an insulating organic layer or an insulating inorganic layer.
  • the voltage signal wiring is a VSS wiring or a VDD wiring.
  • the display area further includes a pixel definition layer, a cathode, and the packaging structure layer disposed on the anode;
  • the encapsulation structure layer corresponding to the display area includes a first inorganic layer, an organic layer, and a second inorganic layer disposed on the cathode.
  • the display panel and the display device of the present application have a longer than the orthographic projection of the overlapped portion on the substrate by connecting the lead wire and the voltage signal wire to the overlapped portion.
  • the length is set to shorten the projection length of the voltage signal trace on the substrate, so that the distance between the edge of the packaging structure layer and the edge of the second retaining wall is not shortened when the frame width is reduced; it solves the problem that the existing narrow frame display panel is compressed When the width is larger, the bonding force between the package structure layer and the substrate is weak, which leads to technical problems of poor edge package.
  • FIG. 1 is a schematic structural diagram of a narrow-frame display panel in the prior art
  • FIG. 2 is a schematic structural diagram of an embodiment of the display panel of the application.
  • FIG. 2 is a schematic structural diagram of an embodiment of the display panel of the present application.
  • the display panel 100 of the embodiment of the present application includes a display area 10a (only part of which is shown in FIG. 2) and a frame area 10b located on both sides of the display area 10a.
  • the frame area 10 b includes a substrate 11, a substrate layer 12, voltage signal traces 13, a flat layer 14, a lead trace 15 and a packaging structure layer 16 sequentially disposed on the substrate 11.
  • the packaging structure layer 16 extends from the display area 10 a to the outside of the flat layer 14 and is connected to the substrate 11.
  • the display area 10 a includes a substrate 11 and a driving circuit unit 17, a planarization layer 14, an anode 18, a pixel definition layer 19, a cathode 120 and an encapsulation structure layer 16 sequentially disposed on the substrate 11.
  • the encapsulation structure layer 16 corresponding to the display area 10a includes a first inorganic layer 161, an organic layer 162, and a second inorganic layer 163 disposed on the cathode 120.
  • the lead wire 15 extends from one side of the anode 18 and overlaps the voltage signal wire 13.
  • the overlapping length of the overlapping portion of the lead wire 15 and the voltage signal wire 13 is greater than the length of the orthographic projection of the overlapping portion on the substrate 11.
  • the display panel 100 of this embodiment shortens the voltage signal wiring by setting the overlapping length of the lead wire 15 and the voltage signal wiring 13 to be longer than the length of the orthographic projection of the overlapping portion on the substrate 11
  • the projection length of 13 on the substrate 11 can be achieved without shortening the distance L from the edge of the packaging structure layer 16 to the edge 122 of the second retaining wall when the frame width is reduced.
  • the substrate layer 12 is provided with a plurality of trenches 121.
  • the grooves 121 are arranged at intervals.
  • the voltage signal wiring 13 is formed on the substrate layer 12 so that the voltage signal wiring 13 has a concave-convex structure.
  • the concave-convex structure of the voltage signal trace 13 on the one hand ensures the effective overlap length with the lead trace 13, on the other hand, it reduces the planar projection width of the voltage signal trace 13, thereby increasing the distance between the edge of the package structure layer 16 and the second barrier.
  • the distance L from the edge of the wall 122 improves the packaging effect of the panel frame area 12b.
  • the base layer 12 is an insulating organic layer or an insulating inorganic layer.
  • the substrate layer 12 is an organic layer.
  • the use of organic materials for the substrate layer 12 can improve the bending formation of the frame area 12b.
  • the longitudinal cross-sectional shape of the voltage signal wiring 13 is a convex-concave structure, which also improves the bending performance of the voltage signal wiring 13.
  • the voltage signal wiring 13 may be a VSS wiring or a VDD wiring. It should be noted that, in the OLED display panel circuit, the VDD trace is connected to the anode terminal of the OLED light-emitting diode to transmit the anode voltage; the VSS trace is connected to the cathode terminal of the OLED light-emitting diode to transmit the cathode terminal Voltage.
  • the lead wires 15 have a concave-convex structure, and they are concave-convex lap fit with the voltage signal wires 13. This arrangement makes the lead wire 15 and the voltage signal wire 13 fully overlap, so as to achieve the maximum overlap length of the lead wire 15 and the voltage signal wire 13.
  • the packaging structure layer 16 includes a first inorganic layer 161 disposed on the lead wire 15.
  • the overlapping area between the first inorganic layer 161 and the lead wire 15 is a concave-convex structure that matches with each other. Such an arrangement increases the overlap area between the first inorganic layer 161 and the lead wire 15, thereby increasing the bonding area of the first inorganic layer 161 and the lead wire 15, and improves the stability of the package.
  • the portion of the packaging structure layer 16 corresponding to the above-mentioned overlapping area further includes a second inorganic layer 163, and the second inorganic layer 163 is formed on the first inorganic layer 161.
  • the first inorganic layer 161 and the second inorganic layer 163 are lapped and matched with each other. Such an arrangement increases the overlap area of the first inorganic layer 161 and the second inorganic layer 163, thereby increasing the bonding area of the first inorganic layer 161 and the second inorganic layer 163, and improves the stability of the package.
  • the frame area 10b also includes a first retaining wall 121 and a second retaining wall 122 disposed at the ends of the lead wires 15.
  • the first retaining wall 121 is close to the display area 10a, and the second retaining wall 122 is far away from the display area 10a.
  • the display panel 100 includes a substrate 11 on which a first setting area for setting the display area 10a and a second setting area for setting the frame area 10b are provided.
  • the manufacturing process of the display panel 100 of this embodiment is:
  • a buffer layer, a gate metal layer, an insulating layer, an active layer, and an interlayer dielectric layer are sequentially formed on the first placement area of the substrate 11, and an interlayer dielectric layer is formed on the second placement area of the substrate 11.
  • the interlayer dielectric layer corresponding to the second setting area is processed by the halftone mask technology to form the substrate layer 12 with the trench 121.
  • a voltage signal wiring 13 is formed on the substrate layer 12, and a source and drain metal layer is formed at the interlayer dielectric layer corresponding to the first arrangement area to complete the driving circuit unit 17 of the display area 10a.
  • a flat layer 14 is formed on the driving circuit unit 17 and the voltage signal wiring 13.
  • the lead wires 15, the first retaining wall 121, and the second retaining wall 122 are sequentially formed at the flat layer 14 corresponding to the first installation area, and the anode 18, the anode 18 and the second retaining wall 122 are sequentially formed at the flat layer 14 corresponding to the second installation area.
  • Pixel definition layer 19 and cathode 120 are sequentially formed at the flat layer 14 corresponding to the first installation area.
  • a packaging structure layer 16 is formed on the above structure.
  • the present application also relates to a display device, which includes a display panel, the display panel includes a display area and a frame area located on both sides of the display area, wherein the frame area includes a substrate and is sequentially arranged on the substrate A substrate layer, voltage signal traces, a flat layer, lead-out traces, and a packaging structure layer, the packaging structure layer extends to the outside of the flat layer and is connected to the substrate;
  • the display area includes the substrate and the driving circuit unit, the flat layer and the anode which are sequentially arranged on the substrate, and the lead wires extend outward from one side of the anode and are connected to the voltage Signal routing;
  • the overlapping length of the overlapping portion of the lead wire and the voltage signal wire is greater than the length of the orthographic projection of the overlapping portion on the substrate.
  • the substrate layer is provided with a plurality of trenches, and the voltage signal wiring is formed on the substrate layer, so that the voltage signal wiring is in a concave-convex structure.
  • the lead wires are in the shape of a concave-convex structure, and the voltage signal wires are concave-convex lap fit.
  • the encapsulation structure layer includes a first inorganic layer disposed on the lead wire, and the overlapping area of the first inorganic layer and the lead wire is a concave-convex structure that matches with each other .
  • the substrate layer is an insulating organic layer or an insulating inorganic layer.
  • the voltage signal wiring is a VSS wiring or a VDD wiring.
  • the display area further includes a pixel definition layer, a cathode, and the packaging structure layer disposed on the anode;
  • the encapsulation structure layer corresponding to the display area includes a first inorganic layer, an organic layer, and a second inorganic layer disposed on the cathode.
  • the display panel and the display device of the present application have a longer than the orthographic projection of the overlapped portion on the substrate by connecting the lead wire and the voltage signal wire to the overlapped portion.
  • the length is set to shorten the projection length of the voltage signal trace on the substrate, so that the distance between the edge of the packaging structure layer and the edge of the second retaining wall is not shortened when the frame width is reduced; it solves the problem that the existing narrow frame display panel compresses the frame When the width is larger, the bonding force between the package structure layer and the substrate is weak, which leads to technical problems of poor edge package.

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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Abstract

本申请提供一种显示面板，包括边框区和显示区，边框区包括基板、衬底层、电压信号走线、平坦层、引出走线和封装结构层，封装结构层延伸至平坦层的外侧并和基板连接；显示区包括阳极，引出走线自阳极的一侧向外延伸并搭接在电压信号走线上；引出走线和电压信号走线的搭接部分的搭接长度大于搭接部分于基板上的正投影的长度。

Description

显示面板及显示装置 技术领域
本申请涉及一种显示技术，特别涉及一种显示面板及显示装置。
 背景技术
随着显示行业技术的发展，客户对显示面板的要求越来越高，如对于一些高端显示面板，客户会要求做窄边框设计。
如图1所示，图1为现有技术窄边框显示面板的结构示意图，图中100′为基板；101′为GOA驱动电路单元；102′为有机平坦层；103′为阳极；104′为像素定义层；105′为阴极；106′为封装结构层的第一无机层；107′为封装结构层的有机层；108′为封装结构层的第二无机层；109′为源/漏金属膜层，即VSS信号走线，110′为第二挡墙。
图1中面板左右边框处，第二无机层108′至第二挡墙110′边缘的距离为L，L值越大则封装结构层中的第一无机层106′和第二无机层108′和基板100′的膜层接触面积越大；接触面积越大，则封装结构层和基板100′间的结合力越大，不容易发生脱落（Peeling）。而实现窄边框时，需要压缩L′值，这样导致封装结构层容易和基板100′之间发生Peelinng，同时容易出现边缘封装不良。
 技术问题
本申请实施例提供一种显示面板及显示装置，以解决现有的窄边框显示面板在压缩边框宽度时，出现封装结构层和基板结合力较弱，导致边缘封装不良的技术问题。
 技术解决方案
本申请实施例提供一种显示面板，包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度；
所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状；
所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
在本申请的显示面板中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
在本申请的显示面板中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
在本申请的显示面板中，所述衬底层为绝缘的有机层或绝缘的无机层。
在本申请的显示面板中，所述电压信号走线为VSS走线或VDD走线。
本申请实施例提供还一种显示面板，包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度。
在本申请的显示面板中，所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状。
在本申请的显示面板中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
在本申请的显示面板中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
所述边框区还包括设置在所述引出走线末端的第一挡墙和第二挡墙，所述第一挡墙靠近所述显示区，所述第二挡墙远离所述显示区。
在本申请的显示面板中，所述衬底层为绝缘的有机层或绝缘的无机层。
在本申请的显示面板中，所述电压信号走线为VSS走线或VDD走线。
在本申请的显示面板中，所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
本申请还涉及一种显示装置，其包括一显示面板，所述显示面板包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度。
在本申请的显示装置中，所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状。
在本申请的显示装置中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
在本申请的显示装置中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
在本申请的显示装置中，所述衬底层为绝缘的有机层或绝缘的无机层。
在本申请的显示装置中，所述电压信号走线为VSS走线或VDD走线。
在本申请的显示装置中，所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
 有益效果
相较于现有技术的窄边框显示面板，本申请的显示面板及显示装置通过将引出走线和电压信号走线的搭接部分的搭接长度大于该搭接部分于基板上的正投影的长度的设置，以缩短电压信号走线于基板上的投影长度，从而达到缩小边框宽度时不用缩短封装结构层边缘到第二挡墙边缘的距离；解决了现有的窄边框显示面板在压缩边框宽度时，出现封装结构层和基板结合力较弱，导致边缘封装不良的技术问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为现有技术的窄边框显示面板的结构示意图；
图2为本申请的显示面板的实施例的结构示意图。
 本发明的实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
请参照图2，图2为本申请的显示面板的实施例的结构示意图。本申请实施例的显示面板100包括显示区10a（图2中仅示出部分）和位于显示区10a两侧的边框区10b。
边框区10b包括基板11和依次设置在基板11上的衬底层12、电压信号走线13、平坦层14、引出走线15和封装结构层16。封装结构层16自显示区10a延伸至平坦层14的外侧并和基板11连接。
显示区10a包括基板11与依次设置在基板11上的驱动电路单元17、平坦层14、阳极18、像素定义层19、阴极120和封装结构层16。对应于显示区10a的封装结构层16包括设置在阴极120上的第一无机层161、有机层162和第二无机层163。
引出走线15自阳极18的一侧向外延伸并搭接在电压信号走线13上。
其中引出走线15和电压信号走线13的搭接部分的搭接长度大于该搭接部分于基板11上的正投影的长度。
本实施例的显示面板100通过将引出走线15和电压信号走线13的搭接部分的搭接长度大于该搭接部分于基板11上的正投影的长度的设置，以缩短电压信号走线13于基板11上的投影长度，从而达到缩小边框宽度时不用缩短封装结构层16边缘到第二挡墙边缘122的距离L。
在本实施例的显示面板100中，具体的，衬底层12设置有多个沟槽121。多个沟槽121之间间隔设置。电压信号走线13形成在衬底层12上，以使电压信号走线13呈凹凸结构状。凹凸结构状的电压信号走线13一方面保证了和引出走线13的有效搭接长度，另一方面压缩了电压信号走线13的平面投影宽度，进而增加封装结构层16边缘距离第二挡墙122边缘的距离L，从而改善面板边框区12b的封装效果。
另外，衬底层12为绝缘的有机层或绝缘的无机层。在本实施例中，衬底层12为有机层。衬底层12采用有机材料可提高边框区12b的弯折形成。电压信号走线13的纵向截面形状呈凸凹结构也提高了电压信号走线13的弯折性能。
其中，电压信号走线13可以为VSS走线或VDD走线。需要说明的是，在OLED显示面板电路中，VDD走线连接于OLED发光二极管的阳极端，用于传输阳极性的电压；VSS走线连接于OLED发光二极管的阴极端，用于传输阴极性的电压。
在本实施例的显示面板100中，引出走线15为凹凸结构状，且和电压信号走线13凹凸搭接配合。这样的设置，使得引出走线15和电压信号走线13充分的搭接，以达到引出走线15和电压信号走线13的搭接长度达到最大。
在本实施例的显示面板100中，封装结构层16包括设置在引出走线15上的第一无机层161。第一无机层161和引出走线15的搭接区为互相配合的凹凸结构。这样的设置，提高了第一无机层161和引出走线15的搭接面积，进而提高了第一无机层161和引出走线15的结合面积，提供了封装的稳定性。
封装结构层16对应于上述搭接区的部分还包括第二无机层163，第二无机层163形成在第一无机层161上。在对应于上述搭接区的部分，第一无机层161和第二无机层163互相凹凸搭接配合。这样的设置，提高了第一无机层161和第二无机层163的搭接面积，进而提高了第一无机层161和第二无机层163的结合面积，提供了封装的稳定性。
另外，边框区10b还包括设置在引出走线15末端的第一挡墙121和第二挡墙122。第一挡墙121靠近显示区10a，第二挡墙122远显示区10a。
显示面板100包括基板11，基板11上设置有用于设置显示区10a的第一设置区域和用于设置边框区10b的第二设置区域。本实施例的显示面板100的制备过程是：
第一步，在基板11的第一设置区域上依次形成缓冲层、栅极金属层、绝缘层、有源层、层间介质层，在基板11的第二设置区域上形成层间介质层。
第二步，通过半色调掩模技术对对应于第二设置区域的层间介质层处理，形成具有沟槽121的衬底层12。
第三步，在衬底层12上形成电压信号走线13，在第一设置区对应的层间介质层处形成源漏金属层，以完成显示区10a的驱动电路单元17。
第四步，在驱动电路单元17和电压信号走线13上形成平坦层14。
第五步，在第一设置区对应的平坦层14处依次形成引出走线15、第一挡墙121和第二挡墙122，在第二设置区对应的平坦层14处依次形成阳极18、像素定义层19和阴极120。
最后，在上述结构上形成封装结构层16。
这样便完成了本实施例的制备过程。
本申请还涉及一种显示装置，其包括一显示面板，所述显示面板包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度。
在本申请的显示装置中，所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状。
在本申请的显示装置中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
在本申请的显示装置中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
在本申请的显示装置中，所述衬底层为绝缘的有机层或绝缘的无机层。
在本申请的显示装置中，所述电压信号走线为VSS走线或VDD走线。
在本申请的显示装置中，所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
相较于现有技术的窄边框显示面板，本申请的显示面板及显示装置通过将引出走线和电压信号走线的搭接部分的搭接长度大于该搭接部分于基板上的正投影的长度的设置，以缩短电压信号走线于基板上的投影长度，从而达到缩小边框宽度时不用缩短封装结构层边缘到第二挡墙边缘的距离；解决了现有的窄边框显示面板在压缩边框宽度时，出现封装结构层和基板结合力较弱，导致边缘封装不良的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (19)

  1. 一种显示面板，包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
    所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
    其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度；
    所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状；
    所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
    对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
  2. 根据权利要求1所述的显示面板，其中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
  3. 根据权利要求2所述的显示面板，其中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
  4. 根据权利要求1所述的显示面板，其中，所述衬底层为绝缘的有机层或绝缘的无机层。
  5. 根据权利要求1所述的显示面板，其中，所述电压信号走线为VSS走线或VDD走线。
  6. 一种显示面板，包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
    所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
    其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度。
  7. 根据权利要求6所述的显示面板，其中，所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状。
  8. 根据权利要求7所述的显示面板，其中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
  9. 根据权利要求8所述的显示面板，其中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
  10. 根据权利要求7所述的显示面板，其中，所述衬底层为绝缘的有机层或绝缘的无机层。
  11. 根据权利要求6所述的显示面板，其中，所述电压信号走线为VSS走线或VDD走线。
  12. 根据权利要求6所述的显示面板，其中，所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
    对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
  13. 一种显示装置，包括一显示面板，所述显示面板包括显示区和位于所述显示区两侧的边框区，其中，所述边框区包括基板和依次设置在所述基板上的衬底层、电压信号走线、平坦层、引出走线和封装结构层，所述封装结构层延伸至所述平坦层的外侧并和所述基板连接；
    所述显示区包括所述基板与依次设置在所述基板上的驱动电路单元、所述平坦层和阳极，所述引出走线自所述阳极的一侧向外延伸并搭接在所述电压信号走线上；
    其中所述引出走线和所述电压信号走线的搭接部分的搭接长度大于所述搭接部分于所述基板上的正投影的长度。
  14. 根据权利要求13所述的显示装置，其中，所述衬底层设置有多个沟槽，所述电压信号走线形成在所述衬底层上，以使所述电压信号走线呈凹凸结构状。
  15. 根据权利要求14所述的显示装置，其中，所述引出走线为凹凸结构状，且和所述电压信号走线凹凸搭接配合。
  16. 根据权利要求15所述的显示装置，其中，所述封装结构层包括设置在所述引出走线上的第一无机层，所述第一无机层和所述引出走线的搭接区为互相配合的凹凸结构。
  17. 根据权利要求14所述的显示装置，其中，所述衬底层为绝缘的有机层或绝缘的无机层。
  18. 根据权利要求13所述的显示装置，其中，所述电压信号走线为VSS走线或VDD走线。
  19. 根据权利要求13所述的显示装置，其中，所述显示区还包括设置在所述阳极上的像素定义层、阴极和所述封装结构层；
    对应于所述显示区的所述封装结构层包括设置在所述阴极上的第一无机层、有机层和第二无机层。
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