WO2020151540A1 - 一种电荷泵电路以及控制电荷泵电路的纹波电压的方法 - Google Patents

一种电荷泵电路以及控制电荷泵电路的纹波电压的方法 Download PDF

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WO2020151540A1
WO2020151540A1 PCT/CN2020/072162 CN2020072162W WO2020151540A1 WO 2020151540 A1 WO2020151540 A1 WO 2020151540A1 CN 2020072162 W CN2020072162 W CN 2020072162W WO 2020151540 A1 WO2020151540 A1 WO 2020151540A1
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transistor
current
load
capacitor
clock signal
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PCT/CN2020/072162
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English (en)
French (fr)
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董渊
王云松
黄建刚
程剑涛
孙洪军
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上海艾为电子技术股份有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of charge pump technology, and more specifically, to a charge pump circuit and a method for controlling the ripple voltage of the charge pump circuit.
  • the charge pump is one of the commonly used modules in the integrated circuit system. It uses the principle that the voltage across the capacitor cannot change suddenly, so that the output voltage can double the input reference voltage and discharge the output load in turn.
  • the charge pump has the advantages of small area, simple structure, and no need for off-chip components, so it has become a power supply module for many on-chip high-voltage systems.
  • the ripple voltage generated by the charge pump output will increase, resulting in too much voltage fluctuation on the load, which affects the stability of the output stage and greatly limits the charge. The scope of application of the pump.
  • the present invention provides a charge pump circuit to solve the problem of excessive voltage fluctuation on the load of the existing charge pump.
  • the present invention provides the following technical solutions:
  • a charge pump circuit includes a clock signal generation module, a first capacitor, a second capacitor, a charge and discharge control module, and a bias current generation module;
  • the bias current generating module is used for sampling the current on the load, and generating a bias current according to the sampled current;
  • the clock signal generating module is used to generate a clock signal according to the bias current
  • the charge and discharge control module is used to control one of the first capacitor and the second capacitor to charge, and the other to supply power to the load according to the clock signal.
  • the bias current generation module includes a sampling resistor, a transconductance amplifier, a first transistor, a second transistor, and a fixed bias current source;
  • the sampling resistor is connected in series with the load for sampling the current on the load and converting the current into voltage;
  • One input end of the transconductance amplifier is connected to one end of the sampling resistor, the other input end of the transconductance amplifier is connected to the other end of the sampling resistor, and the transconductance amplifier is used to connect the sampling resistor The voltage is converted to current;
  • the first terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the first transistor is connected to the gate of the second transistor, and the second terminal of the first transistor is connected to The gate of the first transistor is connected, the second terminal of the first transistor is connected to one output terminal of the transconductance amplifier, and the other output terminal of the transconductance amplifier is grounded; the first transistor and The second transistor is used to generate a mirror current according to the current output by the transconductance amplifier;
  • One end of the fixed bias current source is connected to the first end of the second transistor, and the other end of the fixed bias current source is connected to the second end of the second transistor, so that the fixed bias The fixed bias current output by the current source and the mirror current are superimposed to form the bias current.
  • the first transistor and the second transistor are PMOS transistors.
  • the clock signal generation module includes a comparator, a first inverter, a second inverter, and a third capacitor;
  • the first input terminal of the comparator is connected to the second terminal of the second transistor, the second input terminal of the comparator is connected to a reference voltage, and the first input terminal of the comparator passes through the third The capacitor is grounded;
  • the output terminal of the comparator is connected to the output terminal of the clock signal generating module through the first inverter and the second inverter.
  • the charge and discharge control module includes a third inverter, a fourth inverter, and third to sixth transistors;
  • the input terminal of the third inverter is connected to the output terminal of the clock signal generating module, the output terminal of the third inverter is connected to one end of the first capacitor, and the other end of the first capacitor Connected to the gate of the third transistor;
  • the input end of the fourth inverter is connected to the output end of the third inverter, the output end of the fourth inverter is connected to one end of the second capacitor, and the other end of the second capacitor One end is connected to the gate of the fourth transistor;
  • the first end of the third transistor is connected to the first end of the fourth transistor, the second end of the third transistor is connected to the gate of the fourth transistor, and the second end of the third transistor is connected to the gate of the fourth transistor.
  • Terminal is connected to the first terminal of the fifth transistor, the gate of the fifth transistor is connected to the gate of the third transistor, and the second terminal of the fifth transistor is connected to the power terminal;
  • the second end of the fourth transistor is connected to the gate of the third transistor, the second end of the fourth transistor is connected to the first end of the sixth transistor, and the gate of the sixth transistor is connected to the gate of the sixth transistor.
  • the gate of the fourth transistor is connected, and the second end of the sixth transistor is connected to the second end of the fifth transistor;
  • the first terminal of the third transistor is connected to the output terminal of the charge and discharge control module, and the output terminal of the charge and discharge control module is connected to the load.
  • the third transistor and the fourth transistor are PMOS transistors, and the fifth transistor and the sixth transistor are NMOS transistors.
  • a method for controlling the ripple voltage of a charge pump circuit, applied to the charge pump circuit as described in any one of the above, includes:
  • one of the first capacitor and the second capacitor in the charge pump circuit is controlled to charge, and the other is to supply power to the load.
  • the step of sampling the load current on the load connected to the charge pump circuit and generating a bias current according to the sampled current includes:
  • the fixed bias current and the mirror current are superimposed to form the bias current.
  • the bias current generation module samples the current on the load and generates the bias current according to the sampled current, and the clock signal generation module generates the bias current according to the current Clock signal.
  • the current and bias current on the sampled load will change accordingly, so that the frequency of the generated clock signal will also change accordingly, so that the ripple voltage fluctuation range is relatively reduced or remains unchanged, and then This reduces the voltage fluctuation range on the load.
  • FIG. 1 is a schematic diagram of the structure of an existing charge pump
  • FIG. 2 is a schematic structural diagram of a charge pump circuit provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the structure of a charge pump circuit and a clock signal generation module provided by an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for controlling the ripple voltage of a charge pump circuit according to an embodiment of the present invention.
  • the clock signal generation module uses a fixed period signal generated by the fixed current output from the fixed bias current source IB as the clock signal CLK.
  • V A1 2V IN
  • V A2 V IN
  • the transistor MN1 is turned on.
  • the gate of transistor MP2 i.e., the voltage of the node A2 pulled up to V iN
  • the transistor MP2 is turned on, the first capacitor C1 L R to supply power to the load through the transistor MP2.
  • the ripple voltage V ripple is also a fixed value.
  • the current I in the load R L is small, the load R L L becomes large, the ripple voltage V ripple also becomes large, resulting in voltage fluctuations across the load R L is too large.
  • the present invention provides a charge pump circuit and a method for controlling the ripple voltage of the charge pump circuit to overcome the above-mentioned problems in the prior art.
  • the charge pump circuit includes a clock signal generating module, a first capacitor, and a second capacitor. Capacitor, charge and discharge control module and bias current generation module;
  • the bias current generating module is used for sampling the current on the load, and generating a bias current according to the sampled current;
  • the clock signal generating module is used to generate a clock signal according to the bias current
  • the charge and discharge control module is used to control one of the first capacitor and the second capacitor to charge, and the other to supply power to the load according to the clock signal.
  • the bias current generation module samples the current on the load and generates the bias current according to the sampled current, and the clock signal generation module generates the clock according to the bias current
  • the current and bias current on the sampled load will change accordingly, so that the frequency of the generated clock signal will also change accordingly, so that the ripple voltage fluctuation range is relatively reduced or remains unchanged, thereby making The voltage fluctuation range on the load is reduced.
  • the embodiment of the present invention provides a charge pump circuit, which can be widely used in power transmitters, overvoltage protectors and signal transmission chips.
  • the charge pump circuit includes a clock signal generating module, The first capacitor C1, the second capacitor C2, the charge and discharge control module, and the bias current generation module.
  • bias current generating means for sampling the current on the load R L I L, and generates the bias current I IB_IN The sampled current I L; CLK clock signal generating means for generating a bias current I IB_IN The clock signal; discharge control module according to a charging clock signal to control the first capacitor C1 and second capacitor C2, the other power supply to the load L R.
  • the load R L is connected in parallel with the load capacitor C L ;
  • the bias current generation module includes a sampling resistor R SNS , a transconductance amplifier G M , a first transistor M1, a second transistor M2 and a fixed bias current source IB1.
  • R SNS sampling resistor in series with the load R L, for the current sampling load R L, and the current into a voltage; a is connected to one input terminal of the sampling resistor R SNS G M of the transconductance amplifier, the transconductance amplifier G M the other input terminal and the other end connected to the sampling resistor R SNS, G M transconductance amplifier for sampling resistor R SNS voltage into a current.
  • the first end of the first transistor M1 is connected to the first end of the second transistor M2, the gate of the first transistor M1 is connected to the gate of the second transistor M2, and the second end of the first transistor M1 is connected to the gate of the first transistor M1.
  • a first transistor M1 and the transistor M2 according to a second cross- G M output current amplifier produces a mirror current I ACT, current I L on the mirror current I ACT positive correlation with the load R L.
  • bias current IB1 One end of the fixed bias current source IB1 is connected to the first end of the second transistor M2, and the other end of the fixed bias current source IB1 is connected to the second end of the second transistor M2, so that the output of the fixed bias current source IB1 is fixed
  • the clock signal generation module includes a comparator COMP, a first inverter INV1, a second inverter INV2, and a third capacitor C CLK ; the first input terminal of the comparator COMP is connected to The second end of the second transistor M2 is connected, the second input end of the comparator COMP is connected to the reference voltage V CLK , and the first input end of the comparator COMP is grounded through the third capacitor C CLK ; the output end of the comparator COMP passes through the first An inverter INV1 and a second inverter INV2 are connected to the output terminal of the clock signal generating module.
  • the power input terminals of the first inverter INV1 and the second inverter INV2 in FIG. 3 are connected to the power terminal V IN .
  • the first inverter INV1 and the second inverter The power input terminal of the phase inverter INV2 can also be connected to other power terminals, which will not be repeated here.
  • the charge and discharge control module includes a third inverter INV3, a fourth inverter INV4, a third transistor M3 to a sixth transistor M6; the input terminal of the third inverter INV3 and the clock signal
  • the output terminal of the generating module is connected, the output terminal of the third inverter INV3 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the gate of the third transistor M3;
  • the input of the fourth inverter INV4 The terminal is connected to the output terminal of the third inverter INV3, the output terminal of the fourth inverter INV4 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the gate of the fourth transistor M4;
  • the first end of the transistor M3 is connected to the first end of the fourth transistor M4, the second end of the third transistor M3 is connected to the gate of the fourth transistor M4, and the second end of the third transistor M3 is connected to the fifth transistor M5.
  • the first end is connected, the gate of the fifth transistor M5 is connected to the gate of the third transistor M3, the second end of the fifth transistor M5 is connected to the power supply terminal V IN ; the second end of the fourth transistor M4 is connected to the third transistor M3 The second end of the fourth transistor M4 is connected to the first end of the sixth transistor M6, the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4, and the second end of the sixth transistor M6 is connected to the The second end of the five transistor M5 is connected; the first end of the third transistor M3 is connected to the output end of the charge and discharge control module, and the output end of the charge and discharge control module is connected to the load RL .
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all PMOS transistors, and the fifth transistor M5 and the sixth transistor M6 are all NMOS transistors.
  • the embodiment of the present invention only uses this as an example for description, but it is not limited to this.
  • FIG. 4 is a ripple characteristic diagram of the output voltage V OUT1 of the conventional charge pump and the output voltage V OUT2 of the charge pump circuit provided by the embodiment of the present invention.
  • the frequency f CLK of the charge pump circuit provided by the embodiment will also become larger, and the output ripple will be reduced.
  • the load current IL suddenly becomes smaller, the frequency f CLK of the charge pump circuit provided by the embodiment of the present invention will also become smaller. The power consumption is reduced while the output ripple remains unchanged.
  • the embodiment of the present invention may be provided in the charge pump circuit CLK load R L size, or the size of the current I L in accordance with the load R L, the clock signal is dynamically adjusted in accordance with the frequency f, so as to reduce output ripple and improve
  • the overall efficiency of the charge pump circuit expands the application range of the charge pump circuit. Therefore, the charge pump circuit provided by the embodiment of the present invention has the characteristics of small output ripple, high efficiency and low power consumption.
  • the bias current generation module samples the current on the load and generates the bias current according to the sampled current.
  • the clock signal generation module generates the clock signal according to the bias current.
  • the embodiment of the present invention also provides a method for controlling the ripple voltage of a charge pump circuit, which is applied to the charge pump circuit provided in any of the above embodiments. As shown in FIG. 5, the method includes:
  • S101 Sampling the load current on the load connected to the charge pump circuit, and generating a bias current according to the sampled current;
  • S103 Control one of the first capacitor and the second capacitor in the charge pump circuit to charge, and the other to supply power to the load according to the clock signal.
  • the charge pump circuit includes a clock signal generation module, a first capacitor C1, a second capacitor C2, a charge and discharge control module, and a bias current generation module.
  • the bias current generating current on the load R L I L sampling module, and generating a bias current I L I IB_IN The sampled current.
  • Clock signal generating module generates the clock signal CLK in accordance with the bias current I IB_IN; discharge control module in accordance with a clock signal for controlling the charging of the first capacitor C1 and second capacitor C2, the other power supply to the load L R.
  • the step of sampling the load current on the load connected to the charge pump circuit and generating a bias current according to the sampled current includes:
  • the fixed bias current and the mirror current are superimposed to form the bias current.
  • bias current generator module comprises a sampling resistor R SNS, the transconductance amplifier G M, the first transistor M1, a second transistor M2, and a fixed bias current source IB1.
  • the clock signal generation module generates the clock signal CLK according to the bias current I IB_IN .
  • the clock signal CLK is at a high level
  • the clock signal CLK1 output by the third inverter INV3 is at a low level
  • the clock signal CLK2 output by the fourth inverter INV4 is at a high level.
  • V A1 V IN
  • V A2 2V IN
  • the sixth transistor M6 is turned on, pulling the voltage of the node A1 to V IN , such that the fifth transistor M5 is turned off, the third transistor M3 is turned on, the fourth transistor M4 is turned off, this time, the second capacitor C2 through the third transistor M3 power to the load L R, V IN terminal to the second through the sixth transistor M6 A capacitor C1 is charged.

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Abstract

一种电荷泵电路以及控制该电荷泵电路的纹波电压的方法，其中电荷泵电路包括时钟信号产生模块、第一电容、第二电容、充放电控制模块和偏置电流产生模块；所述偏置电流产生模块用于采样负载上的电流，并根据所述采样的电流产生偏置电流；所述时钟信号产生模块用于根据所述偏置电流产生时钟信号；所述充放电控制模块用于根据所述时钟信号控制所述第一电容和所述第二电容中的一个充电、另一个对所述负载供电。当负载变化时，采样的负载上的电流和偏置电流会相应变化，使得产生的时钟信号的频率也会相应变化，从而使得纹波电压波动范围相对减小或维持不变，进而使得负载上的电压波动范围减小。

Description

一种电荷泵电路以及控制电荷泵电路的纹波电压的方法
本申请要求于2019年01月22日提交中国专利局、申请号为CN201910056713.2、发明名称为“一种电荷泵电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电荷泵技术领域，更具体地说，涉及一种电荷泵电路以及控制电荷泵电路的纹波电压的方法。
背景技术
电荷泵是集成电路系统中常用的模块之一，它利用电容两端电压不能突变的原理，使得输出电压实现对输入参考电压倍压增大的功能，同时轮流对输出负载进行放电。电荷泵由于具有面积小、结构简单、无需片外元器件的优点，因此，已经成为许多片内高压系统的供电模块。但是，现有的电荷泵中，当电荷泵的负载减小时，电荷泵输出产生的纹波电压会增大，导致负载上的电压波动太大，影响输出级的稳定性，极大地限制了电荷泵的应用范围。
发明内容
有鉴于此，本发明提供了一种电荷泵电路，以解决现有的电荷泵负载上的电压波动太大的问题。
为实现上述目的，本发明提供如下技术方案：
一种电荷泵电路，包括时钟信号产生模块、第一电容、第二电容、充放电 控制模块和偏置电流产生模块；
所述偏置电流产生模块用于采样负载上的电流，并根据所述采样的电流产生偏置电流；
所述时钟信号产生模块用于根据所述偏置电流产生时钟信号；
所述充放电控制模块用于根据所述时钟信号控制所述第一电容和所述第二电容中的一个充电、另一个对所述负载供电。
可选地，所述偏置电流产生模块包括采样电阻、跨导放大器、第一晶体管、第二晶体管以及固定偏置电流源；
所述采样电阻与所述负载串联，用于采样所述负载上的电流，并将所述电流转换为电压；
所述跨导放大器的一个输入端与所述采样电阻的一端相连，所述跨导放大器的另一个输入端与所述采样电阻的另一端相连，所述跨导放大器用于将所述采样电阻的电压转换为电流；
所述第一晶体管的第一端与所述第二晶体管的第一端相连，所述第一晶体管的栅极与所述第二晶体管的栅极相连，所述第一晶体管的第二端与所述第一晶体管的栅极相连，且所述第一晶体管的第二端与所述跨导放大器的一个输出端相连，所述跨导放大器的另一个输出端接地；所述第一晶体管和所述第二晶体管用于根据所述跨导放大器输出的电流产生镜像电流；
所述固定偏置电流源的一端与所述第二晶体管的第一端相连，所述固定偏置电流源的另一端与所述第二晶体管的第二端相连，以使所述固定偏置电流源输出的固定偏置电流与所述镜像电流叠加形成所述偏置电流。
可选地，所述第一晶体管和所述第二晶体管为PMOS晶体管。
可选地，所述时钟信号产生模块包括比较器、第一反相器、第二反相器和第三电容；
所述比较器的第一输入端与所述第二晶体管的第二端相连，所述比较器的第二输入端与参考电压相连，且所述比较器的第一输入端通过所述第三电容接地；
所述比较器的输出端通过所述第一反相器和所述第二反相器与所述时钟信号产生模块的输出端相连。
可选地，所述充放电控制模块包括第三反相器、第四反相器、第三晶体管至第六晶体管；
所述第三反相器的输入端与所述时钟信号产生模块的输出端相连，所述第三反相器的输出端与所述第一电容的一端相连，所述第一电容的另一端与所述第三晶体管的栅极相连；
所述第四反相器的输入端与所述第三反相器的输出端相连，所述第四反相器的输出端与所述第二电容的一端相连，所述第二电容的另一端与所述第四晶体管的栅极相连；
所述第三晶体管的第一端与所述第四晶体管的第一端相连，所述第三晶体管的第二端与所述第四晶体管的栅极相连，且所述第三晶体管的第二端与第五晶体管的第一端相连，所述第五晶体管的栅极与所述第三晶体管的栅极相连，所述第五晶体管的第二端与电源端相连；
所述第四晶体管的第二端与所述第三晶体管的栅极相连，所述第四晶体管的第二端与所述第六晶体管第一端相连，所述第六晶体管的栅极与所述第四晶体管的栅极相连，所述第六晶体管的第二端与所述第五晶体管的第二端相连；
所述第三晶体管的第一端与所述充放电控制模块的输出端相连，所述充放电控制模块的输出端与所述负载相连。
可选地，所述第三晶体管和所述第四晶体管为PMOS晶体管，所述第五晶体管和所述第六晶体管为NMOS晶体管。
一种控制电荷泵电路的纹波电压的方法，应用于如上任一项所述的电荷泵电路，包括：
采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流；
根据所述偏置电流产生时钟信号；
根据所述时钟信号控制电荷泵电路中的第一电容和第二电容中的一个充电、另一个对所述负载供电。
可选地，所述采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流的步骤包括：
通过采样电阻采样所述负载上的负载电流，并将所述负载电流转换为采样电阻电压；
对所述采样电阻电压进行转换，得到转换电流，并根据所述转换电流得到镜像电流，所述镜像电流与所述负载电流正相关；
将固定偏置电流与所述镜像电流叠加形成所述偏置电流。
与现有技术相比，本发明所提供的技术方案具有以下优点：
本发明所提供的电荷泵电路以及控制电荷泵电路的纹波电压的方法，偏置电流产生模块采样负载上的电流，并根据采样的电流产生偏置电流，时钟信号产生模块根据偏置电流产生时钟信号，当负载变化时，采样的负载上的电流和 偏置电流会相应变化，使得产生的时钟信号的频率也会相应变化，从而使得纹波电压波动范围相对减小或维持不变，进而使得负载上的电压波动范围减小。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为现有的一种电荷泵的结构示意图；
图2为本发明实施例提供的一种电荷泵电路的结构示意图；
图3为本发明实施例提供的一种电荷泵电路和时钟信号产生模块的结构示意图；
图4为本发明实施例提供的输出电压的纹波特性图；
图5为本发明实施例提供的一种控制电荷泵电路的纹波电压的方法的流程示意图。
具体实施方式
正如背景技术所述，现有的电荷泵中，当电荷泵的负载减小时，电荷泵输出产生的纹波电压会增大，导致负载上的电压波动太大。发明人研究发现，造成这种问题的原因主要是，现有的电荷泵中的时钟信号产生模块产生的时钟信号的周期都是固定的。
如图1所示，时钟信号产生模块是根据固定偏置电流源IB输出的固定电 流产生的固定周期的信号来作为时钟信号CLK的，当时钟信号CLK为高电平时，CLK1为低电平，CLK2为高电平。因为第一电容C1和第二电容C2两端的电压不能突变，因此，节点A1的电压V A1＝V IN，节点A2的电压V A2＝2V IN，此时，晶体管MN2导通，将节点A1的电压(即晶体管MN1的栅极)拉至V IN，使得晶体管MN1关断，晶体管MP1导通，晶体管MP2关断，此时，第二电容C2通过晶体管MP1向负载R L供电，V IN端通过晶体管MN2向第一电容C1充电；当时钟信号CLK为低电平时，CLK1为高电平，CLK2为低电平，此时，V A1＝2V IN，V A2＝V IN，晶体管MN1开启，将晶体管MP2的栅极(即节点A2的电压)拉至V IN，使得晶体管MP2导通，第一电容C1通过晶体管MP2向负载R L供电。
由此可知，输出电压
Figure PCTCN2020072162-appb-000001
因为电荷泵是利用电容充放电对负载进行供电，因此，充放电的过程会使输出电压V OUT产生纹波，即产生纹波电压V ripple，且
Figure PCTCN2020072162-appb-000002
由于时钟信号CLK的时钟周期f为固定值，因此，当负载R L固定时，负载R L上的电流I L是固定值，根据上述公式可知，纹波电压V ripple也是固定值。但是，当负载R L变小、负载R L上的电流I L变大时，纹波电压V ripple也会变大，导致负载R L上的电压波动太大。
基于此，本发明提供了一种电荷泵电路以及控制电荷泵电路的纹波电压的方法，以克服现有技术存在的上述问题，该电荷泵电路包括时钟信号产生模块、第一电容、第二电容、充放电控制模块和偏置电流产生模块；
所述偏置电流产生模块用于采样负载上的电流，并根据所述采样的电流产 生偏置电流；
所述时钟信号产生模块用于根据所述偏置电流产生时钟信号；
所述充放电控制模块用于根据所述时钟信号控制所述第一电容和所述第二电容中的一个充电、另一个对所述负载供电。
本发明提供的电荷泵电路以及控制电荷泵电路的纹波电压的方法，偏置电流产生模块采样负载上的电流，并根据采样的电流产生偏置电流，时钟信号产生模块根据偏置电流产生时钟信号，当负载变化时，采样的负载上的电流和偏置电流会相应变化，使得产生的时钟信号的频率也会相应变化，从而使得纹波电压波动范围相对减小或维持不变，进而使得负载上的电压波动范围减小。
以上是本发明的核心思想，为使本发明的上述目的、特征和优点能够更加明显易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种电荷泵电路，该电荷泵电路可广泛应用于功率传输器、过压保护器和信号传输芯片中，如图2所示，该电荷泵电路包括时钟信号产生模块、第一电容C1、第二电容C2、充放电控制模块和偏置电流产生模块。
其中，偏置电流产生模块用于采样负载R L上的电流I L，并根据采样的电流I L产生偏置电流I IB_IN；时钟信号产生模块用于根据偏置电流I IB_IN产生时钟信号CLK；充放电控制模块用于根据时钟信号控制第一电容C1和第二电容C2中的一个充电、另一个对负载R L供电。
本发明实施例中，负载R L与负载电容C L并联；偏置电流产生模块包括采样电阻R SNS、跨导放大器G M、第一晶体管M1、第二晶体管M2以及固定偏置电流源IB1。
采样电阻R SNS与负载R L串联，用于采样负载R L上的电流，并将电流转换为电压；跨导放大器G M的一个输入端与采样电阻R SNS的一端相连，跨导放大器G M的另一个输入端与采样电阻R SNS的另一端相连，跨导放大器G M用于将采样电阻R SNS的电压转换为电流。
第一晶体管M1的第一端与第二晶体管M2的第一端相连，第一晶体管M1的栅极与第二晶体管M2的栅极相连，第一晶体管M1的第二端与第一晶体管M1的栅极相连，且第一晶体管M1的第二端与跨导放大器G M的一个输出端相连，跨导放大器G M的另一个输出端接地；第一晶体管M1和第二晶体管M2用于根据跨导放大器G M输出的电流产生镜像电流I ACT，该镜像电流I ACT与负载R L上的电流I L正相关。
固定偏置电流源IB1的一端与第二晶体管M2的第一端相连，固定偏置电流源IB1的另一端与第二晶体管M2的第二端相连，以使固定偏置电流源IB1输出的固定偏置电流I B1与镜像电流I ACT叠加形成偏置电流I IB_IN＝I B1+I ACT。
本发明实施例中，如图3所示，时钟信号产生模块包括比较器COMP、第一反相器INV1、第二反相器INV2和第三电容C CLK；比较器COMP的第一输入端与第二晶体管M2的第二端相连，比较器COMP的第二输入端与参考电压V CLK相连，且比较器COMP的第一输入端通过第三电容C CLK接地；比较器COMP的输出端通过第一反相器INV1和第二反相器INV2与时钟信号产生模块的输出端相连。
需要说明的是，图3中第一反相器INV1和第二反相器INV2的电源输入端与电源端V IN相连，当然，本发明实施例中，第一反相器INV1和第二反相器INV2的电源输入端也可以与其他电源端相连，在此不再赘述。
如图2和图3所示，充放电控制模块包括第三反相器INV3、第四反相器INV4、第三晶体管M3至第六晶体管M6；第三反相器INV3的输入端与时钟信号产生模块的输出端相连，第三反相器INV3的输出端与第一电容C1的一端相连，第一电容C1的另一端与第三晶体管M3的栅极相连；第四反相器INV4的输入端与第三反相器INV3的输出端相连，第四反相器INV4的输出端与第二电容C2的一端相连，第二电容C2的另一端与第四晶体管M4的栅极相连；第三晶体管M3的第一端与第四晶体管M4的第一端相连，第三晶体管M3的第二端与第四晶体管M4的栅极相连，且第三晶体管M3的第二端与第五晶体管M5的第一端相连，第五晶体管M5的栅极与第三晶体管M3的栅极相连，第五晶体管M5的第二端与电源端V IN相连；第四晶体管M4的第二端与第三晶体管M3的栅极相连，第四晶体管M4的第二端与第六晶体管M6第一端相连，第六晶体管M6的栅极与第四晶体管M4的栅极相连，第六晶体管M6的第二端与第五晶体管M5的第二端相连；第三晶体管M3的第一端与充放电控制模块的输出端相连，充放电控制模块的输出端与负载R L相连。
需要说明的是，本发明实施例中，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4都为PMOS晶体管，第五晶体管M5和第六晶体管M6都为NMOS晶体管。当然，本发明实施例中仅以此为例进行说明，但并不仅限于此。
当时钟信号CLK为高电平时，第三反相器INV3输出的时钟信号CLK1 为低电平，第四反相器INV4输出的时钟信号CLK2为高电平。因为第一电容C1和第二电容C2两端的电压不能突变，因此，V A1＝V IN，V A2＝2V IN，此时，第六晶体管M6导通，将节点A1的电压拉至V IN，使得第五晶体管M5关断，第三晶体管M3导通，第四晶体管M4关断，此时，第二电容C2通过第三晶体管M3向负载R L供电，V IN端通过第六晶体管M6向第一电容C1充电。
当时钟信号CLK为低电平时，第三反相器INV3输出的时钟信号CLK1为高电平，第四反相器INV4输出的时钟信号CLK2为低电平，此时，V A1＝2V IN，V A2＝V IN，第五晶体管M5开启，将第四晶体管M4的栅极拉至V IN，使得第四晶体管M4导通，第一电容C1通过第四晶体管M4向负载R L供电。
设N为第一晶体管M1或第二晶体管M2的宽长比，则镜像电流I ACT＝N*I L*R SNS*g m，其中，g m为跨导放大器G M的等效跨导。因此，时钟信号产生模块产生的时钟信号的频率
Figure PCTCN2020072162-appb-000003
其中，C CLK、V CLK、R SNS、g m、I B1和N都为固定值，电荷泵电路输出电压V OUT的纹波电压
Figure PCTCN2020072162-appb-000004
根据该公式可知，当负载R L减小时，采样的负载R L上的电流I L和偏置电流I IB_IN会增大，使得产生的时钟信号的频率f CLK也会增大，此时，第一电容和第二电容的充放电速度会加快，且纹波电压V ripple基本维持不变，波动范围相对于现有技术中的纹波电压V ripple的波动范围有所减小，进而使得负载R L上的电压波动波动范围减小。
当负载R L不变时，采样的负载R L上的电流I L和偏置电流I IB_IN不变，使得产生的时钟信号的频率f CLK也固定不变，纹波电压V ripple也固定不变。
当负载R L增大时，采样的负载R L上的电流I L和偏置电流I IB_IN减小，使得产生的时钟信号的频率f CLK减小，功耗降低，且纹波电压V ripple基本维持不变，进而使得负载R L上的电压波动范围减小。
参考图4，图4为传统的电荷泵的输出电压V OUT1和本发明实施例提供的电荷泵电路的输出电压V OUT2的纹波特性图，当负载电流I L突然变大时，本发明实施例提供的电荷泵电路的频率f CLK也会变大，输出纹波会减小，当负载电流I L突然变小时，本发明实施例提供的电荷泵电路的频率f CLK也会变小，功耗降低，同时输出纹波维持不变。
也就是说，本发明实施例提供的电荷泵电路可以根据负载R L大小，或者说根据负载R L上的电流I L大小，动态调整时钟信号的频率f CLK，从而减小输出纹波，提高电荷泵电路的整体效率，扩大电荷泵电路的应用范围。因此，本发明实施例提供的电荷泵电路具有输出纹波小、效率高和功耗低的特性。
本发明所提供的电荷泵电路，偏置电流产生模块采样负载上的电流，并根据采样的电流产生偏置电流，时钟信号产生模块根据偏置电流产生时钟信号，当负载变化时，采样的负载上的电流和偏置电流会相应变化，使得产生的时钟信号的频率也会相应变化，从而使得纹波电压波动范围减小或维持不变，进而使得负载上的电压波动范围减小。
本发明实施例还提供了一种控制电荷泵电路的纹波电压的方法，应用于如上任一实施例提供的电荷泵电路，如图5所示，该方法包括：
S101：采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流；
S102：根据所述偏置电流产生时钟信号；
S103：根据所述时钟信号控制电荷泵电路中的第一电容和第二电容中的一个充电、另一个对所述负载供电。
如图2所示，电荷泵电路包括时钟信号产生模块、第一电容C1、第二电容C2、充放电控制模块和偏置电流产生模块。其中，偏置电流产生模块采样负载R L上的电流I L，并根据采样的电流I L产生偏置电流I IB_IN。时钟信号产生模块根据偏置电流I IB_IN产生时钟信号CLK；充放电控制模块根据时钟信号控制第一电容C1和第二电容C2中的一个充电、另一个对负载R L供电。
可选地，所述采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流的步骤包括：
通过采样电阻采样所述负载上的负载电流，并将所述负载电流转换为采样电阻电压；
对所述采样电阻电压进行转换，得到转换电流，并根据所述转换电流得到镜像电流，所述镜像电流与所述负载电流正相关；
将固定偏置电流与所述镜像电流叠加形成所述偏置电流。
如图2所示，负载R L与负载电容C L并联；偏置电流产生模块包括采样电阻R SNS、跨导放大器G M、第一晶体管M1、第二晶体管M2以及固定偏置电流源IB1。
采样电阻R SNS与负载R L串联，采样电阻R SNS采样负载R L上的电流，并将电流转换为电压；跨导放大器G M将采样电阻R SNS的电压转换为电流即得到转换电流。第一晶体管M1和第二晶体管M2根据跨导放大器G M输出的转换电流产生镜像电流I ACT，该镜像电流I ACT与负载R L上的电流I L正相关。之后，固定偏置电流源IB1输出的固定偏置电流I B1与镜像电流I ACT叠加形成偏置电 流I IB_IN＝I B1+I ACT。
如图3所示，时钟信号产生模块根据偏置电流I IB_IN产生时钟信号CLK。当时钟信号CLK为高电平时，第三反相器INV3输出的时钟信号CLK1为低电平，第四反相器INV4输出的时钟信号CLK2为高电平。因为第一电容C1和第二电容C2两端的电压不能突变，因此，V A1＝V IN，V A2＝2V IN，此时，第六晶体管M6导通，将节点A1的电压拉至V IN，使得第五晶体管M5关断，第三晶体管M3导通，第四晶体管M4关断，此时，第二电容C2通过第三晶体管M3向负载R L供电，V IN端通过第六晶体管M6向第一电容C1充电。
当时钟信号CLK为低电平时，第三反相器INV3输出的时钟信号CLK1为高电平，第四反相器INV4输出的时钟信号CLK2为低电平，此时，V A1＝2V IN，V A2＝V IN，第五晶体管M5开启，将第四晶体管M4的栅极拉至V IN，使得第四晶体管M4导通，第一电容C1通过第四晶体管M4向负载R L供电。
设N为第一晶体管M1或第二晶体管M2的宽长比，则镜像电流I ACT＝N*I L*R SNS*g m，其中，g m为跨导放大器G M的等效跨导。因此，时钟信号产生模块产生的时钟信号的频率
Figure PCTCN2020072162-appb-000005
其中，C CLK、V CLK、R SNS、g m、I B1和N都为固定值，电荷泵电路输出电压V OUT的纹波电压
Figure PCTCN2020072162-appb-000006
根据该公式可知，当负载R L减小时，采样的负载R L上的电流I L和偏置电流I IB_IN会增大，使得产生的时钟信号的频率f CLK也会增大，此时，第一电容和第二电容的充放电速度会加快，且纹波电压V ripple基本维持不变，波动范围相对于现有技术中的纹波电压V ripple的波动范围有所减小，进而使得负载R L上的电 压波动波动范围减小。
当负载R L不变时，采样的负载R L上的电流I L和偏置电流I IB_IN不变，使得产生的时钟信号的频率f CLK也固定不变，纹波电压V ripple也固定不变。
当负载R L增大时，采样的负载R L上的电流I L和偏置电流I IB_IN减小，使得产生的时钟信号的频率f CLK减小，功耗降低，且纹波电压V ripple基本维持不变，进而使得负载R L上的电压波动范围减小。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (8)

  1. 一种电荷泵电路，其特征在于，包括时钟信号产生模块、第一电容、第二电容、充放电控制模块和偏置电流产生模块；
    所述偏置电流产生模块用于采样负载上的电流，并根据所述采样的电流产生偏置电流；
    所述时钟信号产生模块用于根据所述偏置电流产生时钟信号；
    所述充放电控制模块用于根据所述时钟信号控制所述第一电容和所述第二电容中的一个充电、另一个对所述负载供电。
  2. 根据权利要求1所述的电路，其特征在于，所述偏置电流产生模块包括采样电阻、跨导放大器、第一晶体管、第二晶体管以及固定偏置电流源；
    所述采样电阻与所述负载串联，用于采样所述负载上的电流，并将所述电流转换为电压；
    所述跨导放大器的一个输入端与所述采样电阻的一端相连，所述跨导放大器的另一个输入端与所述采样电阻的另一端相连，所述跨导放大器用于将所述采样电阻的电压转换为电流；
    所述第一晶体管的第一端与所述第二晶体管的第一端相连，所述第一晶体管的栅极与所述第二晶体管的栅极相连，所述第一晶体管的第二端与所述第一晶体管的栅极相连，且所述第一晶体管的第二端与所述跨导放大器的一个输出端相连，所述跨导放大器的另一个输出端接地；所述第一晶体管和所述第二晶体管用于根据所述跨导放大器输出的电流产生镜像电流；
    所述固定偏置电流源的一端与所述第二晶体管的第一端相连，所述固定偏置电流源的另一端与所述第二晶体管的第二端相连，以使所述固定偏置电流源 输出的固定偏置电流与所述镜像电流叠加形成所述偏置电流。
  3. 根据权利要求2所述的电路，其特征在于，所述第一晶体管和所述第二晶体管为PMOS晶体管。
  4. 根据权利要求2所述的电路，其特征在于，所述时钟信号产生模块包括比较器、第一反相器、第二反相器和第三电容；
    所述比较器的第一输入端与所述第二晶体管的第二端相连，所述比较器的第二输入端与参考电压相连，且所述比较器的第一输入端通过所述第三电容接地；
    所述比较器的输出端通过所述第一反相器和所述第二反相器与所述时钟信号产生模块的输出端相连。
  5. 根据权利要求4所述的电路，其特征在于，所述充放电控制模块包括第三反相器、第四反相器、第三晶体管至第六晶体管；
    所述第三反相器的输入端与所述时钟信号产生模块的输出端相连，所述第三反相器的输出端与所述第一电容的一端相连，所述第一电容的另一端与所述第三晶体管的栅极相连；
    所述第四反相器的输入端与所述第三反相器的输出端相连，所述第四反相器的输出端与所述第二电容的一端相连，所述第二电容的另一端与所述第四晶体管的栅极相连；
    所述第三晶体管的第一端与所述第四晶体管的第一端相连，所述第三晶体管的第二端与所述第四晶体管的栅极相连，且所述第三晶体管的第二端与第五晶体管的第一端相连，所述第五晶体管的栅极与所述第三晶体管的栅极相连，所述第五晶体管的第二端与电源端相连；
    所述第四晶体管的第二端与所述第三晶体管的栅极相连，所述第四晶体管的第二端与所述第六晶体管第一端相连，所述第六晶体管的栅极与所述第四晶体管的栅极相连，所述第六晶体管的第二端与所述第五晶体管的第二端相连；
    所述第三晶体管的第一端与所述充放电控制模块的输出端相连，所述充放电控制模块的输出端与所述负载相连。
  6. 根据权利要求5所述的电路，其特征在于，所述第三晶体管和所述第四晶体管为PMOS晶体管，所述第五晶体管和所述第六晶体管为NMOS晶体管。
  7. 一种控制电荷泵电路的纹波电压的方法，其特征在于，应用于权利要求1～6任一项所述的电荷泵电路，包括：
    采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流；
    根据所述偏置电流产生时钟信号；
    根据所述时钟信号控制电荷泵电路中的第一电容和第二电容中的一个充电、另一个对所述负载供电。
  8. 根据权利要求7所述的方法，其特征在于，所述采样电荷泵电路所接负载上的负载电流，根据所述采样的电流产生偏置电流的步骤包括：
    通过采样电阻采样所述负载上的负载电流，并将所述负载电流转换为采样电阻电压；
    对所述采样电阻电压进行转换，得到转换电流，并根据所述转换电流得到镜像电流，所述镜像电流与所述负载电流正相关；
    将固定偏置电流与所述镜像电流叠加形成所述偏置电流。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115882839A (zh) * 2022-12-19 2023-03-31 锐石创芯(深圳)科技股份有限公司 信号输出系统及电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109639135B (zh) * 2019-01-22 2024-03-01 上海艾为电子技术股份有限公司 一种电荷泵电路

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661894A (zh) * 2004-02-27 2005-08-31 恩益禧电子股份有限公司 电源电路
CN102055320A (zh) * 2011-01-24 2011-05-11 昆山睿识微电子有限公司 电荷泵电路及其实现方法
CN104052261A (zh) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 用于控制电荷泵的装置和方法
CN105634268A (zh) * 2016-01-15 2016-06-01 西安紫光国芯半导体有限公司 一种具有低纹波电压的电荷泵电源
US20160352217A1 (en) * 2015-05-28 2016-12-01 Sandisk Technologies Inc. Dynamic Clock Period Modulation Scheme for Variable Charge Pump Load Currents
US20180026527A1 (en) * 2016-07-25 2018-01-25 Taiwan Semiconductor Manufacturing Co., Inc. Regulated voltage systems and methods using intrinsically varied process characteristics
CN109639135A (zh) * 2019-01-22 2019-04-16 上海艾为电子技术股份有限公司 一种电荷泵电路
CN209184485U (zh) * 2019-01-22 2019-07-30 上海艾为电子技术股份有限公司 一种电荷泵电路

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815012A (en) * 1996-08-02 1998-09-29 Atmel Corporation Voltage to current converter for high frequency applications
EP0899643B1 (en) * 1997-08-29 2005-03-09 STMicroelectronics S.r.l. Low consumption linear voltage regulator with high supply line rejection
US6407623B1 (en) * 2001-01-31 2002-06-18 Qualcomm Incorporated Bias circuit for maintaining a constant value of transconductance divided by load capacitance
CN1252480C (zh) * 2001-04-05 2006-04-19 深圳赛意法微电子有限公司 低压电流检测放大器电路
US7324035B2 (en) * 2004-05-13 2008-01-29 University Of Florida Research Foundation, Inc. Amplifier with pulse coded output and remote signal reconstruction from the pulse output
TWI331266B (en) * 2006-09-18 2010-10-01 Analog Integrations Corp Current generating apparatus and feedback-controlled system utilizing the current generating apparatus
US20090251227A1 (en) * 2008-04-03 2009-10-08 Jasa Hrvoje Hery Constant gm oscillator
US7750837B2 (en) * 2008-08-01 2010-07-06 Qualcomm Incorporated Adaptive bias current generation for switched-capacitor circuits
US8212599B2 (en) * 2009-12-30 2012-07-03 Sandisk Technologies Inc. Temperature-stable oscillator circuit having frequency-to-current feedback
EP2372485B1 (en) * 2010-04-01 2014-03-19 ST-Ericsson SA Voltage regulator
JP2012161051A (ja) * 2011-02-03 2012-08-23 Sony Corp 周波数制御装置、周波数制御方法、クロック生成回路、電子機器、及び、プログラム
CN103023461A (zh) * 2011-09-28 2013-04-03 华润矽威科技（上海）有限公司 Rc振荡电路
CN102427359B (zh) * 2011-12-06 2014-03-26 四川和芯微电子股份有限公司 插值电路及插值系统
KR101356912B1 (ko) * 2012-01-27 2014-01-28 교통안전공단 가변 인덕턴스 회로장치 및 그 가변 인덕턴스 회로 장치를 이용한 자기장 무선통신 시스템
CN202748694U (zh) * 2012-06-15 2013-02-20 西安华迅微电子有限公司 一种实时时钟电路
CN104104331B (zh) * 2013-04-15 2018-12-14 深圳先进技术研究院 跨导增强电路单元及晶体振荡器电路
KR20150074651A (ko) * 2013-12-24 2015-07-02 삼성전기주식회사 전하 펌프 회로의 구동 회로 및 이를 포함하는 전하 펌프 시스템
CN203967961U (zh) * 2014-06-30 2014-11-26 成都芯源系统有限公司 跨导调整电路、跨导型误差放大单元及开关型功率变换器
US9325323B2 (en) * 2014-08-30 2016-04-26 Stmicroelectronics International N.V. CMOS oscillator having stable frequency with process, temperature, and voltage variation
CN104796171B (zh) * 2015-03-25 2018-09-11 广东拓思软件科学园有限公司 一种应用于soi cmos射频开关的控制电路
JP6510288B2 (ja) * 2015-03-30 2019-05-08 ローム株式会社 チャージポンプ回路
CN105207480B (zh) * 2015-09-21 2017-09-01 西安三馀半导体有限公司 一种轻载时低输出纹波的同步降压型dc‑dc转换器
CN106374881B (zh) * 2016-10-21 2023-10-31 深圳市汇春科技股份有限公司 一种快启动低功耗时钟振荡器
CN106712495B (zh) * 2016-12-29 2023-10-31 兆易创新科技集团股份有限公司 一种电荷泵电路
CN106658866B (zh) * 2017-02-09 2018-12-25 上海晶丰明源半导体股份有限公司 用于消除led驱动系统电流纹波的控制器、芯片和方法
CN108459651B (zh) * 2017-02-22 2021-01-08 上海莱狮半导体科技有限公司 恒流控制器及其功率调节电路
CN207200572U (zh) * 2017-08-01 2018-04-06 北京兆易创新科技股份有限公司 一种电荷泵电路
CN108418418B (zh) * 2018-03-06 2020-07-14 芯海科技（深圳）股份有限公司 用于mos管本体偏置的自适应双向电荷泵动态调节器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661894A (zh) * 2004-02-27 2005-08-31 恩益禧电子股份有限公司 电源电路
CN102055320A (zh) * 2011-01-24 2011-05-11 昆山睿识微电子有限公司 电荷泵电路及其实现方法
CN104052261A (zh) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 用于控制电荷泵的装置和方法
US20160352217A1 (en) * 2015-05-28 2016-12-01 Sandisk Technologies Inc. Dynamic Clock Period Modulation Scheme for Variable Charge Pump Load Currents
CN105634268A (zh) * 2016-01-15 2016-06-01 西安紫光国芯半导体有限公司 一种具有低纹波电压的电荷泵电源
US20180026527A1 (en) * 2016-07-25 2018-01-25 Taiwan Semiconductor Manufacturing Co., Inc. Regulated voltage systems and methods using intrinsically varied process characteristics
CN109639135A (zh) * 2019-01-22 2019-04-16 上海艾为电子技术股份有限公司 一种电荷泵电路
CN209184485U (zh) * 2019-01-22 2019-07-30 上海艾为电子技术股份有限公司 一种电荷泵电路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115882839A (zh) * 2022-12-19 2023-03-31 锐石创芯(深圳)科技股份有限公司 信号输出系统及电子设备

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