WO2020148879A1 - Semiconductor device, production method for semiconductor device, and power conversion device - Google Patents

Semiconductor device, production method for semiconductor device, and power conversion device Download PDF

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Publication number
WO2020148879A1
WO2020148879A1 PCT/JP2019/001378 JP2019001378W WO2020148879A1 WO 2020148879 A1 WO2020148879 A1 WO 2020148879A1 JP 2019001378 W JP2019001378 W JP 2019001378W WO 2020148879 A1 WO2020148879 A1 WO 2020148879A1
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WO
WIPO (PCT)
Prior art keywords
lead frame
semiconductor device
sealing member
bent portion
bent
Prior art date
Application number
PCT/JP2019/001378
Other languages
French (fr)
Japanese (ja)
Inventor
坂本　健
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2019/001378 priority Critical patent/WO2020148879A1/en
Priority to JP2020566062A priority patent/JP7053897B2/en
Priority to CN201980088014.4A priority patent/CN113261095A/en
Publication of WO2020148879A1 publication Critical patent/WO2020148879A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the present invention relates to a semiconductor device having a plurality of terminals arranged at a narrow pitch, a method for manufacturing the semiconductor device, and a power conversion device.
  • a semiconductor element of a type in which a conduction path is a vertical direction of the element for the purpose of responding to a high voltage or a large current is generally a power semiconductor element (for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Transistor)). , Bipolar transistors, diodes, etc.).
  • a power semiconductor element for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Transistor)). , Bipolar transistors, diodes, etc.
  • a semiconductor device in which a power semiconductor element is mounted on a circuit board and packaged with a sealing resin is used in a wide range of fields such as industrial equipment, automobiles, and railways.
  • a conventional package structure of a semiconductor device includes a mold sealing type.
  • a power semiconductor element is mounted on a lead frame, the power semiconductor element and a lead frame terminal are bonded by wire bonding, and the whole is epoxy.
  • the structure is sealed with resin.
  • a transfer molding method is used in which a lead frame is clamped by upper and lower molds and epoxy resin is injected into a cavity. After molding the resin by molding, the lead frame terminals protruding from the side surface of the package are bent to form the external terminal electrodes.
  • the resin is arranged below the bent portion of the terminal exposed from the side surface of the molding resin to secure the space distance.
  • the terminal arrangement on the side surface of the molding resin is ensured. Since only the portion is recessed, a recessed portion corresponding to the number of terminals is required.
  • the placement of the recesses formed on the side surface of the mold resin depends on the molding precision and strength of the mold, so when using multiple terminals on the same side surface, it is possible to use terminals with an arbitrary narrow pitch. However, there is a problem that it is difficult to reduce the size of the semiconductor device.
  • the present invention has been made to solve the above-mentioned problems, and it is possible to reduce the size of the lead frame terminal portion while ensuring the space distance between the lead frame terminal portion and the molding resin, which corresponds to the narrow pitch of the lead frame terminal interval.
  • the purpose is to obtain a good semiconductor device.
  • a semiconductor device has a semiconductor element, a mounting portion on which a semiconductor element is mounted, and a plurality of terminal portions which are provided above the mounting portion and are arranged in parallel at a distance and have a bent portion at one end.
  • the plurality of terminal portions are bent at the respective bent portions toward the upper surface side of the mounting portion, and the plurality of terminal portions are exposed from the side surfaces, and the side surfaces between the plurality of terminal portions are flat and above the bent portions.
  • a sealing member that is provided inside the inner surfaces of the plurality of terminal portions, is provided below the bent portion and is in contact with the lower portion of the bent portion to the outside of the bent portion, and integrally seals the semiconductor element and the metal member. It is a semiconductor device provided with.
  • the sealing member has a flat side surface between the plurality of terminal portions above the exposed bent portion and is provided inside the inner surfaces of the plurality of terminal portions, and below the bent portion, Since it is provided in contact with the lower part to the outside of the bent part, the pitch of the terminals exposed from the side surface of the sealing member can be narrowed while there is no space distance and the creepage distance is expanded, and the semiconductor device can be miniaturized. Is possible.
  • FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional structure diagram showing the semiconductor device in the first embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram showing another semiconductor device in the first embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end portion of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a schematic sectional structure view in which an outer peripheral end portion of another semiconductor device according to the first embodiment of the present invention is enlarged.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention.
  • FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention.
  • FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention.
  • FIG. 7 is a schematic sectional structure view showing another manufacturing step of the semiconductor device in the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram showing a semiconductor device according to a second embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram showing another semiconductor device in the second embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram showing a manufacturing step of the semiconductor device in the second embodiment of the present invention. It is a block diagram which shows the structure of the power converter system to which the power converter device in Embodiment 3 of this invention is applied.
  • FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional structure diagram showing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1 is a plan view of the semiconductor device 100 as viewed from above.
  • FIG. 2 is a schematic cross-sectional structure diagram taken along one-dot chain line AA in FIG.
  • a semiconductor device 100 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
  • the lead frame 3 has an upper surface and a lower surface, and the members included in the lead frame 3 also have an upper surface and a lower surface.
  • the upper surface corresponds to the inner surface and the lower surface corresponds to the outer surface due to the structure.
  • the outer shape of the sealing member 4 is different between the upper surface side and the lower surface side of the lead frame 3.
  • the outer shape of the sealing member 4 on the lower surface side of the lead frame 3 is larger than that of the sealing member 4 on the upper surface side of the lead frame 3 on the side surface side where the terminal portion 3e of the lead frame 3 is exposed (projected). ..
  • the sealing member 4 projects outward from the outer surface of the terminal portion 3e of the lead frame 3 on the lower surface side of the lead frame 3. Is provided.
  • the sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 on the upper surface side of the lead frame 3.
  • the side surface of the sealing member 4 from which the terminal portion 3e of the lead frame 3 is exposed has a flat shape (without unevenness) in the arrangement direction of the terminal portion 3e of the lead frame 3.
  • the plurality of terminal portions 3e of the lead frame 3 are arranged in parallel at intervals.
  • the side surface of the sealing member 4 between the adjacent terminal portions 3e of the plurality of terminal portions 3e of the lead frame 3 is a flat surface.
  • a plurality of terminal portions 3e of the lead frame 3 are exposed at the same height from the same side surface of the sealing member 4.
  • the lead frame 3 is provided between the plurality of terminal portions 3e of the lead frame 3.
  • the sealing member 4 for insulating between the plurality of terminal portions 3e is not provided.
  • the distance between the plurality of terminal portions 3e of the lead frame 3 can be determined by considering only the insulation distance between the terminal portions 3e of the adjacent lead frames 3, so that the semiconductor device 100 can be downsized.
  • the lead frame 3 is one in principle, but may be separated (a plurality may be provided).
  • the plurality of terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 which face each other, it is not necessarily required to be exposed from both side surfaces of the sealing member 4 which face each other, and at least the sealing member 4e. It suffices that the plurality of terminal portions 3e of the lead frame 3 be exposed from one side surface of No. 4 of FIG.
  • the lead frame 3 includes a plurality of members.
  • the lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, and a terminal portion 3e.
  • the semiconductor element 1 is mounted on the upper surface of the mounting portion 3 a of the lead frame 3.
  • a region extending continuously from the mounting portion 3a of the lead frame 3 to the upper side of the lead frame 3 is an inclined portion (first inclined portion) 3b.
  • the flat portion 3c is a region that is connected to the upper end of the first inclined portion 3b on the opposite side of the connection portion of the lead frame 3 with the mounting portion 3a and extends toward the outside of the sealing member 4.
  • the bent portion 3d is the portion of the lead frame 3 exposed from the sealing member 4 and the lead frame 3 is bent.
  • the region extending from the bent portion 3d of the lead frame 3 to the tip (the other end) of the lead frame 3 is the terminal portion 3e.
  • the terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portion 3d of the lead frame 3 is located at one end of the terminal portion 3e of the lead frame 3, the bent portion 3d is provided in the same number as the terminal portions 3e of the lead frame 3.
  • the flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3.
  • One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3.
  • a bent portion is provided at one end of the terminal portion 3e of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3.
  • the terminal portion 3e of the lead frame 3 is bent at the bent portion toward the upper surface side of the mounting portion 3a of the lead frame 3.
  • a flat portion 3c on which the electronic component 2 is mounted is provided above the mounting portion 3a of the lead frame 3 so as to be separated from the mounting portion 3a of the lead frame 3 on which the semiconductor element 1 is mounted.
  • the bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3.
  • the terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3.
  • the regions of these lead frames 3 are electrically connected by using bonding wires 6 and the like as necessary.
  • a plurality of flat portions 3c of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3. Since one end of the flat portion 3c of the lead frame 3 is not necessarily connected to the first inclined portion 3b of the lead frame 3, the number of the first inclined portions 3b of the lead frame 3 is the same as that of the lead frame 3. Is less than the number of flat portions 3c.
  • the lead frame 3 may be configured such that the mounting portion 3a of the lead frame 3 is directly connected to the flat portion 3c of the lead frame 3 without providing the first inclined portion 3b of the lead frame 3.
  • the terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 which are both sides of the mounting portion 3a of the lead frame 3, and the respective terminal portions 3e of the lead frame 3 are sealed by the sealing member 4. Is bent toward the upper surface side of. A sealing member 4 is provided below the bent portion 3d of the lead frame 3.
  • the thickness of the lead frame 3 can be appropriately selected from 0.1 mm to 1 mm in accordance with the value of the current flowing through the terminal portion 3e by stably manufacturing the lead frame 3 by pressing. Since the lead frame 3 is basically manufactured by pressing a plate-shaped member, each member has a uniform thickness. However, in the plurality of members of the lead frame 3, the lead frame 3 may have different thicknesses depending on the functions of the members. In particular, the thickness related to the regulation of the outer peripheral position of the sealing member 4 is the thickness of the terminal portion 3e of the lead frame 3. The terminal portion 3e of the lead frame 3 has a uniform thickness.
  • the semiconductor element 1 generally, a power semiconductor element such as an IGBT, MOSFET, bipolar transistor or diode can be used.
  • a material of the semiconductor element silicon (Si: Silicon) or silicon carbide (SiC: Silicon carbide) or the like can be used.
  • the semiconductor element 1 is joined to a predetermined position of the mounting portion 3a of the lead frame 3 by using solder or the like (not shown) which is a joining member.
  • an IC (Integrated Circuit) element As the electronic component 2, an IC (Integrated Circuit) element, a resistor, a capacitor or the like can be used.
  • the electronic component 2 is bonded to a predetermined position of the flat portion 3c of the lead frame 3 using a resin paste or the like (not shown) which is a bonding member.
  • Bonding wire 6 connects lead frame 3 and semiconductor element 1.
  • the bonding wire 6 connects the plurality of semiconductor elements 1 to each other. Furthermore, the bonding wire 6 connects the semiconductor element 1 and the electronic component 2.
  • the bonding wire 6 When the bonding wire 6 is used for connection with the semiconductor element 1, the bonding wire 6 is generally not high in electrical conductivity for connection with a member of the semiconductor element 1 through which a large current flows. Inexpensive aluminum (Al) is selected, and the diameter is about 0.1 to 0.5 mm, and the pad on the lead frame 3 and the bonding portion of the semiconductor element 1 are ultrasonically bonded. Further, when the bonding wire 6 is used for connection with a member other than the semiconductor element 1 through which a large current flows or the electronic component 2, the material of the bonding wire 6 is selected from those having high electric conductivity such as gold, silver and copper. Then, it is finely processed to have a diameter of 0.05 mm or less, and wire bonding is performed on a small pad on the semiconductor element 1 or the electronic component 2.
  • Inexpensive aluminum (Al) is selected, and the diameter is about 0.1 to 0.5 mm, and the pad on the lead frame 3 and the bonding portion of the semiconductor element 1 are ultrasonically bonded
  • the sealing member 4 ensures the insulation between the sealed members and also functions as a case of the semiconductor device 100.
  • the sealing member 4 integrally seals the semiconductor element 1 mounted on the lead frame 3, the electronic component 2 mounted on the lead frame 3, the bonding wire 6 and the lead frame 3.
  • the outer peripheral position (size) of the sealing member 4 is different between the upper surface side of the lead frame 3 and the lower surface side of the lead frame 3.
  • the outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is a position sandwiched by the terminal portions 3e of each (both sides) of the facing lead frame 3 exposed from the respective facing side surfaces of the sealing member 4. ..
  • the outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is on the inner peripheral side of the inner surface of each terminal portion 3e of the opposing lead frame 3 exposed from the respective opposing side surfaces of the sealing member 4 ( Inside).
  • the outer peripheral position of the sealing member 4 on the lower surface side of the lead frame 3 is on the outer peripheral side (outer side) than the outer surface of each terminal portion 3e of the opposing lead frame 3 exposed from each side surface of the sealing member 4 facing each other. ).
  • the sealing member 4 is below the bent portion 3d of the lead frame 3 and leads from the outer surface of the terminal portion 3e of the lead frame 3.
  • the frame 3 is provided so as to project outward by more than the thickness of the frame 3.
  • the sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 above the bent portion 3d of the lead frame 3. Further, the sealing member 4 is provided directly below the bent portion 3d of the lead frame 3 and is provided up to the outside of the bent portion 3d of the lead frame 3.
  • the upper surface of the sealing member 4 is provided above the upper surface of the flat portion 3c of the lead frame 3. Even when the bent portion 3d of the lead frame 3 is replaced with the flat portion 3c of the lead frame 3, the sealing member 4 has the same arrangement relationship.
  • thermosetting epoxy resin is generally used as the material of the sealing member 4. This thermosetting epoxy resin is filled with silicon dioxide (SiO 2 ) and has a linear expansion coefficient close to that of copper.
  • an insulating heat dissipation material such as aluminum nitride (AlN), boron nitride (BN) or silicon dioxide (SiO 2 ) which is a high heat dissipation filler. It is also possible to apply a sheet body having a thickness of 0.1 mm to 0.3 mm with an epoxy resin filled with) to improve heat dissipation while maintaining insulation.
  • a high heat dissipation insulating material such as aluminum nitride (AlN), silicon nitride (SiN), silicon dioxide (SiO 2 ) or a DBC (Direct Bonded Copper) substrate formed by combining these high heat dissipation insulating materials is applied.
  • AlN aluminum nitride
  • SiN silicon nitride
  • SiO 2 silicon dioxide
  • DBC Direct Bonded Copper
  • FIG. 3 is a schematic sectional view showing another semiconductor device according to the first embodiment of the present invention.
  • a semiconductor device 200 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
  • the difference between the semiconductor device 100 and the semiconductor device 200 shown in FIG. 2 is the position of the outer peripheral end of the sealing member 4 on the lower surface side of the lead frame 3.
  • the outer peripheral end position of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the same position as the outer surface of the terminal portion 3e of the lead frame 3 in the bent portion 3d of the lead frame 3. ing.
  • the outer peripheral end position of the sealing member 4 above the bent portion 3d of the lead frame 3 is equal to the thickness of the lead frame 3 than the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3. Only provided inside. Since the other points are similar to those of the semiconductor device 100, detailed description thereof will be omitted.
  • FIG. 4 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end of another semiconductor device according to the first embodiment of the present invention.
  • a heat dissipation member 9 is provided on the lower surface side of the sealing member 4 on the lower surface side of the lead frame 3.
  • the heat dissipation member 9 is generally made of a metal material such as copper or aluminum.
  • the path indicated by the arrow in FIGS. 4 and 5 is the creepage distance 8 between the lead frame 3 and the heat dissipation member 9.
  • the sealing member 4 is provided directly on the lower surface of the bent portion 3d of the lead frame 3. Therefore, even when the semiconductor devices 100 and 200 are arranged on the heat dissipation member 9 by being tightened with screws or the like, it is possible to eliminate the spatial distance from the lower portion of the bent portion 3d of the lead frame 3 to the upper surface of the heat dissipation member 9, The sealing member 4 enables insulation protection.
  • the creepage distance 8 is also increased, even if dust, contaminants or moisture penetrate between the lower region of the bent portion 3d of the lead frame 3 and the heat dissipation member 9, it is possible to withstand the insulation failure of tracking. It is possible to achieve high pollution resistance according to the international standard IEC60664-1 and improve the reliability life of the semiconductor device. Further, the insulation characteristics and the contamination degree of the semiconductor device can be made equal to those of the case type semiconductor device in which the terminal for external connection is inserted or outsert in the case member.
  • the sealing member 4 is arranged in contact with the lower portion of the bent portion 3d of the lead frame 3, so that the heat dissipation member 9 is arranged on the lower surface side of the semiconductor devices 100 and 200. It is possible to eliminate the spatial distance and secure the creepage distance. Further, in the semiconductor devices 100 and 200, the side surface of the sealing member 4 between the exposed terminal portions 3e of the lead frame 3 is made flat (without unevenness) in the arrangement direction of the terminal portions 3e of the lead frame 3, so that a plurality of The distance between the terminal portions 3e of the lead frame 3 can be shortened, and the semiconductor devices 100 and 200 can be downsized.
  • FIG. 6 to 9 are schematic cross-sectional structure diagrams showing each manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a schematic plan view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a schematic sectional structure view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 8 is a schematic plan view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 9 is a schematic sectional structure view showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. Through these steps, the semiconductor device 100 shown in FIG. 2 can be manufactured.
  • the semiconductor element 1 and the electronic component 2 are prepared and, as shown in FIG. 6, at a predetermined position of the mounting portion 3a on the upper surface side of the lead frame 3 which is processed into a predetermined shape and has an upper surface and a lower surface.
  • the semiconductor element 1 is mounted, and the electronic component 2 is mounted at a predetermined position on the flat portion 3c of the lead frame 3.
  • the semiconductor element 1 is bonded to the mounting portion 3a of the lead frame 3 via solder.
  • the electronic component 2 is joined to the flat portion 3c of the lead frame 3 via a resin paste.
  • the semiconductor element 1, the electronic component 2, and the lead frame 3 provided at predetermined positions of the mounting portion 3a or the flat portion 3c of the lead frame 3 are connected by a bonding wire 6 having a diameter according to the purpose and wired (semiconductor Element mounting process).
  • the lead frame 3 on which the semiconductor element 1 and the electronic component 2 are mounted is placed in the mold 20 (metal member placement step).
  • the mold 20 includes an upper mold 10 and a lower mold 11.
  • the terminal portion 3e side the region exposed from the sealing member 4
  • the lead frame 3 is formed in the space 40 in the die 20. keeping.
  • the upper mold 10 at least the side surface (inner wall) sandwiching the terminal portion 3e from the flat portion 3c of the lead frame 3 is flat (no unevenness) in the arrangement direction of the terminal portion 3e of the lead frame 3.
  • the inner wall of the upper die 10 between the plurality of terminal portions 3e of the lead frame 3 is flat.
  • the inner side wall of the upper die 10 is provided inside the inner side wall of the lower die 11.
  • the inner side wall of the lower mold 11 is provided outside the inner side wall of the upper mold 10.
  • the difference between the inner side wall of the upper die 10 and the inner side wall of the lower die 11 is equal to or more than the thickness of the lead frame 3.
  • the bent portion 3d of the lead frame 3 projects from the outer peripheral region of the sealing member 4 ( Since the lower surface side of is exposed), a spatial distance is generated.
  • the sealing member 4 can be arranged below the bent portion 3d of the lead frame 3 and the generation of the spatial distance can be suppressed. ..
  • the space 40 of the mold 20 in which the lead frame 3 is arranged is filled with the sealing member 4 to integrally seal the lead frame 3 (sealing step).
  • the sealing member 4 is filled in the mold 20 according to the shape of the mold 20. Generally, it is molded using a transfer molding method. After the sealing member 4 is filled in the mold 20, the filled sealing member 4 is cured.
  • the upper surface of the sealing member 4 is provided above the bent portion 3d of the lead frame 3 formed around the lower surface of the inner wall of the upper mold 10.
  • the lead frame 3 sealed with the sealing member 4 is taken out from the mold 20 (metal member taking-out step).
  • the respective terminal portions 3e of the lead frame 3 exposed from the side surface side of the sealing member 4 are bent by the bent portions 3d provided on both sides of the lead frame 3 so that the upper surfaces of the lead frames 3 face each other. Bending (bending) (metal member processing step).
  • the semiconductor device 100 shown in FIG. 2 can be manufactured through the above steps.
  • FIG. 10 is a schematic sectional structure enlarged view of the outer peripheral end showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end showing the manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 12 is a schematic sectional structure enlarged view of an outer peripheral end showing another manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a schematic sectional structure view showing a manufacturing process of the semiconductor device in the first embodiment of the present invention.
  • FIG. 14 is a schematic sectional structure view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • a mold release is performed on the lower surface side of the lead frame 3 in a region including the bent portion 3d between the other end of the flat portion 3c on the lower surface side of the lead frame 3 and the terminal portion 3e.
  • a plating film 12 that is a member is provided.
  • the plating film 12 on the lower surface side of the lead frame 3 is provided in a region in contact with the sealing member 4.
  • the lead frame 3 is bent at the bent portion 3d toward the upper surface side of the mounting portion 3a of the lead frame 3.
  • the plating film 12 is separated from the sealing member 4 on the outer surface side of the terminal portion 3e of the lead frame 3, but the region of the bent portion 3d of the lead frame 3 corresponding to the thickness of the lead frame 3 is in contact with the sealing member 4. It is still done.
  • the plating film 12 has the same width as the width of the lead frame 3, is provided on the lower surface side of the lead frame 3 exposed from the sealing member 4, and is in contact with the sealing member 4.
  • the region of the lead frame 3 exposed from the side surface of the sealing member 4 on the upper surface side of the lead frame 3 is bent at the bent portion 3d.
  • the mounting portion 3a is bent toward the upper surface side (the terminal portion 3e of the lead frame 3 is directed toward the side surface of the sealing member 4).
  • the plating film 12 is formed in the area on the lower surface side of the lead frame 3, the adhesive force between the area on the lower surface side of the lead frame 3 on which the plating film 12 is formed and the sealing member 4 is small. Since it becomes weaker than the adhesive force of the region where the plating film 12 is not formed, the lead frame 3 and the sealing member 4 can be easily separated.
  • the peeling process of the lead frame 3 from the sealing member 4 is performed immediately after the molding of the sealing member 4, and the curing of the sealing member 4 is not sufficient. It is effective to carry out when the adhesive force with 4 is small.
  • a suppressing jig that suppresses the upper surface side of the lead frame 3 may be used, but in this case, the upper surface of the sealing member 4 is used.
  • a gap 3g corresponding to the size (thickness) of the holding jig is formed between the side surface on the side and the upper surface side of the lead frame 3.
  • the position of the side surface (outer peripheral end) of the sealing member 4 on which the lead frame 3 on the upper surface side of the lead frame 3 is exposed is provided inside the inner surface of the terminal portion 3e of the lead frame 3 by a gap 3g.
  • holes 13 which are holes penetrating the lead frame 3 and the plated film 12 may be provided in the region of the lead frame 3 where the plated film 12 is formed.
  • the holes 13 may be provided with only the holes 13 without providing the plating film 12.
  • the semiconductor device 200 is manufactured by using the upper mold 10 in which the position of the inner wall of the upper mold 10 shown in FIG. 7 is closer to the position of the inner wall of the lower mold 11 (expanded to the outer peripheral side). Is possible.
  • the inner side wall of the lower die 11 is provided outside the inner side wall of the upper die 10 by the thickness of the lead frame 3.
  • the sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 are provided. Since the side surface of the sealing member 4 between them is made flat, the pitch of the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed while there is no space distance and the creepage distance is increased. Therefore, the semiconductor devices 100 and 200 can be downsized.
  • the sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the side surface of the sealing member 4 exposed between the plurality of terminal portions 3e of the lead frame 3 is flattened. Therefore, there is no space distance and the creepage distance can be expanded, and the withstand voltage from the exposed portion of the lead frame 3 from the sealing member 4 to the heat dissipation member 9 is improved. Therefore, an insulating sheet is added to the lead frame 3 and the heat dissipation member. The inverter design can be facilitated without the trouble of shielding 9 and 9.
  • the sealing member 4 is arranged below the bent portion 3d of the lead frame 3, the creeping distance 8 can be increased, and dust and contaminants can be provided between the exposed portion of the lead frame 3 and the heat dissipation member 9. Even if moisture or moisture intrudes, the tracking insulation failure can be endured, and the reliability of the semiconductor devices 100 and 200 can be improved.
  • Embodiment 2 the height of the upper surface of the sealing member 4, which is the height of the sealing member 4 on the upper surface side of the lead frame 3 used in the first embodiment, is reduced so that the lead frame 3 has a second height.
  • the difference is that the inclined portion 3f is provided.
  • the semiconductor device since the height of the upper surface of the sealing member 4, which is the upper surface side of the lead frame 3, is reduced and the second inclined portion 3f is provided on the lead frame 3, the semiconductor device has no spatial distance and a creeping distance. While expanding, the semiconductor device can be downsized. Since the other points are the same as those in the first embodiment, detailed description thereof will be omitted.
  • the sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the sealing member 4 is exposed between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4. Since the side surfaces are flattened, the space between the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed while there is no space distance and the creepage distance can be increased, and the semiconductor device can be miniaturized. It will be possible.
  • FIG. 15 is a schematic sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
  • the lead frame 3 includes a plurality of members.
  • the lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, a terminal portion 3e, and an inclined portion (second inclined portion) 3f.
  • the semiconductor element 1 is mounted on the upper surface of the mounting portion 3 a of the lead frame 3.
  • a region extending continuously from the mounting portion 3a of the lead frame 3 to the upper side of the lead frame 3 is an inclined portion (first inclined portion) 3b.
  • the flat portion 3c is a region that is connected to the upper end portion of the first inclined portion 3b on the opposite side of the connection portion of the lead frame 3 with the mounting portion 3a and extends toward the outside of the sealing member 4.
  • a region continuously extending from the flat portion 3c of the lead frame 3 toward the upper surface side of the sealing member 4 is an inclined portion (second inclined portion) 3f.
  • the bent portion 3d is a portion which is connected to the upper end portion of the second inclined portion 3f of the lead frame 3 and is exposed from the sealing member 4, and the lead frame 3 is bent.
  • the region extending from the bent portion 3d of the lead frame 3 to the tip (the other end) of the lead frame 3 is the terminal portion 3e.
  • the terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portion 3d of the lead frame 3 is located at one end of the terminal portion 3e of the lead frame 3, the bent portion 3d is provided in the same number as the terminal portions 3e of the lead frame 3.
  • the flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3.
  • One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3.
  • the other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is connected to the upper end of the second inclined portion 3f of the lead frame 3.
  • the terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3.
  • a flat portion 3c, on which the electronic component 2 is mounted, is provided above the mounting portion 3a of the lead frame 3 separately from the mounting portion 3a on which the semiconductor element 1 is mounted.
  • the other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3.
  • the bent portion 3d of the lead frame 3 is connected to the upper end of the second inclined portion 3f of the lead frame 3.
  • the terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3.
  • the regions of these lead frames 3 are electrically connected by using bonding wires 6 and the like as necessary.
  • a plurality of flat portions 3c of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3.
  • the number of the first inclined portions 3b of the lead frame 3 is the same as that of the lead frame 3. Is less than the number of flat portions 3c. Further, a plurality of second inclined portions 3f of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3.
  • the terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 on both sides of the mounting portion 3a of the lead frame 3, and the respective terminal portions 3e of the lead frame 3 are sealed by the sealing member 4. Is bent toward the upper surface side of.
  • the sealing member 4 is provided below the bent portion 3d of the lead frame 3.
  • the sealing member 4 projects outward from the outer surface of the terminal portion 3e of the lead frame 3 below the bent portion 3d of the lead frame 3. It is provided.
  • the sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 above the bent portion 3d of the lead frame 3.
  • sealing member 4 is provided below the bent portion 3d of the lead frame 3 so as to be in direct contact therewith, up to the outside of the bent portion 3d of the lead frame 3.
  • the upper surface of the sealing member 4 is provided at the same height as the upper end of the second inclined portion 3f of the lead frame 3.
  • FIG. 16 is a schematic sectional view showing another semiconductor device according to the second embodiment of the present invention.
  • a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
  • the difference between the semiconductor device 400 and the semiconductor device 300 shown in FIG. 16 is the position of the outer peripheral end of the sealing member 4 below the bent portion 3d of the lead frame 3.
  • the outer peripheral end position of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the same position as the outer surface of the terminal portion 3e of the lead frame 3. Therefore, the inner surface of the terminal portion 3e of the lead frame 3 is located inside the outer peripheral end of the sealing member 4 below the bent portion 3d of the lead frame 3 by 0.1 mm to 1 mm which is the thickness of the lead frame 3. It has a certain structure. Since the other points are similar to those of the semiconductor device 300, detailed description will be omitted.
  • the semiconductor devices 300 and 400 will be described. Basically, it can be manufactured by going through the same steps as the method of manufacturing the semiconductor devices 100 and 200 described in the first embodiment. However, the shape of the mold used for molding the sealing member 4 is different.
  • FIG. 17 is a schematic sectional structure diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.
  • the mold 30 includes an upper mold 31 and a lower mold 32.
  • the upper mold 31 used in the second embodiment has a role like a lid for sandwiching the lead frame 3 with the lower mold 32 and holding the lead frame 3 in the mold 30. .. Therefore, the upper mold 31 does not have the space 40 (cavity) filled with the sealing member 4.
  • the lower mold 32 has a cavity 40 in which the entire lead frame 3 is arranged.
  • the lead frame 3 is provided with a second inclined portion 3f.
  • the upper surface of the sealing member 4 has the same height as that of the bent portion 3d of the lead frame 3 formed around the bottom surface of the upper mold 10.
  • the cavity 40 is formed only in the lower die 32, the cost for producing the die is reduced as compared with the case where the cavity 40 is formed also in the upper die 31, and the die cleaning and the die cleaning are performed. It is possible to efficiently perform maintenance work for mold part replacement.
  • the sealing member 4 is provided on the lower side of the bent portion 3d of the lead frame 3, and the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 are provided. Since the side surface of the sealing member 4 between them is made flat, there is no space distance and the creepage distance is increased, and the pitch of the intervals of the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be reduced. Therefore, the semiconductor devices 300 and 400 can be downsized.
  • the sealing member 4 is provided below the bent portion 3d of the lead frame 3, the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat. Since there is no space distance and the creepage distance can be expanded, and the withstand voltage between the exposed portion of the lead frame 3 and the heat dissipating member 9 is improved, there is no need to add an insulating sheet to shield and facilitate inverter design. You can
  • the sealing member 4 is arranged below the bent portion 3d of the lead frame 3, the creepage distance 8 between the bent portion 3d of the lead frame 3 and the heat dissipation member 9 can be increased, and the lead frame 3 can be made longer. Even if dust, contaminants, or moisture intrude between the exposed portion and the heat dissipating member 9, the insulating defect of tracking can be endured, and the reliability of the semiconductor devices 300 and 400 can be improved.
  • the lead frame 3 is provided with the second inclined portion 3f, the creepage distance of the lead frame 3 exposed from the sealing member 4 can be increased, and the reliability of the semiconductor devices 300 and 400 can be improved. ..
  • Embodiment 3 is an application of the semiconductor device according to the first or second embodiment described above to a power conversion device.
  • the present invention is not limited to a specific power converter, a case where the present invention is applied to a three-phase inverter will be described below as a third embodiment.
  • FIG. 18 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the third embodiment of the present invention is applied.
  • the power conversion system shown in FIG. 18 includes a power supply 1000, a power conversion device 2000, and a load 3000.
  • the power supply 1000 is a DC power supply and supplies DC power to the power converter 2000.
  • the power supply 1000 can be configured by various types, for example, a DC system, a solar battery, a storage battery, or a rectifier circuit, an AC/DC converter, etc. connected to an AC system. Good. Further, the power supply 1000 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, converts DC power supplied from the power supply 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 18, the power conversion device 2000 converts the DC power input from the power supply 1000 into AC power and outputs the AC power, and a main conversion circuit 2001 that outputs a control signal for controlling the main conversion circuit 2001. And a control circuit 2003 for outputting
  • the load 3000 is a three-phase electric motor driven by the AC power supplied from the power converter 2000.
  • the load 3000 is not limited to a specific use, and is an electric motor mounted on various electric devices, and is used as, for example, an electric motor for hybrid cars, electric cars, railway vehicles, elevators, air conditioners, and the like.
  • the main conversion circuit 2001 includes a switching element and a return diode (not shown) built in the semiconductor device 2002, and the switching element switches to convert DC power supplied from the power supply 1000 into AC power. And supply it to the load 3000.
  • the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can consist of six freewheeling diodes connected in anti-parallel.
  • the main conversion circuit 2001 is configured by the semiconductor device 2002 corresponding to any one of the above-described first to fifth embodiments, which incorporates each switching element, each reflux diode, and the like.
  • the six switching elements are connected in series for every two switching elements to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of each upper and lower arm that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
  • the main conversion circuit 2001 also includes a drive circuit (not shown) that drives each switching element.
  • the driving circuit may be incorporated in the semiconductor device 2002, or may be provided with a driving circuit separately from the semiconductor device 2002.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements according to a control signal from a control circuit 2003 described later.
  • the drive signal When maintaining the switching element in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
  • the control circuit 2003 controls the switching element of the main conversion circuit 2001 so that desired power is supplied to the load 3000. Specifically, the time (ON time) in which each switching element of the main conversion circuit 2001 should be in the ON state is calculated based on the power to be supplied to the load 3000.
  • the main conversion circuit 2001 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.
  • a control command is issued to the drive circuit included in the main conversion circuit 2001 so that the ON signal is output to the switching element that should be in the ON state and the OFF signal is output to the switching element that is to be in the OFF state.
  • Control signal According to this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
  • the semiconductor device according to the first or second embodiment is applied as the semiconductor device 2002 of the main conversion circuit 2001, reliability improvement is realized. be able to.
  • the present invention is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is used, but a three-level or multilevel power conversion device may be used. You may apply.
  • the present invention can be applied to a DC/DC converter, an AC/DC converter, etc. when supplying electric power to a DC load or the like.
  • the power converter to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor, and for example, an electric discharge machine, a laser machine, an induction heating cooker, a non-contact device power supply device power supply system. It can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.
  • the power semiconductor element when SiC is used as the semiconductor element 1, the power semiconductor element is operated at a higher temperature than that of Si in order to make the most of its characteristics. Since higher reliability is required in a semiconductor device equipped with a SiC device, the merit of the present invention of realizing a highly reliable semiconductor device becomes more effective.
  • 1 semiconductor element 1 semiconductor element, 2 electronic parts, 3 lead frame, 3a mounting part, 3b inclined part (first inclined part), 3c flat part, 3d bent part, 3e terminal part, 3f inclined part (second inclined part), 3g gap 4, sealing member, 6 bonding wire, 8 creepage distance, 9 heat dissipation member, 20,30 mold, 10,31 upper mold, 11,32 lower mold, 12 plating film, 13 holes, 40 space (cavity) , 100, 200, 300, 400, 2002 semiconductor device, 1000 power supply, 2000 power conversion device, 2001 main conversion circuit, 2003 control circuit, 3000 load.

Abstract

The present invention achieves a semiconductor device that ensures space/distance between terminal parts and achieves size reduction that corresponds to the narrowing of the pitch at which terminals are arranged. A semiconductor device that comprises: a semiconductor element (1); a metal member (3) that has an installation part (3a) that has the semiconductor element (1) installed on an upper surface thereof and a plurality of terminal parts (3e) that are provided above the installation part (3a), that are parallel with an interval therebetween, and that have a bent part (3d) at one end, the bent part (3d) of each of the plurality of terminal parts (3e) being bent toward the upper surface side of the installation surface (3a); and a sealing member (4) that has a side surface from which the plurality of terminal parts (3e) are exposed, that is flat at a side surface that is between the plurality of terminal parts (3e), that, above the bent parts (3d), is provided inside inner surfaces of the plurality of terminal parts (3e), that, below the bent parts (3d), contacts the bottoms of the bent parts (3d) and extends outside the bent parts (3d), and that integrally seals the semiconductor element (1) and the metal member (3).

Description

半導体装置、半導体装置の製造方法及び電力変換装置SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION DEVICE
　この発明は、狭ピッチで配置された複数の端子部を備えた半導体装置、半導体装置の製造方法及び電力変換装置に関する。 The present invention relates to a semiconductor device having a plurality of terminals arranged at a narrow pitch, a method for manufacturing the semiconductor device, and a power conversion device.
　高電圧や大電流に対応する目的で通電経路を素子の縦方向としたタイプの半導体素子は、一般的にパワー半導体素子（たとえばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　ＳｅｍＩＣｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、バイポーラトランジスタ、ダイオードなど）と呼ばれている。パワー半導体素子が回路基板上に実装され、封止樹脂によりパッケージングされた半導体装置は、産業機器、自動車、鉄道など、幅広い分野において用いられている。近年、半導体装置を搭載した機器の高性能化に伴い、定格電圧および定格電流の増加、小型化といった半導体装置の高性能化への要求が高まってきている。 A semiconductor element of a type in which a conduction path is a vertical direction of the element for the purpose of responding to a high voltage or a large current is generally a power semiconductor element (for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Transistor)). , Bipolar transistors, diodes, etc.). A semiconductor device in which a power semiconductor element is mounted on a circuit board and packaged with a sealing resin is used in a wide range of fields such as industrial equipment, automobiles, and railways. 2. Description of the Related Art In recent years, along with higher performance of devices equipped with semiconductor devices, there has been an increasing demand for higher performance of semiconductor devices such as an increase in rated voltage and rated current and a reduction in size.
　従来の半導体装置のパッケージ構造には、モールド封止型があり、この半導体装置は、リードフレーム上にパワー半導体素子が実装され、パワー半導体素子とリードフレーム端子がワイヤボンディングで接合され、全体をエポキシ樹脂で封止した構造である。一般的な製造方法としては、リードフレームをモールド上下金型でクランプして、エポキシ樹脂をキャビティに注入するトランスファーモールド成型法が用いられる。モールド樹脂成型後、パッケージ側面から出ているリードフレーム端子を曲げることによって外部端子電極を形成している。 A conventional package structure of a semiconductor device includes a mold sealing type. In this semiconductor device, a power semiconductor element is mounted on a lead frame, the power semiconductor element and a lead frame terminal are bonded by wire bonding, and the whole is epoxy. The structure is sealed with resin. As a general manufacturing method, a transfer molding method is used in which a lead frame is clamped by upper and lower molds and epoxy resin is injected into a cavity. After molding the resin by molding, the lead frame terminals protruding from the side surface of the package are bent to form the external terminal electrodes.
　しかし、この構造では、パッケージの下面の放熱部に平らな放熱フィンなどの放熱部材を置くと、パッケージの側面から露出したリードフレーム端子端から放熱フィンまでの沿面距離が、パッケージの上面からリードフレーム端子が出ている構造に比べると短くなるため、絶縁耐圧が低くなる問題があった。 However, in this structure, if a flat heat dissipation member such as a heat dissipation fin is placed on the heat dissipation part on the bottom surface of the package, the creepage distance from the lead frame terminal end exposed from the side surface of the package to the heat dissipation fin is the top surface of the package to the lead frame. Since it is shorter than the structure in which the terminals are exposed, there is a problem that the withstand voltage is lowered.
　この問題に対して、パッケージの側面から露出したリードフレーム端子の折り曲げ部の下部にモールド樹脂を配置することで沿面距離と空間距離を確保した半導体装置が開示されている。（例えば、特許文献１）。 For this problem, there is disclosed a semiconductor device in which a creeping distance and a spatial distance are secured by placing a molding resin under the bent portion of the lead frame terminal exposed from the side surface of the package. (For example, patent document 1).
特開平１０－１２５８２６号公報Japanese Patent Laid-Open No. 10-125826
　しかしながら、特許文献１に記載の従来の半導体装置では、モールド樹脂の側面から露出した端子の折り曲げ部の下部に樹脂を配置することで空間距離を確保しているが、モールド樹脂の側面の端子配置部分のみを窪ませているので、端子数に応じた窪み部が必要となる。モールド樹脂の側面に形成された窪み部の配置は、金型の成型精度、強度に依存するので、同一側面に複数の端子を用いた場合には、任意の狭ピッチに設けられた端子に対応することができない場合があり、半導体装置の小型化が難しいという課題があった。 However, in the conventional semiconductor device described in Patent Document 1, the resin is arranged below the bent portion of the terminal exposed from the side surface of the molding resin to secure the space distance. However, the terminal arrangement on the side surface of the molding resin is ensured. Since only the portion is recessed, a recessed portion corresponding to the number of terminals is required. The placement of the recesses formed on the side surface of the mold resin depends on the molding precision and strength of the mold, so when using multiple terminals on the same side surface, it is possible to use terminals with an arbitrary narrow pitch. However, there is a problem that it is difficult to reduce the size of the semiconductor device.
　この発明は、上述のような課題を解決するためになされたもので、リードフレーム端子部とモールド樹脂との空間距離を確保しつつ、リードフレーム端子間隔の狭ピッチ化に対応した小型化が可能な半導体装置を得ることを目的としている。 The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the size of the lead frame terminal portion while ensuring the space distance between the lead frame terminal portion and the molding resin, which corresponds to the narrow pitch of the lead frame terminal interval. The purpose is to obtain a good semiconductor device.
　この発明に係る半導体装置は、半導体素子と、上面に半導体素子が搭載された搭載部と、搭載部の上方に設けられ間隔を空けて並列し一端に屈曲部を有する複数の端子部とを有し、複数の端子部はそれぞれの屈曲部で搭載部の上面側へ屈曲した金属部材と、複数の端子部を側面から露出し、複数の端子部の間の側面は平坦で、屈曲部より上方では複数の端子部の内面より内側に設けられ、屈曲部より下方では屈曲部の下方に接して屈曲部の外側まで設けられ、半導体素子と金属部材とを一体的に封止する封止部材とを備えた半導体装置である。 A semiconductor device according to the present invention has a semiconductor element, a mounting portion on which a semiconductor element is mounted, and a plurality of terminal portions which are provided above the mounting portion and are arranged in parallel at a distance and have a bent portion at one end. However, the plurality of terminal portions are bent at the respective bent portions toward the upper surface side of the mounting portion, and the plurality of terminal portions are exposed from the side surfaces, and the side surfaces between the plurality of terminal portions are flat and above the bent portions. And a sealing member that is provided inside the inner surfaces of the plurality of terminal portions, is provided below the bent portion and is in contact with the lower portion of the bent portion to the outside of the bent portion, and integrally seals the semiconductor element and the metal member. It is a semiconductor device provided with.
　この発明によれば、封止部材は、露出した屈曲部より上方では複数の端子部の間の側面は平坦であり複数の端子部の内面より内側に設けられ、屈曲部より下方では屈曲部の下方に接して屈曲部の外側まで設けたので、空間距離がなくかつ沿面距離が拡大したまま、封止部材の側面から露出する複数の端子の間隔を狭ピッチ化ができ、半導体装置の小型化が可能となる。 According to the present invention, the sealing member has a flat side surface between the plurality of terminal portions above the exposed bent portion and is provided inside the inner surfaces of the plurality of terminal portions, and below the bent portion, Since it is provided in contact with the lower part to the outside of the bent part, the pitch of the terminals exposed from the side surface of the sealing member can be narrowed while there is no space distance and the creepage distance is expanded, and the semiconductor device can be miniaturized. Is possible.
この発明の実施の形態１における半導体装置を示す平面構造模式図である。FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態１における半導体装置を示す断面構造模式図である。FIG. 3 is a schematic cross-sectional structure diagram showing the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における他の半導体装置を示す断面構造模式図である。FIG. 7 is a schematic cross-sectional structure diagram showing another semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の外周端部を拡大した断面構造模式図である。FIG. 3 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end portion of the semiconductor device according to the first embodiment of the present invention. この発明の実施の形態１における他の半導体装置の外周端部を拡大した断面構造模式図である。FIG. 6 is a schematic sectional structure view in which an outer peripheral end portion of another semiconductor device according to the first embodiment of the present invention is enlarged. この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す外周端部を拡大した断面構造模式図である。FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す外周端部を拡大した断面構造模式図である。FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す外周端部を拡大した断面構造模式図である。FIG. 3 is an enlarged cross-sectional structure schematic diagram of an outer peripheral end showing a manufacturing step of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の他の製造工程を示す断面構造模式図である。FIG. 7 is a schematic sectional structure view showing another manufacturing step of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。FIG. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. この発明の実施の形態２における半導体装置を示す断面構造模式図である。FIG. 9 is a schematic cross-sectional structure diagram showing a semiconductor device according to a second embodiment of the present invention. この発明の実施の形態２における他の半導体装置を示す断面構造模式図である。FIG. 9 is a schematic cross-sectional structure diagram showing another semiconductor device in the second embodiment of the present invention. この発明の実施の形態２における半導体装置の製造工程を示す断面構造模式図である。FIG. 9 is a schematic cross-sectional structure diagram showing a manufacturing step of the semiconductor device in the second embodiment of the present invention. この発明の実施の形態３における電力変換装置を適用した電力変換システムの構成を示すブロック図である。It is a block diagram which shows the structure of the power converter system to which the power converter device in Embodiment 3 of this invention is applied.
　はじめに、本発明の半導体装置の全体構成について、図面を参照しながら説明する。なお、図は模式的なものであり、示された構成要素の正確な大きさなどを反映するものではない。また、同一の符号を付したものは、同一又はこれに相当するものであり、このことは明細書の全文において共通することである。 First, the overall configuration of the semiconductor device of the present invention will be described with reference to the drawings. It should be noted that the drawings are schematic and do not reflect the exact sizes of the components shown. Further, the components denoted by the same reference numerals are the same or equivalent, and this is common to all the texts of the specification.
実施の形態１．
　図１は、この発明の実施の形態１における半導体装置を示す平面構造模式図である。図２は、この発明の実施の形態１における半導体装置を示す断面構造模式図である。図１は、半導体装置１００を上面から見た平面図である。図１中の一点鎖線ＡＡにおける断面構造模式図が図２である。図において、半導体装置１００は、半導体素子１、電子部品２、金属部材であるリードフレーム３、封止部材４、ボンディングワイヤ６を備えている。ここで、リードフレーム３は、上面と下面とを有し、リードフレーム３が備える複数の部材も同様に上面と下面とを有している。なお、リードフレーム３の端子部３ｅにおいては、構造上、上面が内面、下面が外面にそれぞれ対応する。 Embodiment 1.
FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional structure diagram showing the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a plan view of the semiconductor device 100 as viewed from above. FIG. 2 is a schematic cross-sectional structure diagram taken along one-dot chain line AA in FIG. In the figure, a semiconductor device 100 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6. Here, the lead frame 3 has an upper surface and a lower surface, and the members included in the lead frame 3 also have an upper surface and a lower surface. In addition, in the terminal portion 3e of the lead frame 3, the upper surface corresponds to the inner surface and the lower surface corresponds to the outer surface due to the structure.
　図１において、封止部材４は、リードフレーム３の上面側と下面側とで外形の大きさが異なっている。リードフレーム３の下面側の封止部材４の外形は、リードフレーム３の上面側の封止部材４の外形よりもリードフレーム３の端子部３ｅが露出（突出）する側面側で大きくなっている。言い換えると、リードフレーム３の端子部３ｅが露出する封止部材４の側面側において、封止部材４は、リードフレーム３の下面側では、リードフレーム３の端子部３ｅの外面よりも外側へ突出して設けられる。また、封止部材４は、リードフレーム３の上面側では、リードフレーム３の端子部３ｅの内面よりも内側に設けられる。リードフレーム３の端子部３ｅが露出する封止部材４の側面は、リードフレーム３の端子部３ｅの配置方向に対して、平坦な（凹凸のない）形状である。リードフレーム３の複数の端子部３ｅは、間隔を空けて並列して設けられる。リードフレーム３の複数の端子部３ｅの隣接する端子部３ｅの間の封止部材４の側面は平坦面である。リードフレーム３の端子部３ｅは、封止部材４の同一側面から、同じ高さで複数本が露出している。 In FIG. 1, the outer shape of the sealing member 4 is different between the upper surface side and the lower surface side of the lead frame 3. The outer shape of the sealing member 4 on the lower surface side of the lead frame 3 is larger than that of the sealing member 4 on the upper surface side of the lead frame 3 on the side surface side where the terminal portion 3e of the lead frame 3 is exposed (projected). .. In other words, on the side surface side of the sealing member 4 where the terminal portion 3e of the lead frame 3 is exposed, the sealing member 4 projects outward from the outer surface of the terminal portion 3e of the lead frame 3 on the lower surface side of the lead frame 3. Is provided. Further, the sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 on the upper surface side of the lead frame 3. The side surface of the sealing member 4 from which the terminal portion 3e of the lead frame 3 is exposed has a flat shape (without unevenness) in the arrangement direction of the terminal portion 3e of the lead frame 3. The plurality of terminal portions 3e of the lead frame 3 are arranged in parallel at intervals. The side surface of the sealing member 4 between the adjacent terminal portions 3e of the plurality of terminal portions 3e of the lead frame 3 is a flat surface. A plurality of terminal portions 3e of the lead frame 3 are exposed at the same height from the same side surface of the sealing member 4.
　このため、リードフレーム３の複数の端子部３ｅを封止部材４の側面側から封止部材４の外部へ露出する場合、リードフレーム３の複数の端子部３ｅの間には、リードフレーム３の複数の端子部３ｅの間を絶縁するための封止部材４が設けられていない。しかしながら、隣接するリードフレーム３の端子部３ｅの間の絶縁距離だけを考慮して、リードフレーム３の複数の端子部３ｅの間隔を決定することができるので、半導体装置１００の小型化が可能となる。なお、リードフレーム３は、原則として一つであるが、分離していてもよい（複数でもよい）。また、リードフレーム３の複数の端子部３ｅは、封止部材４の対向する両側面から露出しているが、必ずしも封止部材４の対向する両側面から露出する必要はなく、少なくとも封止部材４の１側面からリードフレーム３の複数の端子部３ｅが露出していればよい。 Therefore, when the plurality of terminal portions 3e of the lead frame 3 are exposed to the outside of the sealing member 4 from the side surface side of the sealing member 4, the lead frame 3 is provided between the plurality of terminal portions 3e of the lead frame 3. The sealing member 4 for insulating between the plurality of terminal portions 3e is not provided. However, the distance between the plurality of terminal portions 3e of the lead frame 3 can be determined by considering only the insulation distance between the terminal portions 3e of the adjacent lead frames 3, so that the semiconductor device 100 can be downsized. Become. In addition, the lead frame 3 is one in principle, but may be separated (a plurality may be provided). Further, although the plurality of terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 which face each other, it is not necessarily required to be exposed from both side surfaces of the sealing member 4 which face each other, and at least the sealing member 4e. It suffices that the plurality of terminal portions 3e of the lead frame 3 be exposed from one side surface of No. 4 of FIG.
　図２において、リードフレーム３は、複数の部材を備えている。リードフレーム３は、搭載部３ａ、傾斜部（第一傾斜部）３ｂ、平坦部３ｃ、屈曲部３ｄおよび端子部３ｅを備えている。リードフレーム３の搭載部３ａの上面には、半導体素子１が搭載される。リードフレーム３の搭載部３ａから連続してリードフレーム３の上方へ伸びる領域が傾斜部（第一傾斜部）３ｂである。リードフレーム３の搭載部３ａとの接続部の反対側の第一傾斜部３ｂの上端部に接続し、封止部材４の外部へ向かって伸びる領域が平坦部３ｃである。リードフレーム３の封止部材４から露出しリードフレーム３が屈曲する部分が屈曲部３ｄである。リードフレーム３の屈曲部３ｄから延在し、リードフレーム３の先端部（他端）までの領域が端子部３ｅである。リードフレーム３の端子部３ｅは、リードフレーム３の搭載部３ａの上方に設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の端子部３ｅの一端にあるため、リードフレーム３の端子部３ｅと同数の複数個備えている。 In FIG. 2, the lead frame 3 includes a plurality of members. The lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, and a terminal portion 3e. The semiconductor element 1 is mounted on the upper surface of the mounting portion 3 a of the lead frame 3. A region extending continuously from the mounting portion 3a of the lead frame 3 to the upper side of the lead frame 3 is an inclined portion (first inclined portion) 3b. The flat portion 3c is a region that is connected to the upper end of the first inclined portion 3b on the opposite side of the connection portion of the lead frame 3 with the mounting portion 3a and extends toward the outside of the sealing member 4. The bent portion 3d is the portion of the lead frame 3 exposed from the sealing member 4 and the lead frame 3 is bent. The region extending from the bent portion 3d of the lead frame 3 to the tip (the other end) of the lead frame 3 is the terminal portion 3e. The terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portion 3d of the lead frame 3 is located at one end of the terminal portion 3e of the lead frame 3, the bent portion 3d is provided in the same number as the terminal portions 3e of the lead frame 3.
　リードフレーム３の平坦部３ｃは、リードフレーム３の搭載部３ａの上方に設けられている。リードフレーム３の平坦部３ｃの一端はリードフレーム３の第一傾斜部３ｂの上端部に接続している。リードフレーム３の端子部３ｅの一端には、屈曲部が設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の平坦部３ｃの他端と接続している。リードフレーム３の端子部３ｅは、屈曲部でリードフレーム３の搭載部３ａの上面側へ屈曲している。 The flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3. A bent portion is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent at the bent portion toward the upper surface side of the mounting portion 3a of the lead frame 3.
　また、上面に半導体素子１が搭載されたリードフレーム３の搭載部３ａから連続しているリードフレーム３の端子部３ｅが露出した側面の反対側（対向する辺側）には、リードフレーム３の半導体素子１が搭載されたリードフレーム３の搭載部３ａと分離されて、リードフレーム３の搭載部３ａの上方に、電子部品２が搭載された平坦部３ｃが設けられている。リードフレーム３の端子部３ｅの一端には、リードフレーム３の屈曲部３ｄが設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の平坦部３ｃの他端と接続している。リードフレーム３の端子部３ｅは、リードフレーム３の屈曲部３ｄでリードフレーム３の搭載部３ａの上面側へ屈曲している。これらのリードフレーム３の領域は、必要に応じて、ボンディングワイヤ６等を用いて電気的に接続されている。なお、リードフレーム３の平坦部３ｃは、リードフレーム３の複数の端子部３ｅに対応して複数設けられている。また、リードフレーム３の平坦部３ｃの一端は、必ずしも、リードフレーム３の第一傾斜部３ｂと接続されているわけではないため、リードフレーム３の第一傾斜部３ｂの数は、リードフレーム３の平坦部３ｃの数未満である。さらに、リードフレーム３の構成としては、リードフレーム３の第一傾斜部３ｂを設けずに、リードフレーム３の搭載部３ａが、リードフレーム３の平坦部３ｃと直接接続された構成でもよい。 Further, on the opposite side (opposing side) of the side surface where the terminal portion 3e of the lead frame 3 which is continuous from the mounting portion 3a of the lead frame 3 having the semiconductor element 1 mounted on the upper surface is exposed, A flat portion 3c on which the electronic component 2 is mounted is provided above the mounting portion 3a of the lead frame 3 so as to be separated from the mounting portion 3a of the lead frame 3 on which the semiconductor element 1 is mounted. The bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3. The regions of these lead frames 3 are electrically connected by using bonding wires 6 and the like as necessary. A plurality of flat portions 3c of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3. Since one end of the flat portion 3c of the lead frame 3 is not necessarily connected to the first inclined portion 3b of the lead frame 3, the number of the first inclined portions 3b of the lead frame 3 is the same as that of the lead frame 3. Is less than the number of flat portions 3c. Further, the lead frame 3 may be configured such that the mounting portion 3a of the lead frame 3 is directly connected to the flat portion 3c of the lead frame 3 without providing the first inclined portion 3b of the lead frame 3.
　リードフレーム３は、リードフレーム３の端子部３ｅを、リードフレーム３の搭載部３ａの両側である封止部材４の両側面から露出し、リードフレーム３のそれぞれの端子部３ｅが封止部材４の上面側へ向いて屈曲している。そして、リードフレーム３の屈曲部３ｄの下部には、封止部材４が設けられている。 In the lead frame 3, the terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 which are both sides of the mounting portion 3a of the lead frame 3, and the respective terminal portions 3e of the lead frame 3 are sealed by the sealing member 4. Is bent toward the upper surface side of. A sealing member 4 is provided below the bent portion 3d of the lead frame 3.
　リードフレーム３の材質としては、一般的に銅が用いられる。リードフレーム３の厚さは、リードフレーム３を安定してプレスで製造し、端子部３ｅに流れる電流値に合わせて、０．１ｍｍから１ｍｍの間で適宜選択可能である。リードフレーム３の厚みは、基本的に板状の部材をプレスして製造するため、各部材では均一な厚みである。しかしながら、リードフレーム３の複数の部材においては、その部材の機能に応じて、リードフレーム３の厚みは異なる厚みでもよい。特に、封止部材４の外周位置の規定に関する厚みは、リードフレーム３の端子部３ｅの厚みである。リードフレーム３の端子部３ｅの厚みは、均一な厚みである。 Copper is generally used as the material of the lead frame 3. The thickness of the lead frame 3 can be appropriately selected from 0.1 mm to 1 mm in accordance with the value of the current flowing through the terminal portion 3e by stably manufacturing the lead frame 3 by pressing. Since the lead frame 3 is basically manufactured by pressing a plate-shaped member, each member has a uniform thickness. However, in the plurality of members of the lead frame 3, the lead frame 3 may have different thicknesses depending on the functions of the members. In particular, the thickness related to the regulation of the outer peripheral position of the sealing member 4 is the thickness of the terminal portion 3e of the lead frame 3. The terminal portion 3e of the lead frame 3 has a uniform thickness.
　半導体素子１としては、一般的にパワー半導体素子、例えば、ＩＧＢＴ、ＭＯＳＦＥＴ、バイポーラトランジスタまたはダイオード等を用いることができる。半導体素子１の材料としては、シリコン（Ｓｉ：Ｓｉｌｉｃｏｎ）あるいは炭化ケイ素（ＳｉＣ：Ｓｉｌｉｃｏｎ　ｃａｒｂｉｄｅ）等を用いることができる。半導体素子１は、接合部材であるはんだ等（図示せず）を用いてリードフレーム３の搭載部３ａの所定の位置に接合される。 As the semiconductor element 1, generally, a power semiconductor element such as an IGBT, MOSFET, bipolar transistor or diode can be used. As a material of the semiconductor element 1, silicon (Si: Silicon) or silicon carbide (SiC: Silicon carbide) or the like can be used. The semiconductor element 1 is joined to a predetermined position of the mounting portion 3a of the lead frame 3 by using solder or the like (not shown) which is a joining member.
　電子部品２としては、ＩＣ（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）素子、抵抗およびコンデンサ等を用いることができる。電子部品２は、接合部材である樹脂ペースト等（図示せず）を用いてリードフレーム３の平坦部３ｃの所定の位置に接合される。 As the electronic component 2, an IC (Integrated Circuit) element, a resistor, a capacitor or the like can be used. The electronic component 2 is bonded to a predetermined position of the flat portion 3c of the lead frame 3 using a resin paste or the like (not shown) which is a bonding member.
　ボンディングワイヤ６は、リードフレーム３と半導体素子１とを接続する。また、ボンディングワイヤ６は、複数の半導体素子１同士を接続する。さらに、ボンディングワイヤ６は、半導体素子１と電子部品２とを接続する。 Bonding wire 6 connects lead frame 3 and semiconductor element 1. The bonding wire 6 connects the plurality of semiconductor elements 1 to each other. Furthermore, the bonding wire 6 connects the semiconductor element 1 and the electronic component 2.
　また、ボンディングワイヤ６を半導体素子１との接続に用いる場合、半導体素子１の大電流が流れる部材との接続には、ボンディングワイヤ６の材質としては、一般的に、電気伝導度は高くないが、安価なアルミニウム（Ａｌ）を選択して、直径は０．１から０．５ｍｍ程度であり、リードフレーム３上のパッドと半導体素子１の接合部に超音波で接合する。また、ボンディングワイヤ６を半導体素子１大電流が流れる以外の部材または電子部品２との接続に用いる場合、ボンディングワイヤ６の材質としては、金、銀、銅の電気伝導度が高いものを選択して、直径０．０５ｍｍ以下に細く加工して、半導体素子１または電子部品２上の小さなパッド上にワイヤボンディングする。 When the bonding wire 6 is used for connection with the semiconductor element 1, the bonding wire 6 is generally not high in electrical conductivity for connection with a member of the semiconductor element 1 through which a large current flows. Inexpensive aluminum (Al) is selected, and the diameter is about 0.1 to 0.5 mm, and the pad on the lead frame 3 and the bonding portion of the semiconductor element 1 are ultrasonically bonded. Further, when the bonding wire 6 is used for connection with a member other than the semiconductor element 1 through which a large current flows or the electronic component 2, the material of the bonding wire 6 is selected from those having high electric conductivity such as gold, silver and copper. Then, it is finely processed to have a diameter of 0.05 mm or less, and wire bonding is performed on a small pad on the semiconductor element 1 or the electronic component 2.
　封止部材４は、封止した部材間の絶縁性を確保するとともに、半導体装置１００のケースとしても機能する。封止部材４は、リードフレーム３に搭載された半導体素子１、リードフレーム３に搭載された電子部品２、ボンディングワイヤ６およびリードフレーム３を一体的に封止している。上述のように、封止部材４の外周位置（大きさ）は、リードフレーム３の上面側とリードフレーム３の下面側とで異なっている。リードフレーム３の上面側の封止部材４の外周位置は、封止部材４の対向するそれぞれの側面から露出した対向するリードフレーム３のそれぞれ（両側）の端子部３ｅに挟まれた位置である。すなわち、リードフレーム３の上面側の封止部材４の外周位置は、封止部材４の対向するそれぞれの側面から露出した対向するリードフレーム３のそれぞれの端子部３ｅの内面よりも内周側（内側）である。また、リードフレーム３の下面側の封止部材４の外周位置は、封止部材４の対向するそれぞれの側面から露出した対向するリードフレーム３のそれぞれの端子部３ｅの外面よりも外周側（外側）である。 The sealing member 4 ensures the insulation between the sealed members and also functions as a case of the semiconductor device 100. The sealing member 4 integrally seals the semiconductor element 1 mounted on the lead frame 3, the electronic component 2 mounted on the lead frame 3, the bonding wire 6 and the lead frame 3. As described above, the outer peripheral position (size) of the sealing member 4 is different between the upper surface side of the lead frame 3 and the lower surface side of the lead frame 3. The outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is a position sandwiched by the terminal portions 3e of each (both sides) of the facing lead frame 3 exposed from the respective facing side surfaces of the sealing member 4. .. That is, the outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is on the inner peripheral side of the inner surface of each terminal portion 3e of the opposing lead frame 3 exposed from the respective opposing side surfaces of the sealing member 4 ( Inside). The outer peripheral position of the sealing member 4 on the lower surface side of the lead frame 3 is on the outer peripheral side (outer side) than the outer surface of each terminal portion 3e of the opposing lead frame 3 exposed from each side surface of the sealing member 4 facing each other. ).
　言い換えると、リードフレーム３の端子部３ｅが露出する封止部材４の側面側において、封止部材４は、リードフレーム３の屈曲部３ｄより下方では、リードフレーム３の端子部３ｅの外面よりリードフレーム３の厚み分以上外側へ突出して設けられる。また、封止部材４は、リードフレーム３の屈曲部３ｄより上方では、リードフレーム３の端子部３ｅの内面より内側に設けられる。さらに、リードフレーム３の屈曲部３ｄの下部には、封止部材４が直接接して、リードフレーム３の屈曲部３ｄの外側まで設けられている。また、封止部材４の上面は、リードフレーム３の平坦部３ｃの上面より上方に設けられている。なお、リードフレーム３の屈曲部３ｄをリードフレーム３の平坦部３ｃと置き換えて見た場合でも、封止部材４は同様の配置関係である。 In other words, on the side surface side of the sealing member 4 where the terminal portion 3e of the lead frame 3 is exposed, the sealing member 4 is below the bent portion 3d of the lead frame 3 and leads from the outer surface of the terminal portion 3e of the lead frame 3. The frame 3 is provided so as to project outward by more than the thickness of the frame 3. The sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 above the bent portion 3d of the lead frame 3. Further, the sealing member 4 is provided directly below the bent portion 3d of the lead frame 3 and is provided up to the outside of the bent portion 3d of the lead frame 3. The upper surface of the sealing member 4 is provided above the upper surface of the flat portion 3c of the lead frame 3. Even when the bent portion 3d of the lead frame 3 is replaced with the flat portion 3c of the lead frame 3, the sealing member 4 has the same arrangement relationship.
　封止部材４の材料としては、一般的に、熱硬化性エポキシ樹脂が用いられる。この熱硬化性エポキシ樹脂には、二酸化ケイ素（ＳｉＯ２）が充填され、線膨張係数を銅に近づけている。 A thermosetting epoxy resin is generally used as the material of the sealing member 4. This thermosetting epoxy resin is filled with silicon dioxide (SiO 2 ) and has a linear expansion coefficient close to that of copper.
　リードフレーム３の搭載部３ａの下面の下側には、封止部材４ではなく、絶縁性放熱材料として、高放熱フィラーである窒化アルミニウム（ＡｌＮ）、窒化ホウ素（ＢＮ）または二酸化ケイ素（ＳｉＯ２）を充填したエポキシ樹脂で、厚みが０．１ｍｍから０．３ｍｍのシート体を適用して絶縁性を維持したまま放熱性を高めることもできる。また、高放熱絶縁材料である窒化アルミニウム（ＡｌＮ）、窒化ケイ素（ＳｉＮ）、二酸化ケイ素（ＳｉＯ２）、または、これら高放熱絶縁材料を組み合わせて形成されたＤＢＣ（Ｄｉｒｅｃｔ　ｂｏｎｄｅｄ　Ｃｏｐｐｅｒ）基板を適用することもできる。さらに、ＡＭＢ（Ａｃｔｉｖｅ　Ｍｅｔａｌ　Ｂｒａｚｉｎｇ)基板またはＤＢＡ（Ｄｉｒｅｃｔ　Ｂｏｎｄｅｄ　Ａｌｕｍｉｎｕｍ）基板を適用しても同様の効果を得ることができる。 On the lower side of the lower surface of the mounting portion 3a of the lead frame 3, not the sealing member 4, but an insulating heat dissipation material such as aluminum nitride (AlN), boron nitride (BN) or silicon dioxide (SiO 2 ) which is a high heat dissipation filler. It is also possible to apply a sheet body having a thickness of 0.1 mm to 0.3 mm with an epoxy resin filled with) to improve heat dissipation while maintaining insulation. Further, a high heat dissipation insulating material such as aluminum nitride (AlN), silicon nitride (SiN), silicon dioxide (SiO 2 ) or a DBC (Direct Bonded Copper) substrate formed by combining these high heat dissipation insulating materials is applied. You can also Further, the same effect can be obtained by applying an AMB (Active Metal Brazing) substrate or a DBA (Direct Bonded Aluminum) substrate.
　図３は、この発明の実施の形態１における他の半導体装置を示す断面構造模式図である。図において、半導体装置２００は、半導体素子１、電子部品２、金属部材であるリードフレーム３、封止部材４、ボンディングワイヤ６を備えている。 FIG. 3 is a schematic sectional view showing another semiconductor device according to the first embodiment of the present invention. In the figure, a semiconductor device 200 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
　図２に示した半導体装置１００と半導体装置２００との違いは、リードフレーム３の下面側の封止部材４の外周端部の位置である。半導体装置２００においては、リードフレーム３の屈曲部３ｄより下方の封止部材４の外周端部位置が、リードフレーム３の屈曲部３ｄにおいてリードフレーム３の端子部３ｅの外面と同じ位置に設けられている。言い換えると、リードフレーム３の屈曲部３ｄより上方の封止部材４の外周端部位置は、リードフレーム３の屈曲部３ｄより下方の封止部材４の外周端部よりもリードフレーム３の厚み分だけ内側に設けられている。なお、その他の点については、半導体装置１００と同様であるので、詳しい説明は省略する。 The difference between the semiconductor device 100 and the semiconductor device 200 shown in FIG. 2 is the position of the outer peripheral end of the sealing member 4 on the lower surface side of the lead frame 3. In the semiconductor device 200, the outer peripheral end position of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the same position as the outer surface of the terminal portion 3e of the lead frame 3 in the bent portion 3d of the lead frame 3. ing. In other words, the outer peripheral end position of the sealing member 4 above the bent portion 3d of the lead frame 3 is equal to the thickness of the lead frame 3 than the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3. Only provided inside. Since the other points are similar to those of the semiconductor device 100, detailed description thereof will be omitted.
　次に、上述のような構造を有する半導体装置１００，２００の効果について説明する。 Next, the effects of the semiconductor devices 100 and 200 having the above-described structure will be described.
　図４は、この発明の実施の形態１における半導体装置の外周端部を拡大した断面構造模式図である。図５は、この発明の実施の形態１における他の半導体装置の外周端部を拡大した断面構造模式図である。図４、図５において、リードフレーム３の下面側の封止部材４の下面側には放熱部材９が設けられている。放熱部材９は、一般的には、銅やアルミニウム等の金属材料が用いられる。また、図４、図５において矢印で示した経路が、リードフレーム３と放熱部材９との間が沿面距離８である。 FIG. 4 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end of the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end of another semiconductor device according to the first embodiment of the present invention. In FIGS. 4 and 5, a heat dissipation member 9 is provided on the lower surface side of the sealing member 4 on the lower surface side of the lead frame 3. The heat dissipation member 9 is generally made of a metal material such as copper or aluminum. Further, the path indicated by the arrow in FIGS. 4 and 5 is the creepage distance 8 between the lead frame 3 and the heat dissipation member 9.
　図４、図５に示したように、リードフレーム３の屈曲部３ｄの下面には、封止部材４が直接接して設けられている。このため、半導体装置１００，２００を放熱部材９上に、ネジ等で締め付けて配置する場合でも、リードフレーム３の屈曲部３ｄの下部から放熱部材９の上面までの空間距離を無くすことができ、封止部材４により絶縁保護が可能となる。また、このような構成としたので、リードフレーム３の屈曲部３ｄの下部から放熱部材９の上面までの沿面距離８だけが半導体装置の絶縁設計上の制約となり、リードフレーム３の屈曲部３ｄから放熱部材９間の絶縁耐圧が向上し、リードフレーム３の屈曲部３ｄの下部に絶縁シート等の絶縁部材を追加して絶縁保護する手間がなく、インバータ設計を容易にすることができる。 As shown in FIGS. 4 and 5, the sealing member 4 is provided directly on the lower surface of the bent portion 3d of the lead frame 3. Therefore, even when the semiconductor devices 100 and 200 are arranged on the heat dissipation member 9 by being tightened with screws or the like, it is possible to eliminate the spatial distance from the lower portion of the bent portion 3d of the lead frame 3 to the upper surface of the heat dissipation member 9, The sealing member 4 enables insulation protection. Further, because of such a configuration, only the creepage distance 8 from the lower portion of the bent portion 3d of the lead frame 3 to the upper surface of the heat dissipation member 9 is a constraint in the insulation design of the semiconductor device, and the bent portion 3d of the lead frame 3 The withstand voltage between the heat dissipating members 9 is improved, and there is no need to add an insulating member such as an insulating sheet to the lower portion of the bent portion 3d of the lead frame 3 for insulation protection, and the inverter design can be facilitated.
　さらに、沿面距離８も長くしたので、リードフレーム３の屈曲部３ｄの下部領域から放熱部材９までの間にほこり、汚染物質または水分が侵入した場合においても、トラッキングの絶縁不具合に耐えることができ、国際規格であるＩＥＣ６０６６４－１に準じた高汚染耐性を達成することができ、半導体装置の信頼性寿命が向上する。また、半導体装置の絶縁特性と汚染度とを、外部接続ための端子がケース部材にインサートまたはアウトサートされたケース型半導体装置と同等とすることができる。 Further, since the creepage distance 8 is also increased, even if dust, contaminants or moisture penetrate between the lower region of the bent portion 3d of the lead frame 3 and the heat dissipation member 9, it is possible to withstand the insulation failure of tracking. It is possible to achieve high pollution resistance according to the international standard IEC60664-1 and improve the reliability life of the semiconductor device. Further, the insulation characteristics and the contamination degree of the semiconductor device can be made equal to those of the case type semiconductor device in which the terminal for external connection is inserted or outsert in the case member.
　このように構成された半導体装置１００，２００では、リードフレーム３の屈曲部３ｄの下部に封止部材４を接して配置したので、半導体装置１００，２００の下面側に放熱部材９を配置した場合に空間距離を無くし、かつ沿面距離を確保することができる。また、半導体装置１００，２００は、露出したリードフレーム３の端子部３ｅの間の封止部材４の側面をリードフレーム３の端子部３ｅの配置方向に平坦に（凹凸なく）したので、複数のリードフレーム３の端子部３ｅ間の距離を短くすることができ、半導体装置１００，２００の小型化が可能となる。 In the semiconductor devices 100 and 200 configured in this way, the sealing member 4 is arranged in contact with the lower portion of the bent portion 3d of the lead frame 3, so that the heat dissipation member 9 is arranged on the lower surface side of the semiconductor devices 100 and 200. It is possible to eliminate the spatial distance and secure the creepage distance. Further, in the semiconductor devices 100 and 200, the side surface of the sealing member 4 between the exposed terminal portions 3e of the lead frame 3 is made flat (without unevenness) in the arrangement direction of the terminal portions 3e of the lead frame 3, so that a plurality of The distance between the terminal portions 3e of the lead frame 3 can be shortened, and the semiconductor devices 100 and 200 can be downsized.
　次に、上述のように構成された本実施の形態１の半導体装置１００の製造方法について説明する。 Next, a method of manufacturing the semiconductor device 100 of the first embodiment configured as described above will be described.
　図６から図９は、この発明の実施の形態１における半導体装置の各製造工程を示す断面構造模式図である。図６は、この発明の実施の形態１における半導体装置の製造工程を示す平面構造模式図である。図７は、この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。図８は、この発明の実施の形態１における半導体装置の製造工程を示す平面構造模式図である。図９は、この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。これらの工程を経ることで、図２に記載の半導体装置１００を製造することができる。 6 to 9 are schematic cross-sectional structure diagrams showing each manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a schematic plan view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a schematic sectional structure view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a schematic plan view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 9 is a schematic sectional structure view showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. Through these steps, the semiconductor device 100 shown in FIG. 2 can be manufactured.
　はじめに、半導体素子１と電子部品２とを準備し、図６に示すように、所定の形状に加工された、上面と下面とを有するリードフレーム３の上面側の搭載部３ａの所定の位置に半導体素子１を搭載し、リードフレーム３の平坦部３ｃの所定の位置に電子部品２を搭載する。半導体素子１は、はんだを介してリードフレーム３の搭載部３ａに接合される。電子部品２は、樹脂ペーストを介してリードフレーム３の平坦部３ｃに接合される。そして、リードフレーム３の搭載部３ａまたは平坦部３ｃの所定の位置に設けられた半導体素子１、電子部品２およびリードフレーム３を目的に応じた径のボンディングワイヤ６で接続し、配線する（半導体素子搭載工程）。 First, the semiconductor element 1 and the electronic component 2 are prepared and, as shown in FIG. 6, at a predetermined position of the mounting portion 3a on the upper surface side of the lead frame 3 which is processed into a predetermined shape and has an upper surface and a lower surface. The semiconductor element 1 is mounted, and the electronic component 2 is mounted at a predetermined position on the flat portion 3c of the lead frame 3. The semiconductor element 1 is bonded to the mounting portion 3a of the lead frame 3 via solder. The electronic component 2 is joined to the flat portion 3c of the lead frame 3 via a resin paste. Then, the semiconductor element 1, the electronic component 2, and the lead frame 3 provided at predetermined positions of the mounting portion 3a or the flat portion 3c of the lead frame 3 are connected by a bonding wire 6 having a diameter according to the purpose and wired (semiconductor Element mounting process).
　次に、図７に示すように、半導体素子１および電子部品２が搭載されたリードフレーム３を金型２０内へ配置する（金属部材配置工程）。金型２０は、上金型１０と下金型１１とを備えている。上金型１０と下金型１１とでリードフレーム３の平坦部３ｃから端子部３ｅ側（封止部材４から露出させる領域）を挟み込むことで、リードフレーム３を金型２０内の空間４０で保持している。上金型１０は、少なくともリードフレーム３の平坦部３ｃから端子部３ｅを挟み込む側面（内側壁）が、リードフレーム３の端子部３ｅの配置方向に平坦（凹凸なし）である。特に、リードフレーム３の複数の端子部３ｅの間になる上金型１０の内側壁は平坦である。また、上金型１０の内側壁は、下金型１１の内側壁よりも内側に設けられている。言い換えると、下金型１１の内側壁は、上金型１０の内側壁よりも外側に設けられている。上金型１０の内側壁と下金型１１の内側壁との差は、リードフレーム３の厚み分以上である。上金型１０の内側壁と下金型１１の内側壁との差が、リードフレーム３の厚み分未満である場合は、封止部材４の外周領域からリードフレーム３の屈曲部３ｄが突出（の下面側が露出）するため、空間距離が発生してしまう。しかしながら、上金型１０の内側壁が、下金型１１の内側壁よりも内側になるので、リードフレーム３の屈曲部３ｄの下部に封止部材４を配置でき、空間距離の発生を抑制できる。 Next, as shown in FIG. 7, the lead frame 3 on which the semiconductor element 1 and the electronic component 2 are mounted is placed in the mold 20 (metal member placement step). The mold 20 includes an upper mold 10 and a lower mold 11. By sandwiching the terminal portion 3e side (the region exposed from the sealing member 4) from the flat portion 3c of the lead frame 3 between the upper die 10 and the lower die 11, the lead frame 3 is formed in the space 40 in the die 20. keeping. In the upper mold 10, at least the side surface (inner wall) sandwiching the terminal portion 3e from the flat portion 3c of the lead frame 3 is flat (no unevenness) in the arrangement direction of the terminal portion 3e of the lead frame 3. In particular, the inner wall of the upper die 10 between the plurality of terminal portions 3e of the lead frame 3 is flat. Further, the inner side wall of the upper die 10 is provided inside the inner side wall of the lower die 11. In other words, the inner side wall of the lower mold 11 is provided outside the inner side wall of the upper mold 10. The difference between the inner side wall of the upper die 10 and the inner side wall of the lower die 11 is equal to or more than the thickness of the lead frame 3. When the difference between the inner wall of the upper mold 10 and the inner wall of the lower mold 11 is less than the thickness of the lead frame 3, the bent portion 3d of the lead frame 3 projects from the outer peripheral region of the sealing member 4 ( Since the lower surface side of is exposed), a spatial distance is generated. However, since the inner side wall of the upper die 10 is located inside the inner side wall of the lower die 11, the sealing member 4 can be arranged below the bent portion 3d of the lead frame 3 and the generation of the spatial distance can be suppressed. ..
　次に、図８に示すように、リードフレーム３が配置された金型２０の空間４０内に封止部材４を充填し、リードフレーム３を一体的に封止する（封止工程）。封止部材４は、金型２０の形状に合わせて金型２０内に充填される。一般的には、トランスファーモールド成型法を用いて成型される。金型２０内に、封止部材４を充填後、充填された封止部材４の硬化処理を行う。ここで、封止部材４の上面は、上金型１０の内側壁の下端と接する周囲に形成されるリードフレーム３の屈曲部３ｄより上方に設けられる。 Next, as shown in FIG. 8, the space 40 of the mold 20 in which the lead frame 3 is arranged is filled with the sealing member 4 to integrally seal the lead frame 3 (sealing step). The sealing member 4 is filled in the mold 20 according to the shape of the mold 20. Generally, it is molded using a transfer molding method. After the sealing member 4 is filled in the mold 20, the filled sealing member 4 is cured. Here, the upper surface of the sealing member 4 is provided above the bent portion 3d of the lead frame 3 formed around the lower surface of the inner wall of the upper mold 10.
　次に、図９に示すように、金型２０から封止部材４で封止されたリードフレーム３を取り出す（金属部材取出工程）。金型２０から取り出し後、封止部材４の側面側から露出したリードフレーム３のそれぞれの端子部３ｅをリードフレーム３の上面側が対向するようにリードフレーム３の両側に設けられた屈曲部３ｄで屈曲（折り曲げ）させる（金属部材加工工程）。 Next, as shown in FIG. 9, the lead frame 3 sealed with the sealing member 4 is taken out from the mold 20 (metal member taking-out step). After taking out from the mold 20, the respective terminal portions 3e of the lead frame 3 exposed from the side surface side of the sealing member 4 are bent by the bent portions 3d provided on both sides of the lead frame 3 so that the upper surfaces of the lead frames 3 face each other. Bending (bending) (metal member processing step).
　以上の工程を経ることで、図２に記載の半導体装置１００を製造することができる。 The semiconductor device 100 shown in FIG. 2 can be manufactured through the above steps.
　図１０は、この発明の実施の形態１における半導体装置の製造工程を示す外周端部を拡大した断面構造模式図である。図１１は、この発明の実施の形態１における半導体装置の製造工程を示す外周端部を拡大した断面構造模式図である。図１２は、この発明の実施の形態１における半導体装置の他の製造工程を示す外周端部を拡大した断面構造模式図である。図１３は、この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。図１４は、この発明の実施の形態１における半導体装置の製造工程を示す断面構造模式図である。図１０、図１１、図１２は、上述の金属部材加工工程の一実施例をしている。図１３、図１４は封止部材４からリードフレーム３が露出した半導体装置１００の側面側を示している。 FIG. 10 is a schematic sectional structure enlarged view of the outer peripheral end showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a schematic cross-sectional structure diagram showing an enlarged outer peripheral end showing the manufacturing process of the semiconductor device in the first embodiment of the present invention. FIG. 12 is a schematic sectional structure enlarged view of an outer peripheral end showing another manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 13 is a schematic sectional structure view showing a manufacturing process of the semiconductor device in the first embodiment of the present invention. FIG. 14 is a schematic sectional structure view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 10, FIG. 11 and FIG. 12 show an example of the above-mentioned metal member processing step. 13 and 14 show the side surface side of the semiconductor device 100 in which the lead frame 3 is exposed from the sealing member 4.
　図１０、図１１、図１２、図１３において、リードフレーム３の下面側の平坦部３ｃの他端から端子部３ｅの間で、屈曲部３ｄを含む領域のリードフレーム３の下面側に離型部材であるめっき膜１２が設けられている。図１０においては、リードフレーム３の下面側のめっき膜１２は、封止部材４に接する領域に設けられている。めっき膜１２の配置位置に対応するリードフレーム３の上面側には、封止部材４がなく、リードフレーム３の上面が露出している。図１１においては、リードフレーム３は、屈曲部３ｄでリードフレーム３の搭載部３ａの上面側へ屈曲している。めっき膜１２は、リードフレーム３の端子部３ｅの外面側では封止部材４から剥離するが、リードフレーム３の屈曲部３ｄのリードフレーム３の厚みに対応する領域は、封止部材４と接したままである。図１３においては、めっき膜１２は、リードフレーム３の幅と同じ幅で、封止部材４から露出したリードフレーム３の下面側に設けられ、封止部材４に接している。 10, 11, 12, and 13, a mold release is performed on the lower surface side of the lead frame 3 in a region including the bent portion 3d between the other end of the flat portion 3c on the lower surface side of the lead frame 3 and the terminal portion 3e. A plating film 12 that is a member is provided. In FIG. 10, the plating film 12 on the lower surface side of the lead frame 3 is provided in a region in contact with the sealing member 4. There is no sealing member 4 on the upper surface side of the lead frame 3 corresponding to the arrangement position of the plating film 12, and the upper surface of the lead frame 3 is exposed. In FIG. 11, the lead frame 3 is bent at the bent portion 3d toward the upper surface side of the mounting portion 3a of the lead frame 3. The plating film 12 is separated from the sealing member 4 on the outer surface side of the terminal portion 3e of the lead frame 3, but the region of the bent portion 3d of the lead frame 3 corresponding to the thickness of the lead frame 3 is in contact with the sealing member 4. It is still done. In FIG. 13, the plating film 12 has the same width as the width of the lead frame 3, is provided on the lower surface side of the lead frame 3 exposed from the sealing member 4, and is in contact with the sealing member 4.
　図１１、図１２において、リードフレーム３の上面側の封止部材４の側面から露出したリードフレーム３の領域（平坦部３ｃの一部から端子部３ｅまで）を屈曲部３ｄでリードフレーム３の搭載部３ａの上面側へ（リードフレーム３の端子部３ｅを封止部材４の側面へ向かって）屈曲させる。このとき、リードフレーム３の下面側であった領域には、めっき膜１２が形成されているため、リードフレーム３の下面側のめっき膜１２が形成された領域と封止部材４との密着力は、めっき膜１２を形成していない領域の密着力よりも弱くなるため、リードフレーム３と封止部材４とを容易に剥離させることができる。このため、リードフレーム３の封止部材４からの剥離に伴う樹脂バリの発生も低減することができる。この封止部材４からリードフレーム３の剥離処理は、封止部材４の成型直後で、封止部材４の硬化が十分でなく、封止部材４が高温の状態のリードフレーム３と封止部材４との接着力が小さいときに行うことが有効である。 In FIG. 11 and FIG. 12, the region of the lead frame 3 exposed from the side surface of the sealing member 4 on the upper surface side of the lead frame 3 (from a part of the flat portion 3c to the terminal portion 3e) is bent at the bent portion 3d. The mounting portion 3a is bent toward the upper surface side (the terminal portion 3e of the lead frame 3 is directed toward the side surface of the sealing member 4). At this time, since the plating film 12 is formed in the area on the lower surface side of the lead frame 3, the adhesive force between the area on the lower surface side of the lead frame 3 on which the plating film 12 is formed and the sealing member 4 is small. Since it becomes weaker than the adhesive force of the region where the plating film 12 is not formed, the lead frame 3 and the sealing member 4 can be easily separated. Therefore, it is possible to reduce the occurrence of resin burrs due to the peeling of the lead frame 3 from the sealing member 4. The peeling process of the lead frame 3 from the sealing member 4 is performed immediately after the molding of the sealing member 4, and the curing of the sealing member 4 is not sufficient. It is effective to carry out when the adhesive force with 4 is small.
　なお、図１２に示すように、リードフレーム３を屈曲部３ｄで屈曲させるときに、リードフレーム３の上面側を抑える抑え冶具を用いる場合があるが、この場合には、封止部材４の上面側の側面とリードフレーム３の上面側との間に抑え冶具の大きさ（厚み）に対応した隙間３ｇが形成される。この場合、リードフレーム３の上面側のリードフレーム３が露出する封止部材４の側面（外周端部）の位置は、リードフレーム３の端子部３ｅの内面よりも、隙間３ｇ分だけ内側に設けられる。 Note that, as shown in FIG. 12, when the lead frame 3 is bent at the bending portion 3d, a suppressing jig that suppresses the upper surface side of the lead frame 3 may be used, but in this case, the upper surface of the sealing member 4 is used. A gap 3g corresponding to the size (thickness) of the holding jig is formed between the side surface on the side and the upper surface side of the lead frame 3. In this case, the position of the side surface (outer peripheral end) of the sealing member 4 on which the lead frame 3 on the upper surface side of the lead frame 3 is exposed is provided inside the inner surface of the terminal portion 3e of the lead frame 3 by a gap 3g. To be
　リードフレーム３の下面側にめっき膜１２を形成するためには、リードフレーム３を金型２０内に配置する前に、リードフレーム３の下面側の対応する位置にめっき膜を形成する処理（金属部材めっき膜形成工程）を行うことで対応可能である。 In order to form the plating film 12 on the lower surface side of the lead frame 3, before the lead frame 3 is placed in the mold 20, a process of forming the plating film at the corresponding position on the lower surface side of the lead frame 3 (metal This can be dealt with by performing a member plating film forming step).
　また、図１４に示すように、リードフレーム３のめっき膜１２が形成された領域にリードフレーム３とめっき膜１２を貫通する孔部である孔１３を設けてもよい。このように、孔１３を設けることで、めっき膜１２を形成した領域の封止部材４との接着力を低下することができ、容易に封止部材４からリードフレーム３を剥離することができる。このようにすることで、半導体装置１００の機能を損なうことなく、リードフレーム３を加工することができる。なお、孔１３は、めっき膜１２を設けずに孔１３だけを設けてもよい。 Further, as shown in FIG. 14, holes 13 which are holes penetrating the lead frame 3 and the plated film 12 may be provided in the region of the lead frame 3 where the plated film 12 is formed. By providing the holes 13 in this way, the adhesive force with the sealing member 4 in the region where the plating film 12 is formed can be reduced, and the lead frame 3 can be easily separated from the sealing member 4. .. By doing so, the lead frame 3 can be processed without impairing the function of the semiconductor device 100. The holes 13 may be provided with only the holes 13 without providing the plating film 12.
　さらに、半導体装置２００は、図７に示した上金型１０の内壁の位置を下金型１１の内壁の位置に近づけた（外周側へ拡げた）上金型１０を用いることで製造することが可能である。下金型１１の内側壁は、上金型１０の内側壁よりもリードフレーム３の厚み分だけ外側に設けられる。 Further, the semiconductor device 200 is manufactured by using the upper mold 10 in which the position of the inner wall of the upper mold 10 shown in FIG. 7 is closer to the position of the inner wall of the lower mold 11 (expanded to the outer peripheral side). Is possible. The inner side wall of the lower die 11 is provided outside the inner side wall of the upper die 10 by the thickness of the lead frame 3.
　以上のように構成された半導体装置１００，２００においては、封止部材４はリードフレーム３の屈曲部３ｄの下部に設けられ、封止部材４から露出したリードフレーム３の複数の端子部３ｅの間の封止部材４の側面を平坦にしたので、空間距離がなくかつ沿面距離を拡大しながら、封止部材４の側面から露出するリードフレーム３の端子部３ｅの間隔の狭ピッチ化ができ、半導体装置１００，２００の小型化が可能となる。 In the semiconductor devices 100 and 200 configured as described above, the sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 are provided. Since the side surface of the sealing member 4 between them is made flat, the pitch of the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed while there is no space distance and the creepage distance is increased. Therefore, the semiconductor devices 100 and 200 can be downsized.
　また、封止部材４は、リードフレーム３の屈曲部３ｄの下部に設けられ、封止部材４から露出したリードフレーム３の複数の端子部３ｅの間の封止部材４の側面を平坦にしたので、空間距離がなくかつ沿面距離が拡大でき、リードフレーム３の封止部材４からの露出部分から放熱部材９までの絶縁耐圧が向上するため、絶縁シートを追加してリードフレーム３と放熱部材９とをシールドする手間がなく、インバータ設計を容易にすることができる。 The sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the side surface of the sealing member 4 exposed between the plurality of terminal portions 3e of the lead frame 3 is flattened. Therefore, there is no space distance and the creepage distance can be expanded, and the withstand voltage from the exposed portion of the lead frame 3 from the sealing member 4 to the heat dissipation member 9 is improved. Therefore, an insulating sheet is added to the lead frame 3 and the heat dissipation member. The inverter design can be facilitated without the trouble of shielding 9 and 9.
　さらに、封止部材４は、リードフレーム３の屈曲部３ｄの下部に配置したので、沿面距離８も長くすることができ、リードフレーム３の露出部分から放熱部材９までの間にほこりや汚染物質や水分が侵入してもトラッキングの絶縁不具合に耐えることができ、半導体装置１００，２００の信頼性を向上することができる。 Further, since the sealing member 4 is arranged below the bent portion 3d of the lead frame 3, the creeping distance 8 can be increased, and dust and contaminants can be provided between the exposed portion of the lead frame 3 and the heat dissipation member 9. Even if moisture or moisture intrudes, the tracking insulation failure can be endured, and the reliability of the semiconductor devices 100 and 200 can be improved.
実施の形態２．
　本実施の形態２においては、実施の形態１で用いたリードフレーム３の上面側の封止部材４の高さである封止部材４の上面の高さを低くし、リードフレーム３に第二傾斜部３ｆを設けた点が異なる。このように、リードフレーム３の上面側である封止部材４の上面の高さを低くし、リードフレーム３に第二傾斜部３ｆを設けたので、半導体装置の空間距離がなくかつ沿面距離が拡大しながら、半導体装置の小型化が可能となる。なお、その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。 Embodiment 2.
In the second embodiment, the height of the upper surface of the sealing member 4, which is the height of the sealing member 4 on the upper surface side of the lead frame 3 used in the first embodiment, is reduced so that the lead frame 3 has a second height. The difference is that the inclined portion 3f is provided. As described above, since the height of the upper surface of the sealing member 4, which is the upper surface side of the lead frame 3, is reduced and the second inclined portion 3f is provided on the lead frame 3, the semiconductor device has no spatial distance and a creeping distance. While expanding, the semiconductor device can be downsized. Since the other points are the same as those in the first embodiment, detailed description thereof will be omitted.
　このような場合においても、封止部材４は、リードフレーム３の屈曲部３ｄの下部に設けられ、封止部材４から露出したリードフレーム３の複数の端子部３ｅの間の封止部材４の側面を平坦にしたので、空間距離がなくかつ沿面距離が拡大しながら、封止部材４の側面から露出するリードフレーム３の端子部３ｅの間隔の狭ピッチ化ができ、半導体装置の小型化が可能となる。 Even in such a case, the sealing member 4 is provided below the bent portion 3d of the lead frame 3, and the sealing member 4 is exposed between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4. Since the side surfaces are flattened, the space between the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed while there is no space distance and the creepage distance can be increased, and the semiconductor device can be miniaturized. It will be possible.
　図１５は、この発明の実施の形態２における半導体装置を示す断面構造模式図である。図において、半導体装置３００は、半導体素子１、電子部品２、金属部材であるリードフレーム３、封止部材４、ボンディングワイヤ６を備えている。 FIG. 15 is a schematic sectional view showing a semiconductor device according to the second embodiment of the present invention. In the figure, a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
　図１５において、リードフレーム３は、複数の部材を備えている。リードフレーム３は、搭載部３ａ、傾斜部（第一傾斜部）３ｂ、平坦部３ｃ、屈曲部３ｄ、端子部３ｅおよび傾斜部（第二傾斜部）３ｆを備えている。リードフレーム３の搭載部３ａの上面には、半導体素子１が搭載される。リードフレーム３の搭載部３ａから連続してリードフレーム３の上方へ伸びる領域が傾斜部（第一傾斜部）３ｂである。リードフレーム３の搭載部３ａとの接続部の反対側の第一傾斜部３ｂの上端部と接続し、封止部材４の外部へ向かって伸びる領域が平坦部３ｃである。リードフレーム３の平坦部３ｃから連続して封止部材４の上面側へ向かって伸びる領域が傾斜部（第二傾斜部）３ｆである。リードフレーム３の第二傾斜部３ｆの上端部に接続して封止部材４から露出し、リードフレーム３が屈曲する部分が屈曲部３ｄである。リードフレーム３の屈曲部３ｄから延在し、リードフレーム３の先端部（他端）までの領域が端子部３ｅである。リードフレーム３の端子部３ｅは、リードフレーム３の搭載部３ａの上方に設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の端子部３ｅの一端にあるため、リードフレーム３の端子部３ｅと同数の複数個備えている。 In FIG. 15, the lead frame 3 includes a plurality of members. The lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, a terminal portion 3e, and an inclined portion (second inclined portion) 3f. The semiconductor element 1 is mounted on the upper surface of the mounting portion 3 a of the lead frame 3. A region extending continuously from the mounting portion 3a of the lead frame 3 to the upper side of the lead frame 3 is an inclined portion (first inclined portion) 3b. The flat portion 3c is a region that is connected to the upper end portion of the first inclined portion 3b on the opposite side of the connection portion of the lead frame 3 with the mounting portion 3a and extends toward the outside of the sealing member 4. A region continuously extending from the flat portion 3c of the lead frame 3 toward the upper surface side of the sealing member 4 is an inclined portion (second inclined portion) 3f. The bent portion 3d is a portion which is connected to the upper end portion of the second inclined portion 3f of the lead frame 3 and is exposed from the sealing member 4, and the lead frame 3 is bent. The region extending from the bent portion 3d of the lead frame 3 to the tip (the other end) of the lead frame 3 is the terminal portion 3e. The terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portion 3d of the lead frame 3 is located at one end of the terminal portion 3e of the lead frame 3, the bent portion 3d is provided in the same number as the terminal portions 3e of the lead frame 3.
　リードフレーム３の平坦部３ｃは、リードフレーム３の搭載部３ａの上方に設けられている。リードフレーム３の平坦部３ｃの一端はリードフレーム３の第一傾斜部３ｂの上端部に接続している。リードフレーム３の平坦部３ｃの他端は、リードフレーム３の平坦部３ｃの上方に設けられたリードフレーム３の第二傾斜部３ｆの下端部に接続している。リードフレーム３の端子部３ｅの一端には、リードフレーム３の屈曲部３ｄが設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の第二傾斜部３ｆの上端部と接続している。リードフレーム３の端子部３ｅは、リードフレーム３の屈曲部３ｄでリードフレーム３の搭載部３ａの上面側へ屈曲している。 The flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3. The other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3. The bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the upper end of the second inclined portion 3f of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3.
　また、上面に半導体素子１が搭載されたリードフレーム３の搭載部３ａから連続しているリードフレーム３の端子部３ｅが露出した側面の反対側（対向する辺側）には、リードフレーム３の半導体素子１が搭載された搭載部３ａと分離されて、リードフレーム３の搭載部３ａの上方に、電子部品２が搭載された平坦部３ｃが設けられている。リードフレーム３の平坦部３ｃの他端は、リードフレーム３の平坦部３ｃの上方に設けられたリードフレーム３の第二傾斜部３ｆの下端部に接続している。リードフレーム３の端子部３ｅの一端には、リードフレーム３の屈曲部３ｄが設けられている。リードフレーム３の端子部３ｅの一端には、リードフレーム３の屈曲部３ｄが設けられている。リードフレーム３の屈曲部３ｄは、リードフレーム３の第二傾斜部３ｆの上端部と接続している。リードフレーム３の端子部３ｅは、リードフレーム３の屈曲部３ｄでリードフレーム３の搭載部３ａの上面側へ屈曲している。これらのリードフレーム３の領域は、必要に応じて、ボンディングワイヤ６等を用いて電気的に接続されている。なお、リードフレーム３の平坦部３ｃは、リードフレーム３の複数の端子部３ｅに対応して複数設けられている。また、リードフレーム３の平坦部３ｃの一端は、必ずしも、リードフレーム３の第一傾斜部３ｂと接続されているわけではないため、リードフレーム３の第一傾斜部３ｂの数は、リードフレーム３の平坦部３ｃの数未満である。さらに、リードフレーム３の第二傾斜部３ｆは、リードフレーム３の複数の端子部３ｅに対応して複数設けられている。 Further, on the opposite side (opposing side) of the side surface where the terminal portion 3e of the lead frame 3 which is continuous from the mounting portion 3a of the lead frame 3 having the semiconductor element 1 mounted on the upper surface is exposed, A flat portion 3c, on which the electronic component 2 is mounted, is provided above the mounting portion 3a of the lead frame 3 separately from the mounting portion 3a on which the semiconductor element 1 is mounted. The other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3. The bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the upper end of the second inclined portion 3f of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent at the bent portion 3d of the lead frame 3 toward the upper surface side of the mounting portion 3a of the lead frame 3. The regions of these lead frames 3 are electrically connected by using bonding wires 6 and the like as necessary. A plurality of flat portions 3c of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3. Since one end of the flat portion 3c of the lead frame 3 is not necessarily connected to the first inclined portion 3b of the lead frame 3, the number of the first inclined portions 3b of the lead frame 3 is the same as that of the lead frame 3. Is less than the number of flat portions 3c. Further, a plurality of second inclined portions 3f of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3.
　リードフレーム３は、リードフレーム３の端子部３ｅを、リードフレーム３の搭載部３ａの両側である封止部材４の両側面から露出し、リードフレーム３のそれぞれの端子部３ｅが封止部材４の上面側へ向いて屈曲している。そして、リードフレーム３の屈曲部３ｄの下方には、封止部材４が設けられている。
　リードフレーム３の端子部３ｅが露出する封止部材４の側面側において、封止部材４は、リードフレーム３の屈曲部３ｄより下方では、リードフレーム３の端子部３ｅの外面より外側へ突出して設けられている。また、封止部材４は、リードフレーム３の屈曲部３ｄより上方では、リードフレーム３の端子部３ｅの内面より内側に設けられる。さらに、リードフレーム３の屈曲部３ｄの下部には、封止部材４が直接接してリードフレーム３の屈曲部３ｄの外側まで設けられている。また、封止部材４の上面は、リードフレーム３の第二傾斜部３ｆの上端部と同じ高さに設けられている。 In the lead frame 3, the terminal portions 3e of the lead frame 3 are exposed from both side surfaces of the sealing member 4 on both sides of the mounting portion 3a of the lead frame 3, and the respective terminal portions 3e of the lead frame 3 are sealed by the sealing member 4. Is bent toward the upper surface side of. The sealing member 4 is provided below the bent portion 3d of the lead frame 3.
On the side surface side of the sealing member 4 where the terminal portion 3e of the lead frame 3 is exposed, the sealing member 4 projects outward from the outer surface of the terminal portion 3e of the lead frame 3 below the bent portion 3d of the lead frame 3. It is provided. The sealing member 4 is provided inside the inner surface of the terminal portion 3e of the lead frame 3 above the bent portion 3d of the lead frame 3. Further, the sealing member 4 is provided below the bent portion 3d of the lead frame 3 so as to be in direct contact therewith, up to the outside of the bent portion 3d of the lead frame 3. The upper surface of the sealing member 4 is provided at the same height as the upper end of the second inclined portion 3f of the lead frame 3.
　図１６は、この発明の実施の形態２における他の半導体装置を示す断面構造模式図である。図において、半導体装置３００は、半導体素子１、電子部品２、金属部材であるリードフレーム３、封止部材４、ボンディングワイヤ６を備えている。 FIG. 16 is a schematic sectional view showing another semiconductor device according to the second embodiment of the present invention. In the figure, a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 which is a metal member, a sealing member 4, and a bonding wire 6.
　図１６に示した半導体装置４００と半導体装置３００の違いは、リードフレーム３の屈曲部３ｄより下方の封止部材４の外周端部の位置である。半導体装置４００においては、リードフレーム３の屈曲部３ｄより下方の封止部材４の外周端部位置が、リードフレーム３の端子部３ｅの外面と同じ位置に設けられている。このため、リードフレーム３の端子部３ｅの内面は、リードフレーム３の屈曲部３ｄより下方の封止部材４の外周端部より、リードフレーム３の厚み分である０．１ｍｍから１ｍｍの内側にある構造である。なお、その他の点については、半導体装置３００と同様であるので、詳しい説明は省略する。 The difference between the semiconductor device 400 and the semiconductor device 300 shown in FIG. 16 is the position of the outer peripheral end of the sealing member 4 below the bent portion 3d of the lead frame 3. In the semiconductor device 400, the outer peripheral end position of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the same position as the outer surface of the terminal portion 3e of the lead frame 3. Therefore, the inner surface of the terminal portion 3e of the lead frame 3 is located inside the outer peripheral end of the sealing member 4 below the bent portion 3d of the lead frame 3 by 0.1 mm to 1 mm which is the thickness of the lead frame 3. It has a certain structure. Since the other points are similar to those of the semiconductor device 300, detailed description will be omitted.
　次に、半導体装置３００，４００の製造方法について説明する。基本的には、実施の形態１で説明した半導体装置１００，２００の製造方法と同様の工程を経ることで製造することができる。ただし、封止部材４の成型に用いる金型の形状が異なる。 Next, a method of manufacturing the semiconductor devices 300 and 400 will be described. Basically, it can be manufactured by going through the same steps as the method of manufacturing the semiconductor devices 100 and 200 described in the first embodiment. However, the shape of the mold used for molding the sealing member 4 is different.
　図１７は、この発明の実施の形態２における半導体装置の製造工程を示す断面構造模式である。図において、金型３０は、上金型３１と下金型３２とを備えている。 FIG. 17 is a schematic sectional structure diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. In the figure, the mold 30 includes an upper mold 31 and a lower mold 32.
　図１７に示すように、本実施の形態２で用いる上金型３１は、下金型３２とでリードフレーム３を挟み込み金型３０内でリードフレーム３を保持するための蓋的な役割である。このため、上金型３１には、封止部材４が充填される空間４０（キャビティ）はない。一方、下金型３２には、リードフレーム３の全体が配置されるキャビティ４０を有する。このキャビティ４０にリードフレーム３を配置するためにリードフレーム３には、第二傾斜部３ｆを設けている。この場合、封止部材４の上面は、上金型１０の底面と接する周囲に形成されるリードフレーム３の屈曲部３ｄと同じ高さとなる。
　このように、下金型３２にのみにキャビティ４０を形成しているので、上金型３１に対してもキャビティ４０形成する場合に比べて、金型作製のコストが低減し、金型清掃や金型部品交換のメンテナンス作業を効率よく実施できる。 As shown in FIG. 17, the upper mold 31 used in the second embodiment has a role like a lid for sandwiching the lead frame 3 with the lower mold 32 and holding the lead frame 3 in the mold 30. .. Therefore, the upper mold 31 does not have the space 40 (cavity) filled with the sealing member 4. On the other hand, the lower mold 32 has a cavity 40 in which the entire lead frame 3 is arranged. In order to dispose the lead frame 3 in the cavity 40, the lead frame 3 is provided with a second inclined portion 3f. In this case, the upper surface of the sealing member 4 has the same height as that of the bent portion 3d of the lead frame 3 formed around the bottom surface of the upper mold 10.
As described above, since the cavity 40 is formed only in the lower die 32, the cost for producing the die is reduced as compared with the case where the cavity 40 is formed also in the upper die 31, and the die cleaning and the die cleaning are performed. It is possible to efficiently perform maintenance work for mold part replacement.
　以上のように構成された半導体装置３００，４００においては、封止部材４はリードフレーム３の屈曲部３ｄの下部側に設けられ、封止部材４から露出したリードフレーム３の複数の端子部３ｅの間の封止部材４の側面を平坦にしたので、空間距離がなくかつ沿面距離が拡大しながら、封止部材４の側面から露出するリードフレーム３の端子部３ｅの間隔の狭ピッチ化ができ、半導体装置３００，４００の小型化が可能となる。 In the semiconductor devices 300 and 400 configured as described above, the sealing member 4 is provided on the lower side of the bent portion 3d of the lead frame 3, and the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 are provided. Since the side surface of the sealing member 4 between them is made flat, there is no space distance and the creepage distance is increased, and the pitch of the intervals of the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be reduced. Therefore, the semiconductor devices 300 and 400 can be downsized.
　また、封止部材４はリードフレーム３の屈曲部３ｄの下部に設けられ、封止部材４から露出したリードフレーム３の複数の端子部３ｅの間の封止部材４の側面を平坦にしたので、空間距離がなくかつ沿面距離が拡大でき、リードフレーム３の露出部分から放熱部材９間の絶縁耐圧が向上するので、絶縁シートを追加してシールドする手間がなく、インバータ設計を容易にすることができる。 Further, since the sealing member 4 is provided below the bent portion 3d of the lead frame 3, the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat. Since there is no space distance and the creepage distance can be expanded, and the withstand voltage between the exposed portion of the lead frame 3 and the heat dissipating member 9 is improved, there is no need to add an insulating sheet to shield and facilitate inverter design. You can
　さらに、封止部材４はリードフレーム３の屈曲部３ｄの下部に配置したので、リードフレーム３の屈曲部３ｄから放熱部材９との間の沿面距離８も長くすることができ、リードフレーム３の露出部分から放熱部材９までの間にほこりや汚染物質や水分が侵入してもトラッキングの絶縁不具合に耐えることができ、半導体装置３００，４００の信頼性を向上することができる。 Further, since the sealing member 4 is arranged below the bent portion 3d of the lead frame 3, the creepage distance 8 between the bent portion 3d of the lead frame 3 and the heat dissipation member 9 can be increased, and the lead frame 3 can be made longer. Even if dust, contaminants, or moisture intrude between the exposed portion and the heat dissipating member 9, the insulating defect of tracking can be endured, and the reliability of the semiconductor devices 300 and 400 can be improved.
　また、リードフレーム３に第二傾斜部３ｆを設けたので、封止部材４から露出したリードフレーム３の沿面距離を拡大することができ、半導体装置３００，４００の信頼性を向上することができる。 Further, since the lead frame 3 is provided with the second inclined portion 3f, the creepage distance of the lead frame 3 exposed from the sealing member 4 can be increased, and the reliability of the semiconductor devices 300 and 400 can be improved. ..
実施の形態３．
　本実施の形態３は、上述した実施の形態１または２にかかる半導体装置を電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態３として、三相のインバータに本発明を適用した場合について説明する。 Embodiment 3.
The third embodiment is an application of the semiconductor device according to the first or second embodiment described above to a power conversion device. Although the present invention is not limited to a specific power converter, a case where the present invention is applied to a three-phase inverter will be described below as a third embodiment.
　図１８は、この発明の実施の形態３における電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 18 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the third embodiment of the present invention is applied.
　図１８に示す電力変換システムは、電源１０００、電力変換装置２０００、負荷３０００を備えている。電源１０００は、直流電源であり、電力変換装置２０００に直流電力を供給する。電源１０００は種々のもので構成することができ、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路、ＡＣ／ＤＣコンバータなどで構成することとしてもよい。また、電源１０００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 18 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power converter 2000. The power supply 1000 can be configured by various types, for example, a DC system, a solar battery, a storage battery, or a rectifier circuit, an AC/DC converter, etc. connected to an AC system. Good. Further, the power supply 1000 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
　電力変換装置２０００は、電源１０００と負荷３０００との間に接続された三相のインバータであり、電源１０００から供給された直流電力を交流電力に変換し、負荷３０００に交流電力を供給する。電力変換装置２０００は、図１８に示すように、電源１０００から入力される直流電力を交流電力に変換して出力する主変換回路２００１と、主変換回路２００１を制御する制御信号を主変換回路２００１に出力する制御回路２００３とを備えている。 The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, converts DC power supplied from the power supply 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 18, the power conversion device 2000 converts the DC power input from the power supply 1000 into AC power and outputs the AC power, and a main conversion circuit 2001 that outputs a control signal for controlling the main conversion circuit 2001. And a control circuit 2003 for outputting
　負荷３０００は、電力変換装置２０００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３０００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車、電気自動車、鉄道車両、エレベーター、空調機器向けの電動機等として用いられる。 The load 3000 is a three-phase electric motor driven by the AC power supplied from the power converter 2000. The load 3000 is not limited to a specific use, and is an electric motor mounted on various electric devices, and is used as, for example, an electric motor for hybrid cars, electric cars, railway vehicles, elevators, air conditioners, and the like.
　以下、電力変換装置２０００の詳細を説明する。主変換回路２００１は、半導体装置２００２に内蔵されたスイッチング素子と還流ダイオードとを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１０００から供給される直流電力を交流電力に変換し、負荷３０００に供給する。主変換回路２００１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２００１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列に接続された６つの還流ダイオードとから構成することができる。主変換回路２００１は、各スイッチング素子、各還流ダイオードなどを内蔵する上述した実施の形態１から５のいずれかに相当する半導体装置２００２によって構成される。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。各上下アームの出力端子、すなわち主変換回路２００１の３つの出力端子は、負荷３０００に接続される。 The details of the power conversion device 2000 will be described below. The main conversion circuit 2001 includes a switching element and a return diode (not shown) built in the semiconductor device 2002, and the switching element switches to convert DC power supplied from the power supply 1000 into AC power. And supply it to the load 3000. Although there are various concrete circuit configurations of the main conversion circuit 2001, the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can consist of six freewheeling diodes connected in anti-parallel. The main conversion circuit 2001 is configured by the semiconductor device 2002 corresponding to any one of the above-described first to fifth embodiments, which incorporates each switching element, each reflux diode, and the like. The six switching elements are connected in series for every two switching elements to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
　また、主変換回路２００１は、各スイッチング素子を駆動する駆動回路（図示なし）を備えている。駆動回路は半導体装置２００２に内蔵されていてもよいし、半導体装置２００２とは別に駆動回路を備える構成であってもよい。駆動回路は、主変換回路２００１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２００１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２００３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 The main conversion circuit 2001 also includes a drive circuit (not shown) that drives each switching element. The driving circuit may be incorporated in the semiconductor device 2002, or may be provided with a driving circuit separately from the semiconductor device 2002. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements according to a control signal from a control circuit 2003 described later. When maintaining the switching element in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
　制御回路２００３は、負荷３０００に所望の電力が供給されるよう主変換回路２００１のスイッチング素子を制御する。具体的には、負荷３０００に供給すべき電力に基づいて主変換回路２００１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２００１を制御することができる。また、各時点においてオン状態となるべきスイッチング素子にはオン信号を出力し、オフ状態となるべきスイッチング素子にはオフ信号を出力されるように、主変換回路２００１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 2003 controls the switching element of the main conversion circuit 2001 so that desired power is supplied to the load 3000. Specifically, the time (ON time) in which each switching element of the main conversion circuit 2001 should be in the ON state is calculated based on the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Also, at each time point, a control command is issued to the drive circuit included in the main conversion circuit 2001 so that the ON signal is output to the switching element that should be in the ON state and the OFF signal is output to the switching element that is to be in the OFF state. Control signal). According to this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
　以上のように構成された本実施の形態３に係る電力変換装置においては、主変換回路２００１の半導体装置２００２として実施の形態１または２にかかる半導体装置を適用するため、信頼性向上を実現することができる。 In the power conversion device according to the third embodiment configured as described above, since the semiconductor device according to the first or second embodiment is applied as the semiconductor device 2002 of the main conversion circuit 2001, reliability improvement is realized. be able to.
　本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、本発明は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベル、マルチレベルの電力変換装置であってもよいし、単相負荷に電力を供給する場合には単相のインバータに本発明を適用してもよい。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータ、ＡＣ／ＤＣコンバータなどに本発明を適用することもできる。 In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multilevel power conversion device may be used. You may apply. Further, the present invention can be applied to a DC/DC converter, an AC/DC converter, etc. when supplying electric power to a DC load or the like.
　また、本発明を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機、レーザー加工機、誘導加熱調理器、非接触器給電システムの電源装置等として用いることもでき、さらには、太陽光発電システム、蓄電システム等のパワーコンディショナーとして用いることもできる。 Further, the power converter to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor, and for example, an electric discharge machine, a laser machine, an induction heating cooker, a non-contact device power supply device power supply system. It can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.
　特に、半導体素子１として、ＳｉＣを用いた場合、電力半導体素子はその特徴を生かすために、Ｓｉの時と比較してより高温で動作させることになる。ＳｉＣデバイスを搭載する半導体装置においては、より高い信頼性が求められるため、高信頼の半導体装置を実現するという本発明のメリットはより効果的なものとなる。 In particular, when SiC is used as the semiconductor element 1, the power semiconductor element is operated at a higher temperature than that of Si in order to make the most of its characteristics. Since higher reliability is required in a semiconductor device equipped with a SiC device, the merit of the present invention of realizing a highly reliable semiconductor device becomes more effective.
　上述した実施の形態は、すべての点で例示であって制限的なものではないと解されるべきである。本発明の範囲は、上述した実施形態の範囲ではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更を含むものである。また、上記の実施形態に開示されている複数の構成要素を適宜組み合わせることにより発明を形成してもよい。 It should be understood that the above-described embodiments are exemplifications in all points and are not restrictive. The scope of the present invention is shown not by the scope of the above-described embodiment but by the scope of the claims, and includes meaning equivalent to the scope of the claims and all modifications within the scope. Further, the invention may be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments.
１　半導体素子、２　電子部品、３　リードフレーム、３ａ　搭載部、３ｂ　傾斜部（第一傾斜部）、３ｃ　平坦部、３ｄ　屈曲部、３ｅ　端子部、３ｆ　傾斜部（第二傾斜部）、３ｇ　隙間、４　封止部材、６　ボンディングワイヤ、８　沿面距離、９　放熱部材、２０，３０　金型、１０，３１　上金型、１１，３２　下金型、１２　めっき膜、１３　孔、４０　空間（キャビティ）、１００，２００，３００，４００，２００２　半導体装置、１０００　電源、２０００　電力変換装置、２００１　主変換回路、２００３　制御回路、３０００　負荷。 1 semiconductor element, 2 electronic parts, 3 lead frame, 3a mounting part, 3b inclined part (first inclined part), 3c flat part, 3d bent part, 3e terminal part, 3f inclined part (second inclined part), 3g gap 4, sealing member, 6 bonding wire, 8 creepage distance, 9 heat dissipation member, 20,30 mold, 10,31 upper mold, 11,32 lower mold, 12 plating film, 13 holes, 40 space (cavity) , 100, 200, 300, 400, 2002 semiconductor device, 1000 power supply, 2000 power conversion device, 2001 main conversion circuit, 2003 control circuit, 3000 load.

Claims (11)

  1. 半導体素子と、
    上面に前記半導体素子が搭載された搭載部と、前記搭載部の上方に設けられ間隔を空けて並列し一端に屈曲部を有する複数の端子部とを有し、前記複数の端子部はそれぞれの前記屈曲部で前記搭載部の前記上面側へ屈曲した金属部材と、
    前記複数の端子部を側面から露出し、前記複数の端子部の間の前記側面は平坦で、前記屈曲部より上方では前記複数の端子部の内面より内側に設けられ、前記屈曲部より下方では前記屈曲部の下方に接して前記屈曲部の外側まで設けられ、前記半導体素子と前記金属部材とを一体的に封止する封止部材と、
    を備えた半導体装置。     Semiconductor element,
    The semiconductor device is mounted on the upper surface of the mounting portion, and a plurality of terminal portions that are provided above the mounting portion and are parallel to each other at intervals and have a bent portion at one end. A metal member bent toward the upper surface of the mounting portion at the bent portion,
    The plurality of terminal portions are exposed from the side surface, the side surface between the plurality of terminal portions is flat, and is provided inside the inner surfaces of the plurality of terminal portions above the bent portion and below the bent portion. A sealing member that is provided up to the outside of the bent portion in contact with the lower side of the bent portion and integrally seals the semiconductor element and the metal member,
    A semiconductor device provided with.
  2. 前記封止部材は、前記屈曲部より下方に設けられた前記封止部材の外周位置が前記屈曲部より上方に設けられた前記封止部材の外周位置よりも前記金属部材の厚み分以上外側に配置される、請求項１に記載の半導体装置。 The sealing member is arranged such that the outer peripheral position of the sealing member provided below the bent portion is outside the outer peripheral position of the sealing member provided above the bent portion by at least the thickness of the metal member. The semiconductor device according to claim 1, which is arranged.
  3. 前記封止部材は、前記屈曲部より上方に設けられた前記封止部材の外周位置が前記屈曲部より下方に設けられた前記封止部材の外周位置よりも前記金属部材の厚み分内側に配置される、請求項１または請求項２に記載の半導体装置。 The sealing member is arranged such that the outer peripheral position of the sealing member provided above the bent portion is inside the outer peripheral position of the sealing member provided below the bent portion by the thickness of the metal member. The semiconductor device according to claim 1 or 2, which is provided.
  4. 前記金属部材は、前記搭載部より上方に設けられた複数の平坦部と、前記搭載部と前記複数の平坦部の一端とを接続する複数の第一傾斜部とを有し、前記複数の平坦部の他端は、それぞれが前記屈曲部と接続した、請求項１から請求項３のいずれか１項に記載の半導体装置。 The metal member has a plurality of flat portions provided above the mounting portion, and a plurality of first inclined portions connecting the mounting portion and one end of the plurality of flat portions, and the plurality of flat portions. The semiconductor device according to any one of claims 1 to 3, wherein each of the other ends of the parts is connected to the bent part.
  5. 前記金属部材は、前記搭載部より上方に設けられた複数の平坦部と、前記搭載部と前記複数の平坦部の一端とを接続する複数の第一傾斜部と、前記複数の第一傾斜部より上方に設けられ前記複数の平坦部の他端と複数の前記屈曲部とを接続する複数の第二傾斜部とを有し、前記封止部材の上面は、前記第二傾斜部の上端と同じ高さに設けられた、請求項１から請求項３のいずれか１項に記載の半導体装置。 The metal member includes a plurality of flat portions provided above the mounting portion, a plurality of first inclined portions connecting the mounting portion and one end of the plurality of flat portions, and the plurality of first inclined portions. It has a plurality of second inclined portions that connect the other ends of the plurality of flat portions and the plurality of bent portions provided above, and the upper surface of the sealing member has an upper end of the second inclined portion. The semiconductor device according to claim 1, wherein the semiconductor devices are provided at the same height.
  6. 前記金属部材は、前記屈曲部が前記封止部材と面する領域から前記端子部の外面にわたる領域に離型部材が設けられた、請求項１から請求項５のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the metal member is provided with a release member in a region extending from a region where the bent portion faces the sealing member to an outer surface of the terminal portion. apparatus.
  7. 前記離型部材は、めっき膜である、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the release member is a plating film.
  8. 前記金属部材は、前記離型部材が設けられた領域に孔部が設けられた、請求項６または請求項７に記載の半導体装置。 The semiconductor device according to claim 6, wherein the metal member has a hole provided in a region where the release member is provided.
  9. 金属部材の搭載部の上面に半導体素子を搭載する半導体素子搭載工程と、
    上金型の複数の端子部を挟み込む内側壁が前記複数の端子部の間で平坦であり、前記上金型の内側壁より外側に下金型の内側壁が設けられ、前記上金型と前記下金型とを有する金型内に、前記搭載部と前記搭載部の上方に設けられ間隔を空けて並列させた複数の端子部とを有する前記金属部材を配置する金属部材配置工程と、
    前記金属部材が配置された前記金型内に封止部材を充填し前記半導体素子と前記金属部材とを一体的に封止する封止工程と、
    前記封止部材の側面から露出させた前記複数の端子部を屈曲部で前記搭載面の前記上面側へ屈曲させる金属部材加工工程と、
    を備えた半導体装置の製造方法。     A semiconductor element mounting step of mounting a semiconductor element on the upper surface of the mounting portion of the metal member,
    An inner side wall of the upper mold sandwiching the plurality of terminal parts is flat between the plurality of terminal parts, and an inner side wall of the lower mold is provided outside the inner side wall of the upper mold, and the upper mold and In a mold having the lower mold, a metal member disposing step of disposing the metal member having the mounting portion and a plurality of terminal portions provided above the mounting portion and arranged in parallel at intervals,
    A sealing step of filling a sealing member in the mold in which the metal member is arranged to integrally seal the semiconductor element and the metal member,
    A metal member processing step of bending the plurality of terminal portions exposed from the side surface of the sealing member to the upper surface side of the mounting surface at a bending portion,
    A method for manufacturing a semiconductor device comprising:
  10. 前記金属部材の前記複数の端子部のそれぞれの前記屈曲部を含む領域にめっき膜を形成する金属部材めっき膜形成工程をさらに備えた請求項９に記載の半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 9, further comprising a metal member plating film forming step of forming a plating film on a region including the bent portion of each of the plurality of terminal portions of the metal member.
  11. 請求項１から請求項８のいずれか１項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
    前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、
    を備えた電力変換装置。     A main conversion circuit which has the semiconductor device according to claim 1 and converts input power and outputs the converted power.
    A control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit;
    Power conversion device equipped with.
PCT/JP2019/001378 2019-01-18 2019-01-18 Semiconductor device, production method for semiconductor device, and power conversion device WO2020148879A1 (en)

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