CN113261095A - Semiconductor device, method for manufacturing semiconductor device, and power conversion device - Google Patents
Semiconductor device, method for manufacturing semiconductor device, and power conversion device Download PDFInfo
- Publication number
- CN113261095A CN113261095A CN201980088014.4A CN201980088014A CN113261095A CN 113261095 A CN113261095 A CN 113261095A CN 201980088014 A CN201980088014 A CN 201980088014A CN 113261095 A CN113261095 A CN 113261095A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- sealing member
- semiconductor device
- portions
- bent portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 173
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 238000006243 chemical reaction Methods 0.000 title claims description 26
- 238000000034 method Methods 0.000 title claims description 11
- 238000007789 sealing Methods 0.000 claims abstract description 158
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000007747 plating Methods 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 description 26
- 238000010586 diagram Methods 0.000 description 22
- 230000017525 heat dissipation Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229920005989 resin Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- 238000009413 insulation Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor device which can ensure a space distance with a terminal part and realize miniaturization corresponding to narrow pitch of terminal arrangement. A semiconductor device includes: a semiconductor element (1); a metal member (3) having a mounting portion (3a) on the upper surface of which the semiconductor element (1) is mounted, and a plurality of terminal portions (3e) that are provided above the mounting portion (3a), are arranged in parallel with a space therebetween, and have a bent portion (3d) at one end, the plurality of terminal portions (3e) being bent toward the upper surface side of the mounting portion (3a) at the respective bent portions (3 d); and a sealing member (4) that exposes the plurality of terminal portions (3e) from a side surface of the sealing member, wherein the side surface of the sealing member between the plurality of terminal portions (3e) is flat, the sealing member is provided above the bent portion (3d) at a position inside the inner surfaces of the plurality of terminal portions (3e), contacts the lower portion of the bent portion (3d) below the bent portion (3d), and is provided outside the bent portion (3d), and the sealing member integrally seals the semiconductor element (1) and the metal member (3).
Description
Technical Field
The present invention relates to a semiconductor device including a plurality of terminal portions arranged at a narrow pitch, a method of manufacturing the semiconductor device, and a power conversion device.
Background
A Semiconductor device of a type in which a conduction path is formed in a vertical direction of the device in order to cope with a high voltage and a large current is generally called a power Semiconductor device (for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Bipolar Transistor, a diode, or the like). A semiconductor device in which a power semiconductor element is mounted on a circuit board and sealed with a sealing resin is used in a wide range of fields such as industrial equipment, automobiles, railways, and the like. In recent years, as the performance of devices equipped with semiconductor devices has been improved, there has been an increasing demand for higher performance of semiconductor devices, such as an increase in rated voltage and rated current and a reduction in size.
A conventional package structure of a semiconductor device is a molded package type, and the semiconductor device has the following structure: a power semiconductor element is mounted on a lead frame, and the power semiconductor element is bonded to a lead frame terminal by wire bonding (wire bonding), and the whole is sealed with an epoxy resin. As a general production method, the following transfer molding method can be used: the lead frame is clamped by upper and lower molds and epoxy resin is injected into the cavity. After molding the resin, the lead frame terminals protruding from the side surfaces of the package body are bent to form external terminal electrodes.
However, in this structure, when a heat dissipation member such as a flat heat dissipation fin is placed on the heat dissipation portion on the lower surface of the package, the creepage distance from the lead frame terminal end exposed from the side surface of the package to the heat dissipation fin is shorter than the structure in which the lead frame terminal protrudes from the upper surface of the package, and therefore, there is a problem that the dielectric breakdown voltage is low.
To address this problem, the following semiconductor device is disclosed: the mold resin is disposed at the lower part of the bent part of the lead frame terminal exposed from the side surface of the package body, thereby ensuring creepage distance and space distance. (for example, patent document 1).
Prior art documents
Patent document
Patent document 1: japanese laid-open patent publication No. 10-125826
Disclosure of Invention
Problems to be solved by the invention
However, in the conventional semiconductor device described in patent document 1, the resin is disposed below the bent portions of the terminals exposed from the side surfaces of the mold resin to secure a space distance, but since only the terminal disposition portions of the side surfaces of the mold resin are recessed, recessed portions corresponding to the number of terminals are required. Since the arrangement of the recessed portions formed in the side surfaces of the mold resin depends on the molding accuracy and strength of the mold, there are problems as follows: when a plurality of terminals are used on the same side surface, terminals provided at an arbitrary narrow pitch may not be accommodated, and it is difficult to miniaturize the semiconductor device.
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device which can secure a space distance between a lead frame terminal portion and a molding resin and which can be miniaturized in response to a narrow pitch of a lead frame terminal interval.
Means for solving the problems
The semiconductor device of the present invention includes: a semiconductor element; a metal member having a mounting portion on which a semiconductor element is mounted on an upper surface thereof, and a plurality of terminal portions which are provided above the mounting portion, are arranged in parallel with an interval therebetween, and have a bent portion at one end thereof, the plurality of terminal portions being bent toward the upper surface side of the mounting portion at the respective bent portions; and a sealing member that exposes the plurality of terminal portions from a side surface of the sealing member, wherein the side surface of the sealing member between the plurality of terminal portions is flat, the sealing member is provided above the bent portion at a position inside an inner surface of the plurality of terminal portions, and is provided below the bent portion in contact with a lower portion of the bent portion to an outer side of the bent portion, and the sealing member integrally seals the semiconductor element and the metal member.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, since the side surface of the sealing member between the plurality of terminal portions is flat, and the sealing member is provided above the exposed bent portion at a position inside the inner surface of the plurality of terminal portions, and is provided below the bent portion so as to contact the lower portion of the bent portion to the outside of the bent portion, the interval between the plurality of terminals exposed from the side surface of the sealing member can be narrowed without a space distance and with an increased creepage distance, and the semiconductor device can be downsized.
Drawings
Fig. 1 is a schematic plan view showing a semiconductor device according to embodiment 1 of the present invention.
Fig. 2 is a schematic sectional configuration diagram showing a semiconductor device in embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional structure diagram showing another semiconductor device in embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional structure view of a semiconductor device according to embodiment 1 of the present invention, the cross-sectional structure being enlarged at an outer peripheral end portion thereof.
Fig. 5 is a schematic cross-sectional structure view of another semiconductor device according to embodiment 1 of the present invention, the outer peripheral end portion of the semiconductor device being enlarged.
Fig. 6 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention.
Fig. 10 is a schematic cross-sectional structure view of a semiconductor device in embodiment 1 of the present invention, with an enlarged outer peripheral end portion.
Fig. 11 is a schematic cross-sectional structure view of a semiconductor device in embodiment 1 of the present invention, with an outer peripheral end portion enlarged.
Fig. 12 is a schematic cross-sectional view of a semiconductor device according to embodiment 1 of the present invention, with an enlarged outer peripheral end portion.
Fig. 13 is a schematic cross-sectional structure diagram showing another manufacturing process of the semiconductor device in embodiment 1 of the present invention.
Fig. 14 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention.
Fig. 15 is a schematic sectional configuration diagram showing a semiconductor device in embodiment 2 of the present invention.
Fig. 16 is a schematic cross-sectional structure diagram showing another semiconductor device in embodiment 2 of the present invention.
Fig. 17 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 2 of the present invention.
Fig. 18 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to embodiment 3 of the present invention is applied.
Detailed Description
First, the overall structure of the semiconductor device of the present invention is described with reference to the drawings. The drawings are schematic and do not reflect the exact size and the like of the components shown. Note that the same reference numerals denote the same or equivalent parts, and this is common throughout the specification.
Fig. 1 is a schematic plan view showing a semiconductor device according to embodiment 1 of the present invention. Fig. 2 is a schematic sectional configuration diagram showing a semiconductor device in embodiment 1 of the present invention. Fig. 1 is a plan view of a semiconductor device 100 as viewed from the top surface. Fig. 2 is a schematic sectional view of the structure shown by a one-dot chain line AA in fig. 1. In the drawing, a semiconductor device 100 includes a semiconductor element 1, an electronic component 2, a lead frame 3 as a metal member, a sealing member 4, and a bonding wire 6. Here, the lead frame 3 has an upper surface and a lower surface, and a plurality of members included in the lead frame 3 similarly have an upper surface and a lower surface. Further, in the terminal portions 3e of the lead frame 3, the upper surface corresponds to the inner surface and the lower surface corresponds to the outer surface in structure.
In fig. 1, the outer shape of the sealing member 4 is different in size between the upper surface side and the lower surface side of the lead frame 3. On the side surface side where the terminal portions 3e of the lead frame 3 are exposed (projected), the outer shape of the sealing member 4 on the lower surface side of the lead frame 3 is larger than the outer shape of the sealing member 4 on the upper surface side of the lead frame 3. In other words, the sealing member 4 is provided on the side surface of the sealing member 4 where the terminal portions 3e of the lead frame 3 are exposed, so that the sealing member 4 protrudes from the lower surface side of the lead frame 3 to the outside of the outer surface of the terminal portions 3e of the lead frame 3. The sealing member 4 is provided on the upper surface side of the lead frame 3 at a position inward of the inner surface of the terminal portion 3e of the lead frame 3. The side surface of the sealing member 4 where the terminal portions 3e of the lead frame 3 are exposed is flat (has no unevenness) with respect to the arrangement direction of the terminal portions 3e of the lead frame 3. The plurality of terminal portions 3e of the lead frame 3 are arranged in parallel with an interval therebetween. The side surface of the sealing member 4 between the adjacent terminal portions 3e of the plurality of terminal portions 3e of the lead frame 3 is a flat surface. The plurality of terminal portions 3e of the lead frame 3 are exposed from the same side surface of the sealing member 4 at the same height.
Therefore, when the plurality of terminal portions 3e of the lead frame 3 are exposed from the side surface side of the sealing member 4 to the outside of the sealing member 4, the sealing member 4 for insulating between the plurality of terminal portions 3e of the lead frame 3 is not provided between the plurality of terminal portions 3e of the lead frame 3. However, since the intervals between the plurality of terminal portions 3e of the lead frame 3 can be determined by considering only the insulation distance between the terminal portions 3e of the adjacent lead frames 3, the semiconductor device 100 can be miniaturized. Further, the lead frame 3 is one in principle, but may be separated (may be plural). The plurality of terminal portions 3e of the lead frame 3 are exposed from both opposing side surfaces of the sealing member 4, but it is not always necessary to be exposed from both opposing side surfaces of the sealing member 4, and the plurality of terminal portions 3e of the lead frame 3 may be exposed from at least one side surface of the sealing member 4.
In fig. 2, the lead frame 3 includes a plurality of members. The lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, and a terminal portion 3 e. The semiconductor element 1 is mounted on the upper surface of the mounting portion 3a of the lead frame 3. A region extending continuously upward from the mounting portion 3a of the lead frame 3 is an inclined portion (first inclined portion) 3 b. A region connected to the upper end of the first inclined portion 3b on the opposite side of the connection portion with the mounting portion 3a of the lead frame 3 and extending outside the sealing member 4 is a flat portion 3 c. The portion of the lead frame 3 exposed from the sealing member 4 and bent is a bent portion 3 d. A region extending from the bent portion 3d of the lead frame 3 to the tip end portion (the other end) of the lead frame 3 is a terminal portion 3 e. The terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portions 3d of the lead frame 3 are located at one end of the terminal portions 3e of the lead frame 3, a plurality of bent portions 3d are provided, the number of which is the same as that of the terminal portions 3e of the lead frame 3.
The flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3. A bent portion is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent at the bent portion toward the upper surface side of the mounting portion 3a of the lead frame 3.
Further, a flat portion 3c on which the electronic component 2 is mounted is provided above the mounting portion 3a of the lead frame 3, separately from the mounting portion 3a of the lead frame 3 on which the semiconductor element 1 is mounted, on the side opposite to (the side facing) the side surface exposed from the terminal portion 3e of the lead frame 3 continuous from the mounting portion 3a of the lead frame 3 on which the semiconductor element 1 is mounted on the upper surface. A bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the other end of the flat portion 3c of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent toward the upper surface side of the mounting portion 3a of the lead frame 3 at the bent portion 3d of the lead frame 3. These lead frame 3 regions are electrically connected by bonding wires 6 or the like as necessary. The flat portion 3c of the lead frame 3 is provided in plural numbers corresponding to the plural terminal portions 3e of the lead frame 3. In addition, since one end of the flat portion 3c of the lead frame 3 is not necessarily connected to the first inclined portion 3b of the lead frame 3, the number of the first inclined portions 3b of the lead frame 3 is smaller than the number of the flat portions 3c of the lead frame 3. In addition, as the configuration of the lead frame 3, the mounting portion 3a of the lead frame 3 may be directly connected to the flat portion 3c of the lead frame 3 without providing the first inclined portion 3b of the lead frame 3.
The lead frame 3 has the terminal portions 3e of the lead frame 3 exposed from both side surfaces of the sealing member 4, which are both sides of the mounting portion 3a of the lead frame 3, and the terminal portions 3e of the lead frame 3 are bent toward the upper surface side of the sealing member 4. A sealing member 4 is provided below the bent portion 3d of the lead frame 3.
Copper is generally used as a material of the lead frame 3. Regarding the thickness of the lead frame 3, the lead frame 3 is stably manufactured by punching, and can be appropriately selected between 0.1mm and 1mm in accordance with the value of the current flowing in the terminal portion 3 e. Since the lead frame 3 is basically manufactured by pressing a plate-shaped member, the thickness of the lead frame 3 is uniform among the members. However, in the plurality of members of the lead frame 3, the thickness of the lead frame 3 may be different thicknesses according to the function of the members. In particular, the thickness associated with the definition of the outer peripheral position of the sealing member 4 is the thickness of the terminal portions 3e of the lead frame 3. The terminal portions 3e of the lead frame 3 have a uniform thickness.
As the semiconductor element 1, a power semiconductor element such as an IGBT, a MOSFET, a bipolar transistor, a diode, or the like can be generally used. As a material of the semiconductor element 1, Silicon (Si: Silicon) or Silicon carbide (SiC: Silicon carbide) can be used. The semiconductor element 1 is bonded to a predetermined position of the mounting portion 3a of the lead frame 3 using solder or the like (not shown) as a bonding member.
As the electronic component 2, an IC (Integrated Circuit) element, a resistor, a capacitor, or the like can be used. The electronic component 2 is bonded to a predetermined position of the flat portion 3c of the lead frame 3 using a resin paste or the like (not shown) as a bonding member.
The bonding wire 6 connects the lead frame 3 and the semiconductor element 1. Further, bonding wires 6 connect the plurality of semiconductor elements 1 to each other. Then, bonding wire 6 connects semiconductor element 1 and electronic component 2.
When the bonding wire 6 is used for connection to the semiconductor element 1, aluminum (Al) having a diameter of about 0.1 to 0.5mm, which is inexpensive and has low electrical conductivity, is generally selected as a material for the bonding wire 6 in connection to a member through which a large current flows, such as the semiconductor element 1, and the bonding pad on the lead frame 3 is bonded to the bonding portion of the semiconductor element 1 by ultrasonic waves. When the bonding wire 6 is used for connecting a member other than a member through which a large current flows, such as the semiconductor element 1, or the electronic component 2, a material having a high electrical conductivity, such as gold, silver, or copper, is selected as a material of the bonding wire 6, finely processed to a diameter of 0.05mm or less, and wire-bonded to a small pad on the semiconductor element 1 or the electronic component 2.
The sealing member 4 ensures insulation between the members to be sealed, and also functions as a case of the semiconductor device 100. The sealing member 4 integrally seals the semiconductor element 1 mounted on the lead frame 3, the electronic component 2 mounted on the lead frame 3, the bonding wire 6, and the lead frame 3. As described above, the outer peripheral position (size) of the sealing member 4 differs between the upper surface side of the lead frame 3 and the lower surface side of the lead frame 3. The outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is a position sandwiched by the terminal portions 3e of the respective opposing lead frames 3 (both sides) exposed from the respective opposing side surfaces of the sealing member 4. That is, the outer peripheral position of the sealing member 4 on the upper surface side of the lead frame 3 is located on the inner peripheral side (inner side) of the inner surface of each terminal portion 3e of the lead frame 3 facing each other exposed from each facing side surface of the sealing member 4. The outer peripheral position of the sealing member 4 on the lower surface side of the lead frame 3 is located on the outer peripheral side (outer side) of the outer surface of each terminal portion 3e of the lead frame 3 facing each other exposed from each facing side surface of the sealing member 4.
In other words, the sealing member 4 is provided below the bent portion 3d of the lead frame 3 and on the side surface side of the sealing member 4 where the terminal portion 3e of the lead frame 3 is exposed, so as to protrude outward from the outer surface of the terminal portion 3e of the lead frame 3 by the thickness of the lead frame 3 or more. The sealing member 4 is provided above the bent portion 3d of the lead frame 3 and inside the inner surface of the terminal portion 3e of the lead frame 3. Further, the sealing member 4 is provided outside the bent portion 3d of the lead frame 3 in direct contact with the lower portion of the bent portion 3d of the lead frame 3. The upper surface of the sealing member 4 is located above the upper surface of the flat portion 3c of the lead frame 3. Note that, when the bent portion 3d of the lead frame 3 is replaced with the flat portion 3c of the lead frame 3 and observed, the sealing member 4 is also arranged in the same manner.
As a material of the sealing member 4, a thermosetting epoxy resin can be generally used. The thermosetting epoxy resin is filled with Silica (SiO)2) The coefficient of linear expansion is made close to that of copper.
On the lower side of the lower surface of the mounting portion 3a of the lead frame 3, aluminum nitride (AlN), Boron Nitride (BN) or silicon dioxide (SiO) filled as a high heat dissipation filler is applied as an insulating heat dissipation material, without applying the sealing member 42) The sheet of epoxy resin (2) having a thickness of 0.1mm to 0.3mm can have improved heat dissipation properties while maintaining insulation properties. In addition, aluminum nitride (AlN), silicon nitride (SiN), and silicon dioxide (SiO) can also be used as high heat dissipation insulating materials2) Or a DBC (Direct bonded coater: directly plated with copper) substrate. The same effect can be obtained by using an AMB (Active Metal Brazing) substrate or a DBA (Direct Bonded Aluminum) substrate.
Fig. 3 is a schematic cross-sectional structure diagram showing another semiconductor device in embodiment 1 of the present invention. In the drawing, a semiconductor device 200 includes a semiconductor element 1, an electronic component 2, a lead frame 3 as a metal member, a sealing member 4, and a bonding wire 6.
The semiconductor device 100 shown in fig. 2 differs from the semiconductor device 200 in the position of the outer peripheral end portion of the sealing member 4 on the lower surface side of the lead frame 3. In the semiconductor device 200, the outer peripheral end position of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the bent portion 3d of the lead frame 3 at the same position as the outer surface of the terminal portion 3e of the lead frame 3. In other words, the outer peripheral end portion of the sealing member 4 above the bent portion 3d of the lead frame 3 is located inward of the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3 by the thickness of the lead frame 3. Since other points are the same as those of the semiconductor device 100, detailed description thereof is omitted.
Next, effects of the semiconductor devices 100 and 200 having the above-described structure will be described.
Fig. 4 is an enlarged cross-sectional structural view of the outer peripheral end portion of the semiconductor device in embodiment 1 of the present invention. Fig. 5 is an enlarged cross-sectional structural view of the outer peripheral end portion of another semiconductor device in embodiment 1 of the present invention. In fig. 4 and 5, a heat dissipation member 9 is provided on the lower surface side of the sealing member 4 on the lower surface side of the lead frame 3. The heat radiating member 9 can be made of a metal material such as copper or aluminum. In fig. 4 and 5, a path shown by an arrow between the lead frame 3 and the heat dissipation member 9 is a creepage distance 8.
As shown in fig. 4 and 5, the sealing member 4 is provided on the lower surface of the bent portion 3d of the lead frame 3 so as to directly contact therewith. Therefore, even when the semiconductor devices 100 and 200 are fastened and arranged to the heat dissipation member 9 with screws or the like, the spatial distance from the lower portion of the bent portion 3d of the lead frame 3 to the upper surface of the heat dissipation member 9 can be eliminated, and the sealing member 4 can perform insulation protection. Further, with such a configuration, the creepage distance 8 from only the lower portion of the bent portion 3d of the lead frame 3 to the upper surface of the heat dissipating member 9 is a limitation in insulation design of the semiconductor device, the dielectric strength between the bent portion 3d of the lead frame 3 and the heat dissipating member 9 is improved, and the inverter design can be facilitated without requiring a labor and time for insulation protection by adding an insulating member such as an insulating sheet to the lower portion of the bent portion 3d of the lead frame 3.
Further, since the creepage distance 8 is also extended, even when dust, contaminants, or moisture intrudes between the lower region of the bent portion 3d of the lead frame 3 and the heat dissipating member 9, it is possible to withstand insulation failure such as leakage, and high contamination resistance in conformity with international standard IEC60664-1 is achieved, thereby improving the reliability life of the semiconductor device. Further, the insulation property and the degree of contamination of the semiconductor device can be made equivalent to those of a case-type semiconductor device in which a terminal for external connection is fitted into or externally inserted into a case member.
In the semiconductor devices 100 and 200 configured as described above, since the sealing member 4 is disposed in contact with the lower portion of the bent portion 3d of the lead frame 3, it is possible to eliminate a spatial distance and secure a creepage distance when the heat dissipation member 9 is disposed on the lower surface side of the semiconductor devices 100 and 200. In the semiconductor devices 100 and 200, the side surfaces of the sealing member 4 between the exposed terminal portions 3e of the lead frame 3 are flat (have no irregularities) in the arrangement direction of the terminal portions 3e of the lead frame 3, so that the distance between the terminal portions 3e of the lead frames 3 can be shortened, and the semiconductor devices 100 and 200 can be downsized.
Next, a method for manufacturing the semiconductor device 100 of embodiment 1 configured as described above will be described.
Fig. 6 to 9 are schematic cross-sectional structural views showing respective manufacturing steps of a semiconductor device in embodiment 1 of the present invention. Fig. 6 is a schematic plan-view structural view showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Fig. 7 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Fig. 8 is a schematic plan-view structural view showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Fig. 9 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Through these steps, the semiconductor device 100 shown in fig. 2 can be manufactured.
First, semiconductor element 1 and electronic component 2 are prepared, and as shown in fig. 6, semiconductor element 1 is mounted on a predetermined position of mounting portion 3a on the upper surface side of lead frame 3 having an upper surface and a lower surface which are processed into a predetermined shape, and electronic component 2 is mounted on a predetermined position of flat portion 3c of lead frame 3. The semiconductor element 1 is joined to the mounting portion 3a of the lead frame 3 via solder. The electronic component 2 is bonded to the flat portion 3c of the lead frame 3 via the resin paste. Then, the semiconductor element 1, the electronic component 2, and the lead frame 3 provided at a predetermined position of the mounting portion 3a or the flat portion 3c of the lead frame 3 are connected by bonding wires 6 having a diameter corresponding to the purpose, and wiring is performed (semiconductor element mounting step).
Next, as shown in fig. 7, the lead frame 3 on which the semiconductor element 1 and the electronic component 2 are mounted is disposed in the mold 20 (metal member disposing step). The mold 20 includes an upper mold 10 and a lower mold 11. The lead frame 3 is held in the space 40 in the mold 20 by sandwiching the terminal portion 3e side (the region exposed from the sealing member 4) from the flat portion 3c of the lead frame 3 by the upper mold 10 and the lower mold 11. The side surfaces (inner walls) of the upper mold 10 sandwiching the terminal portions 3e at least from the flat portions 3c of the lead frame 3 are flat (have no unevenness) in the arrangement direction of the terminal portions 3e of the lead frame 3. In particular, the inner side walls of the upper mold 10 between the plurality of terminal portions 3e of the lead frame 3 are flat. Further, the inner wall of the upper mold 10 is provided at a position inside the inner wall of the lower mold 11. In other words, the inner wall of the lower mold 11 is provided at a position outside the inner wall of the upper mold 10. The difference between the inner side wall of the upper mold 10 and the inner side wall of the lower mold 11 is equal to or greater than the thickness of the lead frame 3. When the difference between the inner wall of the upper mold 10 and the inner wall of the lower mold 11 is smaller than the thickness of the lead frame 3, the bent portion 3d of the lead frame 3 protrudes from the outer peripheral region of the sealing member 4 (the lower surface side of the bent portion 3d is exposed), and therefore a space distance is generated. However, since the inner wall of the upper mold 10 is located inward of the inner wall of the lower mold 11, the sealing member 4 can be disposed below the bent portion 3d of the lead frame 3, and the occurrence of a spatial distance can be suppressed.
Next, as shown in fig. 8, the sealing member 4 is filled in the space 40 of the mold 20 in which the lead frame 3 is arranged, and the lead frame 3 is integrally sealed (sealing step). The sealing member 4 is filled into the mold 20 in conformity with the shape of the mold 20. Generally, the molding is performed by transfer molding. After the sealing member 4 is filled in the mold 20, the curing process of the filled sealing member 4 is performed. Here, the upper surface of the sealing member 4 is provided above the bent portion 3d of the lead frame 3 formed in the periphery in contact with the lower end of the inner wall of the upper mold 10.
Next, as shown in fig. 9, the lead frame 3 sealed with the sealing member 4 is taken out from the mold 20 (metal member taking-out step). After being taken out of the mold 20, the terminal portions 3e of the lead frame 3 exposed from the side surface side of the sealing member 4 are bent (bent) at the bent portions 3d provided on both sides of the lead frame 3 so that the upper surface sides of the lead frame 3 face each other (a metal member processing step).
Through the above steps, the semiconductor device 100 shown in fig. 2 can be manufactured.
Fig. 10 is a schematic cross-sectional structure view of a semiconductor device in embodiment 1 of the present invention, with an enlarged outer peripheral end portion. Fig. 11 is a schematic cross-sectional structure view of a semiconductor device in embodiment 1 of the present invention, with an outer peripheral end portion enlarged. Fig. 12 is a schematic cross-sectional view of a semiconductor device according to embodiment 1 of the present invention, with an enlarged outer peripheral end portion, showing another manufacturing process. Fig. 13 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Fig. 14 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 1 of the present invention. Fig. 10, 11, and 12 show an example of the metal member processing step. Fig. 13 and 14 show the side surface side of the semiconductor device 100 where the lead frame 3 is exposed from the sealing member 4.
In fig. 10, 11, 12, and 13, a plating film 12 as a mold release member is provided on the lower surface side of the lead frame 3 in a region including the bent portion 3d between the other end of the flat portion 3c and the terminal portion 3e on the lower surface side of the lead frame 3. In fig. 10, the plating film 12 on the lower surface side of the lead frame 3 is provided in a region in contact with the sealing member 4. The sealing member 4 is not present on the upper surface side of the lead frame 3 corresponding to the position where the plating film 12 is disposed, and the upper surface of the lead frame 3 is exposed. In fig. 11, the lead frame 3 is bent at a bent portion 3d toward the upper surface side of the mounting portion 3a of the lead frame 3. The plating film 12 is peeled off from the sealing member 4 on the outer surface side of the terminal portion 3e of the lead frame 3, but the region corresponding to the thickness of the lead frame 3 in the bent portion 3d of the lead frame 3 is kept in contact with the sealing member 4. In fig. 13, the plating film 12 has the same width as the lead frame 3, is provided on the lower surface side of the lead frame 3 exposed from the sealing member 4, and is in contact with the sealing member 4.
In fig. 11 and 12, a region of the lead frame 3 (from a part of the flat portion 3c to the terminal portion 3e) exposed from the side surface of the sealing member 4 on the upper surface side of the lead frame 3 is bent at the bent portion 3d toward the upper surface side of the mounting portion 3a of the lead frame 3 (the terminal portion 3e of the lead frame 3 is bent toward the side surface of the sealing member 4). At this time, since the plating film 12 is formed in the region on the lower surface side of the lead frame 3, the adhesion force between the region on the lower surface side of the lead frame 3 where the plating film 12 is formed and the sealing member 4 is weaker than the adhesion force between the region where the plating film 12 is not formed, and therefore the lead frame 3 and the sealing member 4 can be easily peeled. Therefore, the occurrence of resin burrs caused by the separation of the lead frame 3 from the sealing member 4 can also be reduced. Immediately after the sealing member 4 is molded, it is effective to perform a process of peeling the lead frame 3 from the sealing member 4 when the sealing member 4 is not sufficiently cured and the adhesion between the lead frame 3 and the sealing member 4 in a state where the sealing member 4 is at a high temperature is small.
As shown in fig. 12, when the lead frame 3 is bent at the bent portion 3d, a pressing jig that presses the upper surface side of the lead frame 3 may be used, but in this case, a gap 3g corresponding to the size (thickness) of the pressing jig is formed between the side surface on the upper surface side of the sealing member 4 and the upper surface side of the lead frame 3. In this case, the position of the side surface (outer peripheral end portion) of the sealing member 4, which is exposed from the lead frame 3 on the upper surface side of the lead frame 3, is set to a position corresponding to the gap 3g inside the inner surface of the terminal portion 3e of the lead frame 3.
In order to form the plating film 12 on the lower surface side of the lead frame 3, a process (metal member plating film forming step) of forming a plating film at a corresponding position on the lower surface side of the lead frame 3 is performed before the lead frame 3 is placed in the mold 20.
As shown in fig. 14, a hole 13 may be provided in a region of the lead frame 3 where the plating film 12 is formed, and the hole 13 may be a hole portion penetrating the lead frame 3 and the plating film 12. By providing the hole 13 in this manner, the adhesion force with the sealing member 4 in the region where the plating film 12 is formed can be reduced, and the lead frame 3 can be easily peeled off from the sealing member 4. This enables the lead frame 3 to be processed without impairing the function of the semiconductor device 100. Further, only the hole 13 may be provided without providing the plating film 12.
By using the upper mold 10 in which the position of the inner wall of the upper mold 10 shown in fig. 7 is close to the position of the inner wall of the lower mold 11 (expanded to the outer circumferential side), the semiconductor device 200 can be manufactured. The inner wall of the lower mold 11 is provided at a position outside the inner wall of the upper mold 10 by an amount corresponding to the thickness of the lead frame 3.
In the semiconductor devices 100 and 200 configured as described above, the sealing member 4 is provided at the lower portion of the bent portion 3d of the lead frame 3, and the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat, so that there is no space and a creepage distance can be increased, and a narrow pitch of the interval of the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 is achieved, and the semiconductor devices 100 and 200 can be downsized.
Further, since the sealing member 4 is provided below the bent portion 3d of the lead frame 3 and the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat, there is no space and a creepage distance can be increased, and the insulating withstand voltage from the exposed portion of the self-sealing member 4 of the lead frame 3 to the heat dissipating member 9 is improved, so that there is no labor and time for adding an insulating sheet to shield the lead frame 3 and the heat dissipating member 9, and the inverter design can be facilitated.
Further, since the sealing member 4 is disposed below the bent portion 3d of the lead frame 3, the creepage distance 8 can be extended, and even if dust, contaminants, or moisture intrudes between the exposed portion of the lead frame 3 and the heat dissipating member 9, an insulation failure such as a leakage trace can be received, and the reliability of the semiconductor devices 100 and 200 can be improved.
In this case, since the sealing member 4 is provided below the bent portion 3d of the lead frame 3 and the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat, there is no space and a creepage distance can be increased, and a pitch between the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed, thereby making it possible to reduce the size of the semiconductor device.
Fig. 15 is a schematic sectional configuration diagram showing a semiconductor device in embodiment 2 of the present invention. In the drawing, a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 as a metal member, a sealing member 4, and a bonding wire 6.
In fig. 15, the lead frame 3 includes a plurality of members. The lead frame 3 includes a mounting portion 3a, an inclined portion (first inclined portion) 3b, a flat portion 3c, a bent portion 3d, a terminal portion 3e, and an inclined portion (second inclined portion) 3 f. The semiconductor element 1 is mounted on the upper surface of the mounting portion 3a of the lead frame 3. A region extending continuously upward from the mounting portion 3a of the lead frame 3 is an inclined portion (first inclined portion) 3 b. A region connected to the upper end of the first inclined portion 3b on the opposite side of the connection portion with the mounting portion 3a of the lead frame 3 and extending outside the sealing member 4 is a flat portion 3 c. A region continuously extending from the flat portion 3c of the lead frame 3 toward the upper surface side of the sealing member 4 is a slope portion (second slope portion) 3 f. A portion connected to the upper end portion of the second inclined portion 3f of the lead frame 3 and exposed from the sealing member 4, at which the lead frame 3 is bent, is a bent portion 3 d. A region extending from the bent portion 3d of the lead frame 3 to the tip end portion (the other end) of the lead frame 3 is a terminal portion 3 e. The terminal portion 3e of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. Since the bent portions 3d of the lead frame 3 are located at one end of the terminal portions 3e of the lead frame 3, a plurality of bent portions 3d are provided, the number of which is the same as that of the terminal portions 3e of the lead frame 3.
The flat portion 3c of the lead frame 3 is provided above the mounting portion 3a of the lead frame 3. One end of the flat portion 3c of the lead frame 3 is connected to the upper end of the first inclined portion 3b of the lead frame 3. The other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3. A bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the upper end portion of the second inclined portion 3f of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent toward the upper surface side of the mounting portion 3a of the lead frame 3 at the bent portion 3d of the lead frame 3.
Further, a flat portion 3c on which the electronic component 2 is mounted is provided above the mounting portion 3a of the lead frame 3, separately from the mounting portion 3a on which the semiconductor element 1 of the lead frame 3 is mounted, on the side opposite to (the side facing) the side surface exposed from the terminal portion 3e of the lead frame 3 continuing from the mounting portion 3a of the lead frame 3 on which the semiconductor element 1 is mounted. The other end of the flat portion 3c of the lead frame 3 is connected to the lower end of the second inclined portion 3f of the lead frame 3 provided above the flat portion 3c of the lead frame 3. A bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. A bent portion 3d of the lead frame 3 is provided at one end of the terminal portion 3e of the lead frame 3. The bent portion 3d of the lead frame 3 is connected to the upper end portion of the second inclined portion 3f of the lead frame 3. The terminal portion 3e of the lead frame 3 is bent toward the upper surface side of the mounting portion 3a of the lead frame 3 at the bent portion 3d of the lead frame 3. These lead frame 3 regions are electrically connected by bonding wires 6 or the like as necessary. The flat portion 3c of the lead frame 3 is provided in plural numbers corresponding to the plural terminal portions 3e of the lead frame 3. In addition, since one end of the flat portion 3c of the lead frame 3 is not necessarily connected to the first inclined portion 3b of the lead frame 3, the number of the first inclined portions 3b of the lead frame 3 is smaller than the number of the flat portions 3c of the lead frame 3. A plurality of second inclined portions 3f of the lead frame 3 are provided corresponding to the plurality of terminal portions 3e of the lead frame 3.
The lead frame 3 has the terminal portions 3e of the lead frame 3 exposed from both side surfaces of the sealing member 4, which are both sides of the mounting portion 3a of the lead frame 3, and the terminal portions 3e of the lead frame 3 are bent toward the upper surface side of the sealing member 4. A sealing member 4 is provided below the bent portion 3d of the lead frame 3.
On the side surface side of the sealing member 4 where the terminal portions 3e of the lead frame 3 are exposed, the sealing member 4 is provided so as to protrude outward from the outer surface of the terminal portions 3e of the lead frame 3 below the bent portions 3d of the lead frame 3. The sealing member 4 is provided above the bent portion 3d of the lead frame 3 and inside the inner surface of the terminal portion 3e of the lead frame 3. Also, the sealing member 4 is directly in contact with the lower portion of the bent portion 3d of the lead frame 3 and is disposed to the outside of the bent portion 3d of the lead frame 3. In addition, the upper surface of the sealing member 4 is provided at the same height as the upper end of the second inclined portion 3f of the lead frame 3.
Fig. 16 is a schematic cross-sectional structure diagram showing another semiconductor device in embodiment 2 of the present invention. In the drawing, a semiconductor device 300 includes a semiconductor element 1, an electronic component 2, a lead frame 3 as a metal member, a sealing member 4, and a bonding wire 6.
The semiconductor device 400 shown in fig. 16 differs from the semiconductor device 300 in the position of the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3. In the semiconductor device 400, the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3 is provided at the same position as the outer surface of the terminal portion 3e of the lead frame 3. Therefore, the following configuration: the inner surface of the terminal portion 3e of the lead frame 3 is located at a position 0.1mm to 1mm inside the outer peripheral end portion of the sealing member 4 below the bent portion 3d of the lead frame 3 by the thickness of the lead frame 3. Since other points are the same as those of the semiconductor device 300, detailed description thereof is omitted.
Next, a method for manufacturing the semiconductor devices 300 and 400 will be described. Basically, the semiconductor device can be manufactured through the same steps as the manufacturing method of the semiconductor devices 100 and 200 described in embodiment 1. However, the shape of the mold used for molding the sealing member 4 is different.
Fig. 17 is a schematic cross-sectional structure diagram showing a manufacturing process of a semiconductor device in embodiment 2 of the present invention. In the drawing, the mold 30 includes an upper mold 31 and a lower mold 32.
As shown in fig. 17, the upper die 31 used in embodiment 2 has a function of a cover for sandwiching the lead frame 3 with the lower die 32 and holding the lead frame 3 in the die 30. Therefore, in the upper mold 31, the space 40 (cavity) of the sealing member 4 is not filled. On the other hand, the lower mold 32 has a cavity 40 in which the lead frame 3 is disposed as a whole. In order to dispose the lead frame 3 in the cavity 40, the lead frame 3 is provided with a second inclined portion 3 f. In this case, the upper surface of the sealing member 4 has the same height as the bent portion 3d of the lead frame 3 formed around the periphery in contact with the bottom surface of the upper die 10.
Since the cavity 40 is formed only in the lower mold 32, the cost for mold production is reduced as compared with the case where the cavity 40 is formed also in the upper mold 31, and maintenance work such as mold cleaning and mold part replacement can be performed efficiently.
In the semiconductor devices 300 and 400 configured as described above, since the sealing member 4 is provided on the lower portion side of the bent portion 3d of the lead frame 3 and the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat, there is no space and a creepage distance can be increased, and the pitch of the interval between the terminal portions 3e of the lead frame 3 exposed from the side surface of the sealing member 4 can be narrowed, and the semiconductor devices 300 and 400 can be downsized.
Further, since the sealing member 4 is provided at the lower portion of the bent portion 3d of the lead frame 3 and the side surface of the sealing member 4 between the plurality of terminal portions 3e of the lead frame 3 exposed from the sealing member 4 is made flat, there is no space and a creepage distance can be increased, and since the dielectric breakdown voltage between the exposed portion of the lead frame 3 and the heat dissipating member 9 is improved, there is no labor and time for shielding by adding an insulating sheet, and it is possible to facilitate the inverter design.
Further, since the sealing member 4 is disposed below the bent portion 3d of the lead frame 3, the creepage distance 8 from the bent portion 3d of the lead frame 3 to the heat dissipating member 9 can be increased, and even if dust, contaminants, or moisture intrudes between the exposed portion of the lead frame 3 and the heat dissipating member 9, an insulation failure such as a tracking can be received, and the reliability of the semiconductor devices 300 and 400 can be improved.
Further, since the second inclined portion 3f is provided in the lead frame 3, the creepage distance of the lead frame 3 exposed from the sealing member 4 can be increased, and the reliability of the semiconductor devices 300 and 400 can be improved.
In embodiment 3, the semiconductor device according to embodiment 1 or 2 is applied to a power conversion device. The present invention is not limited to a specific power conversion device, and a case where the present invention is applied to a three-phase inverter will be described below as embodiment 3.
Fig. 18 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to embodiment 3 of the present invention is applied.
The power conversion system shown in fig. 18 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a dc power supply and supplies dc power to the power conversion device 2000. The power supply 1000 may be configured by various components, and may be configured by, for example, a DC system, a solar cell, or a storage battery, or may be configured by a rectifier circuit connected to an AC system, an AC/DC converter, or the like. Further, power supply 1000 may be configured by a DC/DC converter that converts DC power output from a DC system into predetermined power.
The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts dc power supplied from the power supply 1000 into ac power and supplies the ac power to the load 3000. As shown in fig. 18, the power conversion device 2000 includes a main conversion circuit 2001 that converts dc power input from the power supply 1000 into ac power and outputs the ac power, and a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the main conversion circuit 2001.
The load 3000 is a three-phase motor driven by ac power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, and is a motor mounted on various electric devices, for example, a motor for a hybrid car, an electric car, a railway vehicle, an elevator, an air conditioner, or the like.
Hereinafter, details of the power conversion device 2000 will be described. The main converter circuit 2001 includes a switching element and a free wheeling diode (not shown) incorporated in the semiconductor device 2002, and converts dc power supplied from the power supply 1000 into ac power by switching the switching element, and supplies the ac power to the load 3000. The main converter circuit 2001 has various specific circuit configurations, and the main converter circuit 2001 of the present embodiment is a 2-level three-phase full bridge circuit and can be configured with 6 switching elements and 6 free wheeling diodes connected in anti-parallel to the respective switching elements. The main converter circuit 2001 is configured by a semiconductor device 2002 corresponding to any one of embodiments 1 to 5, in which each switching element, each free wheeling diode, and the like are incorporated. The 6 switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main converter circuit 2001 are connected to a load 3000.
The main converter circuit 2001 includes a drive circuit (not shown) for driving each switching element. The driver circuit may be incorporated in the semiconductor device 2002, or may be provided separately from the semiconductor device 2002. The drive circuit generates a drive signal for driving the switching element of the main converter circuit 2001, and supplies the drive signal to the control electrode of the switching element of the main converter circuit 2001. Specifically, a drive signal for turning the switching element into an on state and a drive signal for turning the switching element into an off state are output to the control electrode of each switching element in accordance with a control signal from a control circuit 2003 described later. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.
The control circuit 2003 controls the switching elements of the main converter circuit 2001 so as to supply a desired power to the load 3000. Specifically, based on the power to be supplied to the load 3000, the time (on time) for which each switching element of the main converter circuit 2001 should be brought into an on state is calculated. For example, the main converter circuit 2001 can be controlled by PWM control for modulating the on time of the switching element in accordance with a voltage to be output. Further, a control command (control signal) is output to the drive circuit provided in the main converter circuit 2001 so that an on signal is output to the switching element to be turned on and an off signal is output to the switching element to be turned off at each time. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.
In the power converter of embodiment 3 configured as described above, the semiconductor device according to embodiment 1 or 2 is applied as the semiconductor device 2002 of the main converter circuit 2001, and therefore, reliability can be improved.
In the present embodiment, an example in which the present invention is applied to a 2-level three-phase inverter has been described, but the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, the power converter is a 2-level power converter, but a 3-level or multilevel power converter is also possible, and the present invention may be applied to a single-phase inverter when power is supplied to a single-phase load. In addition, the present invention can be applied to a DC/DC converter, an AC/DC converter, and the like even when power is supplied to a DC load or the like.
The power converter to which the present invention is applied is not limited to the case where the load is a motor, and can be used as a power conditioner for a solar power generation system, a power storage system, or the like, as well as a power discharge machine, a laser processing machine, an induction heating cooker, a power supply device for a non-contact power supply system, or the like, for example.
In particular, when SiC is used as the semiconductor element 1, the power semiconductor element is operated at a higher temperature than that of Si in order to exhibit its characteristics. Since higher reliability is required in a semiconductor device on which an SiC device is mounted, the advantages of the present invention, which realizes a highly reliable semiconductor device, are more effective.
It should be understood that the above-described embodiments are illustrative only and not restrictive in all respects. The scope of the present invention is defined not by the scope of the above embodiments but by the appended claims, and includes all modifications within the meaning and scope equivalent to the claims. In addition, the invention may be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments.
Description of reference numerals
1 semiconductor element, 2 electronic component, 3 lead frame, 3a carrying portion, 3b inclined portion (first inclined portion), 3c flat portion, 3d curved portion, 3e terminal portion, 3f inclined portion (second inclined portion), 3g gap, 4 sealing member, 6 bonding wire, 8 creepage distance, 9 heat dissipation member, 20, 30 die, 10, 31 upper die, 11, 32 lower die, 12 plating film, 13 hole, 40 space (cavity), 100, 200, 300, 400, 2002 semiconductor device, 1000 power supply, 2000 power conversion device, 2001 main conversion circuit, 2003 control circuit, 3000 load.
Claims (11)
1. A semiconductor device, wherein the semiconductor device comprises:
a semiconductor element;
a metal member having a mounting portion on which the semiconductor element is mounted on an upper surface thereof, and a plurality of terminal portions that are provided above the mounting portion, are arranged in parallel with an interval therebetween, and have a bent portion at one end thereof, the plurality of terminal portions being bent toward the upper surface side of the mounting portion at the bent portions thereof; and
and a sealing member that exposes the plurality of terminal portions from a side surface of the sealing member, the side surface between the plurality of terminal portions being flat, the sealing member being provided above the bent portion at a position inside an inner surface of the plurality of terminal portions, and being provided below the bent portion in contact with a lower portion of the bent portion to an outer side of the bent portion, the sealing member integrally sealing the semiconductor element and the metal member.
2. The semiconductor device according to claim 1,
in the sealing member, an outer circumferential position of the sealing member disposed below the bent portion is disposed at a position outside an outer circumferential position of the sealing member disposed above the bent portion by an amount corresponding to a thickness of the metal member or more.
3. The semiconductor device according to claim 1 or claim 2,
in the sealing member, an outer circumferential position of the sealing member disposed above the bent portion is disposed inward of an outer circumferential position of the sealing member disposed below the bent portion by an amount corresponding to a thickness of the metal member.
4. The semiconductor device according to any one of claims 1 to 3,
the metal member has a plurality of flat portions provided above the mounting portion and a plurality of first inclined portions connecting the mounting portion and one ends of the flat portions, and the other ends of the flat portions are connected to the bent portions, respectively.
5. The semiconductor device according to any one of claims 1 to 3,
the metal member has a plurality of flat portions provided above the mounting portion, a plurality of first inclined portions connecting the mounting portion and one ends of the flat portions, and a plurality of second inclined portions provided above the plurality of first inclined portions and connecting the other ends of the flat portions and the plurality of bent portions, and the upper surface of the sealing member is provided at the same height as the upper end of the second inclined portions.
6. The semiconductor device according to any one of claims 1 to 5,
the metal member is provided with a mold release member in a region from a region where the bent portion faces the sealing member to an outer surface of the terminal portion.
7. The semiconductor device according to claim 6,
the release member is a plating film.
8. The semiconductor device according to claim 6 or claim 7,
the metal member is provided with a hole in a region where the mold release member is provided.
9. A method for manufacturing a semiconductor device, comprising:
a semiconductor element mounting step of mounting a semiconductor element on an upper surface of a mounting portion of a metal member;
a metal member disposing step of disposing a metal member having the mounting portion and the plurality of terminal portions arranged above the mounting portion and spaced apart from each other in a mold having the upper mold and the lower mold, the metal member having an inner wall of the upper mold, the inner wall sandwiching the plurality of terminal portions, being flat between the plurality of terminal portions, the inner wall of the upper mold being provided with an inner wall of the lower mold outside the inner wall of the upper mold;
a sealing step of filling a sealing member into the mold in which the metal member is disposed, and integrally sealing the semiconductor element and the metal member; and
and a metal member processing step of bending the plurality of terminal portions exposed from the side surface of the sealing member at a bent portion toward the upper surface side of the mounting portion.
10. The method for manufacturing a semiconductor device according to claim 9,
the method for manufacturing a semiconductor device further includes a metal member plating film forming step of forming a plating film in a region including the bent portion of each of the plurality of terminal portions of the metal member.
11. A power conversion device, comprising:
a main conversion circuit having the semiconductor device according to any one of claims 1 to 8, converting an input power and outputting the converted power; and
and the control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2019/001378 WO2020148879A1 (en) | 2019-01-18 | 2019-01-18 | Semiconductor device, production method for semiconductor device, and power conversion device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113261095A true CN113261095A (en) | 2021-08-13 |
Family
ID=71614151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980088014.4A Pending CN113261095A (en) | 2019-01-18 | 2019-01-18 | Semiconductor device, method for manufacturing semiconductor device, and power conversion device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP7053897B2 (en) |
| CN (1) | CN113261095A (en) |
| WO (1) | WO2020148879A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7479771B2 (en) * | 2020-10-01 | 2024-05-09 | 三菱電機株式会社 | Semiconductor device, manufacturing method thereof, and power conversion device |
| JP7535909B2 (en) | 2020-10-20 | 2024-08-19 | 三菱電機株式会社 | Power semiconductor device, its manufacturing method, and power conversion device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005051109A (en) * | 2003-07-30 | 2005-02-24 | Matsushita Electric Ind Co Ltd | Power semiconductor module |
| US20060056213A1 (en) * | 2004-08-21 | 2006-03-16 | Joosang Lee | Power module package having excellent heat sink emission capability and method for manufacturing the same |
| CN103972198A (en) * | 2013-01-25 | 2014-08-06 | 三菱电机株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| WO2015173862A1 (en) * | 2014-05-12 | 2015-11-19 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing same |
| JP2017147332A (en) * | 2016-02-17 | 2017-08-24 | 株式会社三井ハイテック | Lead frame and manufacturing method thereof, and semiconductor package |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174453U (en) * | 1986-05-30 | 1988-11-11 | ||
| JPH02232957A (en) * | 1989-03-06 | 1990-09-14 | Yamada Seisakusho:Kk | Lead frame of resin sealed type semiconductor device |
| JPH03108744A (en) * | 1989-09-22 | 1991-05-08 | Toshiba Corp | Resin-sealed semiconductor device |
| JPH04286355A (en) * | 1991-03-15 | 1992-10-12 | Matsushita Electron Corp | Lead frame |
| JP3108744B2 (en) | 1994-04-28 | 2000-11-13 | 京セラ株式会社 | Noise prevention circuit |
| JP4286355B2 (en) | 1998-12-16 | 2009-06-24 | 富士重工業株式会社 | Composite material forming method and forming jig |
| JP2010003947A (en) | 2008-06-23 | 2010-01-07 | Yamaha Corp | Method for manufacturing semiconductor device |
| JP6305176B2 (en) | 2014-04-11 | 2018-04-04 | 三菱電機株式会社 | Semiconductor device and manufacturing method |
| WO2018185974A1 (en) | 2017-04-06 | 2018-10-11 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same, and power conversion device |
-
2019
- 2019-01-18 JP JP2020566062A patent/JP7053897B2/en active Active
- 2019-01-18 CN CN201980088014.4A patent/CN113261095A/en active Pending
- 2019-01-18 WO PCT/JP2019/001378 patent/WO2020148879A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005051109A (en) * | 2003-07-30 | 2005-02-24 | Matsushita Electric Ind Co Ltd | Power semiconductor module |
| US20060056213A1 (en) * | 2004-08-21 | 2006-03-16 | Joosang Lee | Power module package having excellent heat sink emission capability and method for manufacturing the same |
| CN103972198A (en) * | 2013-01-25 | 2014-08-06 | 三菱电机株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| WO2015173862A1 (en) * | 2014-05-12 | 2015-11-19 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing same |
| JP2017147332A (en) * | 2016-02-17 | 2017-08-24 | 株式会社三井ハイテック | Lead frame and manufacturing method thereof, and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7053897B2 (en) | 2022-04-12 |
| JPWO2020148879A1 (en) | 2021-09-27 |
| WO2020148879A1 (en) | 2020-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109727960B (en) | Semiconductor module, method for manufacturing the same, and power conversion device | |
| US11244836B2 (en) | Semiconductor apparatus, power conversion device, and method for manufacturing semiconductor apparatus | |
| US9437508B2 (en) | Method for manufacturing semiconductor device and semiconductor device | |
| JP7091878B2 (en) | Power modules, power converters, and methods for manufacturing power modules | |
| WO2021181831A1 (en) | Electrical circuit body, power conversion device, and electrical circuit body manufacturing method | |
| CN113454773A (en) | Semiconductor device, method for manufacturing semiconductor device, and power conversion device | |
| CN111293087B (en) | Semiconductor device and power conversion device | |
| JP7053897B2 (en) | Semiconductor devices, manufacturing methods for semiconductor devices, and power conversion devices | |
| CN111052325A (en) | Semiconductor module and power conversion device | |
| WO2019216161A1 (en) | Power semiconductor module, method for producing same and electric power converter | |
| US11652032B2 (en) | Semiconductor device having inner lead exposed from sealing resin, semiconductor device manufacturing method thereof, and power converter including the semiconductor device | |
| CN113841235B (en) | Semiconductor module, method for manufacturing semiconductor module, and power conversion device | |
| WO2022049660A1 (en) | Semiconductor device, power conversion device, and mobile body | |
| US11784105B2 (en) | Semiconductor device and power converter | |
| US11887903B2 (en) | Power semiconductor device, method for manufacturing power semiconductor device, and power conversion apparatus | |
| JP7535909B2 (en) | Power semiconductor device, its manufacturing method, and power conversion device | |
| WO2022123870A1 (en) | Electrical circuit body, power conversion device, and electrical circuit body manufacturing method | |
| JP6851559B1 (en) | Semiconductor devices and power converters | |
| US20240290695A1 (en) | Semiconductor device and power conversion apparatus | |
| JP7555257B2 (en) | Electrical circuit body, power conversion device, and method for manufacturing the electrical circuit body | |
| WO2024009613A1 (en) | Electrical circuit body and power conversion device | |
| JP7171516B2 (en) | Power semiconductor module, power converter, and method for manufacturing power semiconductor module | |
| WO2022137701A1 (en) | Electric circuit element and power converting apparatus | |
| US11145616B2 (en) | Semiconductor device, power conversion apparatus, and method for manufacturing semiconductor device | |
| US20220223546A1 (en) | Semiconductor device and power converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |