WO2020146994A1 - 芯片及芯片的制造方法 - Google Patents

芯片及芯片的制造方法 Download PDF

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Publication number
WO2020146994A1
WO2020146994A1 PCT/CN2019/071682 CN2019071682W WO2020146994A1 WO 2020146994 A1 WO2020146994 A1 WO 2020146994A1 CN 2019071682 W CN2019071682 W CN 2019071682W WO 2020146994 A1 WO2020146994 A1 WO 2020146994A1
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Prior art keywords
chip
porous silicon
substrate
layer
silicon structure
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PCT/CN2019/071682
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English (en)
French (fr)
Inventor
陆斌
沈健
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to CN201980000113.2A priority Critical patent/CN111699551B/zh
Priority to PCT/CN2019/071682 priority patent/WO2020146994A1/zh
Publication of WO2020146994A1 publication Critical patent/WO2020146994A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the embodiments of the present application relate to information security technology, and in particular to a chip and a method for manufacturing the chip.
  • the embodiments of the present application provide a chip and a method for manufacturing the chip to solve the problem of low reliability of the self-destructing chip in the prior art.
  • an embodiment of the present application provides a chip
  • the chip body includes:
  • the device layer which is located on the substrate
  • Porous silicon structure the porous silicon structure is arranged on the substrate, and the porous silicon structure is used to react with the chemical capping solution to destroy the chip body.
  • the substrate has at least one reserved area, and the porous silicon structure is arranged in the reserved area and is exposed at least outside the substrate.
  • the reserved area includes a receiving cavity provided on the substrate, and the porous silicon structure is provided in the receiving cavity.
  • the chip body further includes an insulating passivation layer, the insulating passivation layer is located on the substrate, and the insulating passivation layer covers the device layer.
  • the insulating passivation layer has a first opening, and the first opening is in communication with the accommodating cavity on the substrate.
  • the chip body further includes a conductive interconnection layer, the conductive interconnection layer is located on the substrate, and the insulating passivation layer covers the conductive interconnection layer.
  • the porous silicon structure is a porous silicon layer formed in a reserved area.
  • the porous silicon structure is a porous silicon chip arranged in the containing cavity.
  • the porous silicon layer is located on the side of the substrate away from the device layer.
  • the porous silicon structure is located outside the device layer.
  • the porous silicon structure is distributed on the four corners of the chip body.
  • the accommodating cavity is located in the region of the chip body corresponding to the dicing lane.
  • the accommodating cavity is located on the side of the substrate away from the device layer.
  • the gap between the accommodating cavity and the porous silicon wafer is filled with an organic material that can be dissolved in a chemical capping solution.
  • the porous silicon layer is covered with an organic material that can be dissolved in a chemical capping solution.
  • the holes of the porous silicon structure are filled with an oxidant.
  • the chip body further includes a pad, the pad is located in the insulating passivation layer, and the insulating passivation layer has a second opening, and the second opening is connected to the pad .
  • the thickness of the porous silicon structure is 1 ⁇ m to 200 ⁇ m.
  • the chip provided in the embodiment of the present application has a substrate resistivity of 1-20 ⁇ cm.
  • the chip provided in the embodiment of the present application further has a conductive layer on the substrate, and the conductive layer is located on the side of the substrate that is away from the porous silicon structure.
  • the chip further includes a packaging structure, and the packaging structure is used for packaging the chip body.
  • the chip provided in the embodiment of the present application has a silicon substrate as the substrate.
  • an embodiment of the present application provides a method for manufacturing a chip, including the following steps:
  • a porous silicon structure is fabricated on the substrate to obtain a chip body; wherein, the porous silicon structure is used to react with a chemical capping solution to destroy the chip body.
  • the method for manufacturing a chip provided by the embodiment of the present application, fabricating a porous silicon structure on a substrate to obtain a chip body specifically includes:
  • the porous silicon structure is arranged in the reserved area, and the porous silicon structure is exposed at least outside the substrate.
  • the method for manufacturing a chip provided in the embodiment of the present application, arranging the porous silicon structure in the reserved area specifically includes: etching the porous silicon layer in the reserved area.
  • the method for manufacturing a chip provided in the embodiment of the present application, arranging the porous silicon structure in a reserved area specifically includes:
  • An embodiment of the application provides a chip and a method for manufacturing the chip.
  • Nitric acid as a chemical decap solution reacts with the porous silicon structure to destroy the chip body, thereby preventing the information stored in the chip from being maliciously deciphered and stolen, preventing reverse engineering of the chip manufacturing process, and preventing the analysis of the structural parameters and material components of the chip. In this way, the security of the chip is improved in all aspects.
  • FIG. 1 is a schematic structural diagram of a chip provided in Embodiment 1 of the application;
  • FIG. 2 is a diagram of the position between the area of the dicing lane and the insulating passivation layer in a chip provided in the first embodiment of the application;
  • FIG. 3 is a schematic structural diagram of a chip provided in Embodiment 2 of the application.
  • FIG. 4 is a schematic structural diagram of a chip provided in Embodiment 3 of the application.
  • FIG. 5 is a schematic structural diagram of a porous silicon chip in a chip provided in Embodiment 3 of the application
  • FIG. 6 is a schematic structural diagram of a chip provided in Embodiment 4 of the application.
  • FIG. 7 is a flowchart of a method for manufacturing a chip provided in Embodiment 5 of the application.
  • FIG. 8 is a schematic structural diagram of the package of the chip body in a method for manufacturing a chip provided in the fifth embodiment of the application.
  • 10 chip body; 101—substrate; 1011—accommodating cavity; 1012—porous silicon layer; 1013—porous silicon wafer; 1014—organic material; 102—device layer; 103—conductive interconnection layer; 104—insulating passivation layer 1041—the first opening; 1042—the second opening; 105—the area of the cutting track; 106—the conductive layer; 20—single crystal silicon; 30—the base; 40—metal lead; 50—lead frame; 60—plastic packaging material .
  • FIG. 1 is a schematic structural diagram of a chip provided in Embodiment 1 of the application.
  • the chip provided in this embodiment includes a chip body 10, which includes a substrate 101, a device layer 102, and a porous silicon structure.
  • the device layer 102 is located on a substrate 101 and the porous silicon structure is disposed on the substrate 101.
  • the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • the substrate 101 in this embodiment is a silicon substrate, and the material of the substrate 101 can also be germanium, gallium arsenide, silicon-on-insulator or other semiconductor materials.
  • the material of the substrate 101 is not limited in this embodiment. .
  • the chip body 10 further includes an insulating passivation layer 104, the insulating passivation layer 104 is located on the substrate 101, and the insulating passivation layer 101 covers the device layer 102.
  • the chip body 10 further includes a conductive interconnection layer 103, the conductive interconnection layer 103 is located on the substrate 101, and the insulating passivation layer 104 covers the conductive interconnection layer 103.
  • the specific layout in the device layer 102 and the connection mode of the insulating passivation layer 104, the device layer 102 and the conductive interconnection layer 103 can be specifically designed according to chips with different functions, which are not limited in this embodiment.
  • nitric acid which is commonly used for chemical lid opening, can effectively remove the plastic packaging material covering the chip body 10 without damaging the chips, so nitric acid soaking is the most common chemical lid opening method.
  • a porous silicon structure is provided on the substrate 101, so that after the nitric acid removes the molding compound covering the chip, it comes into contact with the porous silicon structure and produces a violent reaction, thereby destroying the chip body 10 and reaching the chip The purpose of destruction.
  • the substrate 101 has at least one reserved area, and the porous silicon structure is arranged in the reserved area and is exposed at least outside the substrate 101. Further, the reserved area includes a receiving cavity 1011 provided on the substrate 101, and the porous silicon structure is provided in the receiving cavity 1011.
  • the porous silicon structure is disposed in the accommodating cavity 1011 on the substrate 101, and after the nitric acid removes the plastic packaging material covering the chip body 10, the nitric acid passes through and is exposed to at least the accommodating outside of the substrate 101.
  • the cavity 1011 enters the porous silicon structure and reacts with the porous silicon structure to destroy the chip body 10, thereby preventing the information stored in the chip from being maliciously stolen, preventing reverse engineering of the chip manufacturing process, and preventing the analysis of the structural parameters and material composition of the chip , In order to improve the security of the chip.
  • the porous silicon structure is a porous silicon layer 1012 formed in a reserved area.
  • the porous silicon layer 1012 is etched in the reserved area, and the porous silicon layer 1012 can be prepared by electrochemical etching.
  • the specific preparation method of chemical etching is not limited in this embodiment.
  • the resistivity of the substrate 101 is 1-20 ⁇ cm
  • the thickness of the porous silicon layer 1012 is 1 ⁇ m-200 ⁇ m. In this way, the porous silicon layer 1012 on the substrate 101 can better react with nitric acid to damage the chip body 10.
  • the porosity of the porous silicon layer 1012 is 20-80%
  • the pore diameter of the pores in the porous silicon layer 1012 is on the order of nm
  • the thickness, porosity, and pore size of the porous silicon layer 1012 can be adjusted during chemical etching.
  • the composition of the etching solution, the current density and the reaction time are adjusted, which is not limited in this embodiment.
  • the substrate 101 further has a conductive layer 106, and the conductive layer 106 is located on the side of the substrate 101 that is away from the porous silicon layer 1012.
  • the conductive layer may be a P-type or N-type heavily doped region formed by doping the substrate, or may be a metal layer or a heavily doped silicon layer obtained by a material deposition process.
  • a P-type heavily doped layer can be formed on the back of the substrate 101 through an ion implantation process in advance, and the P-type heavily doped layer and the porous silicon layer 1012 relatively.
  • the P-type heavily doped layer is used to enhance the electrical contact quality between the substrate 101 and the etching solution during electrochemical corrosion, otherwise a current loop cannot be formed.
  • the conductive layer 106 is formed on the entire back of the substrate 101, or a part of the back of the substrate 101 has a conductive layer 106, as long as the back of the substrate 101 has a conductive layer 106 opposite to the porous silicon layer 1012, This embodiment is not limited here.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3
  • One or more of the oxidants are used to further enhance the reactivity of the porous silicon layer 1012.
  • the porous silicon layer 1012 filled with oxidant will burst when irradiated by the laser, thereby increasing the chip's ability to prevent the laser from being opened.
  • the insulating passivation layer 104 has a first opening 1041, and the first opening 1041 is in communication with the accommodating cavity 1011 on the substrate 101.
  • the chip body 10 further includes a pad, the pad is located in the insulating passivation layer 104, the insulating passivation layer 104 has a second opening 1042, and the second opening 1042 is connected to the pad.
  • the porous silicon layer 1012 is covered with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the chip further includes a packaging structure, and the packaging structure is used to package the chip body 10.
  • the package structure may include a base 30, metal leads 40, a lead frame 50 and a plastic encapsulation material 60.
  • the chip body 10 is pasted on the base 30, and the pads of the chip body 10 and the lead frame 50 are connected with the metal leads 40, and the plastic is sealed Material 60 covers the entire structure.
  • FIG. 2 is a position diagram between the area of the dicing lane and the insulating passivation layer in a chip provided in Embodiment 1 of the application.
  • the accommodating cavity 1011 is located in the area 105 of the chip body 10 corresponding to the dicing lane.
  • the porous silicon structure may also be located outside the device layer 102.
  • the porous silicon structure can also be distributed at the four corners of the chip body 10.
  • FIG. 3 is a schematic structural diagram of a chip provided in Embodiment 2 of the application.
  • the porous silicon layer 1012 is located on the side of the substrate 101 away from the device layer 102.
  • the porous silicon layer 1012 and the insulating passivation layer 104 are respectively located on the back and the front of the substrate 101, and the first opening 1041 on the insulating passivation layer 104 is opposite to the receiving cavity 1011 on the substrate 101.
  • the conductive layer 106 is a P-type heavily doped layer, and the P-type heavily doped layer on the substrate 101 is located in the substrate 101 at the first opening 1041.
  • the first opening 1041 needs to be provided on the insulating passivation layer 104 to determine the location of the porous silicon layer 1012 to be etched. Due to the lateral scooping effect of the electrochemical corrosion, the distance between the edge of the chip device layer 102 and the porous silicon layer 1012 needs to be increased to prevent damage to the chip. Therefore, in this embodiment, the corrosion area of the porous silicon layer 1012 is changed to the side opposite to the device layer 102, which can avoid this problem and obtain a chip with a smaller size.
  • the porous silicon layer 1012 is disposed on the side of the substrate 101 away from the device layer 102. In this way, while improving the security of the chip, the size of the final chip is reduced.
  • FIG. 4 is a schematic structural diagram of a chip provided in Embodiment 3 of this application
  • FIG. 5 is a schematic structural diagram of a porous silicon chip in a chip provided in Embodiment 3 of this application.
  • the porous silicon structure is a porous silicon chip 1013 arranged in a containing cavity 1011.
  • the accommodating cavity 1011 is a groove, which can be made on the substrate 101 by a photolithography process, and the groove is in communication with the first opening 1041.
  • the porous silicon wafer 1013 is separately manufactured by additional wafers.
  • the porous silicon wafer 1013 may be all porous silicon, or may include porous silicon and part of single crystal silicon 20. Due to the relatively large unevenness of the electrochemical etching process, the production of the porous silicon wafer 1013 alone can better control the chip yield. Chip raise the chip.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that is soluble in the chemical capping solution.
  • the organic material 1014 may be a resin material.
  • the porous silicon layer 1012 is etched in the reserved area on the substrate 101. Due to the unevenness of the electrochemical corrosion, the yield of the chip may be affected. Therefore, in the chip provided in this embodiment, a porous silicon wafer 1013 is separately fabricated, and a groove made on the substrate 101 has the porous silicon wafer 1013 arranged in the groove. Due to the relatively large unevenness of the electrochemical etching process, the production of the porous silicon wafer 1013 alone can better control the chip yield.
  • FIG. 6 is a schematic structural diagram of a chip provided in the fourth embodiment of the application.
  • the porous silicon wafer 1013 is located on the side of the substrate 101 away from the device layer 102.
  • the porous silicon wafer 1013 and the device layer 102 are respectively located on two opposite sides of the substrate 101.
  • the first opening 1041 is not provided on the insulating passivation layer 104.
  • the accommodating cavity 1011 is located on the side of the substrate 101 away from the device layer 102
  • FIG. 7 is a flowchart of a method for manufacturing a chip provided in Embodiment 5 of the application. As shown in FIG. 7, an embodiment of the present application provides a method for manufacturing a chip, including the following steps:
  • a silicon wafer is selected as the substrate 101, and a device layer 102, a conductive interconnection layer 103, and an insulating passivation layer 104 are formed on the substrate 101 using a semiconductor manufacturing process.
  • a conductive layer 106 is formed on the substrate 101, and the conductive layer 106 is located on the side of the substrate 101 away from the porous silicon layer 1012.
  • a first opening 1041 is provided on the insulating passivation layer 104.
  • a photolithography process can be used to provide a first opening 1041 on the insulating passivation layer 104 in a specific area of the chip to expose the silicon substrate 101.
  • the first opening 1041 is located at the four corners of the chip, and the first opening 1041 may also be located in the middle of the chip.
  • the shape of the first opening 1041 can be any geometric figure, which is not limited in this embodiment.
  • S102 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • At least one reserved area is provided on the substrate 101, and the porous silicon layer 1012 is etched in the reserved area.
  • the silicon wafer is placed in an electrochemical reaction device, and the porous silicon layer 1012 is etched at the position of the first opening 1041 on the insulating passivation layer 104 (that is, the porous silicon layer is etched at the position of the cavity 1011 on the substrate 101). 1012).
  • the porosity and pore size of the porous silicon layer 1012, as well as the thickness of the porous silicon layer 1012 are adjusted by controlling the composition of the etching solution in the electrochemical reaction device, the current density and the reaction time.
  • the thickness of the porous silicon layer 1012 is controlled to be 1 ⁇ m to 200 ⁇ m,
  • the porosity of the porous silicon layer 1012 is controlled to be 20% to 80%, and the pore diameter of the pores in the porous silicon layer 1012 is controlled to the nm level.
  • the porous silicon layer 1012 is covered with an organic material 1014 that is soluble in a chemical capping solution.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3 One or more of.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • the surface where the metal layer 106 is formed on the substrate 101 is ground and polished to thin the silicon wafer to the required thickness, and then the silicon wafer is cut into individual small pieces along the area 105 of the chip dicing path. chip.
  • the chip body 10 is packaged by a packaging structure.
  • FIG. 8 is a schematic structural diagram of the package of the chip body in a method for manufacturing a chip provided in the fifth embodiment of the application.
  • the chip body 10 is pasted on the base 30, the pads of the chip body 10 and the lead frame 50 are connected with metal leads 40, and the entire structure is covered with a plastic encapsulating material 60.
  • Other packaging methods can also be used, which is not limited in this embodiment.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the second embodiment above.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and a device layer 102, a conductive interconnection layer 103 and an insulating passivation layer 104 are formed on the substrate 101 by using a semiconductor process to realize the pre-designed function of the chip.
  • the first opening 1041 is provided on the insulating passivation layer 104, and the specific method for setting the first opening 1041 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • a P-type heavily doped layer is formed in the substrate 101 at the first opening 1041.
  • the side of the silicon wafer opposite to the device layer 102 is thinned to a desired thickness.
  • S202 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a reserved area is provided on the thinned side of the substrate 101, and the porous silicon layer 1012 is etched in the reserved area.
  • the specific growth method of the porous silicon layer 1012 is the same as that of the fifth embodiment, which will not be repeated in this embodiment.
  • the pores of the porous silicon layer 1012 are filled with an oxidant.
  • the oxidant can be sulfur, Ca(ClO 4 ) 2 , NH 4 ClO 4 , LiClO 4 , NaClO 4 , KClO 4 , Ca(NO 3 ) 2 , NH 4 NO 3 , KNO 3 or Gd(NO 3 ) 3 One or more of.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • the area 105 along the chip dicing lane cuts the silicon wafer into individual small chips.
  • the chip body 10 is packaged by a packaging structure.
  • packaging of the chip body 10 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the third embodiment.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and the device layer 102, the conductive interconnection layer 103 and the insulating passivation layer 104 are formed on the substrate 101 to realize the pre-designed function of the chip, wherein the insulating passivation layer 104 covers The device layer 102 and the conductive interconnection layer 103.
  • the first opening 1041 is provided on the insulating passivation layer 104, and the specific method for setting the first opening 1041 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • a second opening 1042 is provided on the insulating passivation layer 104, and the second opening 1042 is connected to the pad. Specifically, a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in an area corresponding to the pad to expose the pad.
  • S302 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein, the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a groove is provided on the substrate 101 as the accommodating cavity 1011, the accommodating cavity 1011 is connected to the first opening 1041, and the manufactured porous silicon wafer 1013 is put into the accommodating cavity 1011 through the first opening 1041 Inside.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the side of the silicon wafer opposite to the device layer 102 is reduced to a desired thickness, and the silicon wafer is cut into individual small chips along the area 105 of the chip dicing lane.
  • the chip body 10 is packaged by a packaging structure.
  • packaging of the chip body 10 is the same as that of the fifth embodiment, and this embodiment will not be repeated here.
  • the embodiment of the present application provides a method for manufacturing a chip, which corresponds to the chip provided in the fourth embodiment.
  • the embodiment of the application provides a method for manufacturing a chip, which includes the following steps:
  • a silicon wafer is selected as the substrate 101, and the device layer 102, the conductive interconnection layer 103, and the insulating passivation layer 104 are formed on the substrate 101 using a semiconductor processing technology to realize the pre-designed function of the chip;
  • a second opening 1042 is provided on the layer 104, and the second opening 1042 is connected to the pad.
  • a photolithography process is used to open a second opening 1042 on the passivation insulating layer 104 in the region corresponding to the pad to expose the pad; the side of the silicon wafer opposite to the device layer 102 is thinned to a desired thickness.
  • S402 Fabricate a porous silicon layer 1012 on the substrate 101 to obtain the chip body 10; wherein, the porous silicon structure is used to react with the chemical capping solution to destroy the chip body 10.
  • a groove is provided on the substrate 101 as the containing cavity 1011, and the containing cavity 1011 is opposite to the device layer 102, and the manufactured porous silicon wafer 1013 is put into the containing cavity 1011 through the first opening 1041.
  • the gap between the accommodating cavity 1011 and the porous silicon wafer 1013 is filled with an organic material 1014 that can be dissolved in a chemical capping solution.
  • the area 105 along the chip dicing lane cuts the silicon wafer into individual small chips.
  • the chip body 10 is packaged by a packaging structure.
  • the packaging of the chip body 10 is basically the same as that of the fifth embodiment above, and this embodiment will not be repeated here.
  • the chip described in each embodiment of the present application may be an integrated circuit in CMOS process or other semiconductor processes, such as a chip containing a memory circuit, or a microelectromechanical (MEMS) chip.
  • the MEMS chip includes a substrate, and a microstructure and sensor layer processed on the substrate.
  • the device layer may be an integrated circuit layer, a microstructure, or a sensor layer, etc., various structures that can realize various signal detection, control, storage, physical quantity conversion and other functions.

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Abstract

一种芯片及芯片的制造方法。芯片包括芯片本体(10)，芯片本体(10)包括：衬底(101)、器件层(102)和多孔硅结构，器件层(102)位于衬底(101)；多孔硅结构设置于衬底(101)上，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体(10)。所述芯片，作为化学开盖溶液的硝酸与多孔硅结构反应，以破坏芯片本体，防止芯片内存储的信息被破解和窃取，提高芯片的安全性。

Description

芯片及芯片的制造方法 技术领域
本申请实施例涉及信息安全技术，尤其涉及一种芯片及芯片的制造方法。
背景技术
为了防止芯片内存储的信息被恶意破解或泄露，制造具有物理自毁功能的芯片是近年来信息安全研究的一个热点。
在一些现有技术中，人们在芯片的结构中设置可远程接收自毁指令的物理自毁装置。在必要时刻，通过主动发送指令，利用光或电触发含能物质爆炸或释放腐蚀性溶液，从而达到摧毁芯片本体，保护芯片内所存储信息安全的目的。然而，上述自毁装置通常结构复杂，不仅体积大、成本高，并且由于包含高能材料或者腐蚀性物质，芯片的可靠性、安全性难以得到长期保障。
发明内容
本申请实施例提供一种芯片及芯片的制造方法，以解决现有技术中自毁芯片可靠性较低的问题。
第一方面，本申请实施例提供一种芯片，
包括芯片本体，芯片本体包括：
衬底；
器件层，器件层位于衬底；
多孔硅结构，多孔硅结构设置于衬底上，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体。
作为一种可选的方式，本申请实施例提供的芯片，衬底具有至少一个预留区域，多孔硅结构设置在预留区域内并至少暴露于衬底之外。
作为一种可选的方式，本申请实施例提供的芯片，预留区域包括设置在衬底上的容置腔，多孔硅结构设置在容置腔内。
作为一种可选的方式，本申请实施例提供的芯片，芯片本体还包括绝缘 钝化层，绝缘钝化层位于衬底上，绝缘钝化层包覆器件层。
作为一种可选的方式，本申请实施例提供的芯片，绝缘钝化层上具有第一开口，第一开口与衬底上的容置腔连通。
作为一种可选的方式，本申请实施例提供的芯片，芯片本体还包括导电互联层，导电互联层位于衬底上，绝缘钝化层包覆导电互联层。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构为形成在预留区域内的多孔硅层。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构为设置在容置腔内的多孔硅片。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅层位于衬底背离器件层的一面。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构位于器件层的外侧。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构分布在芯片本体的四个角。
作为一种可选的方式，本申请实施例提供的芯片，容置腔位于芯片本体的对应切割道的区域内。
作为一种可选的方式，本申请实施例提供的芯片，容置腔位于衬底背离器件层一面。
作为一种可选的方式，本申请实施例提供的芯片，容置腔和多孔硅片之间的间隙中填充有可溶解于化学开盖溶液的有机材料。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅层上覆盖有可溶解于化学开盖溶液的有机材料。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构的孔内填充有氧化剂。
作为一种可选的方式，本申请实施例提供的芯片，芯片本体还包括焊盘，焊盘位于绝缘钝化层内，绝缘钝化层上具有第二开口，第二开口与焊盘接通。
作为一种可选的方式，本申请实施例提供的芯片，多孔硅结构的厚度为1μm～200μm。
作为一种可选的方式，本申请实施例提供的芯片，衬底的电阻率 1-20Ω.cm。
作为一种可选的方式，本申请实施例提供的芯片，衬底上还具有导电层，导电层位于衬底的与多孔硅结构背离的一面。
作为一种可选的方式，本申请实施例提供的芯片，芯片还包括封装结构，封装结构用于封装芯片本体。
作为一种可选的方式，本申请实施例提供的芯片，衬底为硅衬底。
第二方面，本申请实施例提供一种芯片的制造方法，包括以下步骤：
在衬底上形成器件层；
在衬底上制作多孔硅结构，得到芯片本体；其中，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体。
作为一种可选的方式，本申请实施例提供的芯片的制造方法，在衬底上制作多孔硅结构，得到芯片本体，具体包括：
在衬底上设置至少一个预留区域；
将多孔硅结构设置在预留区域内，并使多孔硅结构至少暴露于衬底之外。
作为一种可选的方式，本申请实施例提供的芯片的制造方法，将多孔硅结构设置在预留区域内，具体包括：在预留区域内腐蚀多孔硅层。作为一种可选的方式，本申请实施例提供的芯片的制造方法，将多孔硅结构设置在预留区域内，具体包括：
在衬底上开设容置腔；
将多孔硅片放入容置腔内。
本申请实施例提供的一种芯片及芯片的制造方法。作为化学开盖溶液的硝酸与多孔硅结构反应，以破坏芯片本体，从而防止芯片内存储的信息被恶意破解和窃取，防止对芯片制造工艺的逆向工程，防止分析芯片的结构参数和材料成分，以此全方位提高芯片的安全性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例一提供的一种芯片的结构示意图；
图2为本申请实施例一提供的一种芯片中切割道的区域和绝缘钝化层之间的位置图；
图3为本申请实施例二提供的一种芯片的结构示意图；
图4为本申请实施例三提供的一种芯片的结构示意图；
图5为本申请实施例三提供的一种芯片中多孔硅片的结构示意图
图6为本申请实施例四提供的一种芯片的结构示意图；
图7为本申请实施例五提供的一种芯片的制造方法的流程图；
图8为本申请实施例五提供的一种芯片的制造方法中芯片本体的封装的结构示意图。
附图标记说明：
10—芯片本体；101—衬底；1011—容置腔；1012—多孔硅层；1013—多孔硅片；1014—有机材料；102—器件层；103—导电互联层；104—绝缘钝化层；1041—第一开口；1042—第二开口；105—切割道的区域；106—导电层；20—单晶硅；30—基座；40—金属引线；50—引线框架；60—塑封材料。
具体实施方式
为了使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。如下结合多个 实例对本申请实施例提供的芯片进行详细说明。
实施例一
图1为本申请实施例一提供的一种芯片的结构示意图。如图1所示，本实施例提供的芯片，包括：芯片本体10，芯片本体10包括衬底101、器件层102和多孔硅结构器件层102位于衬底101上多孔硅结构设置于衬底101上，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体10。
具体的，本实施例中衬底101为硅衬底，衬底101的材料还可以为锗、砷化镓、绝缘体上硅或其它半导体材料，对于衬底101的材料本实施例在此不作限定。
可选的，本实施例提供的芯片，芯片本体10还包括绝缘钝化层104，绝缘钝化层104位于衬底101上，绝缘钝化层101包覆器件层102。
可选的，本实施例提供的芯片，芯片本体10还包括导电互联层103，导电互联层103位于衬底101上，绝缘钝化层104包覆导电互联层103。
具体器件层102中的布局，以及绝缘钝化层104、器件层102与导电互联层103的连接方式，可根据不同功能的芯片进行具体的设计，本实施例在此不作限定。
破解和分析芯片，通常需要预先去除包覆于芯片表面的封装材料(俗称“开盖”)，用以暴露芯片本体，再通过探针或额外引线的方式读取芯片内存储的信息。由于大部分芯片使用塑封材料进行封装，而作为化学开盖常用的硝酸，可以有效地去除包覆芯片本体10的塑封料且不损伤芯片，因此使用硝酸浸泡是最为常见的化学开盖手段。在本实施例中，在衬底101上设置多孔硅结构，这样，当硝酸去除包覆芯片的塑封料后，与多孔硅结构接触并产生剧烈的反应，以此破坏芯片本体10，达到芯片自毁的目的。
由于多孔硅结构需要与硝酸直接接触并反应，才可以破坏芯片本体10。也就是说，硝酸去除包覆芯片本体10的塑封材料后，多孔硅结构直接与硝酸接触并产生剧烈的反应。因此，本实施例中，衬底101具有至少一个预留区域，多孔硅结构设置在预留区域内并至少暴露于衬底101之外。进一步的，预留区域包括设置在衬底101上的容置腔1011，多孔硅结构设置在容置腔1011中。
本实施例提供的芯片，通过将多孔硅结构设置在衬底101上容置腔1011 中，硝酸去除包覆芯片本体10的塑封材料后，硝酸通过与至少暴露于衬底101之外的容置腔1011进入多孔硅结构内，并与多孔硅结构反应，以破坏芯片本体10，从而防止芯片内存储的信息被恶意窃取，防止对芯片制造工艺的逆向工程，防止分析芯片的结构参数和材料成分，以此提高芯片的安全性。
在本实施例中，多孔硅结构为形成在预留区域内的多孔硅层1012。在具体实现时，在预留区域内腐蚀多孔硅层1012，多孔硅层1012可以通过电化学腐蚀制备，具体化学腐蚀的制备方法本实施例在此不作限定。
在具体实现时，衬底101的电阻率1-20Ω.cm，多孔硅层1012的厚度为1μm～200μm。这样，衬底101上的多孔硅层1012能更好的与硝酸反应，以破坏芯片本体10。
可选的，多孔硅层1012的孔隙率为20～80％，多孔硅层1012内的孔的孔径为nm级，多孔硅层1012的厚度、孔隙率和孔径的大小可以通过在化学腐蚀时调整腐蚀液成分、电流密度和反应时间来调节，本实施例在此不作限定。
在本实施例中，衬底101上还具有导电层106，导电层106位于衬底101的与多孔硅层1012背离的一面。在具体实现时，导电层可以为通过对衬底掺杂形成的P型或N型重掺杂区域，也可以是通过材料沉积工艺得到的金属层或重掺杂硅层。例如，为了在衬底101正面的预留区域内腐蚀多孔硅层1012，可以预先在衬底101的背面通过离子注入工艺形成P型重掺杂层，P型重掺杂层与多孔硅层1012相对。P型重掺杂层用于增强电化学腐蚀时衬底101与腐蚀液的电接触质量，否则无法形成电流回路。
在具体实现时，导电层106形成在衬底101的整个背面，或者衬底101背面的局部具有导电层106，只要在衬底101的背面具有与多孔硅层1012相对的导电层106即可，本实施例在此不作限定。
进一步的，在本实施例中，多孔硅层1012的孔内填充有氧化剂。
其中，氧化剂可以为硫、Ca(ClO 4) 2、NH 4ClO 4、LiClO 4、NaClO 4、KClO 4、Ca(NO 3) 2、NH 4NO 3、KNO 3或Gd(NO 3) 3中的一种或多种，氧化剂用于进一步加强多孔硅层1012的反应活性。填充有氧化剂的多孔硅层1012，受到激光照射，会发生爆裂，以此增加芯片防止激光开盖的能力。
进一步的，在本实施例中，绝缘钝化层104上具有第一开口1041，第一开口1041与衬底101上的容置腔1011连通。
在具体实现时，芯片本体10还包括焊盘，焊盘位于绝缘钝化层104内，绝缘钝化层104上具有第二开口1042，第二开口1042与焊盘接通。
可选的，在多孔硅层1012上覆盖有可溶解于化学开盖溶液的有机材料1014。
可选的，芯片还包括封装结构，封装结构用于封装芯片本体10。封装结构可以包括基座30、金属引线40、引线框架50和塑封材料60，将芯片本体10黏贴在基座30上，用金属引线40连接芯片本体10的焊盘和引线框架50，用塑封材料60包覆整个结构。
图2为本申请实施例一提供的一种芯片中切割道的区域和绝缘钝化层之间的位置图。如图2所示，容置腔1011位于芯片本体10的对应切割道的区域105内。可选的，多孔硅结构也可位于器件层102的外侧。
可选的，多孔硅结构也可分布在芯片本体10的四个角。
实施例二
图3为本申请实施例二提供的一种芯片的结构示意图。如图3所示，本实施例提供的芯片，多孔硅层1012位于衬底101背离器件层102的一面。也就是说，多孔硅层1012与绝缘钝化层104分别位于衬底101的背面和正面，绝缘钝化层104上第一开口1041与衬底101上的容置腔1011相对。
具体的，在本实施例中，导电层106为P型重掺杂层，衬底101上的P型重掺杂层位于第一开口1041处的衬底101内。
本实施例提供的芯片的其余结构和实施例一提供的芯片的结构相同，本实施例在此不一一赘述。
由于实施例一在芯片的制作中，需要在绝缘钝化层104上设置第一开口1041，来确定腐蚀多孔硅层1012的位置。由于电化学腐蚀水平方向的侧掏效应，需要增大芯片器件层102边缘和多孔硅层1012之间的间距，防止损坏芯片。因此，本实施例，将多孔硅层1012的腐蚀区域改为与器件层102相对的一面，可以避免这一问题，从而获得尺寸较小的芯片。
本实施例提供的芯片，通过将多孔硅层1012设置在衬底101背离器件层102的一面。这样，在提升芯片的安全性的同时，减小最终芯片的尺寸。
实施例三
图4为本申请实施例三提供的一种芯片的结构示意图；图5为本申请实施例三提供的一种芯片中多孔硅片的结构示意图。如图4所示，本实施例提供的芯片，多孔硅结构为设置在容置腔1011内的多孔硅片1013。
在具体实现时，容置腔1011为凹槽，可以通过光刻工艺在衬底101上制作的凹槽，凹槽与第一开口1041连通。
如图5所示，具体的，多孔硅片1013通过额外的晶圆单独制作而成。多孔硅片1013可以全部为多孔硅，也可以包括多孔硅和部分单晶硅20。由于电化学腐蚀工艺的不均匀性相对较大，单独制作多孔硅片1013可以更好地控制芯片良率。芯片提高芯片。
进一步的，容置腔1011和多孔硅片1013之间的间隙中填充有可溶解于化学开盖溶液的有机材料1014。具体的，有机材料1014可以为树脂类材料。通过使用有机材料1014包覆和固定多孔硅片1013，不仅可以使多孔硅片1013隔绝水氧，从而提高多孔硅材料的寿命，有机材料1014还可以在化学开盖时溶解于硝酸中，使硝酸接触多孔硅。
本实施例提供的芯片的其余结构和实施例一提供的芯片的结构相同，本实施例在此不一一赘述。
在衬底101上的预留区域内腐蚀多孔硅层1012，由于电化学腐蚀存在一些不均匀性，对芯片的良率可能产生影响。因此，本实施例提供的芯片，单独制作多孔硅片1013，在衬底101上制作的凹槽，将多孔硅片1013设置在凹槽内。由于电化学腐蚀工艺的不均匀性相对较大，单独制作多孔硅片1013可以更好地控制芯片良率。
实施例四
图6为本申请实施例四提供的一种芯片的结构示意图。如图6所示，本实施例提供的芯片，多孔硅片1013位于衬底101背离器件层102的一面。也就是说，多孔硅片1013与器件层102分别位于衬底101的相对的两面。
可选的，绝缘钝化层104上不设置第一开口1041。
可选的，容置腔1011位于衬底101背离器件层102一面
本实施例提供的芯片的其余结构和实施例三提供的芯片的结构相同，本 实施例在此不一一赘述。
实施例五
本申请实施例提供一种芯片的制造方法，对应于上述实施例一提供的芯片。图7为本申请实施例五提供的一种芯片的制造方法的流程图。如图7所示，本申请实施例提供一种芯片的制造方法，包括以下步骤：
S101：在衬底101上形成器件层102；
在具体实现时，选用硅晶圆作为衬底101，在衬底101上利用半导体制造工艺形成器件层102、导电互联层103和绝缘钝化层104。在此过程中，在衬底101上形成导电层106，导电层106位于衬底101上与多孔硅层1012背离的一面。
在绝缘钝化层104上设置第一开口1041，具体的，可以利用光刻工艺在芯片的特定区域在绝缘钝化层104上设置第一开口1041，暴露硅衬底101。可选的，第一开口1041位置位于芯片的四角，第一开口1041也可以位于芯片中间。第一开口1041的形状可以为任意几何图形，本实施例在此不作限定。
S102：在衬底101上制作多孔硅层1012，得到芯片本体10；其中，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体10。
在具体实现时，在衬底101上设置至少一个预留区域，在预留区域内腐蚀多孔硅层1012。
具体的，将硅晶圆放置于电化学反应装置中，在绝缘钝化层104上的第一开口1041位置腐蚀多孔硅层1012(即在衬底101上容置腔1011的位置腐蚀多孔硅层1012)。通过控制电化学反应装置中腐蚀液成分，电流密度和反应时间，来调整多孔硅层1012的孔隙率、孔径大小，以及多孔硅层1012厚度，其中多孔硅层1012的厚度控制为1μm～200μm，多孔硅层1012的孔隙率控制为20～80％，多孔硅层1012内的孔的孔径控制为nm级。反应完毕后，将硅晶圆取出，用乙二醇溶液清洗干净残留的腐蚀液，再用氮气枪将硅晶圆吹干。
可选的，在多孔硅层1012上覆盖可溶解于化学开盖溶液的有机材料1014。
可选的，在衬底101上制作多孔硅层1012后，在多孔硅层1012的孔内填充有氧化剂。其中，氧化剂可以为硫、Ca(ClO 4) 2、NH 4ClO 4、LiClO 4、NaClO 4、KClO 4、Ca(NO 3) 2、NH 4NO 3、KNO 3或Gd(NO 3) 3中的一种或多种。
在衬底101上制作多孔硅层1012后，在绝缘钝化层104上设置第二开口 1042，第二开口1042与焊盘接通。具体的，利用光刻工艺在对应焊盘的区域在钝化绝缘层104上开设第二开口1042，以暴露焊盘。
暴露焊盘之后，研磨并抛光衬底101上形成金属层106的面，以使硅晶圆减薄至需要的厚度，然后沿芯片切割道的区域105将硅晶圆切割成一个个独立的小芯片。
可选的，对芯片本体10通过封装结构进行封装。
具体的，图8为本申请实施例五提供的一种芯片的制造方法中芯片本体的封装的结构示意图。如图8所示，将芯片本体10黏贴在基座30上，用金属引线40连接芯片本体10的焊盘和引线框架50，用塑封材料60包覆整个结构。也可以采用其他的封装方式，本实施例在此不作限定。
实施例六
本申请实施例提供一种芯片的制造方法，对应于上述实施例二提供的芯片。本申请实施例提供一种芯片的制造方法，包括以下步骤：
S201：在衬底101上形成器件层102；
在具体实现时，选用硅晶圆作为衬底101，在衬底101上利用半导体工艺形成器件层102、导电互联层103和绝缘钝化层104，以实现芯片预先设计的功能。
在绝缘钝化层104上设置第一开口1041，具体的设置第一开口1041的方法与上述实施例五相同，本实施例在此不一一赘述。
在第一开口1041处的衬底101内形成P型重掺杂层，。
将硅晶圆与形成器件层102相对的一面减薄至需要的厚度。
S202：在衬底101上制作多孔硅层1012，得到芯片本体10；其中，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体10。
在具体实现时，在衬底101减薄的一面设置预留区域，在预留区域内腐蚀多孔硅层1012。具体多孔硅层1012的生长方法与上述实施例五相同，本实施例在此不一一赘述。
可选地，在衬底101上制作多孔硅层1012后，在多孔硅层1012的孔内填充有氧化剂。其中，氧化剂可以为硫、Ca(ClO 4) 2、NH 4ClO 4、LiClO 4、NaClO 4、KClO 4、Ca(NO 3) 2、NH 4NO 3、KNO 3或Gd(NO 3) 3中的一种或多种。
在衬底101上制作多孔硅层1012后，在绝缘钝化层104上设置第二开口1042，第二开口1042与焊盘接通。具体的，利用光刻工艺在对应焊盘的区域在钝化绝缘层104上开设第二开口1042，以暴露焊盘。
沿芯片切割道的区域105将硅晶圆切割成一个个独立的小芯片。
可选的，对芯片本体10通过封装结构进行封装。
其中，对芯片本体10进行封装与上述实施例五相同，本实施例在此不一一赘述。
实施例七
本申请实施例提供一种芯片的制造方法，对应于上述实施例三提供的芯片。本申请实施例提供一种芯片的制造方法，包括以下步骤：
S301：在衬底101上形成器件层102；
在具体实现时，选用硅晶圆作为衬底101，在衬底101上形成器件层102、导电互联层103和绝缘钝化层104以实现芯片预先设计的功能，其中绝缘钝化层104包覆器件层102和导电互联层103。
在绝缘钝化层104上设置第一开口1041，具体的设置第一开口1041的方法与上述实施例五相同，本实施例在此不一一赘述。
在绝缘钝化层104上设置第二开口1042，第二开口1042与焊盘接通。具体的，利用光刻工艺在对应焊盘的区域在钝化绝缘层104上开设第二开口1042，以暴露焊盘。
S302：在衬底101上制作多孔硅层1012，得到芯片本体10；其中，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体10。
在具体实现时，在衬底101上设置凹槽作为容置腔1011，容置腔1011与第一开口1041接通，将制作好的多孔硅片1013通过第一开口1041放入容置腔1011内。
可选的，在容置腔1011和多孔硅片1013之间的间隙中填充可溶解于化学开盖溶液的有机材料1014。
将硅晶圆与形成器件层102相对的一面减薄至需要的厚度，沿芯片切割道的区域105将硅晶圆切割成一个个独立的小芯片。
可选的，对芯片本体10通过封装结构进行封装。
其中，对芯片本体10进行封装与上述实施例五相同，本实施例在此不一一赘述。
实施例八
本申请实施例提供一种芯片的制造方法，对应于上述实施例四提供的芯片。本申请实施例提供一种芯片的制造方法，包括以下步骤：
S401：在衬底101上形成器件层102；
在具体实现时，选用硅晶圆作为衬底101，在衬底101上利用半导体加工工艺形成器件层102、导电互联层103和绝缘钝化层104以实现芯片预先设计的功能；在绝缘钝化层104上设置第二开口1042，第二开口1042与焊盘接通。具体的，利用光刻工艺在对应焊盘的区域在钝化绝缘层104上开设第二开口1042，以暴露焊盘；将硅晶圆与形成器件层102相对的一面减薄至需要的厚度。
S402：在衬底101上制作多孔硅层1012，得到芯片本体10；其中，多孔硅结构用于与化学开盖溶液反应以破坏芯片本体10。
在具体实现时，在衬底101上设置凹槽作为容置腔1011，容置腔1011与器件层102相对，将制作好的多孔硅片1013通过第一开口1041放入容置腔1011内。
可选的，在容置腔1011和多孔硅片1013之间的间隙中填充可溶解于化学开盖溶液的有机材料1014。
沿芯片切割道的区域105将硅晶圆切割成一个个独立的小芯片。
可选的，对芯片本体10通过封装结构进行封装。
其中，对芯片本体10进行封装与上述实施例五基本相同，本实施例在此不一一赘述。
另外，本申请各实施例所述的芯片可以是CMOS工艺或者其他半导体工艺的集成电路，例如含有存储电路的芯片，还可以是微机电(MEMS)芯片。MEMS芯片包含衬底，以及在衬底上加工的微结构和传感器层。在本申请的各实施例中，器件层可以是集成电路层、微结构或传感器层等各种可以实现各种信号检测、控制、存储、物理量转换等功能的结构。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通 技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (26)

  1. 一种芯片，其特征在于，包括芯片本体，所述芯片本体包括：
    衬底；
    器件层，所述器件层位于所述衬底；
    多孔硅结构，所述多孔硅结构设置于所述衬底上，所述多孔硅结构用于与化学开盖溶液反应以破坏所述芯片本体。
  2. 根据权利要求1所述的芯片，其特征在于，所述衬底具有至少一个预留区域，所述多孔硅结构设置在所述预留区域内并至少暴露于所述衬底之外。
  3. 根据权利要求2所述的芯片，其特征在于，所述预留区域包括设置在所述衬底上的容置腔，所述多孔硅结构设置在所述容置腔内。
  4. 根据权利要求3所述的芯片，其特征在于，所述芯片本体还包括绝缘钝化层，所述绝缘钝化层位于所述衬底上，所述绝缘钝化层包覆所述器件层。
  5. 根据权利要求4所述的芯片，其特征在于，所述绝缘钝化层上具有第一开口，所述第一开口与所述衬底上的容置腔连通。
  6. 根据权利要求4所述的芯片，其特征在于，所述芯片本体还包括导电互联层，所述导电互联层位于所述衬底上，所述绝缘钝化层包覆所述导电互联层。
  7. 根据权利要求2所述的芯片，其特征在于，所述多孔硅结构为形成在所述预留区域内的多孔硅层。
  8. 根据权利要求3所述的芯片，其特征在于，所述多孔硅结构为设置在所述容置腔内的多孔硅片。
  9. 根据权利要求7所述的芯片，其特征在于，所述多孔硅层位于所述衬底背离所述器件层的一面。
  10. 根据权利要求1所述的芯片，其特征在于，所述多孔硅结构位于所述器件层的外侧。
  11. 根据权利要求1所述的芯片，其特征在于，所述多孔硅结构分布在所述芯片本体的四个角或者四周。
  12. 根据权利要求3所述的芯片，其特征在于，所述容置腔位于所述芯片本体的对应切割道的区域内。
  13. 根据权利要求3所述的芯片，其特征在于，所述容置腔位于所述衬底 背离所述器件层一面。
  14. 根据权利要求8所述的芯片，其特征在于，所述容置腔和所述多孔硅片之间的间隙中填充有可溶解于所述化学开盖溶液的有机材料。
  15. 根据权利要求7所述的芯片，其特征在于，所述多孔硅层上覆盖有可溶解于所述化学开盖溶液的有机材料。
  16. 根据权利要求1所述的芯片，其特征在于，所述多孔硅结构的孔内填充有氧化剂。
  17. 根据权利要求4所述的芯片，其特征在于，所述芯片本体还包括焊盘，所述焊盘位于所述绝缘钝化层内，所述绝缘钝化层上具有第二开口，所述第二开口与所述焊盘接通。
  18. 根据权利要求1-17任一项所述的芯片，其特征在于，所述多孔硅结构的厚度为1μm～200μm。
  19. 根据权利要求1-17任一项所述的芯片，其特征在于，所述衬底的电阻率1-20Ω.cm。
  20. 根据权利要求1-17任一项所述的芯片，其特征在于，所述衬底上还具有导电层，所述导电层位于所述衬底的与所述多孔硅结构背离的一面。
  21. 根据权利要求1-17任一项所述的芯片，其特征在于，所述芯片还包括封装结构，所述封装结构用于封装所述芯片本体。
  22. 根据权利要求1-17任一项所述的芯片，其特征在于，所述衬底为硅衬底。
  23. 一种芯片的制造方法，其特征在于，包括以下步骤：
    在衬底上形成器件层；
    在所述衬底上制作多孔硅结构，得到芯片本体；其中，所述多孔硅结构用于与化学开盖溶液反应以破坏所述芯片本体。
  24. 根据权利要求23所述的芯片的制造方法，其特征在于，所述在衬底上制作多孔硅结构，得到芯片本体，具体包括：
    在所述衬底上设置至少一个预留区域；
    将所述多孔硅结构设置在所述预留区域内，并使所述多孔硅结构至少暴露于所述衬底之外。
  25. 根据权利要求24所述的芯片的制造方法，其特征在于，所述将所述 多孔硅结构设置在所述预留区域内，
    具体包括：在所述预留区域内腐蚀多孔硅层。
  26. 根据权利要求24所述的芯片的制造方法，其特征在于，所述将所述多孔硅结构设置在所述预留区域内，
    具体包括：
    在所述衬底上开设容置腔；
    将多孔硅片放入所述容置腔内。
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