WO2020143215A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020143215A1
WO2020143215A1 PCT/CN2019/098148 CN2019098148W WO2020143215A1 WO 2020143215 A1 WO2020143215 A1 WO 2020143215A1 CN 2019098148 W CN2019098148 W CN 2019098148W WO 2020143215 A1 WO2020143215 A1 WO 2020143215A1
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Prior art keywords
signal
circuit
sub
transistor
driving
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PCT/CN2019/098148
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English (en)
French (fr)
Inventor
吴剑龙
杭玉莹
胡思明
韩珍珍
朱修剑
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昆山国显光电有限公司
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Publication of WO2020143215A1 publication Critical patent/WO2020143215A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present application relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, and a display device.
  • Active matrix organic light emitting diodes Active Matrix Organic Light Emitting Diode, AMOLED
  • AMOLED Active Matrix Organic Light Emitting Diode
  • AMOLED can emit light by the thin film transistor (Thin Film Transistor, TFT) in the saturated state to generate a driving current and drive the light-emitting element-organic light-emitting diode (Organic Light Emitting Diode, OLED) to achieve light emission, OLED light brightness and OLED device
  • TFT Thi Film Transistor
  • OLED Organic Light Emitting Diode
  • the driving current is proportional to the size, so in order to achieve the best display effect, a larger driving current is required. Since low-temperature polysilicon can provide higher electron mobility, low-temperature polysilicon is more commonly used for TFTs in AMOLED display technology.
  • the OLED drive current is related to the drive TFT threshold voltage Vth, and the low-temperature polysilicon process is not mature. Even with the same process parameters, the Vth of the drive TFTs produced is also very different, making The Vth of the driving TFT at different positions of the array substrate is different, which will result in different driving currents of the OLED, and the brightness of the different positions of the array substrate will be different, and the display will be uneven.
  • Embodiments of the present application provide a pixel circuit, a driving method thereof, and a display device, which can ensure uniformity and uniform display of brightness.
  • an embodiment of the present application provides a pixel circuit.
  • the pixel circuit includes: a data writing sub-circuit, an initialization sub-circuit, a light-emitting control sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit;
  • the data writing sub-circuit is used for receiving the first scanning signal and the data signal, and transmitting the data signal to the driving sub-circuit under the control of the first scanning signal;
  • the initialization sub-circuit is used to receive the second scanning signal and the initialization signal, and under the control of the second scanning signal, transmits the initialization signal to the driving sub-circuit;
  • the lighting control sub-circuit is used to receive the control signal and the power supply voltage signal, and under the control of the control signal, transmit the power supply voltage signal to the driving sub-circuit;
  • the driver sub-circuit is used to receive the data signal, the initialization signal, and the power supply voltage signal, and to perform voltage initialization based on the data signal and the initialization signal, and to generate and store a driving voltage that controls the conduction of the driver sub-circuit based on the data signal, and Under control, the power supply voltage signal is transmitted to the light-emitting sub-circuit;
  • the light emitting sub-circuit is used to emit light based on the power supply voltage signal.
  • an embodiment of the present application provides a driving method for a pixel circuit.
  • the driving method is used to drive the pixel circuit provided by the embodiment of the present application; the method includes:
  • the data writing sub-circuit receives the first scan signal and the data signal, and transmits the data signal to the driving sub-circuit under the control of the first scan signal;
  • the initialization sub-circuit receives the second scan signal and the initialization signal, and Under the control of the two scan signals, the initialization signal is transmitted to the driver sub-circuit;
  • the driver sub-circuit receives the data signal and the initialization signal;
  • the data writing sub-circuit receives the first scanning signal and the data signal, and transmits the data signal to the driving sub-circuit under the control of the first scanning signal;
  • the light-emitting control sub-circuit receives the control signal and the power supply voltage signal, and the control signal
  • the power supply voltage signal is transmitted to the driver sub-circuit under the control of the driver;
  • the driver sub-circuit receives the data signal and the power supply voltage signal;
  • the data writing sub-circuit receives the first scan signal and the data signal, transmits the data signal to the driving sub-circuit under the control of the first scanning signal, the driving sub-circuit receives the data signal, and stores the data for controlling the driving sub-circuit Turn-on driving voltage;
  • the first voltage is the voltage at the common terminal of the driving sub-circuit and the data writing sub-circuit
  • the second voltage is the voltage at the common terminal of the driving sub-circuit and the light-emitting sub-circuit
  • the driving voltage is the first voltage and the second voltage Voltage difference
  • the voltage of the data signal received by the data writing sub-circuit during the programming phase is higher than the voltage of the data signal received by the data writing sub-circuit during the initialization phase and the sampling phase;
  • the lighting control sub-circuit receives the control signal and the power supply voltage signal, and transmits the power supply voltage signal to the driving sub-circuit under the control of the control signal; the driving sub-circuit transmits the power supply voltage signal to the lighting sub-circuit under the control of the driving voltage ;
  • the light-emitting sub-circuit emits light based on the power supply voltage signal.
  • an embodiment of the present application provides a display device including the pixel circuit provided by the embodiment of the present application.
  • the pixel circuit, the driving method and the display device of the embodiments of the present application can eliminate the influence of the threshold voltage Vth of the driving switch on the driving current flowing through the light emitting element, and can also eliminate the resistance voltage drop of the power supply voltage IR on the flowing light emitting element.
  • the influence of driving current can ensure the uniformity of brightness and uniform display.
  • FIG. 1 shows a schematic structural diagram of a pixel circuit provided by an embodiment of the present application
  • FIG. 2 shows a specific structural schematic diagram of a pixel circuit provided by an embodiment of the present application
  • FIG. 3 shows another specific structural schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 4 shows a waveform timing chart during driving of a pixel circuit provided by an embodiment of the present application
  • FIG. 5 shows a schematic flowchart of a pixel circuit provided by an embodiment of the present application.
  • FIG. 1 shows a structure of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes: a data writing sub-circuit 101, an initialization sub-circuit 102, a light-emitting control sub-circuit 103, a driving sub-circuit 104, and a light-emitting sub-circuit 105.
  • the data writing sub-circuit 101 is used to receive the first scan signal and the data signal, and transmit the data signal to the driving sub-circuit 104 under the control of the first scan signal.
  • the initialization sub-circuit 102 is used to receive the second scan signal and the initialization signal, and transmit the initialization signal to the driving sub-circuit 104 under the control of the second scan signal.
  • the light emission control sub-circuit 103 is used to receive the control signal and the power supply voltage signal, and transmit the power supply voltage signal to the driving sub-circuit 104 under the control of the control signal.
  • the driving sub-circuit 104 is used to receive the data signal, the initialization signal and the power supply voltage signal, and perform voltage initialization based on the data signal and the initialization signal, and based on the data signal, generate and store the driving voltage that controls the conduction of the driving sub-circuit and the driving voltage Under the control of, the power supply voltage signal is transmitted to the light-emitting sub-circuit 105.
  • the light emitting sub-circuit 105 is used to emit light based on the power supply voltage signal.
  • the driving sub-circuit 104 is connected to the data writing sub-circuit 101, the initialization sub-circuit 102, the light-emission control sub-circuit 103, and the light-emission sub-circuit 105, respectively.
  • the driving sub-circuit 104 may include: a driving transistor T, a first capacitor C1 and a second capacitor C2.
  • the data writing sub-circuit 101 may include: a first transistor T1.
  • the initialization sub-circuit 102 may include: a second transistor T2.
  • the light emission control sub-circuit 103 may include a third transistor T3.
  • the light-emitting sub-circuit 105 may include a light-emitting element D1.
  • the gate (Gate, G) of the driving transistor T is respectively connected to the first electrode of the first transistor T1 and the first end of the first capacitor C1 for receiving The data signal V1 transmitted by the first electrode of the first transistor T1.
  • the first electrode of the driving transistor T is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, respectively, for receiving the initialization signal V2 transmitted by the second electrode of the second transistor T2, and receiving the third transistor The power voltage signal VDD transmitted by the second pole of T3.
  • the second electrode of the driving transistor T is connected to the anode of the light emitting element D1, the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2, respectively, for controlling the power supply voltage under the control of the voltage stored in the first capacitor C1
  • the signal VDD is transmitted to the anode of the light emitting element D1.
  • the gate of the first transistor T1 is used to receive the first scan signal S1.
  • the second electrode of the first transistor T1 is used to receive the data signal V1.
  • the first electrode of the first transistor T1 is used to transfer the data signal V1 to the gate of the driving transistor T under the control of the first scan signal S1.
  • the gate of the second transistor T2 is used to receive the second scan signal S2.
  • the first electrode of the second transistor T2 is connected to the second end of the second capacitor C2 and is used to receive the initialization signal V2.
  • the second electrode of the second transistor T2 is used to transmit the initialization signal V2 to the first electrode of the driving transistor T under the control of the second scan signal S2.
  • the gate of the third transistor T3 is used to receive the control signal EM.
  • the first electrode of the third transistor T3 is used to receive the power supply voltage signal VDD.
  • the second electrode of the third transistor T3 is used to transmit the power supply voltage signal VDD to the first electrode of the driving transistor T under the control of the control signal EM.
  • the cathode of the light-emitting element D1 is grounded. As shown in FIG. 2, the connection of the cathode of the light-emitting element D1 to VSS indicates that the cathode of the light-emitting element D1 is grounded.
  • the function of the first capacitor C1 is to store the voltage difference between the gate and the second electrode of the driving transistor T; in the light-emitting stage, the driving transistor T is controlled to be turned on, thereby causing the light-emitting element D1 to emit light.
  • the function of the second capacitor C2 is to balance the voltage difference stored in the first capacitor C1. By setting the second capacitor C2, the four stages of the driving process of the pixel circuit can be completed.
  • the light-emitting element D1 may be an organic light-emitting diode.
  • the first terminal of the second capacitor C2 may be connected to the second electrode of the driving transistor T, the second terminal of the first capacitor C1, and the anode of the light-emitting element D1, respectively;
  • the second terminal of the second capacitor C2 may be connected to the first electrode of the third transistor T3.
  • the second terminal of the second capacitor C2 is connected to the first electrode of the third transistor T3, and the first electrode of the third transistor T3 is used to receive the power supply voltage signal VDD. Therefore, the second The second terminal of the capacitor C2 also receives the power supply voltage signal VDD. Since the voltage of the power supply voltage signal VDD is very stable, the balance effect is better, and the uniformity of the display effect can be improved. For the convenience of the following description, the voltage of the power supply voltage signal VDD is simply referred to as the power supply voltage VDD below.
  • the driving process of the pixel circuit is described below by taking the above transistor as an N-type MOS transistor as an example.
  • the driving process of the pixel circuit includes four stages, namely an initialization stage, a sampling stage, a programming stage, and a light-emitting stage.
  • the voltage of the initialization signal V2 is represented by the initialization voltage V init ; the initialization stage and the sampling stage, the voltage of the data signal V1 is represented by the reference voltage V ref ; the programming stage, the voltage of the data signal V1 Expressed by the data voltage V data .
  • the initialization voltage V init is always low, and the initialization voltage V init is lower than the reference voltage V ref .
  • the power supply voltage VDD is higher than the data voltage V data
  • the data voltage V data is higher than the reference voltage V ref .
  • FIG. 4 shows a waveform timing diagram during the driving process of the pixel circuit provided by the embodiment of the present application.
  • the first scan signal S1 and the second scan signal S2 are both at a high level, and the control signal EM is at a low level.
  • the first transistor T1 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned on; under the control of the control signal EM, the third transistor T3 is turned off.
  • the reference voltage V ref is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1.
  • the initialization voltage V init is applied to the second end of the second capacitor C2 and is applied to the first pole of the driving transistor T through the second transistor T2.
  • the driving transistor T The voltage of the first pole is V init .
  • the coupling capacitor of the first capacitor C1, the light-emitting element D1 and the second capacitor C2 are connected in series.
  • the voltage divided by the first capacitor C1 is C 1 ⁇ (V ref -V init )/(C 1 +C 2 +C D1 )
  • C 1 is the capacitance value of the first capacitor C1
  • C 2 is the capacitance value of the second capacitor C2
  • CD D1 is the capacitance value of the coupling capacitor of the light emitting element D1 itself.
  • the power supply voltage VDD is applied to the second terminal of the second capacitor C2, and the initialization voltage V init is applied to the first pole of the driving transistor T through the second transistor T2.
  • the voltage of the first pole of the driving transistor T is V init ;
  • the initialization voltage V init is lower than the reference voltage V ref , the voltage of the first pole of the driving transistor T is less than the voltage of the second pole of the driving transistor T, and the source of the first pole of the driving transistor T is turned on at this time .
  • the initialization voltage V init is applied to the second electrode of the drive transistor T (ie, the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2) through the drive transistor T.
  • the first scan signal S1 and the control signal EM are at a high level, and the second scan signal S2 is at a low level.
  • the first transistor T1 is turned on; under the control of the control signal EM, the third transistor T3 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned off.
  • the reference voltage V ref is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1.
  • the voltage of the second pole of the driving transistor T can be calculated according to the principle of capacitance division of the series circuit, and the second pole of the driving transistor T can be obtained
  • the voltage is less than the voltage of the first electrode of the driving transistor T, the source of the second electrode of the driving transistor T, and the driving transistor T is turned on under the control of the reference voltage V ref and the voltage of the second electrode of the driving transistor T.
  • the driving transistor T is turned off, and the sampling ends.
  • the process of calculating the voltage of the second pole of the driving transistor T during the sampling stage is similar to the process of calculating the voltage of the second pole of the driving transistor T during the initialization stage, which will not be repeated here in the embodiments of the present application.
  • the first scan signal S1 is at a high level
  • the second scan signal S2 and the control signal EM are at a low level.
  • the first transistor T1 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned off; under the control of the control signal EM, the third transistor T3 is turned off.
  • the data voltage V data is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1. At this time, the voltage of the gate G of the driving transistor T is V data .
  • the voltage of the gate G of the driving transistor T is V data .
  • the voltage of the second electrode of the driving transistor T is (V ref -V th )+(V data -V ref ) ⁇ C 1 /(C 1 +C 2 +C D1 ).
  • the first scan signal S1 and the second scan signal S2 are low level, and the control signal EM is high level.
  • the third transistor T3 is turned on; under the control of the first scan signal S1, the first transistor T1 is turned off; under the control of the second scan signal S2, the second transistor T2 is turned off.
  • the voltage of the gate G of the driving transistor T is maintained at V data .
  • the second electrode voltage of the driving transistor T is maintained at (V ref- V th ) + (V data- V ref ) ⁇ C 1 /(C 1 +C 2 +C D1 ).
  • the voltage of the first electrode of the driving transistor T is the power supply voltage VDD
  • the voltage of the first electrode of the driving transistor T is higher than the voltage of the second electrode of the driving transistor T
  • the pole drain D, the second pole source S of the driving transistor T at this time, the first capacitor C1 stores the voltage difference between the gate G of the driving transistor T and the second pole V th +(V data -V ref ) ⁇ ( C 2 +C D1 )/(C 1 +C 2 +C D1 ) is the voltage difference V GS between the gate G and the source S of the driving transistor T.
  • the first capacitor C1 stores the voltage difference V th +(V data -V ref ) ⁇ (C 2 +C D1 )/(C 1 +C 2 +C D1 ) of the gate G and the second electrode of the driving transistor T If it is greater than V th , that is, the voltage difference V GS between the gate G and the source S of the driving transistor T is greater than V th , the driving transistor T is turned on. At this time, the third transistor T3, the driving transistor T, and the light-emitting element D1 are in a series path, and the light-emitting element D1 starts to emit light. The current flowing through the light-emitting element D1 is ID1 .
  • ⁇ is the carrier mobility of the drive transistor T
  • Cox is the capacitance of the drive transistor T
  • W is the channel width of the drive transistor T
  • L is the channel length of the drive transistor T
  • V GS is the drive transistor T The voltage difference between the gate G and the source S.
  • V GS V th +(V data -V ref ) ⁇ (C 2 +C D1 )/(C 1 +C 2 +C D1 ) to simplify formula (1) to obtain the current flowing through the light-emitting element D1 :
  • the current I D1 flowing through the light-emitting element D1 has nothing to do with the threshold voltage V th of the driving switch tube T, and has nothing to do with the IR voltage drop of the power supply voltage VDD. Therefore, the driving switch tube T can be eliminated
  • the influence of the threshold voltage V th on the current flowing through the light-emitting element can also eliminate the influence of the IR voltage drop of the power supply voltage VDD on the current flowing through the light-emitting element, and can ensure the uniformity of brightness and uniform display.
  • the deviation rate of the current flowing through the light-emitting element D1 is as high as 10% when the power supply voltage VDD deviates by 0.1V, and the current flows through the light-emitting element D1 when the threshold voltage Vth of the driving transistor T deviates by 0.15V The deviation rate is higher.
  • the pixel circuit provided by the embodiment of the present application when the power supply voltage VDD deviates by 0.1V, the deviation rate of the current flowing through the light-emitting element D1 does not exceed 1%, and when the threshold voltage V th of the driving transistor T deviates by 0.15V, The current deviation rate of the light-emitting element D1 is about 5%. The deviation rate of the current flowing through the light emitting element D1 is reduced, and the current flowing through the light emitting element D1 is compensated.
  • FIG. 5 shows a schematic flowchart of a driving method of a pixel circuit provided by an embodiment of the present application.
  • the driving method of the pixel circuit may include:
  • the data writing sub-circuit 101 receives the first scan signal S1 and the data signal V1, and transmits the data signal V1 to the driving sub-circuit 104 under the control of the first scan signal S1;
  • the initialization sub-circuit 102 receives the second Scan signal S2 and initialization signal V2, and transmit initialization signal V2 to drive sub-circuit 104 under the control of second scan signal S2;
  • drive sub-circuit 104 receives data signal V1 and initialization signal V2.
  • the data writing sub-circuit 101 receives the first scanning signal S1 and the data signal V1, and transmits the data signal V1 to the driving sub-circuit 104 under the control of the first scanning signal S1;
  • the light-emission control sub-circuit 103 receives the control Under the control of the control signal EM, the signal EM and the power supply voltage signal VDD transmit the power supply voltage signal VDD to the driving sub-circuit 104;
  • the driving sub-circuit 104 receives the data signal V1 and the power supply voltage signal VDD.
  • the data writing sub-circuit 101 receives the first scanning signal S1 and the data signal V1, and transmits the data signal V1 to the driving sub-circuit 104 under the control of the first scanning signal S1, and the driving sub-circuit 104 receives the data signal V1, and stores the driving voltage for controlling the conduction of the driving sub-circuit.
  • the first voltage is the voltage at the common terminal of the driving sub-circuit 104 and the data writing sub-circuit 101
  • the second voltage is the voltage at the common terminal of the driving sub-circuit 104 and the light-emitting sub-circuit 105
  • the driving voltage is the voltage of the first voltage and the second voltage Poor
  • the voltage of the data signal V1 received by the data writing sub-circuit 101 during the programming phase is higher than the voltage of the data signal V1 received by the data writing sub-circuit 101 during the initialization phase and the sampling phase.
  • the lighting control sub-circuit 103 receives the control signal EM and the power supply voltage signal VDD, and transmits the power supply voltage signal VDD to the driving sub-circuit 104 under the control of the control signal VDD; the driving sub-circuit 104 is under the control of the driving voltage
  • the power supply voltage signal VDD is transmitted to the light emitting subcircuit; the light emitting subcircuit 105 emits light based on the power supply voltage signal VDD.
  • the driving sub-circuit 104 includes: a driving transistor T, a first capacitor C1 and a second capacitor C2;
  • the data writing sub-circuit 101 includes: a first transistor T1; and the initialization sub-circuit 102 includes: a second The transistor T2;
  • the light emission control sub-circuit 103 includes: a third transistor T3;
  • the light emission sub-circuit 105 includes: a light-emitting element D1.
  • the gate of the driving transistor T is respectively connected to the first electrode of the first transistor T1 and the first terminal of the first capacitor C1, and is used to receive the data signal V1 transmitted by the first electrode of the first transistor T1.
  • the first electrode of the driving transistor T is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, respectively, for receiving the initialization signal V2 transmitted by the second electrode of the second transistor T2 and receiving the third transistor T3
  • the second pole transmits the power supply voltage signal VDD.
  • the second electrode of the driving transistor T is connected to the anode of the light emitting element D1, the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2, respectively, for controlling the power supply voltage under the control of the voltage stored in the first capacitor C1
  • the signal VDD is transmitted to the anode of the light emitting element D1.
  • the gate of the first transistor T1 is used to receive the first scan signal S1.
  • the second electrode of the first transistor T1 is used to receive the data signal V1.
  • the first electrode of the first transistor T1 is used to transfer the data signal V1 to the gate of the driving transistor T under the control of the first scan signal S1.
  • the gate of the second transistor T2 is used to receive the second scan signal S2.
  • the first electrode of the second transistor T2 is connected to the second terminal of the second capacitor C2 for receiving the initialization signal V2, or the second terminal of the second capacitor C2 is connected to the first terminal of the third transistor T3.
  • the second electrode of the second transistor T2 is used to transmit the initialization signal V2 to the first electrode of the driving transistor T under the control of the second scan signal S2.
  • the gate of the third transistor T3 is used to receive the control signal EM.
  • the first electrode of the third transistor T3 is used to receive the power supply voltage signal VDD.
  • the second electrode of the third transistor T3 is used to transmit the power supply voltage signal VDD to the first electrode of the driving transistor T under the control of the control signal EM.
  • the cathode of the light-emitting element D1 is grounded.
  • the first capacitor C1 is used to store a driving voltage which is a voltage difference between the gate and the second electrode of the driving transistor T.
  • the gate of the first transistor T1 receives the first scan signal S1, the second electrode of the first transistor T1 receives the data signal V1, and the first electrode of the first transistor T1 transfers the data under the control of the first scan signal S1
  • the signal V1 is transmitted to the gate of the driving transistor T; the gate of the driving transistor T receives the data signal V1; the gate of the second transistor T2 receives the second scan signal S2, the first electrode of the second transistor T2 receives the initialization signal V2, the first The second electrode of the two transistors T2 transmits the initialization signal V2 to the first electrode of the driving transistor under the control of the second scan signal S2; the first electrode of the driving transistor receives the initialization signal V2.
  • the first scan signal S1 and the second scan signal S2 are both at a high level, and the control signal EM is at a low level. Under the control of the first scan signal S1, the first transistor T1 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned on; under the control of the control signal EM, the third transistor T3 is turned off.
  • the reference voltage V ref is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1.
  • the initialization voltage V init is applied to the second terminal of the second capacitor C2 and applied to the first pole of the driving transistor T through the second transistor T2.
  • the power supply voltage VDD is applied to the second terminal of the second capacitor C2, and the initialization voltage V init is applied to the first pole of the driving transistor T through the second transistor T2.
  • the gate of the first transistor T1 receives the first scan signal S1, the second electrode of the first transistor T1 receives the data signal V1, and the first electrode of the first transistor T1 transfers the data under the control of the first scan signal S1
  • the signal V1 is transmitted to the gate of the driving transistor T; the gate of the driving transistor T receives the data signal V1; the gate of the third transistor T3 receives the control signal EM, the first pole of the third transistor T3 receives the power supply voltage signal VDD, the third The second electrode of the transistor T3 transmits the power supply voltage signal VDD to the first electrode of the driving transistor T under the control of the control signal EM, and the first electrode of the driving transistor T receives the power supply voltage signal VDD; the driving transistor T is based on the data signal V1 and the power supply
  • the voltage signal VDD is turned on, and when the voltage of the second electrode of the driving transistor T rises to the voltage difference between the voltage of the data signal V1 and the threshold voltage of the driving transistor T, the driving transistor T is turned off.
  • the first scan signal S1 and the control signal EM are at a high level, and the second scan signal S2 is at a low level. Under the control of the first scan signal S1, the first transistor T1 is turned on; under the control of the control signal EM, the third transistor T3 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned off.
  • the reference voltage V ref is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1.
  • the driving transistor T is first turned on under the control of the reference voltage V ref and the second electrode voltage of the driving transistor T, when the second electrode voltage of the driving transistor rises to the voltage difference V ref between the reference voltage V ref and the threshold voltage V th of the driving transistor -V th , the drive transistor is turned off.
  • the voltage at the first terminal of the first capacitor C1 (that is, the voltage of the gate G of the driving transistor T) is: V ref
  • the voltage at the second terminal of the first capacitor C1 (that is, the voltage of the second electrode of the driving transistor T) is : V ref -V th
  • the gate of the first transistor T1 receives the first scan signal S1
  • the second electrode of the first transistor T2 receives the data signal V1
  • the first electrode of the first transistor T1 is at the Under the control of a scan signal S1
  • the data signal V1 is transmitted to the gate of the driving transistor T
  • the gate of the driving transistor T receives the data signal V1
  • the first capacitor C1 stores the gate of the driving transistor T and the second pole of the driving transistor T Voltage difference.
  • the first scan signal S1 is at a high level
  • the second scan signal S2 and the control signal EM are at a low level.
  • the first transistor T1 is turned on; under the control of the second scan signal S2, the second transistor T2 is turned off; under the control of the control signal EM, the third transistor T3 is turned off.
  • the data voltage V data is applied to the gate G of the driving transistor T and the first end of the first capacitor C1 through the first transistor T1. At this time, the voltage of the gate G of the driving transistor T is V data .
  • the voltage of the gate G of the driving transistor T is V data .
  • the voltage of the second electrode of the driving transistor T is (V ref -V th )+(V data -V ref ) ⁇ C 1 /(C 1 +C 2 +C D1 ).
  • the first capacitor C1 stores the voltage difference V th +(V data -V ref ) ⁇ (C 2 +C D1 )/(C 1 +C 2 +C D1 ) of the gate G and the second electrode of the drive transistor T.
  • the gate of the third transistor T3 receives the control signal EM; the first electrode of the third transistor T3 receives the power supply voltage signal; the second electrode of the third transistor T3 transmits the power supply voltage signal VDD under the control of the control signal EM To the first pole of the driving transistor T; the first pole of the driving transistor T receives the power supply voltage signal, and under the control of the voltage difference stored in the first capacitor C1, the second pole of the driving transistor T transmits the power supply voltage signal to the light emitting element D1 Anode; the light-emitting element D1 emits light based on the power supply voltage signal.
  • the first scan signal S1 and the second scan signal S2 are at a low level, and the control signal EM is at a high level.
  • the third transistor T3 is turned on; under the control of the first scan signal S1, the first transistor T1 is turned off; under the control of the second scan signal S2, the second transistor T2 is turned off.
  • the voltage of the gate G of the driving transistor T is maintained at V data .
  • the voltage of the second electrode of the driving transistor T remains (V ref -V th )+(V data -V ref ) ⁇ C 1 /(C 1 +C 2 +C D1 ), at this time the source of the second electrode of the driving transistor T .
  • the driving transistor T is turned on.
  • the third transistor T3, the driving transistor T, and the light-emitting element D1 are in a series path, and the light-emitting element D1 starts to emit light.
  • the current flowing through the light-emitting element D1 is:
  • the current flowing through the light emitting element has nothing to do with the threshold voltage V th of the driving switch tube T, and has nothing to do with the IR voltage drop of the power supply voltage VDD. Therefore, the influence of the threshold voltage V th of the driving switch tube T on the current flowing through the light emitting element can be eliminated It can also eliminate the influence of the IR voltage drop of the power supply voltage VDD on the current flowing through the light-emitting element, and can ensure the uniformity of brightness and uniform display.
  • An embodiment of the present application further provides a display device including the pixel circuit provided by the embodiment of the present application.

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Abstract

本申请实施例公开了一种像素电路及其驱动方法、显示装置。该像素电路包括：数据写入子电路、初始化子电路、发光控制子电路、驱动子电路和发光子电路；数据写入子电路将数据信号传输至驱动子电路；初始化子电路将初始化信号传输至驱动子电路；发光控制子电路将电源电压信号传输至驱动子电路；驱动子电路进行电压初始化，存储驱动电压以及将电源电压信号传输至发光子电路；发光子电路基于电源电压信号发光。本申请实施例的像素电路及其驱动方法、显示装置，能够保证亮度的均一性和均匀显示。

Description

像素电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求享有于2019年01月08日提交的名称为“像素电路及其驱动方法、显示装置”的中国专利申请201910017114.X的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
主动矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)能够满足显示器高分辨率和大尺寸的要求，应用越来越广泛。
AMOLED能够发光是由薄膜晶体管(Thin Film Transistor，TFT)在饱和状态时产生驱动电流并驱动发光元件—有机发光二极管(Organic Light Emitting Diode，OLED)发光来实现的，OLED发光亮度和提供给OLED器件的驱动电流的大小成正比，故为了实现最佳的显示效果，需要较大的驱动电流。而低温多晶硅由于可以提供较高的电子迁移率，故AMOLED显示技术中较多的选择低温多晶硅制作TFT。
在最基本的2T1C像素电路中，OLED驱动电流的大小和驱动TFT阈值电压Vth有关，而低温多晶硅工艺不成熟，即便是同样的工艺参数，制作出的驱动TFT的Vth也有较大的差异，使得阵列基板不同位置处驱动TFT的Vth不同，进而会导致OLED的驱动电流大小不一样，阵列基板不同位置处的亮度也就产生差异，显示不均匀。
发明内容
本申请实施例提供一种像素电路及其驱动方法、显示装置，能够保证亮度的均一性和均匀显示。
一方面，本申请实施例提供了一种像素电路，像素电路包括：数据写入子电路、初始化子电路、发光控制子电路、驱动子电路和发光子电路；
数据写入子电路用于接收第一扫描信号和数据信号，并在第一扫描信号的控制下，将数据信号传输至驱动子电路；
初始化子电路用于接收第二扫描信号和初始化信号，并在第二扫描信号的控制下，将初始化信号传输至驱动子电路；
发光控制子电路用于接收控制信号和电源电压信号，并在控制信号的控制下，将电源电压信号传输至驱动子电路；
驱动子电路用于接收数据信号、初始化信号和电源电压信号，并基于数据信号和初始化信号进行电压初始化，以及基于数据信号，生成并存储控制驱动子电路导通的驱动电压，以及在驱动电压的控制下，将电源电压信号传输至发光子电路；
发光子电路用于基于电源电压信号发光。
另一方面，本申请实施例提供了一种像素电路的驱动方法，驱动方法用于驱动本申请实施例提供的像素电路；方法包括：
在初始化阶段，数据写入子电路接收第一扫描信号和数据信号，在第一扫描信号的控制下将数据信号传输至驱动子电路；初始化子电路接收第二扫描信号和初始化信号，并在第二扫描信号的控制下将初始化信号传输至驱动子电路；驱动子电路接收数据信号和初始化信号；
在采样阶段，数据写入子电路接收第一扫描信号和数据信号，在第一扫描信号的控制下将数据信号传输至驱动子电路；发光控制子电路接收控制信号和电源电压信号，在控制信号的控制下将电源电压信号传输至驱动子电路；驱动子电路接收数据信号和电源电压信号；
在编程阶段，数据写入子电路接收第一扫描信号和数据信号，在第一扫描信号的控制下将数据信号传输至驱动子电路，驱动子电路接收数据信号，并存储用于控制驱动子电路导通的驱动电压；第一电压为驱动子电路与数据写入子电路的公共端的电压，第二电压为驱动子电路与发光子电路 的公共端的电压，驱动电压为第一电压和第二电压的电压差；编程阶段数据写入子电路接收到的数据信号的电压高于初始化阶段和采样阶段数据写入子电路接收到的数据信号的电压；
在发光阶段，发光控制子电路接收控制信号和电源电压信号，在控制信号的控制下将电源电压信号传输至驱动子电路；驱动子电路在驱动电压的控制下将电源电压信号传输至发光子电路；发光子电路基于电源电压信号发光。
再一方面，本申请实施例提供一种显示装置，包括本申请实施例提供的像素电路。
本申请实施例的像素电路及其驱动方法、显示装置，能够消除驱动开关管的阈值电压Vth对流经发光元件的驱动电流的影响，也能够消除电源电压的电阻电位IR压降对流经发光元件的驱动电流的影响，能够保证亮度的均一性和均匀显示。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请实施例提供的像素电路的结构示意图；
图2示出了本申请实施例提供的像素电路的一种具体结构示意图；
图3示出了本申请实施例提供的像素电路的另一种具体结构示意图；
图4示出了本申请实施例提供的像素电路驱动过程中的波形时序图；
图5示出了本申请实施例提供的像素电路的流程示意图。
具体实施方式
下面结合附图和实施例对本申请的实施方式作进一步详细描述。以下实施例的详细描述和附图用于示例性地说明本申请的原理，但不能用来限制本申请的范围，即本申请不限于所描述的实施例。
本申请实施例提供一种像素电路，如图1所示。其中，图1示出了本 申请实施例提供的像素电路的结构。如图1所示，像素电路包括：数据写入子电路101、初始化子电路102、发光控制子电路103、驱动子电路104和发光子电路105。
数据写入子电路101用于接收第一扫描信号和数据信号，并在第一扫描信号的控制下，将数据信号传输至驱动子电路104。
初始化子电路102用于接收第二扫描信号和初始化信号，并在第二扫描信号的控制下，将初始化信号传输至驱动子电路104。
发光控制子电路103用于接收控制信号和电源电压信号，并在控制信号的控制下，将电源电压信号传输至驱动子电路104。
驱动子电路104用于接收数据信号、初始化信号和电源电压信号，并基于数据信号和初始化信号进行电压初始化，以及基于数据信号，生成并存储控制驱动子电路导通的驱动电压，以及在驱动电压的控制下，将电源电压信号传输至发光子电路105。
发光子电路105用于基于电源电压信号发光。
在本申请的一个实施例中，驱动子电路104分别与数据写入子电路101、初始化子电路102、发光控制子电路103和发光子电路105连接。
在本申请的一些实施例中，如图2和图3所示，驱动子电路104可以包括：驱动晶体管T、第一电容C1和第二电容C2。数据写入子电路101可以包括：第一晶体管T1。初始化子电路102可以包括：第二晶体管T2。发光控制子电路103可以包括第三晶体管T3。发光子电路105可以包括发光元件D1。
在本申请的一个实施例中，如图2所示，驱动晶体管T的栅极(Gate，G)分别与第一晶体管T1的第一极和第一电容C1的第一端连接，用于接收第一晶体管T1的第一极传输的数据信号V1。
驱动晶体管T的第一极分别与第二晶体管T2的第二极和第三晶体管T3的第二极连接，用于接收第二晶体管T2的第二极传输的初始化信号V2，以及接收第三晶体管T3的第二极传输的电源电压信号VDD。
驱动晶体管T的第二极分别与发光元件D1的阳极、第一电容C1的第二端和第二电容C2的第一端连接，用于在第一电容C1存储的电压的控制 下将电源电压信号VDD传输至发光元件D1的阳极。
第一晶体管T1的栅极用于接收第一扫描信号S1。
第一晶体管T1的第二极用于接收数据信号V1。
第一晶体管T1的第一极用于在第一扫描信号S1的控制下将数据信号V1传输至驱动晶体管T的栅极。
第二晶体管T2的栅极用于接收第二扫描信号S2。
第二晶体管T2的第一极与第二电容C2的第二端连接，用于接收初始化信号V2。
第二晶体管T2的第二极用于在第二扫描信号S2的控制下，将初始化信号V2传输至驱动晶体管T的第一极。
第三晶体管T3的栅极用于接收控制信号EM。
第三晶体管T3的第一极用于接收电源电压信号VDD。
第三晶体管T3的第二极用于在控制信号EM的控制下，将电源电压信号VDD传输至驱动晶体管T的第一极。
发光元件D1的阴极接地。如图2所示，发光元件D1的阴极与VSS连接表示发光元件D1的阴极接地。
第一电容C1的作用为：存储驱动晶体管T栅极和第二极的电压差；在发光阶段，控制驱动晶体管T导通，进而使发光元件D1发光。
第二电容C2的作用为：对第一电容C1存储的电压差进行平衡。通过设置第二电容C2，能够完成像素电路的驱动过程的四个阶段。
在本申请的一个实施例中，发光元件D1可以为有机发光二极管。
在本申请的一个实施例中，如图3所示，第二电容C2的第一端可以分别与驱动晶体管T的第二极、第一电容C1的第二端和发光元件D1的阳极连接；第二电容C2的第二端可以与第三晶体管T3的第一极连接。
在图3所示的实施例中，第二电容C2的第二端与第三晶体管T3的第一极连接，而第三晶体管T3的第一极用于接收电源电压信号VDD，因此，第二电容C2的第二端也接收电源电压信号VDD。由于电源电压信号VDD的电压非常稳定，因此，平衡效果更好，更能提高显示效果的均一性。为了以下说明方便，以下将电源电压信号VDD的电压简称为电源电压VDD。
下面以上述晶体管为N型MOS晶体管为例对像素电路的驱动过程进行说明。像素电路的驱动过程包括四个阶段，分别为初始化阶段、采样阶段、编程阶段和发光阶段。
在本申请的一个实施例中，将初始化信号V2的电压以初始化电压V init表示；将初始化阶段和采样阶段，数据信号V1的电压以参考电压V ref表示；将编程阶段，数据信号V1的电压以数据电压V data表示。
在本申请的一个实施例中，初始化电压V init始终为低电平，且初始化电压V init比参考电压V ref更低。电源电压VDD高于数据电压V data，数据电压V data高于参考电压V ref。
图4示出了本申请实施例提供的像素电路驱动过程中的波形时序图。
在初始化阶段，第一扫描信号S1、第二扫描信号S2均处于高电平，控制信号EM为低电平。在第一扫描信号S1的控制下，第一晶体管T1导通；在第二扫描信号S2的控制下，第二晶体管T2导通；在控制信号EM的控制下，第三晶体管T3关断。参考电压V ref通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。此时对于驱动晶体管T而言，对应于图2，初始化电压V init施加在第二电容C2的第二端，并通过第二晶体管T2施加在驱动晶体管T的第一极，此时驱动晶体管T的第一极的电压为V init。第一电容C1、发光元件D1自身的耦合电容和第二电容C2串联，根据串联电路电容分压原理，第一电容C1分得的电压为C 1×(V ref-V init)/(C 1+C 2+C D1)，C 1为第一电容C1的电容值，C 2为第二电容C2的电容值，C D1为发光元件D1自身的耦合电容的电容值。驱动晶体管T的第二极的电压为V ref-C 1×(V ref-V init)/(C 1+C 2+C D1)＝(C 2+C D1)×V ref/(C 1+C 2+C D1)+C 1×V init/(C 1+C 2+C D1)。由于初始化电压V init比参考电压V ref更低，因此，驱动晶体管T的第一极的电压小于驱动晶体管T的第二极的电压，驱动晶体管T的第一极为源极，此时驱动晶体管T导通。初始化电压V init通过驱动晶体管T施加在驱动晶体管T的第二极(即第一电容C1的第二端、第二电容C2的第一端)。
对应于图3，电源电压VDD施加在第二电容C2的第二端，初始化电压V init通过第二晶体管T2施加在驱动晶体管T的第一极，此时驱动晶体管 T的第一极的电压为V init；第一电容C1、发光元件D1自身的耦合电容和第二电容C2串联，根据串联电路电容分压原理，第一电容C1分得的电压为C 1×(VDD-V ref)/(C 1+C 2+C D1)，则驱动晶体管T的第二极的电压为V ref+C 1×(VDD-V ref)/(C 1+C 2+C D1)＝(C 2+C D1)×V ref/(C 1+C 2+C D1)+C 1×VDD/(C 1+C 2+C D1)。由于初始化电压V init比参考电压V ref更低，驱动晶体管T的第一极的电压小于驱动晶体管T的第二极的电压，驱动晶体管T的第一极为源极，此时驱动晶体管T导通。初始化电压V init通过驱动晶体管T施加在驱动晶体管T的第二极(即第一电容C1的第二端、第二电容C2的第一端)。
在采样阶段，第一扫描信号S1和控制信号EM为高电平，第二扫描信号S2为低电平。在第一扫描信号S1的控制下，第一晶体管T1导通；在控制信号EM的控制下，第三晶体管T3导通；在第二扫描信号S2的控制下，第二晶体管T2关断。参考电压V ref通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。
此时对于驱动晶体管T而言，对应于图2和图3，根据串联电路电容分压原理，可以计算出驱动晶体管T的第二极的电压，并可得出驱动晶体管T的第二极的电压小于驱动晶体管T的第一极的电压，驱动晶体管T的第二极为源极，驱动晶体管T在参考电压V ref和驱动晶体管T的第二极电压的控制下导通。当驱动晶体管T的第二极电压上升至V ref-V th时，驱动晶体管T关断，采样结束。此时第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V ref-(V ref-V th)＝V th。在驱动晶体管T的第二极电压上升至V ref-V th之前，发光元件D1会流经微弱的电流，但该电流不足以使发光元件D1发光。
采样阶段计算驱动晶体管T的第二极的电压的过程与初始化阶段计算驱动晶体管T的第二极的电压的过程相似，本申请实施例在此不对其进行赘述，具体可参考上述初始化阶段计算驱动晶体管T的第二极的电压的过程。
在编程阶段，对应于图2和图3，第一扫描信号S1为高电平，第二扫描信号S2、控制信号EM为低电平。在第一扫描信号S1的控制下，第一 晶体管T1导通；在第二扫描信号S2的控制下，第二晶体管T2关断；在控制信号EM的控制下，第三晶体管T3关断。数据电压V data通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。此时驱动晶体管T的栅极G的电压为V data。驱动晶体管T的栅极G的电压由V ref跳变为V data，驱动晶体管T的栅极G的电压跳变量△u＝V data-V ref；相应的，驱动晶体管T的第二极的电压也会发生跳变。由于第一电容C1、发光元件D1自身的耦合电容和第二电容C2串联，根据串联电路电容分压原理，驱动晶体管T的第二极的电压的跳变量△u′＝△u×C 1/(C 1+C 2+C D1)＝(V data-V ref)×C 1/(C 1+C 2+C D1)。编程阶段完成后，驱动晶体管T的栅极G电压为V data。驱动晶体管T的第二极的电压为(V ref-V th)+(V data-V ref)×C 1/(C 1+C 2+C D1)。第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V data-(V ref-V th)-(V data-V ref)×C 1/(C 1+C 2+C D1)＝V th+(V data-V ref)×(C 2+C D1)/(C 1+C 2+C D1)。
在发光阶段，第一扫描信号S1和第二扫描信号S2为低电平，控制信号EM为高电平。在控制信号EM的控制下，第三晶体管T3导通；在第一扫描信号S1的控制下，第一晶体管T1关断；在第二扫描信号S2的控制下，第二晶体管T2关断。驱动晶体管T的栅极G电压保持V data。驱动晶体管T的第二极电压保持(V ref-V th)+(V data-V ref)×C 1/(C 1+C 2+C D1)。此时对于驱动晶体管T而言，驱动晶体管T的第一极的电压为电源电压VDD，驱动晶体管T的第一极的电压高于驱动晶体管T的第二极的电压，驱动晶体管T的第一极为漏极D，驱动晶体管T的第二极为源极S，此时，第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V th+(V data-V ref)×(C 2+C D1)/(C 1+C 2+C D1)即为驱动晶体管T的栅极G和源极S的电压差V GS。由于，第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V th+(V data-V ref)×(C 2+C D1)/(C 1+C 2+C D1)大于V th，即驱动晶体管T的栅极G和源极S的电压差V GS大于V th，驱动晶体管T导通。此时，第三晶体管T3、驱动晶体管T和发光元件D1在一个串联的通路中，发光元件D1开始发光。流经该发光元件D1的电流为I D1。
Figure PCTCN2019098148-appb-000001
其中，μ为驱动晶体管T的载流子迁移率，C ox为驱动晶体管T的电容，W为驱动晶体管T的沟道宽度，L为驱动晶体管T的沟道长度，V GS为驱动晶体管T的栅极G和源极S的电压差。
利用V GS＝V th+(V data-V ref)×(C 2+C D1)/(C 1+C 2+C D1)对公式(1)化简，得到流经该发光元件D1的电流：
Figure PCTCN2019098148-appb-000002
由公式(2)可以看出，流经该发光元件D1的电流I D1与驱动开关管T的阈值电压V th无关，也与电源电压VDD的IR压降无关，因此，能够消除驱动开关管T的阈值电压V th对流经发光元件的电流的影响，也能够消除电源电压VDD的IR压降对流经发光元件的电流的影响，能够保证亮度的均一性和均匀显示。
采用现有的2T1C像素电路，在电源电压VDD偏差0.1V时，流经发光元件D1电流的偏差率高达10％，在驱动晶体管T的阈值电压V th偏差0.15V时，流经发光元件D1电流的偏差率更高。而采用本申请实施例提供的像素电路，在电源电压VDD偏差0.1V时，流经发光元件D1电流的偏差率不超过1％，在驱动晶体管T的阈值电压V th偏差0.15V时，流经发光元件D1电流的偏差率约为5％。流经发光元件D1电流的偏差率降低，实现了对流经发光元件D1电流补偿。
本申请实施例提供一种像素电路的驱动方法，该驱动方法用于驱动本申请实施例提供的像素电路。图5示出了本申请实施例提供的像素电路的驱动方法的流程示意图。像素电路的驱动方法可以包括：
S501：在初始化阶段，数据写入子电路101接收第一扫描信号S1和数据信号V1，在第一扫描信号S1的控制下将数据信号V1传输至驱动子电路104；初始化子电路102接收第二扫描信号S2和初始化信号V2，并在第二扫描信号S2的控制下将初始化信号V2传输至驱动子电路104；驱动子电路104接收数据信号V1和初始化信号V2。
S502：在采样阶段，数据写入子电路101接收第一扫描信号S1和数据信号V1，在第一扫描信号S1的控制下将数据信号V1传输至驱动子电路104；发光控制子电路103接收控制信号EM和电源电压信号VDD，在控 制信号EM的控制下，将电源电压信号VDD传输至驱动子电路104；驱动子电路104接收数据信号V1和电源电压信号VDD。
S503：在编程阶段，数据写入子电路101接收第一扫描信号S1和数据信号V1，在第一扫描信号S1的控制下将数据信号V1传输至驱动子电路104，驱动子电路104接收数据信号V1，并存储用于控制驱动子电路导通的驱动电压。
第一电压为驱动子电路104与数据写入子电路101的公共端的电压，第二电压为驱动子电路104与发光子电路105的公共端的电压，驱动电压为第一电压和第二电压的电压差；编程阶段数据写入子电路101接收到的数据信号V1的电压高于初始化阶段和采样阶段数据写入子电路101接收到的数据信号V1的电压。
S504：在发光阶段，发光控制子电路103接收控制信号EM和电源电压信号VDD，在控制信号VDD的控制下将电源电压信号VDD传输至驱动子电路104；驱动子电路104在驱动电压的控制下将电源电压信号VDD传输至发光子电路；发光子电路105基于电源电压信号VDD发光。
在本申请的一个实施例中，驱动子电路104包括：驱动晶体管T、第一电容C1和第二电容C2；数据写入子电路101包括：第一晶体管T1；初始化子电路102包括：第二晶体管T2；发光控制子电路103包括：第三晶体管T3；发光子电路105包括：发光元件D1。
驱动晶体管T的栅极分别与第一晶体管T1的第一极和第一电容C1的第一端连接，用于接收第一晶体管T1的第一极传输的数据信号V1。驱动晶体管T的第一极分别与第二晶体管T2的第二极和第三晶体管T3的第二极连接，用于接收第二晶体管T2的第二极传输的初始化信号V2以及接收第三晶体管T3的第二极传输的电源电压信号VDD。驱动晶体管T的第二极分别与发光元件D1的阳极、第一电容C1的第二端和第二电容C2的第一端连接，用于在第一电容C1存储的电压的控制下将电源电压信号VDD传输至发光元件D1的阳极。第一晶体管T1的栅极用于接收第一扫描信号S1。第一晶体管T1的第二极用于接收数据信号V1。第一晶体管T1的第一极用于在第一扫描信号S1的控制下将数据信号V1传输至驱动晶体管T的 栅极。第二晶体管T2的栅极用于接收第二扫描信号S2。第二晶体管T2的第一极与第二电容C2的第二端连接，用于接收初始化信号V2，或第二电容C2的第二端与第三晶体管T3的第一极连接。第二晶体管T2的第二极用于在第二扫描信号S2的控制下，将初始化信号V2传输至驱动晶体管T的第一极。第三晶体管T3的栅极用于接收控制信号EM。第三晶体管T3的第一极用于接收电源电压信号VDD。第三晶体管T3的第二极用于在控制信号EM的控制下，将电源电压信号VDD传输至驱动晶体管T的第一极。发光元件D1的阴极接地。第一电容C1用于存储驱动电压，该驱动电压为驱动晶体管T的栅极和第二极的电压差。
在初始化阶段，第一晶体管T1的栅极接收第一扫描信号S1，第一晶体管T1的第二极接收数据信号V1，第一晶体管T1的第一极在第一扫描信号S1的控制下将数据信号V1传输至驱动晶体管T的栅极；驱动晶体管T的栅极接收数据信号V1；第二晶体管T2的栅极接收第二扫描信号S2，第二晶体管T2的第一极接收初始化信号V2，第二晶体管T2的第二极在第二扫描信号S2的控制下将初始化信号V2传输至驱动晶体管的第一极；驱动晶体管的第一极接收初始化信号V2。
第一扫描信号S1、第二扫描信号S2均处于高电平，控制信号EM为低电平。在第一扫描信号S1的控制下，第一晶体管T1导通；在第二扫描信号S2的控制下，第二晶体管T2导通；在控制信号EM的控制下，第三晶体管T3关断。参考电压V ref通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。
对应于图2，初始化电压V init施加在第二电容C2的第二端，并通过第二晶体管T2施加在驱动晶体管T的第一极。
对应于图3，电源电压VDD施加在第二电容C2的第二端，初始化电压V init通过第二晶体管T2施加在驱动晶体管T的第一极。
在采样阶段，第一晶体管T1的栅极接收第一扫描信号S1，第一晶体管T1的第二极接收数据信号V1，第一晶体管T1的第一极在第一扫描信号S1的控制下将数据信号V1传输至驱动晶体管T的栅极；驱动晶体管T的栅极接收数据信号V1；第三晶体管T3的栅极接收控制信号EM，第三晶 体管T3的第一极接收电源电压信号VDD，第三晶体管T3的第二极在控制信号EM的控制下将电源电压信号VDD传输至驱动晶体管T的第一极，驱动晶体管T的第一极接收电源电压信号VDD；驱动晶体管T基于数据信号V1和电源电压信号VDD导通，当驱动晶体管T的第二极电压上升至数据信号V1的电压与驱动晶体管T的阈值电压的电压差时，驱动晶体管T关断。
第一扫描信号S1和控制信号EM为高电平，第二扫描信号S2为低电平。在第一扫描信号S1的控制下，第一晶体管T1导通；在控制信号EM的控制下，第三晶体管T3导通；在第二扫描信号S2的控制下，第二晶体管T2关断。参考电压V ref通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。驱动晶体管T在参考电压V ref和驱动晶体管T的第二极电压的控制下先导通，当驱动晶体管的第二极电压上升至参考电压V ref与驱动晶体管的阈值电压V th的电压差V ref-V th时，驱动晶体管关断。此时，第一电容C1的第一端的电压(即驱动晶体管T的栅极G电压)为：V ref，第一电容C1的第二端的电压(即驱动晶体管T的第二极电压)为：V ref-V th。第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V ref-(V ref-V th)＝V th。
在本申请的一个实施例中，在编程阶段，第一晶体管T1的栅极接收第一扫描信号S1，第一晶体管T2的第二极接收数据信号V1，第一晶体管T1的第一极在第一扫描信号S1的控制下将数据信号V1传输至驱动晶体管T的栅极；驱动晶体管T的栅极接收数据信号V1；第一电容C1存储驱动晶体管T的栅极和驱动晶体管T的第二极的电压差。
第一扫描信号S1为高电平，第二扫描信号S2、控制信号EM为低电平。在第一扫描信号S1的控制下，第一晶体管T1导通；在第二扫描信号S2的控制下，第二晶体管T2关断；在控制信号EM的控制下，第三晶体管T3关断。数据电压V data通过第一晶体管T1施加在驱动晶体管T的栅极G及第一电容C1的第一端。此时驱动晶体管T的栅极G的电压为V data。驱动晶体管T的栅极G的电压由V ref跳变为V data，驱动晶体管T的栅极G的电压跳变量△u＝V data-V ref；相应的，驱动晶体管T的第二极的电压也会 发生跳变。驱动晶体管T的第二极的电压的跳变量△u′＝△u×C 1/(C 1+C 2+C D1)＝(V data-V ref)×C 1/(C 1+C 2+C D1)。
编程阶段完成后，驱动晶体管T的栅极G电压为V data。驱动晶体管T的第二极电压为(V ref-V th)+(V data-V ref)×C 1/(C 1+C 2+C D1)。第一电容C1存储驱动晶体管T的栅极G和第二极的电压差V th+(V data-V ref)×(C 2+C D1)/(C 1+C 2+C D1)。
在发光阶段，第三晶体管T3的栅极接收控制信号EM；第三晶体管T3的第一极接收电源电压信号；第三晶体管T3的第二极在控制信号EM的控制下将电源电压信号VDD传输至驱动晶体管T的第一极；驱动晶体管T的第一极接收电源电压信号，在第一电容C1存储的电压差的控制下，驱动晶体管T的第二极将电源电压信号传输至发光元件D1的阳极；发光元件D1基于电源电压信号发光。
第一扫描信号S1和第二扫描信号S2为低电平，控制信号EM为高电平。在控制信号EM的控制下，第三晶体管T3导通；在第一扫描信号S1的控制下，第一晶体管T1关断；在第二扫描信号S2的控制下，第二晶体管T2关断。驱动晶体管T的栅极G电压保持V data。驱动晶体管T的第二极电压保持(V ref-V th)+(V data-V ref)×C 1/(C 1+C 2+C D1)，此时驱动晶体管T的第二极为源极。驱动晶体管T导通。此时，第三晶体管T3、驱动晶体管T和发光元件D1在一个串联的通路中，发光元件D1开始发光。流经该发光元件D1的电流为：
Figure PCTCN2019098148-appb-000003
流经发光元件的电流与驱动开关管T的阈值电压V th无关，也与电源电压VDD的IR压降无关，因此，能够消除驱动开关管T的阈值电压V th对流经发光元件的电流的影响，也能够消除电源电压VDD的IR压降对流经发光元件的电流的影响，能够保证亮度的均一性和均匀显示。
本申请实施例还提供一种显示装置，该显示装置包括本申请实施例提供的像素电路。
虽然已经参考优选实施例对本申请进行了描述，但在不脱离本申请的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。 尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本申请并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (14)

  1. 一种像素电路，包括：数据写入子电路、初始化子电路、发光控制子电路、驱动子电路和发光子电路，
    所述数据写入子电路用于接收第一扫描信号和数据信号，并在所述第一扫描信号的控制下，将所述数据信号传输至所述驱动子电路；
    所述初始化子电路用于接收第二扫描信号和初始化信号，并在所述第二扫描信号的控制下，将所述初始化信号传输至所述驱动子电路；
    所述发光控制子电路用于接收控制信号和电源电压信号，并在所述控制信号的控制下，将所述电源电压信号传输至所述驱动子电路；
    所述驱动子电路用于接收所述数据信号、所述初始化信号和所述电源电压信号，并基于所述数据信号和所述初始化信号进行电压初始化，以及基于所述数据信号，生成并存储控制驱动子电路导通的驱动电压，以及在所述驱动电压的控制下，将所述电源电压信号传输至所述发光子电路；
    所述发光子电路用于基于所述电源电压信号发光。
  2. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括：驱动晶体管、第一电容和第二电容；
    所述驱动晶体管的栅极与所述数据写入子电路连接，用于接收所述数据写入子电路传输的所述数据信号；
    所述驱动晶体管的第一极与所述发光控制子电路和所述初始化子电路的公共端连接，用于接收所述初始化子电路传输的初始化信号以及所述发光控制子电路传输的所述电源电压信号；
    所述驱动晶体管的第二极与所述发光子电路连接，用于在所述驱动电压的控制下，将所述电源电压信号传输至所述发光子电路；
    所述第一电容的两端分别与所述驱动晶体管的栅极和所述驱动晶体管的第二极连接，所述第一电容用于存储所述驱动电压，所述驱动电压为所述驱动晶体管的栅极和所述驱动晶体管的第二极的电压差；
    所述第二电容的一端与所述驱动晶体管的第二极连接，所述第二电容的另一端用于接收所述初始化信号。
  3. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括：驱动晶体管、第一电容和第二电容；
    所述驱动晶体管的栅极与所述数据写入子电路连接，用于接收所述数据写入子电路传输的所述数据信号；
    所述驱动晶体管的第一极与所述发光控制子电路和所述初始化子电路的公共端连接，用于接收所述初始化子电路传输的初始化信号以及所述发光控制子电路传输的所述电源电压信号；
    所述驱动晶体管的第二极与所述发光子电路连接，用于在所述驱动电压的控制下，将所述电源电压信号传输至所述发光子电路；
    所述第一电容的两端分别与所述驱动晶体管的栅极和所述驱动晶体管的第二极连接，所述第一电容用于存储所述驱动电压，所述驱动电压为所述驱动晶体管的栅极和所述驱动晶体管的第二极的电压差；
    所述第二电容的一端与所述驱动晶体管的第二极连接，所述第二电容的另一端用于接收所述电源电压信号。
  4. 根据权利要求2或3所述的像素电路，其中，所述数据写入子电路包括：第一晶体管；
    所述第一晶体管的栅极用于接收所述第一扫描信号；
    所述第一晶体管的第一极与所述驱动晶体管的栅极连接，用于在所述第一扫描信号的控制下，将所述数据信号传输至所述驱动晶体管的栅极；
    所述第一晶体管的第二极用于接收所述数据信号。
  5. 根据权利要求4所述的像素电路，其中，所述初始化子电路包括：第二晶体管；
    所述第二晶体管的栅极用于接收所述第二扫描信号；
    所述第二晶体管的第一极用于接收所述初始化信号；
    所述第二晶体管的第二极与所述驱动晶体管的第一极连接，用于在所述第二扫描信号的控制下，将所述初始化信号传输至所述驱动晶体管的第一极。
  6. 根据权利要求5所述的像素电路，其中，所述发光控制子电路包括：第三晶体管；
    所述第三晶体管的栅极用于接收所述控制信号；
    所述第三晶体管的第一极用于接收所述电源电压信号；
    所述第三晶体管的第二极与所述驱动晶体管的第一极连接，用于在所述控制信号的控制下，将所述电源电压信号传输至所述驱动晶体管的第一极。
  7. 根据权利要求6所述的像素电路，其中，所述发光子电路包括：发光元件；
    所述发光元件的阳极与所述驱动晶体管的第二极连接，用于接收所述电源电压信号；
    所述发光元件的阴极接地；
    所述发光元件基于所述电源电压信号发光。
  8. 根据权利要求7所述的像素电路，其中，所述发光元件包括：有机发光二极管。
  9. 一种像素电路的驱动方法，其中，所述驱动方法用于驱动权利要求1至8任一项所述的像素电路；所述方法包括：
    在初始化阶段，所述数据写入子电路接收第一扫描信号和数据信号，在所述第一扫描信号的控制下将所述数据信号传输至所述驱动子电路；所述初始化子电路接收第二扫描信号和初始化信号，并在所述第二扫描信号的控制下将所述初始化信号传输至所述驱动子电路；所述驱动子电路接收所述数据信号和所述初始化信号；
    在采样阶段，所述数据写入子电路接收第一扫描信号和数据信号，在所述第一扫描信号的控制下将所述数据信号传输至所述驱动子电路；所述发光控制子电路接收控制信号和电源电压信号，在所述控制信号的控制下将电源电压信号传输至所述驱动子电路；所述驱动子电路接收所述数据信号和所述电源电压信号；
    在编程阶段，所述数据写入子电路接收第一扫描信号和数据信号，在所述第一扫描信号的控制下将所述数据信号传输至所述驱动子电路；所述驱动子电路接收所述数据信号，并存储用于控制所述驱动子电路导通的驱动电压；第一电压为所述驱动子电路与所述数据写入子电路的公共端的电 压，第二电压为所述驱动子电路与所述发光子电路的公共端的电压，所述驱动电压为所述第一电压和所述第二电压的电压差；编程阶段所述数据写入子电路接收到的数据信号的电压高于初始化阶段和采样阶段所述数据写入子电路接收到的数据信号的电压；
    在发光阶段，所述发光控制子电路接收控制信号和电源电压信号，在所述控制信号的控制下将所述电源电压信号传输至所述驱动子电路；所述驱动子电路在所述驱动电压的控制下将所述电源电压信号传输至所述发光子电路；所述发光子电路基于所述电源电压信号发光。
  10. 根据权利要求9所述的驱动方法，其中，所述驱动方法用于驱动权利要求7或8所述的像素电路；
    在所述初始化阶段，所述第一晶体管的栅极接收所述第一扫描信号，所述第一晶体管的第二极接收所述数据信号，所述第一晶体管的第一极在所述第一扫描信号的控制下将所述数据信号传输至所述驱动晶体管的栅极；所述驱动晶体管的栅极接收所述数据信号；所述第二晶体管的栅极接收所述第二扫描信号，所述第二晶体管的第一极接收所述初始化信号，所述第二晶体管的第二极在所述第二扫描信号的控制下将所述初始化信号传输至所述驱动晶体管的第一极；所述驱动晶体管的第一极接收所述初始化信号。
  11. 根据权利要求10所述的驱动方法，其中，
    在所述采样阶段，所述第一晶体管的栅极接收所述第一扫描信号，所述第一晶体管的第二极接收所述数据信号，所述第一晶体管的第一极在所述第一扫描信号的控制下将所述数据信号传输至所述驱动晶体管的栅极；所述驱动晶体管的栅极接收所述数据信号；所述第三晶体管的栅极接收所述控制信号，所述第三晶体管的第一极接收所述电源电压信号，所述第三晶体管的第二极在所述控制信号的控制下将所述电源电压信号传输至所述驱动晶体管的第一极；所述驱动晶体管的第一极接收所述电源电压信号，所述驱动晶体管基于所述数据信号和所述电源电压信号导通；当所述驱动晶体管的第二极电压上升至所述数据信号的电压与所述驱动晶体管的阈值电压的电压差时，驱动晶体管关断。
  12. 根据权利要求10所述的方法，其中，
    在所述编程阶段，所述第一晶体管的栅极接收所述第一扫描信号，所述第一晶体管的第二极接收所述数据信号，所述第一晶体管的第一极在所述第一扫描信号的控制下将所述数据信号传输至所述驱动晶体管的栅极；所述驱动晶体管的栅极接收所述数据信号；所述第一电容存储所述驱动电压；所述驱动电压为所述驱动晶体管的栅极和所述驱动晶体管的第二极的电压差。
  13. 根据权利要求10所述的方法，其中，
    在所述发光阶段，所述第三晶体管的栅极接收所述控制信号，所述第三晶体管的第一极接收所述电源电压信号，所述第三晶体管的第二极在所述控制信号的控制下将所述电源电压信号传输至所述驱动晶体管的第一极；所述驱动晶体管的第一极接收所述电源电压信号，所述驱动晶体管的第二极在所述驱动电压的控制下将所述电源电压信号传输至所述发光元件的阳极；所述发光元件的阳极接收所述电源电压信号；所述发光元件基于所述电源电压信号发光。
  14. 一种显示装置，包括：权利要求1至8任一项所述的像素电路。
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