WO2020138816A3 - 슬롯이 있는 메타구조체 제조방법 - Google Patents

슬롯이 있는 메타구조체 제조방법 Download PDF

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WO2020138816A3
WO2020138816A3 PCT/KR2019/017940 KR2019017940W WO2020138816A3 WO 2020138816 A3 WO2020138816 A3 WO 2020138816A3 KR 2019017940 W KR2019017940 W KR 2019017940W WO 2020138816 A3 WO2020138816 A3 WO 2020138816A3
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slot
base substrate
layer
critical strain
manufacturing
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PCT/KR2019/017940
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French (fr)
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WO2020138816A2 (ko
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원세정
김재현
정현준
이학주
정민석
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재단법인 파동에너지 극한제어연구단
한국기계연구원
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Publication of WO2020138816A2 publication Critical patent/WO2020138816A2/ko
Publication of WO2020138816A3 publication Critical patent/WO2020138816A3/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Micromachines (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

본 발명의 일실시예는 정밀한 슬롯 제작이 가능한 슬롯이 있는 메타구조체 제조방법을 제공한다. 여기서, 슬롯이 있는 메타구조체 제조방법은 신축성의 베이스기판의 상면에 제1임계변형률을 가지는 판상구조층, 그리고 제1임계변형률보다 작은 제2임계변형률을 가지는 취성층을 순차 마련하고, 제1임계변형률보다는 작고 제2임계변형률보다는 큰 변형률이 발생하도록 베이스기판에 인장력을 가하여, 취성층 및 판상구조층에 균열이 발생하도록 하고, 균열 속 베이스기판의 상부를 에칭하여 베이스기판의 상부에 함몰된 형상의 슬롯을 생성하고, 취성층의 상면에 점착필름을 부착하고, 점착필름을 이동시켜 베이스기판에서 판상구조층을 박리시키고, 슬롯이 오픈되도록 베이스기판의 상면에 도전층을 마련한다.
PCT/KR2019/017940 2018-12-28 2019-12-18 슬롯이 있는 메타구조체 제조방법 WO2020138816A2 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180171801A KR102140248B1 (ko) 2018-12-28 2018-12-28 슬롯이 있는 메타구조체 제조방법
KR10-2018-0171801 2018-12-28

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WO2020138816A2 WO2020138816A2 (ko) 2020-07-02
WO2020138816A3 true WO2020138816A3 (ko) 2020-08-20

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WO (1) WO2020138816A2 (ko)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006222408A (ja) * 2005-01-14 2006-08-24 Ricoh Co Ltd 導体配線構造体、及びその製造方法
KR101831017B1 (ko) * 2014-06-11 2018-03-29 광주과학기술원 그래핀 나노리본의 제조방법 및 이에 의해 제조된 나노리본을 포함하는 센서
KR101867377B1 (ko) * 2016-07-19 2018-06-15 한국기계연구원 나노박막 전사 방법 및 장치
JP2018181863A (ja) * 2017-04-03 2018-11-15 学校法人 名城大学 グラフェン基板、及びこの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101355166B1 (ko) 2011-11-07 2014-01-29 삼성전자주식회사 그래핀 나노-리본, 그래핀 나노-리본의 제조 방법, 및 그래핀 나노-리본을 이용한 전자 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006222408A (ja) * 2005-01-14 2006-08-24 Ricoh Co Ltd 導体配線構造体、及びその製造方法
KR101831017B1 (ko) * 2014-06-11 2018-03-29 광주과학기술원 그래핀 나노리본의 제조방법 및 이에 의해 제조된 나노리본을 포함하는 센서
KR101867377B1 (ko) * 2016-07-19 2018-06-15 한국기계연구원 나노박막 전사 방법 및 장치
JP2018181863A (ja) * 2017-04-03 2018-11-15 学校法人 名城大学 グラフェン基板、及びこの製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SAKORIKAR, TUSHAR ET AL.: "Thickness-dependent Crack Propagation in Uniaxially Strained Conducting Graphene Oxide Films on Flexible Substrates", SCIENTIFIC REPORTS, 1 June 2017 (2017-06-01), pages 1 - 10, XP055622768, DOI: 10.1038/s41598-017-02703-2 *

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KR102140248B1 (ko) 2020-07-31
KR20200081855A (ko) 2020-07-08

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