WO2020133086A1 - Panneau d'affichage et dispositif électronique - Google Patents

Panneau d'affichage et dispositif électronique Download PDF

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Publication number
WO2020133086A1
WO2020133086A1 PCT/CN2018/124437 CN2018124437W WO2020133086A1 WO 2020133086 A1 WO2020133086 A1 WO 2020133086A1 CN 2018124437 W CN2018124437 W CN 2018124437W WO 2020133086 A1 WO2020133086 A1 WO 2020133086A1
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WIPO (PCT)
Prior art keywords
display area
row
pixel
display
rows
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Application number
PCT/CN2018/124437
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English (en)
Chinese (zh)
Inventor
黄斌
金志河
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2018/124437 priority Critical patent/WO2020133086A1/fr
Priority to CN201880097601.5A priority patent/CN113243049A/zh
Publication of WO2020133086A1 publication Critical patent/WO2020133086A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the technical field of display screens, in particular to a display panel and an electronic device.
  • GOA Gate Driver On Array
  • Embodiments of the present application provide a display panel and an electronic device.
  • a display panel includes a display screen and a plurality of driving circuits, and a notch is provided on one side of the display screen, the display screen includes a pixel array, and the pixel array includes a plurality of pixels on one side of the notch A first display area pixel row and a plurality of second display area pixel rows located on the other side of the notch, the first display area pixel row and the second display area pixel row located in the same row are electrically connected, each The driving circuits connect the pixel rows of the first display area and the pixel rows of the second display area located in the same row.
  • the first display region pixel row and the second display region pixel row located in the same row are electrically connected, and each drive circuit connects the first display region pixel row and the second display region located in the same row Pixel rows, so as to ensure the normal display of the display screen, the number of driving circuits can be relatively reduced, thus reducing the circuit wiring area and frame width of the display panel, so that the display panel can meet the needs of narrower frames.
  • the electronic device includes the above-mentioned display panel.
  • the first display area pixel row and the second display area pixel row located in the same row are electrically connected, and each drive circuit connects the first display area pixel row and the second display area located in the same row Pixel rows, so as to ensure the normal display of the display screen, the number of driving circuits can be relatively reduced, thus reducing the circuit wiring area and frame width of the display panel, so that the display panel can meet the needs of narrower frames.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a control timing chart of the display panel according to the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display panel in the prior art.
  • FIG. 4 is a control timing diagram of a conventional display panel.
  • FIG. 5 is a partial schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a drive circuit of a display panel according to an embodiment of the present application.
  • Display panel 100 display screen 10, notch 12, left 14, right 16, lower 17, pixel array 18, first display area pixel row 182, second display area pixel row 184, third display area pixel row 186 , Drive circuit 20, first drive circuit 22, second drive circuit 24, first clock signal line 30, second clock signal line 40, scan signal line 50, first metal layer 60, insulating layer 70, second metal layer 80.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or integrally connected; may be mechanical, electrical, or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediary, may be the connection between two elements or the interaction of two elements relationship.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or integrally connected; may be mechanical, electrical, or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediary, may be the connection between two elements or the interaction of two elements relationship.
  • an embodiment of the present application provides a display panel 100.
  • the display panel 100 includes a display screen 10 and a plurality of driving circuits 20.
  • a notch 12 is formed on one side of the display screen 10, and the display screen 10 includes pixels Array 18, the pixel array 18 includes a plurality of first display area pixel rows 182 on one side of the notch 12 and a plurality of second display area pixel rows 184 on the other side of the notch 12, the first display area pixel rows on the same row 182 and the second display area pixel row 184 are electrically connected, and each driving circuit 20 connects the first display area pixel row 182 and the second display area pixel row 184 located in the same row.
  • the first display area pixel row 182 and the second display area pixel row 184 located in the same row are electrically connected, and each drive circuit 20 connects the first display area pixel row 182 and the first display area pixel row 182 located in the same row.
  • the second display area pixel row 184 so that under the condition of ensuring the normal display of the display screen, the number of driving circuits 20 can be relatively reduced, and thus the circuit wiring area and the frame width of the display panel 100 can be reduced, so that the display panel 100 can meet The need for narrower borders.
  • the display panel 100 may be a Notch (shaped screen) display panel 100.
  • special-shaped screens include Liu Haiping and V-shaped screens.
  • the display screen 10 may be an OLED (Organic Light-Emitting Diode), an LCD (Liquid Crystal Display, liquid crystal display 10), and the type of the display screen 10 is not limited herein.
  • OLED Organic Light-Emitting Diode
  • LCD Liquid Crystal Display, liquid crystal display 10
  • the driving circuit 20 may be a GOA (Gate driver on array, array substrate gate drive) circuit.
  • the GOA circuit provides line scan signals for pixel rows in the display area.
  • the plurality of driving circuits 20 includes a plurality of first driving circuits 22 and a plurality of second driving circuits 24.
  • the plurality of first driving circuits 22 are electrically connected to the odd-numbered first display area pixel rows 182 and the second In the second display area pixel row 184
  • a plurality of second driving circuits 24 are electrically connected to the first display area pixel row 182 and the second display area pixel row 184 of even-numbered lines, respectively.
  • the plurality of first drive circuits 22 can respectively provide scan signals to the odd-numbered first display area pixel rows 182 and the plurality of second-drive circuits 24 can respectively provide even-numbered second display area pixel rows 184 , So that the number of driving circuits 20 can be relatively reduced.
  • the plurality of first display area pixel rows 182 and the plurality of second display area pixel rows 184 are located on the left 14 and right 16 of the notch 12, respectively, and the pixel array 18 includes the lower side 17 of the notch 12
  • the number of driving circuits 20 connected to the pixel rows 186 of the third display area can be reduced, so that the circuit wiring area and the frame width of the display panel 100 can be reduced.
  • the clock signals output by the clock signal line (clk busline) 130 connected to the driving circuit 120 connected to the pixel row of the same row display area are consistent.
  • the pixel rows of the same display area in the left side 114 of the notch 112 and the right side 116 of the notch are respectively controlled by the drive circuits 120 connecting the corresponding display area pixel rows on the left and right sides, but the left and right drive circuits 120 of the same row pass the line scan signal
  • the waveforms of the line scan signals transmitted from the line 150 to the pixel rows of the display area have the same timing.
  • the left and right sides of the pixel row of the same display area on the lower side 117 of the notch are connected to be controlled by two driving circuits 120 of the corresponding pixel row of the display area, and the left and right driving circuits 120 of the same row are transmitted to the pixel row of the display area through the row scanning signal line 150
  • the waveform timing of the line scan signal is consistent.
  • the control method of this driving circuit 120 is in the form of double-feed (bilateral control).
  • the display panel 100 having n rows of display area pixel rows requires 2n drive circuits 120 to be connected, which leads to the area of the circuit wiring of the display panel 100
  • the frame of the display panel 110 is relatively wide, and cannot meet the current demand for narrower frames.
  • the left side 14 of the notch 12 and the right side 16 of the notch 12 are the notch GOA area, and the lower side 18 of the notch 12 is the non-notch GOA area.
  • the pixel rows of the same display area on the left side 14 of the notch 12 and the right side 16 of the notch 12 are connected by digging holes under the display panel 100 and connected by wires, so that the first display area pixel row 182 in the same row is electrically connected to the second display
  • the area pixel rows 184, and only one driving circuit 20 is needed to provide a line scan signal to the first display area pixel row 182 and the second display area pixel row 184 located in the same line.
  • the first driving circuit 22 provides a row scan signal for the first display area pixel row 182 and the second display area pixel row 184 that are electrically connected to odd-numbered rows.
  • the second driving circuit 24 provides a line scan signal for the first display area pixel row 182 and the second display area pixel row 184 electrically connected to the even-numbered rows.
  • This interlace control method is in the form of inter-lace (unilateral drive).
  • the number of driver circuits 20 to be connected is also n, which is different from the prior art Notch display panel 100, without changing the clock signal line (clk) timing of the left and right sides of the display panel 100 without increasing the number of clock signal lines (clk bus lines) on the left and right sides of the display panel 100, and without changing the structure of the driving circuit 20
  • the number of driving circuits 20 is reduced by half, so that the circuit wiring area and frame width of the display panel 100 can be reduced, so that the display panel 100 can meet the requirement of a narrower frame.
  • each first driving circuit 22 is connected to a first display area pixel row 182 and a second display area pixel row 184 of the same odd-numbered row, the number of first drive circuits 22 and the odd-numbered display area pixel row The total number is the same.
  • Each second driving circuit 24 connects the first display area pixel row 182 and the second display area pixel row 184 of the same even-numbered row, and the number of the second drive circuits 24 is the same as the total number of even-numbered display area pixel rows.
  • the number of the first driving circuit 22 is the same as the total number of pixel rows in the display area of odd-numbered rows and the number of the second driving circuit 24 is the same as the total number of pixel rows in the display area of even-numbered rows, this way of unilateral driving
  • the number of driving circuits 20 can be relatively reduced, so that the circuit wiring area and frame width of the display panel 100 can be reduced.
  • all the first driving circuits 22 are provided on one side of the display panel 100, and all the second driving circuits 24 are provided on the other side of the display panel 100.
  • the first drive circuit 22 and the second drive circuit 24 are arranged symmetrically.
  • Each first driving circuit 22 may provide a row scan signal to the first display area pixel row 182 and the second display area pixel row 184 connected to the same odd-numbered row.
  • Each second driving circuit 24 may provide a row scan signal to the first display area pixel row 182 and the second display area pixel row 184 connected to the same even-numbered row.
  • the display panel 100 includes a first clock signal line 30 and a second clock signal line 40, the first clock signal line 30 is connected to the first driving circuit 22, and the second clock signal line 40 is connected In the second driving circuit 24, the clock signal provided by the first clock signal line 30 and the clock signal provided by the second clock signal line 40 are arranged in time sequence.
  • first drive circuit 22 and the second clock signal line 40 are connected to the second drive circuit 24 through the first clock signal line 30, so that the first clock signal line 30 can independently input the clock signal and the second drive signal to the first drive circuit 22
  • the second clock signal line 40 independently inputs the clock signal to the second driving circuit 24.
  • the first clock signal line 30 may send a clock signal to the first driving circuit 22, and the second clock signal line 40 may send a clock signal to the second driving circuit 24.
  • the clock signal is generated by the chip.
  • the clock signal has two levels, one is a low level and the other is a high level. The high and low levels can be set to different voltages according to the requirements of the circuit.
  • the number of first clock signal lines 30 is N1
  • the number of first drive circuits 22 is M1
  • N1 first clock signal lines 30 are connected to each first drive circuit 22 of the K2th first drive circuit 22 group according to preset timing conditions, 1 ⁇ K2 ⁇ K1, M1 , K1, N1 and K2 are positive integers.
  • the first clock signal line 30 can cyclically provide clock signals to all the first driving circuits 22 according to the preset timing conditions, so that the number of the first clock signal lines 30 can be reduced to reduce the circuit wiring area of the display panel 100 And border width.
  • the number of the first clock signal line 30 and the number of the first driving circuit 22 are not limited herein, and can be set according to actual requirements. Preferably, the number of the first clock signal lines 30 is four.
  • the number of second clock signal lines 40 is N2
  • the number of second drive circuits 24 is M2
  • the second clock signal line 40 can cyclically provide clock signals to all the second driving circuits 24 according to the preset timing conditions, so that the number of the second clock signal lines 40 can be reduced to reduce the circuit wiring area of the display panel 100 And border width.
  • the number of the second clock signal line 40 and the number of the second driving circuit 24 are not limited herein, and can be set according to actual requirements. Preferably, the number of the second clock signal lines 40 is 4.
  • the clock signals of the first driving circuit 22 corresponding to the pixel rows of two adjacent odd-numbered rows of the display area differ by one cycle.
  • the clock signals of the second driving circuits 24 corresponding to the pixel rows of the adjacent two even-numbered rows differ by one period.
  • the row scanning signals provided by the first driving circuit 22 to the pixel rows of the adjacent odd-numbered display area can differ by one period and the row scanning signals provided by the second driving circuit 24 to the pixel rows of the adjacent even-numbered row of the display area It can differ by one cycle.
  • the clock signals of the driving circuits 20 corresponding to the pixel rows of the display regions of two adjacent rows differ by half a cycle.
  • the scan signals provided by the drive circuit 20 to the pixel rows of the display regions of two adjacent rows differ by half a cycle.
  • the first driving circuit 22 is connected to four first clock signal lines 30, and the first clock signal lines 1, 2, 3, and 4, respectively, according to preset timing conditions, wherein The clock signals of two adjacent first clock signal lines 30 differ by one cycle. Every four first drive circuits 22 are a group, and every four first drive circuits 22 are connected to the first clock signal lines 1, 2, 3, 4 respectively.
  • the second driving circuit 24 is connected to four second clock signal lines 40, which are respectively the first clock signal lines 5, 6, 7, 8 according to preset timing conditions, wherein the clock signals of two adjacent second clock signal lines 40 are different A cycle. Every four second drive circuits 24 are a group, and every four second drive circuits 24 are connected to the second clock signal lines 5, 6, 7, 8 respectively.
  • a clock signal line connecting the first driving circuit 22 and the second driving circuit 24 provides a clock signal cyclically, for example, the first clock signal lines 1, 2, 3, 4 are connected to the first drive in order Circuits GOA1, GOA3, GOA5 and GOA7.
  • the first clock signal lines 5, 6, 7, and 8 are respectively connected to the second driving circuits GOA2, GOA4, GOA6, and GOA8 in this order.
  • the line scan signal output by the first drive circuit GOA1 is G1
  • the line scan signal output by the first drive circuit GOA3 is G3
  • the line scan signal output by the first drive circuit GOA5 is G5
  • the line scan signal output by the first drive circuit GOA7 is G7, and so on, the GOA(n-1) signal of the first driving circuit is G(n-1).
  • the line scan signal output by the second drive circuit GOA2 is G2
  • the line scan signal output by the second drive circuit GOA4 is G4
  • the line scan signal output by the second drive circuit GOA6 is G6, and so on, the second drive circuit GOA(n )
  • the signal is G(n).
  • the number of the first driving circuits 22 is n/2, and the first driving circuit 22 corresponding to the pixel row of the display area of the kth row is k+2 rows
  • the first driving circuit 22 corresponding to the pixel row of the display area provides an input signal
  • the first driving circuit 22 corresponding to the pixel row of the display area of the k+2th row is the first driving circuit 22 corresponding to the pixel row of the display area of the kth row Provide reset signal.
  • the number of the second driving circuits 24 is n/2.
  • the second driving circuit 24 corresponding to the pixel row of the display area of the k-1th row provides the second driving circuit 24 corresponding to the pixel row of the display area of the k+1th row Input signal, the second driving circuit 24 corresponding to the pixel row of the display area of the k+1th row provides a reset signal for the second driving circuit 24 corresponding to the pixel row of the display area of the k-1th row.
  • an input signal stvL is provided to the first driving circuit GOA1, and the output signal of the first driving circuit GOA1 is used as the input signal of the first driving circuit GOA3, the first driving circuit GOA3 provides a reset signal for the first drive circuit GOA1; the output signal of the first drive circuit GOA3 serves as the input signal of the first drive circuit GOA5, and the first drive circuit GOA5 provides a reset signal for the first drive circuit GOA3; the first drive circuit GOA5 The output signal is used as the input signal of the first drive circuit GOA7.
  • the first drive circuit GOA7 provides the reset signal for the first drive circuit GOA5, and so on.
  • the output signal of the first drive circuit GOA (n-3) is used as the first drive circuit GOA (n-1) input signal, the first drive circuit GOA (n-1) provides a reset signal for the first drive circuit GOA (n-3), and finally, a reset is input to the first drive circuit GOA (n-1) Signal resetL.
  • an input signal stvR is provided to the second drive circuit GOA2, the output signal of the second drive circuit GOA2 is used as the input signal of the second drive circuit GOA4, and the second drive circuit GOA4 provides a reset for the second drive circuit GOA2 Signal; the output signal of the second drive circuit GOA4 as the input signal of the second drive circuit GOA6, the second drive circuit GOA6 provides a reset signal for the second drive circuit GOA4; the output signal of the second drive circuit GOA6 as the second drive circuit GOA8 Input signal, the second drive circuit GOA8 provides a reset signal for the second drive circuit GOA6; and so on, the output signal of the second drive circuit GOA (n-2) as the input signal of the second drive circuit GOA (n), The second driving circuit GOA(n) provides a reset signal for the second driving circuit GOA(n-2). Finally, a reset signal resetR is input to the second driving circuit GOA(n).
  • the display panel 100 includes a scan signal line 50.
  • the drive circuit 20 provides a row scan signal to the pixel row of the display area through the scan signal line 50, and connects a plurality of first
  • the line scan signal lines 50 of the display area pixel row 182 and the scan signal lines 50 of the plurality of second display area pixel rows 184 connecting the second display area 16 have a line width smaller than the plurality of third display areas connecting the third display area 17
  • the line width of the scanning signal line 50 of the pixel row 186 The line width of the scanning signal line 50 of the pixel row 186.
  • the resistance of the line of the first display area 14 and the second display area 16 can be increased, so that the resistance of the line of the first display area 14 and the second display area 16 can be compared with the resistance of the line of the third display area 17 Maintain balance to ensure the quality of the display screen 10.
  • the pixel row of the display area includes a first metal layer 60, an insulating layer 70, and a second metal layer 80 that are sequentially stacked from bottom to top.
  • the first metal layer 60 serves as a scanning signal line.
  • a metal layer 60, an insulating layer 70 and a second metal layer 80 form a capacitor.
  • the capacitance of the line on the left side 14 of the notch 12 and the right side 16 of the notch 12 can be increased, so that the left side of the notch 12
  • the capacitance of the line on the side 14 and the left side 16 of the notch 12 can be balanced with the capacitance of the line on the lower side 17 of the notch 12, thereby ensuring the quality of the display screen 10.
  • the RC loading (resistance and capacitance loading) of the display panel 100 refers to the product of resistance and capacitance generated by the circuit elements of the display panel 100 connected to the scan signal line 50.
  • a larger RC loading in each area on the display panel 100 will result in poor signal transmission quality.
  • Inconsistent RC loading of the scanning signal lines 50 in different rows will result in inconsistent signal transmission environments, and the loading of the scanning signal lines 50 in different rows will be the same Poor sexual performance can easily affect display quality.
  • the Notch display panel 100 where a gap 12 is formed on one side of the display screen 10 and a part of pixels are missing, by reducing the left row 14 of the notch 12 and the right row 16 of the notch 12 by the corresponding row Scan the line width of the signal line 50 to increase the resistance R of the line on the left side 14 of the notch 12 and the right side 16 of the notch 12, and by adding a second metal layer 80 on the insulating layer 70 to make the first metal layer 60,
  • the insulating layer 70 and the second metal layer 80 form an overlap capacitance so that the Rcloading of the row scanning signal lines 50 on the left side 14 of the notch 12, the right side 16 of the notch 12, and the lower side 17 of the notch 12 coincides.
  • the driving circuit 20 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7 And capacitor C1.
  • the gate of the first transistor M1 is connected to the end of the drive circuit 20 that receives the input signal, and the drain of the first transistor M1 is connected to the gate of the first transistor M1.
  • the gate of the second transistor M2 is connected to the positive voltage of the power supply, and the source of the second transistor M2 is connected to the gate of the second transistor M2.
  • the gate of the third transistor M3 is connected to one end of the capacitor C1 and the drain of the first transistor M1, the source of the third transistor M3 is connected to the clock signal terminal, and the drain of the third transistor M3 is connected to the scan signal line 50.
  • the drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and the source of the fourth transistor M4 is connected to the negative voltage of the power supply.
  • the source of the fifth transistor M5 is connected to the drain of the third transistor M3 and one end of the capacitor C1, and the drain of the fifth transistor M5 is connected to the negative voltage of the power supply.
  • the drain of the sixth transistor M6 is connected to the scan signal line 50, the gate of the sixth transistor M6 is connected to one end of the reset signal provided by the driving circuit 20, and the source of the sixth transistor M6 is connected to the negative voltage of the power supply.
  • the gate of the seventh transistor M7 is connected to the drain of the first transistor M1 and the gate of the third transistor M3, and the source of the seventh transistor M7 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5, the seventh transistor The drain of M7 is connected to the negative voltage of the power supply.
  • the display panel 100 first provides a stvL input level to the driving circuit GOA1, the third transistor M3 is turned on, the clock signal line clk1 starts to input the clock signal, and the signal terminal of the driving circuit outputs the line scan signal G1,
  • the clock signal line clk3 starts to input the clock signal, that is, the sixth transistor of the driving circuit is turned on, so that the signal terminal of the driving circuit is grounded, the row scanning signal is reset to a low level, and so on, the nth
  • the signal terminal G(n) of the driving circuit is connected to the signal input terminal of the n+2th driving circuit and the reset signal terminal of the n-2th driving circuit.
  • Embodiments of the present application also provide an electronic device (not shown).
  • the electronic device includes the display panel 100 of any of the above embodiments.
  • the first display area pixel row 182 and the second display area pixel row 184 in the same row are electrically connected, and each drive circuit 20 connects the first display area pixel row 182 and the first display area pixel row in the same row.
  • Two display area pixel rows 184 so that the number of driving circuits 20 can be relatively reduced under the condition of ensuring the normal display of the display screen, so the circuit wiring area and frame width of the display panel 100 can be reduced, so that the display panel 100 can satisfy more The need for narrow borders.
  • electronic devices include but are not limited to mobile phones, tablet computers, notebook computers, e-books, wearable electronic devices, and the like.
  • each part of the present application may be implemented by hardware, software, firmware, or a combination thereof.
  • multiple steps or methods may be performed using software or firmware stored in memory and executed by a suitable instruction execution system.
  • a logic gate circuit for performing a logic function on a data signal
  • PGA programmable gate arrays
  • FPGA field programmable gate arrays
  • each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module.
  • the above-mentioned integrated modules may be executed in the form of hardware or software function modules. If the integrated module is executed in the form of a software function module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.
  • the storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

L'invention concerne un panneau d'affichage (100), comprenant un écran d'affichage (10) et une pluralité de circuits d'attaque (20), une encoche (12) étant ménagée sur un côté de l'écran d'affichage (10), l'écran d'affichage (10) comprenant un réseau de pixels (18), le réseau de pixels (18) comprenant une pluralité de premières rangées de pixels de zone d'affichage (182) situées d'un côté de l'encoche (12) et une pluralité de secondes rangées de pixels de zone d'affichage (184) situées de l'autre côté de l'encoche (18), la première rangée de pixels de zone d'affichage (182) et la seconde rangée de pixels de zone d'affichage (184) situées dans la même rangée étant connectées électriquement, et chaque circuit d'attaque (20) connectant la première rangée de pixels de zone d'affichage (182) et la seconde rangée de pixels de zone d'affichage (184) situées dans la même rangée.
PCT/CN2018/124437 2018-12-27 2018-12-27 Panneau d'affichage et dispositif électronique WO2020133086A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/124437 WO2020133086A1 (fr) 2018-12-27 2018-12-27 Panneau d'affichage et dispositif électronique
CN201880097601.5A CN113243049A (zh) 2018-12-27 2018-12-27 显示面板和电子装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/124437 WO2020133086A1 (fr) 2018-12-27 2018-12-27 Panneau d'affichage et dispositif électronique

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