WO2020125816A1 - 射频开关电路、芯片及通信终端 - Google Patents

射频开关电路、芯片及通信终端 Download PDF

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Publication number
WO2020125816A1
WO2020125816A1 PCT/CN2020/076025 CN2020076025W WO2020125816A1 WO 2020125816 A1 WO2020125816 A1 WO 2020125816A1 CN 2020076025 W CN2020076025 W CN 2020076025W WO 2020125816 A1 WO2020125816 A1 WO 2020125816A1
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Prior art keywords
radio frequency
resistor
switch
port
circuit
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PCT/CN2020/076025
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English (en)
French (fr)
Inventor
李艳伟
林升
Original Assignee
唯捷创芯(天津)电子技术股份有限公司
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Application filed by 唯捷创芯(天津)电子技术股份有限公司 filed Critical 唯捷创芯(天津)电子技术股份有限公司
Priority to CN202080002569.5A priority Critical patent/CN113544974B/zh
Priority to EP20734308.8A priority patent/EP3896854A4/en
Publication of WO2020125816A1 publication Critical patent/WO2020125816A1/zh
Priority to US17/304,383 priority patent/US20210313982A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the invention relates to a radio frequency switch circuit, and also relates to corresponding integrated circuit chips and communication terminals, and belongs to the technical field of radio frequency circuits.
  • FIG 1 is a schematic diagram of the PIFA antenna and its tuning circuit.
  • the dark part is the PIFA antenna, one end is grounded, there is a feed point in the middle, and a tuner is connected to the antenna arm.
  • the tuner is usually composed of a single-pole multi-throw switch and a capacitor (or inductor).
  • the single-pole multi-throw switch can be integrated with the capacitor or can be independent.
  • the rectangular box shown in Figure 2 is a SP4T (single pole 4 throw) switch, the common end of the switch is connected to the PIFA antenna arm, and the four ports of the switch are respectively connected to four capacitors (capacitors C1 ⁇ C4) .
  • the capacitors C1 to C4 can be replaced by some or all of the inductors.
  • the switches that turn off these roads must withstand the voltage swing, and the peak value depends on the position where the tuner is connected to the antenna. Different positions of the tuner have different voltage swings and can reach 80V or even higher.
  • the voltage that the single-pole multi-throw switch bears is distributed to each switch unit.
  • the harmonics generated by the single-pole multi-throw switch will deteriorate. If the voltage is further increased and the breakdown voltage of the single-pole multi-throw switch is exceeded, harmonics will rise in a cliff-like manner, seriously affecting the performance of antenna tuning.
  • Fig. 3 is a diagram of a typical switch structure in the prior art. It consists of three parts: a series structure 100 composed of one or more switching units, a gate bias circuit 101 and a body bias circuit 102. As the voltage swing experienced by the switch increases, the voltage experienced by each switch unit increases accordingly, resulting in the deterioration of harmonics. Within a certain range, this situation can be improved by increasing the number of switching units (number of stacked tubes).
  • Figure 4 reflects the relationship between the voltage that the switch can withstand and the number of switch stacks. The dashed and solid lines correspond to the ideal and actual voltage values that the switch can withstand. When the number of stacked tubes is relatively small, the voltage that the switch can withstand has a linear relationship with the number of stacked tubes.
  • the primary technical problem to be solved by the present invention is to provide a radio frequency switch circuit.
  • Another technical problem to be solved by the present invention is to provide an integrated circuit chip and a communication terminal.
  • a radio frequency switch circuit including a first port and a second port, and a switch link formed by at least one switch unit between the first port and the second port
  • Each of the switch units is respectively connected to a first bias circuit and a second bias circuit, and preset positions of the first bias circuit and the second bias circuit are connected to a bias voltage.
  • the switch link includes one switch unit
  • the input terminal of the switch unit is connected to the first port
  • the output terminal of the switch unit is connected to the second port
  • the output terminal of each switch unit is connected to the input terminal of the next switch unit.
  • the input terminal of the first switch unit is connected to the first port, and the output terminal of the last switch unit of the switch link is connected to the second port.
  • each of the switching units includes a MOS transistor, a first resistor is provided between the source and drain of the MOS transistor, and the gate and body of the MOS transistor are respectively connected to corresponding bias Circuit.
  • the first bias circuit includes at least one first T-type resistance network, each of the first T-type resistance networks is correspondingly connected to the gate of the MOS transistor, and the first one of the first A first capacitor is provided between the T-type resistor network and the last first T-type resistor network corresponding to the first port and the second port, respectively.
  • each of the first T-type resistor networks includes a second resistor, and two adjacent first T-type resistor networks share a third resistor, and both ends of the third resistor are connected adjacent to each other.
  • One end of the second resistor of the two first T-type resistor networks, the other end of the second resistor is connected to the gate of the corresponding MOS transistor, the first one of the first T-type resistor network and One end of the second resistor of the last first T-type resistor network is respectively connected to the corresponding first capacitor through a third resistor.
  • the second bias circuit includes at least one second T-type resistance network, each of the second T-type resistance networks is correspondingly connected to the body of the MOS transistor, and the first one of the second A second capacitor is provided between the T-type resistor network and the last second T-type resistor network corresponding to the first port and the second port, respectively.
  • each of the second T-type resistor networks includes a fourth resistor, and two adjacent second T-type resistor networks share a fifth resistor, and both ends of the fifth resistor are correspondingly connected adjacent One end of the fourth resistor of the two second T-type resistor networks, the other end of the fourth resistor is connected to the body of the corresponding MOS transistor, the first one of the second T-type resistor network and One end of the fourth resistor of the last second T-type resistor network is respectively connected to the corresponding second capacitor through a fifth resistor.
  • the resistors in the first T-type resistor network and the second T-type resistor network respectively use variable resistor arrays; the first capacitor and the second capacitor respectively use capacitor arrays.
  • both the first port and the second port serve as input ports for radio frequency signals.
  • one of the first port and the second port serves as an input port of the radio frequency signal, and the other port is grounded.
  • a third capacitor is provided between the source and the body of the MOS transistor of each switching unit to adjust the ratio of the parasitic capacitance between the MOS transistor and the third capacitor to improve the radio frequency When the switch circuit is turned off, the uniformity of the voltage distribution on the switch link.
  • the size of the MOS transistor of each switch unit and the ratio with the third capacitor are adjusted to improve the uniformity of the voltage distribution on the switch link when the RF switch circuit is turned off; wherein,
  • the size of the MOS transistor refers to the gate width-to-length ratio of the MOS transistor.
  • the radio frequency switch circuit is bidirectional, if the number of the switch units is an odd number, connect two of the third of the first T-shaped resistor network in the middle of the switch unit The middle point of the resistor is connected to the bias voltage, and the middle point of the two fifth resistors connected to the second T-type resistor network in the middle of the switch unit is connected to the bias voltage;
  • bias voltages are respectively connected to the center points of the third resistor and the fifth resistor in the center position.
  • a bias voltage is connected from the side of the first bias circuit and the second bias circuit close to ground, respectively.
  • an integrated circuit chip including the above-mentioned radio frequency switch circuit.
  • a communication terminal including the above-mentioned radio frequency switch circuit.
  • the radio frequency switch circuit connects each switch unit to the first bias circuit and the second bias circuit separately by providing a switch link formed by at least one switch unit between the first port and the second port, and Further adjusting the ratio of the parasitic capacitance between the MOS transistors of each switching unit to the third capacitor, the size of the MOS transistors of each switching unit and the ratio to the third capacitor can improve the uniformity of the voltage distribution on the switching link and increase the radio frequency
  • the overall withstand voltage capability of the switching circuit reduces the occurrence of harmonics.
  • Figure 1 is a schematic diagram of the PIFA antenna and its tuning circuit
  • Figure 2 is a schematic diagram of a single-pole 4-throw switch circuit
  • FIG. 3 is an example diagram of a switch structure in the prior art
  • FIG. 4 is a schematic diagram of the relationship between the voltage that the switch can withstand and the number of switch stacks
  • FIG. 5 is a circuit schematic diagram of the radio frequency switch circuit provided by Embodiment 1 of the present invention.
  • FIG. 6 is a circuit schematic diagram of a radio frequency switch circuit provided by Embodiment 2 of the present invention.
  • FIG. 7 is a circuit schematic diagram of a radio frequency switch circuit provided in Embodiment 3 of the present invention.
  • FIG. 8 is a circuit schematic diagram of a radio frequency switch circuit provided by Embodiment 4 of the present invention.
  • FIG. 9 is a circuit schematic diagram of a radio frequency switch circuit provided by Embodiment 5 of the present invention.
  • FIG. 10 is a circuit schematic diagram of a radio frequency switch circuit provided by Embodiment 6 of the present invention.
  • FIG. 11 is a schematic diagram of the relationship between the voltage swing on each switch unit and the switch stacking sequence in the radio frequency switch circuit provided by the present invention.
  • the radio frequency switch circuit provided in Embodiment 1 includes a first port 1 and a second port 2, and at least one switch unit 3 participates in the formed switch link between the first port 1 and the second port 2.
  • Each switch unit 3 is connected to the first bias circuit 4 and the second bias circuit 5 respectively.
  • the preset positions of the first bias circuit 4 and the second bias circuit 5 are connected to the bias voltage.
  • the switch link When the switch link includes a switch unit 3, the input end of the switch unit serves as the input end of the switch link, and the output end of the switch unit serves as the output end of the switch link.
  • the input terminal of the switch unit 3 is connected to the first port 1, and the output terminal of the switch unit 3 is connected to the second port 2.
  • Both the first port 1 and the second port 2 serve as input ports for radio frequency signals, so that the radio frequency switch circuit is bidirectional, and radio frequency signals can be input from any one port.
  • the switch link uses a switch unit to connect or disconnect the signals at both ends of the switch link.
  • the switch chain includes two or more switch units 3, the output terminal of each switch unit 3 is connected to the input terminal of the next switch unit; and, the input terminal of the first switch unit 3 of the switch chain is connected to the One port 1, the input end of the first switch unit 3 is the input end of the switch link, the output end of the last switch unit 3 of the switch link is connected to the second port 2, and the output end of the last switch unit 3 is used as a switch The output of the link.
  • the RF switch circuit is bidirectional, and RF signals can be input from any port.
  • the switch link uses two or more switch units to ensure that the signals at both ends of the switch link are connected or disconnected, and also meet the requirements of various indicators.
  • the switching unit 3 may be implemented by using MOS transistors, and may specifically be CMOS transistors or SOI NMOS transistors (silicon-based insulator MOS transistors).
  • MOS transistors may specifically be CMOS transistors or SOI NMOS transistors (silicon-based insulator MOS transistors).
  • SOI NMOS transistors SOI and NMOS transistors (abbreviated as NMOS transistors) as examples for each switch unit 3, but the corresponding technical solutions are also applicable to other types of MOS transistors such as CMOS transistors .
  • the source of the NMOS transistor is used as the input of the switching unit 3, and the drain of the NMOS transistor is used as the output of the switching unit 3.
  • a first resistor Rds is provided between the source and the drain of the NMOS transistor. It is used to establish a bias voltage for the drain and source of each NMOS transistor so that the DC voltage of the drain and source of each NMOS transistor is equal.
  • the gate of the NMOS transistor is connected to the first bias circuit 4, the body of the NMOS transistor is connected to the second bias circuit 5, and the gate of the NMOS transistor is controlled by the first bias circuit 4 to reduce the conduction of the NMOS transistor The loss of the RF signal on the gate and improves the uniformity of the voltage distribution on the switch link when the NMOS transistor is off, thereby improving the voltage resistance of the RF switch circuit and improving harmonic performance.
  • the first bias circuit 4 is respectively connected to the gate of the NMOS transistor of each switching unit, and the second bias circuit 5 is respectively connected to the body of the NMOS transistor of each switching unit.
  • the first bias circuit 4 includes at least one first T-type resistor network 40, and each first T-type resistor network 40 corresponds to a gate of an NMOS transistor of a switching unit 3;
  • a first capacitor C1 is provided between the connected first T-shaped resistor network 40 and the first port 1, and a first capacitor C1 is also provided between the first T-shaped resistor network 40 and the second port 2 connected to the last switching unit 3 Capacitor C1.
  • each first T-type resistor network 40 includes a second resistor R1, and two adjacent first T-type resistor networks 40 share a third resistor R2, and two of the third resistor R2
  • the terminal corresponds to one end of the second resistor R1 of two adjacent first T-type resistor networks 40, and the other end of the second resistor R1 is connected to the gate of the NMOS transistor of the corresponding switching unit.
  • One end of the first first T-type resistor network 40 and the second resistor R1 of the last first T-type resistor network 40 are respectively connected to the corresponding first capacitor C1 through a third resistor R2.
  • the first capacitor C1 may be a MIM (metal-insulator-metal, metal-insulator-metal) capacitor or a parasitic capacitor formed between metals.
  • the capacitance density of the MIM capacitor is larger than the parasitic capacitance, so if the required capacitance value is large, the MIM capacitor can be used, which takes up a small area. If the required capacitance value is small, the parasitic capacitance formed between the metals can be used.
  • the parasitic capacitance is generated by the overlap between the metal wires of different levels, and usually the capacitance density is smaller.
  • the radio frequency switch circuit When the radio frequency switch circuit is turned on, the leakage of the radio frequency signal in this direction is blocked by the second resistor R1, thereby reducing the loss of the radio frequency signal on the gate.
  • the 12V voltage is uniform Distributed on the NMOS transistors of the four switch units 3, each NMOS transistor is 3V; however, due to the parasitic capacitance, the voltage division on each switch unit 3 is no longer uniform, such as the NMOS of the first switch unit 3
  • the voltage that the transistor bears is 4V, this voltage value exceeds the rated voltage (such as 3.5V) that the NMOS transistor of the switching unit 3 can withstand under the selected process, then it will cause the harmonics of the RF switching circuit to deteriorate sharply.
  • the radio frequency switch circuit since the first T-type resistance network 40 is adopted, the voltage drop caused by the leakage current on the first T-type resistance network 40 corresponds to the voltage between the drain and the source of each switch unit 3 Uniform, because the first T-type resistor network 40 is also cascaded, each third resistor R2 is equal. Moreover, the radio frequency switch circuit further adjusts the impedance generated by the first NMOS transistor through the first capacitor C1, which also helps to improve the non-uniformity of the voltage distribution on the switch link. Therefore, the first T-shaped resistor network 40 improves the uniformity of the voltage distribution on the switch link, and achieves the objectives of improving the voltage withstand capability of the RF switching circuit and optimizing harmonic performance.
  • the bias circuit 4 has the same structure as the second bias circuit 5.
  • the second bias circuit 5 includes at least one second T-type resistor network 50, and each second T-type resistor network 50 corresponds to the body of the NMOS transistor of one switch unit 3; A second capacitor C2 is provided between the second T-type resistor network 50 and the first port 1, and a second capacitor C2 is also provided between the second T-type resistor network 50 connected to the last switch unit 3 and the second port 2 .
  • each second T-type resistor network 50 includes a fourth resistor R4, and two adjacent second T-type resistor networks 50 share a fifth resistor R3, and two of the fifth resistor R3
  • the terminal corresponds to one end of the fourth resistor R4 of the two adjacent second T-type resistor networks 50, and the other end of the fourth resistor R4 is connected to the body of the NMOS transistor of the corresponding switch unit 3.
  • One end of the first second T-type resistor network 50 and the fourth resistor R4 of the last second T-type resistor network 50 are respectively connected to the corresponding second capacitor C1 through a fifth resistor R3.
  • the resistors (including the second resistor R1, the third resistor R2, the fourth resistor R4, and the fifth resistor R3) in the first T-type resistor network 40 and the second T-type resistor network 50 may be variable resistors Array; the first capacitor C1 and the second capacitor C2 may be a capacitor array.
  • the preset position of the first bias circuit 4 is connected to the bias voltage Vg
  • the preset position of the second bias circuit 5 is connected to the bias voltage Vb
  • the way in which the bias voltages Vg and Vb are connected may depend on the switching unit The number of 3 depends.
  • the access methods of the bias voltages Vg and Vb are related to the parity.
  • the bias voltage Vg is connected to the middle point of the two third resistors R2 of the first T-type resistor network 40 connected to the positive intermediate switching unit 3, and the bias voltage Vb is connected to The middle point of the two fifth resistors R3 of the second T-shaped resistor network 50 of the positive intermediate switching unit 3 is connected.
  • the bias voltage Vg is connected to the center point of the third resistor R2 at the center position (as shown in FIG. 5), and the bias voltage Vb is connected to the center position at the center position The center point of the fifth resistor R3 (as shown in FIG. 5).
  • the access method of the bias voltages Vg and Vb is not unique, and it can be accessed elsewhere in the first bias circuit 4 and the second bias circuit 5.
  • the radio frequency switch circuit provided in this embodiment is based on the radio frequency switch circuit provided in Embodiment 1, and a third capacitor Cx is provided between the source and body of the NMOS transistor of each switch unit 3, and the third capacitor Cx is used as The compensation capacitance of the switching unit 3; alternatively, the third capacitance Cx may also be provided between the source and gate of the NMOS transistor of each switching unit 3, respectively.
  • the ratio of the three capacitors Cx further improves the uniformity of the voltage distribution on the switch link when the RF switch circuit is cut off, thereby improving the pressure resistance of the RF switch circuit and improving harmonic performance.
  • the initial ratio of the parasitic capacitance between the NMOS transistors of each switching unit 3 and the third capacitance Cx is selected, and the voltage distribution of each switching unit 3 is calculated by simulation, and Observe whether the voltage on one or several switch units 3 exceeds the rated voltage. This is an iterative process until a certain ratio is selected so that the voltage distribution on the switch link is most uniform.
  • the radio frequency switch circuit provided in this embodiment further adjusts the gate width-to-length ratio (W/L) of the NMOS transistor of each switch unit 3 on the basis of the radio frequency switch circuit provided in Embodiment 2.
  • the withstand voltage value of the NMOS transistor in each switching unit 3 is related to the length of its gate. The longer the gate length L of the NMOS transistor, the higher the withstand voltage value of the NMOS transistor, which is beneficial to the cut-off of the RF switching circuit When the pressure resistance. However, when the NMOS transistor is turned on, its impedance also becomes higher, resulting in greater insertion loss.
  • adjusting the size of the NMOS transistor of each switching unit 3 refers to adjusting the gate width-to-length ratio (W/L) of the NMOS transistor of each switching unit 3. Specifically, because the size of each MOS transistor contributes to a part of the overall parasitic capacitance of the RF switching circuit, the other part of the overall parasitic capacitance is contributed by the metal wiring.
  • the size of each NMOS transistor and the ratio to the third capacitor Cx the impedance generated by each NMOS transistor can be changed.
  • the voltage unevenness experienced by each switching unit 3 is the product of the impedance from each NMOS transistor and the leakage current. Therefore, adjusting the size of the NMOS transistor of each switching unit 3 and the ratio with the third capacitor Cx can improve the uniformity of the voltage distribution on the switching link.
  • the radio frequency switch circuit in this embodiment is different from the radio frequency switch circuit in embodiment 1 in that one of the first port 1 and the second port 2 serves as an input port for radio frequency signals, and the other port Ground.
  • the radio frequency switch circuit is unidirectional, the radio frequency signal is only input from one port, and the other port cannot always receive the radio frequency signal.
  • the radio frequency switch circuit When the radio frequency switch circuit is turned on, the leakage of the radio frequency signal in this direction is blocked by the second resistor R1, thereby reducing the loss of the radio frequency signal on the gate.
  • the RF switch circuit When the RF switch circuit is turned off, the first T-type resistor network 40 is used, so that the voltage drop generated by the leakage current on the first T-type resistor network 40 corresponds to the drain and source of each switch unit 3 More evenly.
  • the radio frequency switch circuit further adjusts the impedance encountered by the first NMOS transistor through the first capacitor C1, which helps to improve the non-uniformity of the voltage distribution on the switch link. Therefore, the first T-shaped resistor network 40 improves the uniformity of the voltage distribution on the switch link, and achieves the objectives of improving the voltage withstand capability of the RF switching circuit and optimizing harmonic performance.
  • the preset position of the first bias circuit 4 is connected to the bias voltage Vg, and the preset position of the second bias circuit 5 is connected to the bias voltage Vb, wherein preferably, the bias voltages Vg and Vb respectively correspond to The bias circuit 4 and the second bias circuit 5 are connected near the ground.
  • the radio frequency switch circuit provided in this embodiment is based on the radio frequency switch circuit provided in Embodiment 4, and a third capacitor Cx is provided between the source and body of the NMOS transistor of each switch unit 3, and the third capacitor Cx is used as The compensation capacitance of the switching unit 3; alternatively, the third capacitance Cx may also be provided between the source and gate of the NMOS transistor of each switching unit 3, respectively.
  • the ratio of the three capacitors Cx further improves the uniformity of the voltage distribution on the switch link when the RF switch circuit is cut off, thereby achieving the purpose of improving the RF switch circuit's voltage resistance and improving harmonic performance.
  • the radio frequency switch circuit provided in this embodiment further adjusts the gate width-to-length ratio (W/L) of the NMOS transistor of each switch unit 3 on the basis of the radio frequency switch circuit provided in Embodiment 5.
  • the withstand voltage value of the NMOS transistor in each switching unit 3 is related to the length of its gate. The longer the gate length L of the NMOS transistor, the higher the withstand voltage value of the NMOS transistor, which is beneficial to the cut-off of the RF switching circuit When the pressure resistance. However, when the NMOS transistor is turned on, its impedance also becomes higher, resulting in greater insertion loss.
  • adjusting the size of the NMOS transistor of each switching unit 3 refers to adjusting the gate width-to-length ratio (W/L) of the NMOS transistor of each switching unit 3.
  • the figure reflects the relationship between the voltage swing on each switch unit and the switch stacking sequence.
  • 1, 2, 3, and 4 refer to the first, second, third, and fourth switching units from the input end of the switching link, respectively.
  • the total number of switch units is not listed here.
  • Those skilled in the art should know that the specific number of switch units required is related to radio frequency switch circuit design indicators, processes, and other factors.
  • the voltage swing experienced by the switch unit near the input end of the switch link is relatively large (for example, the first and second switch units in FIG.
  • the voltage swing of the switch unit near the input end of the switch link is close to, reaches, or even exceeds the rated voltage that the switch unit can withstand (horizontal line in Figure 11).
  • the harmonics of the RF switching circuit will rapidly deteriorate, and even unrecoverable damage may occur.
  • the RF switching circuit provided by the embodiment of the present invention can reduce the maximum voltage that is easily damaged by the switching unit (shown by the broken line in FIG. 11), improve the uniformity of the voltage distribution on the switching link, and improve the overall resistance of the RF switching circuit. Pressure capacity to reduce the occurrence of harmonics.
  • the radio frequency switch circuit connects each switch unit to the first bias circuit and the second switch unit by providing a switch link formed by at least one switch unit between the first port and the second port Two bias circuits, and further adjusting the ratio of the parasitic capacitance between the MOS transistors of each switching unit and the third capacitor, the size of the MOS transistor of each switching unit and the ratio with the third capacitor, can improve the voltage distribution on the switching link
  • the uniformity of the radio frequency improves the overall withstand voltage capability of the RF switching circuit and reduces the occurrence of harmonics.
  • the radio frequency switch circuit provided by the present invention can be used in an integrated circuit chip.
  • the specific structure of the radio frequency switch circuit in the integrated circuit chip will not be described in detail here.
  • the above-mentioned radio frequency switch circuit can also be used in a communication terminal as an important part of the radio frequency circuit.
  • the communication terminal mentioned here refers to a computer device that can be used in a mobile environment and supports various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE, including mobile phones, notebook computers, tablet computers, and in-vehicle computers.
  • the technical solution provided by the present invention is also applicable to other radio frequency circuit applications, such as communication base stations.

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Abstract

本发明公开了一种射频开关电路、芯片及通信终端。该射频开关电路通过在第一端口和第二端口之间设置至少一个开关单元形成的开关链路，将每个开关单元分别连接第一偏置电路和第二偏置电路，并进一步调整各开关单元的MOS晶体管之间的寄生电容和第三电容的比值、各开关单元的MOS晶体管的尺寸以及和第三电容的比值，可以改善开关链路上电压分布的均匀性，提高射频开关电路的整体耐压能力，减小谐波的发生。

Description

射频开关电路、芯片及通信终端 技术领域
本发明涉及一种射频开关电路，同时也涉及相应的集成电路芯片及通信终端，属于射频电路技术领域。
背景技术
随着无线通信技术的发展，通信标准经历了从3G、4G到5G的时代演化，从早期的单制式、覆盖几个频段发展到今天的多制式、覆盖十几个甚至是几十个频段。为了实现不同频段和制式之间切换，射频开关电路的使用是必不可少的。同时，随着智能手机的轻薄化以及元器件的增加，留给天线的空间越来越少，这严重的影响了天线的效率。为此，人们通常引入调谐开关来改变天线的电学长度，以改善天线的性能。
图1是PIFA天线及其调谐线路示意图。其中深色部分为PIFA天线，其一端接地，中间有一个馈点，天线臂上接入了调谐器。调谐器通常是由一个单刀多掷开关和电容(或电感)构成。单刀多掷开关可以是和电容集成在一起，也可以是独立的。图2所示的矩形框中是一个SP4T(单刀4掷)开关，该开关的公共端接入到PIFA天线臂上，该开关的4个端口分别接到4个电容(电容C1～C4)上。在实际应用中，电容C1～C4可以被部分或全部电感取代。当SP4T开关的一路开启，其余的3路关断时，关断这几路上的开关要承受电压摆动，其峰值大小取决于调谐器接入到天线的位置。调谐器不同的位置，电压摆幅不同，最高可以到达80V甚至更高。
因此，单刀多掷开关承受的电压分配在每个开关单元上，当每个开关单元承受的电压接近其额定击穿电压时，单刀多掷开关产生的谐波会恶化。如果进一步增加电压，超过单刀多掷开关击穿电压，谐波会断崖式上升，严重影响天线调谐的性能。
图3是现有技术中，一个典型的开关结构示例图。它由三部分组成：一个或多个开关单元组成的串联结构100，栅极偏置电路101和体极(body)偏置电路102。当开关承受的电压摆幅增加时，每一个开关单元 承受的电压随之增加，导致谐波恶化。在一定范围内，这种情况可以通过增加开关单元的个数(叠管数)来改善。图4反映的是开关能够承受的电压和开关叠管数的关系。虚线和实线分别对应的开关能承受的电压理想值和实际值。在开关叠管数比较小的时候，开关能够承受的电压和叠管数成线性关系。这是因为这时开关上的电压分布比较均匀，简单地增加开关单元，就可以提高能承受的电压，此时两根曲线重合。随着叠管数的进一步增加，对衬底的寄生电容效应，以及栅极诱发的泄露电流等因素，导致开关承受电压偏离线性，并趋于饱和(参见图4中的实线部分)。
发明内容
针对现有技术的不足，本发明所要解决的首要技术问题在于提供一种射频开关电路。
本发明所要解决的另一技术问题在于提供一种集成电路芯片及通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种射频开关电路，包括第一端口和第二端口，在所述第一端口和所述第二端口之间至少有一个开关单元形成的开关链路，每个所述开关单元分别连接第一偏置电路和第二偏置电路，所述第一偏置电路和所述第二偏置电路的预设位置接入偏置电压。
其中较优地，当所述开关链路包括一个所述开关单元时，所述开关单元的输入端连接所述第一端口，所述开关单元的输出端连接所述第二端口
其中较优地，当所述开关链路包括两个或两个以上所述开关单元时，每个所述开关单元的输出端连接下一个所述开关单元的输入端，所述开关链路的第一个所述开关单元的输入端连接所述第一端口，所述开关链路的最后一个所述开关单元的输出端连接第二端口。
其中较优地，每个所述开关单元包括MOS晶体管，所述MOS晶体管的源极与漏极之间设置有第一电阻，所述MOS晶体管的栅极和体极分别对应连接相应的偏置电路。
其中较优地，所述第一偏置电路包括至少一个第一T型电阻网络， 每个所述第一T型电阻网络对应连接一个所述MOS晶体管的栅极，第一个所述第一T型电阻网络和最后一个所述第一T型电阻网络对应与所述第一端口和所述第二端口之间分别设置有第一电容。
其中较优地，每个所述第一T型电阻网络包括第二电阻，相邻两个所述第一T型电阻网络共用一个第三电阻，所述第三电阻的两端对应连接相邻两个所述第一T型电阻网络的所述第二电阻的一端，所述第二电阻的另一端连接相应的所述MOS晶体管的栅极，第一个所述第一T型电阻网络和最后一个所述第一T型电阻网络的第二电阻的一端分别再通过一个所述第三电阻连接相应的所述第一电容。
其中较优地，所述第二偏置电路包括至少一个第二T型电阻网络，每个所述第二T型电阻网络对应连接一个所述MOS晶体管的体极，第一个所述第二T型电阻网络和最后一个所述第二T型电阻网络对应与所述第一端口和所述第二端口之间分别设置有第二电容。
其中较优地，每个所述第二T型电阻网络包括第四电阻，相邻两个所述第二T型电阻网络共用一个第五电阻，所述第五电阻的两端对应连接相邻两个所述第二T型电阻网络的所述第四电阻的一端，所述第四电阻的另一端连接相应的所述MOS晶体管的体极，第一个所述第二T型电阻网络和最后一个所述第二T型电阻网络的第四电阻的一端分别再通过一个所述第五电阻连接相应的所述第二电容。
其中较优地，所述第一T型电阻网络与所述第二T型电阻网络中的电阻分别采用可变电阻阵列；所述第一电容和所述第二电容分别采用电容阵列。
其中较优地，当所述射频开关电路为双向时，所述第一端口和所述第二端口均作为射频信号的输入口。
其中较优地，当所述射频开关电路为单向时，所述第一端口和所述第二端口中的一个作为所述射频信号的输入口，另一个端口接地。
其中较优地，每个所述开关单元的MOS晶体管的源极和体极之间设置第三电容，调整所述MOS晶体管之间的寄生电容和所述第三电容的比值，改善所述射频开关电路截止时，在所述开关链路上电压分布的均匀性。
其中较优地，调整各所述开关单元的MOS晶体管的尺寸以及和所 述第三电容的比值，改善所述射频开关电路截止时，在所述开关链路上电压分布的均匀性；其中，所述MOS晶体管的尺寸是指所述MOS晶体管的栅极宽长比。
其中较优地，当所述射频开关电路为双向时，如果所述开关单元的个数是奇数，在连接正中间所述开关单元的所述第一T型电阻网络的两个所述第三电阻的中间点接入偏置电压，连接正中间所述开关单元的所述第二T型电阻网络的两个所述第五电阻的中间点接入偏置电压；
如果所述开关单元的个数是偶数，分别在处于正中间位置的所述第三电阻和所述第五电阻的中心点接入偏置电压。
其中较优地，当所述射频开关电路为单向时，分别从所述第一偏置电路、所述第二偏置电路靠近接地的一边接入偏置电压。
根据本发明实施例的第二方面，提供一种集成电路芯片，包括上述的射频开关电路。
根据本发明实施例的第三方面，提供一种通信终端，包括上述的射频开关电路。
本发明所提供的射频开关电路通过在第一端口和第二端口之间设置至少一个开关单元形成的开关链路，将每个开关单元分别连接第一偏置电路和第二偏置电路，并进一步调整各开关单元的MOS晶体管之间的寄生电容和第三电容的比值、各开关单元的MOS晶体管的尺寸以及和第三电容的比值，可以改善开关链路上电压分布的均匀性，提高射频开关电路的整体耐压能力，减小谐波的发生。
附图说明
图1为PIFA天线及其调谐线路的示意图；
图2为单刀4掷开关线路的示意图；
图3为现有技术中，开关结构的示例图；
图4为开关能够承受的电压和开关叠管数的关系示意图；
图5为本发明实施例1提供的射频开关电路的电路原理图；
图6为本发明实施例2提供的射频开关电路的电路原理图；
图7为本发明实施例3提供的射频开关电路的电路原理图；
图8为本发明实施例4提供的射频开关电路的电路原理图；
图9为本发明实施例5提供的射频开关电路的电路原理图；
图10为本发明实施例6提供的射频开关电路的电路原理图；
图11为本发明提供的射频开关电路中，每个开关单元上的电压摆幅和开关叠管序列的关系示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
实施例1
如图5所示，实施例1提供的射频开关电路包括第一端口1和第二端口2，在第一端口1和第二端口2之间至少有一个开关单元3参与形成的开关链路。每个开关单元3分别连接第一偏置电路4和第二偏置电路5，第一偏置电路4和第二偏置电路5的预设位置接入偏置电压。
当开关链路包括一个开关单元3时，开关单元的输入端作为开关链路的输入端，开关单元的输出端作为开关链路的输出端。开关单元3的输入端连接第一端口1，开关单元3的输出端连接第二端口2。第一端口1和第二端口2均作为射频信号的输入口，使得本射频开关电路是双向的，射频信号可以从任意一个端口输入。开关链路采用一个开关单元可以实现连接或关断开关链路两端的信号。
当开关链路包括两个或两个以上开关单元3时，每个开关单元3的输出端连接下一个开关单元的输入端；并且，开关链路的第一个开关单元3的输入端连接第一端口1，第一个开关单元3的输入端即为开关链路的输入端，开关链路的最后一个开关单元3的输出端连接第二端口2，最后一个开关单元3的输出端作为开关链路的输出端。同样该射频开关电路是双向的，射频信号可以从任意一个端口输入。开关链路采用两个或两个以上开关单元在保证连接或关断开关链路两端的信号的同时，还满足各方面的指标要求。
在本发明的实施例中，开关单元3可以采用MOS晶体管实现，具体可以是CMOS晶体管或SOI NMOS晶体管(硅基绝缘体MOS晶体管)。为了便于对本发明实施例的理解，下面主要以每个开关单元3分别采用SOI NMOS晶体管(简称为NMOS晶体管)为例进行详细说明，但相 应的技术方案也适用于CMOS晶体管等其它类型的MOS晶体管。
如图5所示，将NMOS晶体管的源极作为开关单元3的输入端，NMOS晶体管的漏极作为开关单元3的输出端；NMOS晶体管的源极与漏极之间设置有第一电阻Rds，用于为每个NMOS晶体管的漏极和源极建立偏置电压，使每个NMOS晶体管漏极和源极的直流电压相等。NMOS晶体管的栅极连接第一偏置电路4，NMOS晶体管的体极(body)连接第二偏置电路5，通过第一偏置电路4控制NMOS晶体管的栅极，减小在NMOS晶体管导通时射频信号在栅极上的损耗，并改善NMOS晶体管截止时开关链路上电压分布的均匀性，从而提高射频开关电路的抗压能力并改善谐波性能。
如图5所示，第一偏置电路4分别连接每个开关单元的NMOS晶体管的栅极，第二偏置电路5分别连接每个开关单元的NMOS晶体管的体极。其中，第一偏置电路4包括至少一个第一T型电阻网络40，每个第一T型电阻网络40对应连接一个开关单元3的NMOS晶体管的栅极；并且，与第一个开关单元3连接的第一T型电阻网络40和第一端口1之间设置有第一电容C1，与最后一个开关单元3连接的第一T型电阻网络40和第二端口2之间也设置有第一电容C1。
具体地说，如图5所示，每个第一T型电阻网络40包括第二电阻R1，相邻两个第一T型电阻网络40共用一个第三电阻R2，该第三电阻R2的两端对应连接相邻两个第一T型电阻网络40的第二电阻R1的一端，第二电阻R1的另一端连接相应的开关单元的NMOS晶体管的栅极。第一个第一T型电阻网络40和最后一个第一T型电阻网络40的第二电阻R1的一端分别再通过一个第三电阻R2连接相应的第一电容C1。其中，第一电容C1可以是MIM(metal-insulator-metal，金属-绝缘层-金属)电容，也可以是金属间形成的寄生电容。MIM电容的电容密度较寄生电容大一些，因此如果需要的电容值较大，可以使用MIM电容，占的面积小。如果需要的电容值较小，可以利用金属间形成的寄生电容，该寄生电容是靠不同层次金属连线间的交叠产生的，通常电容密度小一些。
当本射频开关电路导通时，通过第二电阻R1阻断射频信号在该方向的泄露，从而减小射频信号在栅极上的损耗。如图5所示，以开关 链路包括4个开关单元3，并且开关链路一端的电压设置为12V，另一端接地为例，当射频开关电路关断时，理想的情况下，12V电压均匀分配在4个开关单元3的NMOS晶体管上，每个NMOS晶体管分别为3V；但是，由于寄生电容的原因，导致各个开关单元3上的分压不再均匀，比如第一个开关单元3的NMOS晶体管承受的电压为4V,该电压值超过了在选择的工艺下，开关单元3的NMOS晶体管能承受的额定电压(比如3.5V)，那么就会造成射频开关电路的谐波急剧恶化。
在本射频开关电路中，由于采用了第一T型电阻网络40，使得泄露电流在该第一T型电阻网络40上产生的电压降对应在各个开关单元3的漏极和源极之间更均匀，因为第一T型电阻网络40也是级联的，各个第三电阻R2都是相等的。并且，本射频开关电路还通过第一电容C1进一步调整第一个NMOS晶体管产生的阻抗，也有助于改善开关链路上电压分布的非均匀性。因此，通过第一T型电阻网络40改善了开关链路上电压分布的均匀性，实现了提高射频开关电路抗压能力和优化谐波性能的目的。
如图5所示，由于每个开关单元3的NMOS管的栅极和体极(body)对应，为了保持本射频开关电路线路的对称性，需要在每个开关单元的体极设置与第一偏置电路4结构相同的第二偏置电路5。第二偏置电路5包括至少一个第二T型电阻网络50，每个第二T型电阻网络50对应连接一个开关单元3的NMOS晶体管的体极；并且，与第一个开关单元3连接的第二T型电阻网络50和第一端口1之间设置有第二电容C2，与最后一个开关单元3连接的第二T型电阻网络50和第二端口2之间也设置有第二电容C2。
具体地说，如图5所示，每个第二T型电阻网络50包括第四电阻R4，相邻两个第二T型电阻网络50共用一个第五电阻R3，该第五电阻R3的两端对应连接相邻两个第二T型电阻网络50的第四电阻R4的一端，第四电阻R4的另一端连接相应的开关单元3的NMOS晶体管的体极。第一个第二T型电阻网络50和最后一个第二T型电阻网络50的第四电阻R4的一端分别再通过一个第五电阻R3连接相应的第二电容C1。
需要强调的是，第一T型电阻网络40与第二T型电阻网络50中 的电阻(包括第二电阻R1、第三电阻R2、第四电阻R4和第五电阻R3)可以是可变电阻阵列；第一电容C1和第二电容C2可以是电容阵列。
此外，第一偏置电路4的预设位置接入偏置电压Vg，第二偏置电路5的预设位置接入偏置电压Vb,偏置电压Vg、Vb接入的方式可以依开关单元3的个数而定。并且，为了保持本射频开关电路线路的对称性，偏置电压Vg、Vb的接入方式和奇偶性有关。如果开关单元3的个数是奇数，那么偏置电压Vg接入到连接正中间开关单元3的第一T型电阻网络40的两个第三电阻R2的中间点，偏置电压Vb接入到连接正中间开关单元3的第二T型电阻网络50的两个第五电阻R3的中间点。如果开关单元3的个数是偶数，那么偏置电压Vg接入到处于正中间位置的第三电阻R2的中心点(如图5所示)，偏置电压Vb接入到处于正中间位置的第五电阻R3的中心点(如图5所示)。本领域的技术人员应该知道，偏置电压Vg、Vb的接入方式不是唯一的，可以在第一偏置电路4与第二偏置电路5的其他地方接入。
实施例2
如图6所示，以每个开关单元3分别采用NMOS晶体管为例。本实施例提供的射频开关电路在实施例1提供的射频开关电路的基础上，在每个开关单元3的NMOS晶体管的源极和体极之间设置第三电容Cx,该第三电容Cx作为开关单元3的补偿电容；或者，还可以将第三电容Cx分别设置在每个开关单元3的NMOS晶体管的源极和栅极之间。由于各开关单元的NMOS晶体管的尺寸可以是不一致的，并且各开关单元3的NMOS晶体管的尺寸越大，寄生电容也越大；因此，调整各开关单元3的NMOS晶体管之间的寄生电容和第三电容Cx的比值，进一步改善射频开关电路截止时在开关链路上电压分布的均匀性，从而提高射频开关电路的抗压能力并改善谐波性能。具体地说，在本射频开关电路设计过程中，首先选定各开关单元3的NMOS晶体管之间的寄生电容和第三电容Cx的初始比值，通过仿真计算出各个开关单元3的电压分布，并观察是否出现某个或几个开关单元3上的电压超过额定电压的现象。这是个迭代过程，直到选定到某一个比值，使得开关链路上电压分布最均匀。
实施例3
如图7所示，以每个开关单元3分别采用NMOS晶体管为例。本实施例提供的射频开关电路在实施例2提供的射频开关电路的基础上，进一步调整各个开关单元3的NMOS晶体管的栅极宽长比(W/L)。具体地说，每个开关单元3中的NMOS晶体管的耐压值和其栅极的长度有关，NMOS晶体管的栅极长度L越长，NMOS晶体管的耐压值越高，有利于射频开关电路截止时的抗压能力。但是，NMOS晶体管开启时其阻抗也变得越高，导致插损也越大。为了保持合理的插损值，可以通过增大射频开关电路的宽度W来保证。这时NMOS晶体管的栅极和源极的交叠电容增加，NMOS晶体管的漏极和源极上的多晶接触(poly contact)随着栅极长度L的增加而带来间距增加，从而导致NMOS晶体管的寄生电容减小。此外，通过调整各开关单元3的NMOS晶体管的尺寸以及和第三电容Cx的比值，从而改善射频开关电路截止时，在开关链路上电压分布的均匀性。其中，调整各开关单元3的NMOS晶体管的尺寸是指调整各开关单元3的NMOS晶体管的栅极宽长比(W/L)。具体地说，由于每个MOS晶体管的尺寸贡献了本射频开关电路整体寄生电容的一部分，整体寄生电容另一部分是金属连线贡献的。通过改变每个NMOS晶体管的尺寸以及和第三电容Cx的比值，可以改变各个NMOS晶体管产生的阻抗。各开关单元3经受的电压不均匀性是来自各个NMOS晶体管的阻抗和泄漏电流的乘积。因此，调整各开关单元3的NMOS晶体管的尺寸以及和第三电容Cx的比值，可以改善开关链路上电压分布的均匀性。
实施例4
如图8所示，本实施例中的射频开关电路与实施例1的射频开关电路的不同之处在于：第一端口1和第二端口2中的一个作为射频信号的输入口，另一个端口接地。该射频开关电路是单向的，射频信号只从一个端口输入，另一个端口始终接收不到射频信号。
当本射频开关电路导通时，通过第二电阻R1阻断射频信号在该方向的泄露，从而减小射频信号在栅极上的损耗。当射频开关电路关断时，由于采用了第一T型电阻网络40，使得泄露电流在该第一T型电阻网络40上产生的电压降对应在各个开关单元3的漏极和源极之间更加均匀。并且，本射频开关电路还通过第一电容C1进一步调整第一个NMOS晶体管遇到的阻抗，有助于改善开关链路上电压分布的非均匀性。 因此，通过第一T型电阻网络40改善了开关链路上电压分布的均匀性，实现了提高射频开关电路抗压能力和优化谐波性能的目的。
第一偏置电路4的预设位置接入偏置电压Vg，第二偏置电路5的预设位置接入偏置电压Vb,其中较优地，偏置电压Vg、Vb分别对应从第一偏置电路4、第二偏置电路5靠近接地的一边接入。
实施例5
如图9所示，以每个开关单元3分别采用NMOS晶体管为例。本实施例提供的射频开关电路在实施例4提供的射频开关电路的基础上，在每个开关单元3的NMOS晶体管的源极和体极之间设置第三电容Cx,该第三电容Cx作为开关单元3的补偿电容；或者，还可以将第三电容Cx分别设置在每个开关单元3的NMOS晶体管的源极和栅极之间。由于各开关单元的NMOS晶体管的尺寸可以是不一致的，并且各开关单元3的NMOS晶体管的尺寸越大，寄生电容也越大；因此，调整各开关单元3的NMOS晶体管之间的寄生电容和第三电容Cx的比值，进一步改善射频开关电路截止时，在开关链路上电压分布的均匀性，从而实现提高射频开关电路抗压能力和改善谐波性能的目的。
实施例6
如图10所示，以每个开关单元3分别采用NMOS晶体管为例。本实施例提供的射频开关电路在实施例5提供的射频开关电路的基础上，进一步调整各个开关单元3的NMOS晶体管的栅极宽长比(W/L)。具体地说，每个开关单元3中的NMOS晶体管的耐压值和其栅极的长度有关，NMOS晶体管的栅极长度L越长，NMOS晶体管的耐压值越高，有利于射频开关电路截止时的抗压能力。但是，NMOS晶体管开启时其阻抗也变得越高，导致插损也越大。为了保持合理的插损值，可以通过增大射频开关电路的宽度W来保证。这时NMOS晶体管的栅极和源极的交叠电容增加，NMOS晶体管的漏极和源极上的多晶接触(poly contact)随着栅极长度L的增加而带来间距增加，从而导致NMOS晶体管的寄生电容减小。此外，通过调整各开关单元3的NMOS晶体管的尺寸以及和第三电容Cx的比值，从而改善射频开关电路截止时，在开关链路上电压分布的均匀性。其中，调整各开关单元3的NMOS晶体管的尺寸是指调整各开关单元3的NMOS晶体管的栅极宽长比(W/L)。
如图11所示，该图反映的是每个开关单元上的电压摆幅和开关叠管序列的关系。其中的1、2、3、4分别是指从开关链路的输入端算起的第1、2、3、4个开关单元。这里没有列出开关单元的总数，本领域技术人员应该知道，具体需要多少开关单元是和射频开关电路设计指标，工艺等因素有关。当使用在先技术设计的射频开关电路时，靠近开关链路输入端的开关单元承受的电压摆幅比较大(例如图11中的第1个和第2个开关单元)，在某些应用场景下，靠近开关链路输入端的开关单元承受的电压摆幅接近、达到、甚至超过开关单元能承受的额定电压(图11中的水平线)。在这种情形下，射频开关电路的谐波会迅速恶化，甚至出现不可恢复性的损伤。而本发明实施例提供的射频开关电路可以降低那些容易受损开关单元承受的最大电压(图11中的虚线所示)，改善开关链路上电压分布的均匀性，提高射频开关电路的整体耐压能力，减小谐波的发生。
与现有技术相比较，本发明提供的射频开关电路通过在第一端口和第二端口之间设置至少一个开关单元形成的开关链路，将每个开关单元分别连接第一偏置电路和第二偏置电路，并进一步调整各开关单元的MOS晶体管之间的寄生电容和第三电容的比值、各开关单元的MOS晶体管的尺寸以及和第三电容的比值，可以改善开关链路上电压分布的均匀性，提高射频开关电路的整体耐压能力，减小谐波的发生。
本发明提供的射频开关电路可以被用在集成电路芯片中。对于该集成电路芯片中的射频开关电路的具体结构，在此就不再详述了。
另外，上述射频开关电路还可以被用在通信终端中，作为射频电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他射频电路应用的场合，例如通信基站等。
以上对本发明所提供的射频开关电路、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (17)

  1. 一种射频开关电路，其特征在于包括第一端口和第二端口，在所述第一端口和所述第二端口之间至少有一个开关单元形成的开关链路，每个所述开关单元分别连接第一偏置电路和第二偏置电路，所述第一偏置电路和所述第二偏置电路的预设位置接入偏置电压。
  2. 如权利要求1所述的射频开关电路，其特征在于：
    当所述开关链路包括一个所述开关单元时，所述开关单元的输入端连接所述第一端口，所述开关单元的输出端连接所述第二端口。
  3. 如权利要求1所述的射频开关电路，其特征在于：
    当所述开关链路包括两个或两个以上所述开关单元时，每个所述开关单元的输出端连接下一个所述开关单元的输入端，所述开关链路的第一个所述开关单元的输入端连接所述第一端口，所述开关链路的最后一个所述开关单元的输出端连接第二端口。
  4. 如权利要求1所述的射频开关电路，其特征在于：
    每个所述开关单元包括MOS晶体管，所述MOS晶体管的源极与漏极之间设置有第一电阻，所述MOS晶体管的栅极和体极分别对应连接相应的偏置电路。
  5. 如权利要求4所述的射频开关电路，其特征在于：
    所述第一偏置电路包括至少一个第一T型电阻网络，每个所述第一T型电阻网络对应连接一个所述MOS晶体管的栅极，第一个所述第一T型电阻网络和最后一个所述第一T型电阻网络对应与所述第一端口和所述第二端口之间分别设置有第一电容。
  6. 如权利要求5所述的射频开关电路，其特征在于：
    每个所述第一T型电阻网络包括第二电阻，相邻两个所述第一T型电阻网络共用一个第三电阻，所述第三电阻的两端对应连接相邻两个所述第一T型电阻网络的所述第二电阻的一端，所述第二电阻的另一端连接相应的所述MOS晶体管的栅极，第一个所述第一T型电阻网络和最后一个所述第一T型电阻网络的第二电阻的一端分别再通过一个所述第三电阻连接相应的所述第一电容。
  7. 如权利要求6所述的射频开关电路，其特征在于：
    所述第二偏置电路包括至少一个第二T型电阻网络，每个所述第二T型电阻网络对应连接一个所述MOS晶体管的体极，第一个所述第二T型电阻网络和最后一个所述第二T型电阻网络对应与所述第一端口和所述第二端口之间分别设置有第二电容。
  8. 如权利要求7所述的射频开关电路，其特征在于：
    每个所述第二T型电阻网络包括第四电阻，相邻两个所述第二T型电阻网络共用一个第五电阻，所述第五电阻的两端对应连接相邻两个所述第二T型电阻网络的所述第四电阻的一端，所述第四电阻的另一端连接相应的所述MOS晶体管的体极，第一个所述第二T型电阻网络和最后一个所述第二T型电阻网络的第四电阻的一端分别再通过一个所述第五电阻连接相应的所述第二电容。
  9. 如权利要求8所述的射频开关电路，其特征在于：
    所述第一T型电阻网络与所述第二T型电阻网络中的电阻分别采用可变电阻阵列；所述第一电容和所述第二电容分别采用电容阵列。
  10. 如权利要求4所述的射频开关电路，其特征在于：
    当所述射频开关电路为双向时，所述第一端口和所述第二端口均作为射频信号的输入口。
  11. 如权利要求4所述的射频开关电路，其特征在于：
    当所述射频开关电路为单向时，所述第一端口和所述第二端口中的一个作为所述射频信号的输入口，另一个端口接地。
  12. 如权利要求10或11所述的射频开关电路，其特征在于：
    每个所述开关单元的MOS晶体管的源极和体极之间设置第三电容，调整所述MOS晶体管之间的寄生电容和所述第三电容的比值，改善所述射频开关电路截止时，在所述开关链路上电压分布的均匀性。
  13. 如权利要求12所述的射频开关电路，其特征在于：
    调整各所述开关单元的MOS晶体管的尺寸以及和所述第三电容的比值，改善所述射频开关电路截止时，在所述开关链路上电压分布的均匀性；其中，所述MOS晶体管的尺寸是指所述MOS晶体管的栅极宽长比。
  14. 如权利要求8所述的射频开关电路，其特征在于：
    当所述射频开关电路为双向时，如果所述开关单元的个数是奇数， 在连接正中间所述开关单元的所述第一T型电阻网络的两个所述第三电阻的中间点接入偏置电压，连接正中间所述开关单元的所述第二T型电阻网络的两个所述第五电阻的中间点接入偏置电压；
    如果所述开关单元的个数是偶数，分别在处于正中间位置的所述第三电阻和所述第五电阻的中心点接入偏置电压。
  15. 如权利要求11所述的射频开关电路，其特征在于：
    当所述射频开关电路为单向时，分别从所述第一偏置电路、所述第二偏置电路靠近接地的一边接入偏置电压。
  16. 一种集成电路芯片，其特征在于包括权利要求1～15中任意一项所述的射频开关电路。
  17. 一种通信终端，其特征在于包括权利要求1～15中任意一项所述的射频开关电路。
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