WO2020125189A1 - 实现数据同步的装置和方法 - Google Patents

实现数据同步的装置和方法 Download PDF

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Publication number
WO2020125189A1
WO2020125189A1 PCT/CN2019/112558 CN2019112558W WO2020125189A1 WO 2020125189 A1 WO2020125189 A1 WO 2020125189A1 CN 2019112558 W CN2019112558 W CN 2019112558W WO 2020125189 A1 WO2020125189 A1 WO 2020125189A1
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synchronization
data
clock signal
signal
frequency
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PCT/CN2019/112558
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English (en)
French (fr)
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李鹏
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深圳市中兴微电子技术有限公司
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Priority to US17/416,260 priority Critical patent/US11502814B2/en
Publication of WO2020125189A1 publication Critical patent/WO2020125189A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present disclosure relates to data synchronization technology, and in particular, to an apparatus and method for data synchronization.
  • the delay difference between each channel is required to be ⁇ 20ns, to ensure that each channel receives and outputs data synchronously while meeting the setup and hold time.
  • the embodiments of the present disclosure provide an apparatus and method for realizing data synchronization, which can meet the requirements of data synchronization input and output and ensure the consistent data transmission speed.
  • an apparatus for implementing data synchronization including:
  • the synchronization circuit between multiple radio frequency chips is used to synchronize the working clock among multiple radio frequency chips
  • the multi-channel synchronization circuit in the single chip is used to realize data synchronization of multiple channels in the single chip.
  • the multi-RF chip synchronization circuit includes:
  • a phase-locked loop circuit for receiving a reference clock signal, and a high-frequency signal whose output frequency is n times the frequency of the reference clock signal, where n is greater than or equal to 2;
  • the frequency divider circuit is used to divide the high frequency signal output by the phase locked loop circuit to obtain the working clock signal of the frequency required by the chip;
  • the phase difference calculation circuit is used to compare the delay difference between the reference clock signal and the working clock signal
  • the phase synchronization control circuit is used to compare the delay difference with a preset delay threshold, and if the delay difference is greater than the preset delay threshold, control the phase-locked loop circuit to adjust the phase of the output high-frequency signal.
  • the phase difference calculation circuit used to compare the delay difference between the reference clock signal and the working clock signal, includes:
  • the multi-channel synchronization circuit in the single chip is set for each channel:
  • the first synchronization unit is used to keep the data extracted by multiple channels consistent through the first synchronization signal
  • the second synchronization unit is used to enable each channel to read data simultaneously when data is transferred from the first synchronization unit to the second synchronization unit;
  • the third synchronization unit is used to enable each channel to read data simultaneously when data is transferred from the second synchronization unit to the third synchronization unit.
  • the second synchronization unit and the third synchronization unit are used to enable each channel to read data simultaneously, including:
  • a method for implementing data synchronization including:
  • the implementation of working clock synchronization among multiple radio frequency chips includes:
  • the comparing the delay difference between the reference clock signal and the working clock signal includes:
  • the clock period of the high-frequency signal obtains the delay difference between the reference clock signal and the working clock signal.
  • the data synchronization of multiple channels in a single chip includes:
  • each channel is simultaneously read the data.
  • causing each channel to simultaneously read the data includes:
  • the device for realizing data synchronization in the embodiments of the present disclosure includes a multi-radio inter-chip synchronization circuit, and/or a single-channel multi-channel synchronization circuit; wherein, the multi-radio inter-chip synchronization circuit is used to implement Working clock synchronization among multiple radio frequency chips; the multi-channel synchronization circuit in the single chip is used to realize data synchronization of multiple channels in the single chip.
  • the embodiments of the present disclosure can meet the requirements of data synchronization input and output, and ensure consistent data transmission speed.
  • FIG. 1 is a block diagram of a device for implementing data synchronization provided by an embodiment of the present disclosure
  • FIG. 2 is a block diagram of each channel in a multi-channel synchronization circuit in a single chip provided by an embodiment of the present disclosure
  • FIG. 3 is a block diagram of multiple RF chip synchronization circuits shown in an application example of the present disclosure
  • FIG. 4 is a block diagram of a multi-channel synchronous circuit in a single chip shown in an application example of the present disclosure
  • FIG. 5 is a flowchart of a method for synchronizing multiple radio frequency chips shown in an application example of the present disclosure
  • FIG. 6 is a flowchart of a single-chip multi-channel synchronization method shown in an application example of the present disclosure.
  • An embodiment of the present disclosure provides an apparatus for implementing data synchronization. As shown in FIG. 1, the apparatus includes:
  • the multi-radio chip synchronization circuit is used to synchronize working clocks among multiple radio frequency chips;
  • the single-chip multi-channel synchronization circuit is used to realize data synchronization of multiple channels in a single chip.
  • the clock phase difference between multiple radio frequency chips can be caused by four parts, one is that the clock chip has different paths to different radio frequency chips; the second is that the clock signals in the radio frequency chip have different paths to their respective phase-locked loops; three The delay of the frequency divider that generates the frequency-divided clock by the phase-locked loop is different; fourth, the path of the clock signal in the transmission data link is different.
  • These problems that cause the clock phase to be out of synchronization can be solved by the design of printed circuit board (Printed Circuit Board) and system calibration.
  • the synchronization between multiple radio frequency chips provided by the embodiments of the present disclosure
  • the circuit is mainly used to solve the problem of clock phase out-of-synchronization caused by a phase-locked loop in the chip.
  • the multi-RF inter-chip synchronization circuit may include:
  • a phase-locked loop circuit is used to receive a reference clock signal, and a high-frequency signal whose output frequency is n times the frequency of the reference clock signal, n is greater than or equal to 2; a frequency divider circuit is used to control the output of the phase-locked loop circuit. Frequency signal is divided to obtain the working clock signal of the required frequency of the chip; the phase difference calculation circuit is used to compare the delay difference between the reference clock signal and the working clock signal; the phase synchronization control circuit is used to divide the delay The difference is compared with a preset delay threshold, and if the delay difference is greater than the preset delay threshold, the phase-locked loop circuit is controlled to adjust the phase of the output high-frequency signal.
  • the above phase difference calculation circuit for comparing the delay difference between the reference clock signal and the working clock signal may include:
  • the synchronization circuit between multiple radio frequency chips achieves the purpose of synchronizing the clock phases of multiple radio frequency chips by synchronizing the output clock signals of the phase locked loop circuits of multiple radio frequency chips with the reference clock signal.
  • the multi-channel synchronization circuit in the single chip is set for each channel:
  • the first synchronization unit is used to keep the data extracted from multiple channels consistent through the first synchronization signal;
  • the first synchronization signal may be a system synchronization signal sys_ref, which is a system synchronization signal that simultaneously reaches multiple channels in a single chip Pulse signal;
  • the second synchronization unit is used to enable each channel to read data simultaneously when data is transferred from the first synchronization unit to the second synchronization unit;
  • the third synchronization unit is used to enable each channel to read data simultaneously when data is transferred from the second synchronization unit to the third synchronization unit.
  • the second synchronization unit and the third synchronization unit are used to enable each channel to read data at the same time, including:
  • the first synchronization signal and the second synchronization signal may be the same.
  • the first synchronization unit may be an ADC clock domain
  • the second synchronization unit may be a calibration clock domain
  • the third synchronization unit may be a 204B clock domain.
  • the multi-channel synchronization circuit in the single chip can make each channel tap into the data at the same time and tap out the data at the same time.
  • FIG. 3 is a block diagram of multiple RF chip synchronization circuits shown in an application example of the present disclosure.
  • the multi-RF chip synchronization circuit includes:
  • Phase-locked loop circuit including: frequency and phase discriminator, charge pump, low-pass filter, voltage-controlled oscillator VCO, delay control circuit and N divider; the phase-locked loop circuit is used to receive the reference clock signal, and The output frequency is a high-frequency signal n times the frequency of the reference clock signal, where n is greater than or equal to 2; where,
  • the frequency discriminator is used to discriminate the phase difference between the reference clock signal and the feedback clock signal. If the reference clock signal leads the phase, a positive pulse signal is output; if the feedback clock signal leads the phase, a negative pulse signal is output;
  • the charge pump is used to control the two current mirrors in the charge pump to charge and discharge a capacitor according to the positive pulse signal and the negative pulse signal: where the positive pulse signal charges the capacitor to increase the voltage; the negative pulse signal discharges the capacitor to cause the voltage reduce;
  • the low-pass filter is used to retain a low-frequency voltage signal representing phase difference information and filter out high-frequency noise
  • VCO used to control the output clock frequency to increase or decrease according to the low-frequency voltage signal representing the phase difference information
  • the N divider is used to generate a feedback clock signal whose frequency is N times the reference clock frequency.
  • the phase-locked loop circuit gradually makes the reference clock signal and the feedback clock signal completely in the same frequency and in phase.
  • the LO frequency divider circuit is used to divide the high frequency signal output by the phase-locked loop circuit to obtain the working clock signal of the frequency required by the chip;
  • a phase difference calculation circuit (that is, a phase discriminator in FIG. 3) is used to compare the delay difference between the reference clock signal and the working clock signal;
  • the phase synchronization control circuit is used to compare the delay difference with a preset delay threshold, and if the delay difference is greater than the preset delay threshold, send a control signal to the delay control module of the phase-locked loop circuit; if the delay difference is less than or equal to The preset delay threshold may not be processed;
  • the delay control circuit is used to receive the control of the phase synchronization control circuit to increase or decrease the phase of the VCO output signal.
  • the delay difference is greater than 180°, increase the phase of the VCO output signal; when the delay When the difference is less than 180° and greater than the preset delay threshold, the phase of the VCO output signal is reduced.
  • each channel mainly includes:
  • the ADC clock domain is used to keep the data extracted from multiple channels consistent through the first synchronization signal;
  • the ADC clock domain includes: a half-band filter and a FIR filter;
  • the half-band filter is used to perform data Synchronization processing is performed during extraction, for example, when the data transmitted in the four channels is abababab, when the half-band filter is used for double extraction, the first synchronization signal makes the data acquired by each channel are aaaa or bbbb ;
  • FIR filter used to filter the data after synchronous processing;
  • the calibration clock domain is used to enable each channel to read data simultaneously when data is transferred from the first synchronization unit to the second synchronization unit;
  • the calibration clock domain includes: QEC calibration, HD2 calibration, DIG gain;
  • the QEC calibration is Refers to IQ imbalance calibration. Due to the difference in gain, phase and flatness between the two IQ signals, the two IQ channels need to be compensated to reduce distortion;
  • the HD2 calibration is used to eliminate the harmonic components of the received signal;
  • the DIG gain refers to the digital gain control module, the control signal gain tends to be stable;
  • the 204B clock domain is used to enable each channel to read data simultaneously when data is transferred from the second synchronization unit to the third synchronization unit;
  • a dual-port RAM that is, a cross-clock domain module in FIG. 3
  • the dual ports are used for different clock domains.
  • the frequency of different clock signals is processed across clock domains; and the function of cross clock domains is completed by using RAM, so that the data between the channels is synchronized at this location.
  • An embodiment of the present disclosure also provides a method for synchronizing data.
  • the method includes:
  • the implementation of working clock synchronization among multiple radio frequency chips includes:
  • the comparing the delay difference between the reference clock signal and the working clock signal includes:
  • the clock period of the high-frequency signal obtains the delay difference between the reference clock signal and the working clock signal.
  • the synchronization method between multiple radio frequency chips achieves the purpose of synchronizing the clock phases of multiple radio frequency chips by synchronizing the output clock signals of the phase locked loop circuits of multiple radio frequency chips with the reference clock signal.
  • the data synchronization of multiple channels in a single chip includes:
  • each channel is simultaneously read the data.
  • causing each channel to read the data at the same time includes: writing the data into the dual-port random access memory RAM, and using the second synchronization signal to make each channel at the same time Read the data in the RAM.
  • the single-chip multi-channel synchronization method provided by the embodiments of the present disclosure can achieve that each channel taps incoming data at the same time and taps out data at the same time.
  • FIG. 5 is a flowchart of a method for synchronizing multiple radio frequency chips shown in an application example of the present disclosure. As shown in the figure, the method includes:
  • FIG. 6 is a working flowchart of a multi-channel synchronization circuit in a single chip shown in an application example of the present disclosure. As shown in the figure, the process includes:
  • the half-band filter in the ADC clock domain After receiving the synchronization calibration command in the ADC clock domain, the half-band filter in the ADC clock domain starts data extraction, the FIR filter performs filtering, and writes the data to the dual-port RAM;
  • the data in the dual-port RAM is synchronously read, and the distortion calibration is performed on the data link. After calibration, the data is synchronously written into the dual-port RAM;
  • the 204B clock domain After receiving the synchronous calibration instruction, the 204B clock domain reads the data in the dual-port RAM synchronously.
  • the term computer storage medium includes both volatile and nonvolatile implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules, or other data Sex, removable and non-removable media.
  • Computer storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and accessible by a computer.
  • the communication medium generally contains computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium .

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Abstract

一种实现数据同步的装置和方法，其中，所述装置包括：多射频芯片间同步电路，和／或，单芯片内多通道同步电路；其中，所述多射频芯片间同步电路，用于实现多个射频芯片间的工作时钟同步；所述单芯片内多通道同步电路，用于实现单芯片内多个通道的数据同步。该装置能够满足数据同步输入输出的要求，保证数据传递速度一致。

Description

实现数据同步的装置和方法 技术领域
本公开涉及数据同步技术，尤其涉及一种实现数据同步的装置和方法。
背景技术
在5G大规模多输入多输出(massive MIMO)天线的应用场景下，要求在使用多个射频芯片的系统中对各射频芯片做同步处理，保证芯片同时接收和输出射频信号；并且在同一射频芯片的多通道间也需要做同步处理，5G制式下要求各通道之间的延迟差<20ns，保证各通道在满足建立保持时间的情况下同步接收和输出数据。
公开内容
为了解决上述技术问题，本公开实施例提供了一种实现数据同步的装置和方法，能够满足数据同步输入输出的要求，保证数据传递速度一致。
根据本公开实施例的一个方面，提供了一种实现数据同步的装置，包括：
多射频芯片间同步电路，和/或，单芯片内多通道同步电路；
其中，所述多射频芯片间同步电路，用于实现多个射频芯片间的工作时钟同步；
所述单芯片内多通道同步电路，用于实现单芯片内多个通道的数据同步。
作为一种实现方式，所述多射频芯片间同步电路，包括：
锁相环电路，用于接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
分频器电路，用于对锁相环电路输出的高频信号分频，得到芯片所需频率的工作时钟信号；
相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差；
相位同步控制电路，用于将所述延迟差与预设延迟阈值比较，若延迟差大于所述预设延迟阈值，控制锁相环电路调整输出的高频信号相位。
作为一种实现方式，所述相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差，包括：
采用所述锁相环电路输出的高频信号采样所述参考时钟信号和所述工作时钟信号的相位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
作为一种实现方式，所述单芯片内多通道同步电路针对每个通道设置：
第一同步单元，用于通过第一同步信号使多个通道抽取的数据保持一致；
第二同步单元，用于在数据从第一同步单元传输到第二同步单元时，使各通道同时读取数据；
第三同步单元，用于在数据从第二同步单元传输到第三同步单元时，使各通道同时读取数据。
作为一种实现方式，所述第二同步单元、所述第三同步单元，用于使各通道同时读取数据，包括：
将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据。
根据本公开实施例的另一个方面，还提供了一种实现数据同步的方法，包括：
实现多个射频芯片间的工作时钟同步；和/或
实现单芯片内多个通道的数据同步。
作为一种实现方式，所述实现多个射频芯片间的工作时钟同步，包括：
接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
对所述高频信号分频，得到芯片所需频率的工作时钟信号；
比较所述参考时钟信号和所述工作时钟信号的延时差，若延迟差大于所述预设延迟阈值，调整输出的高频信号相位。
作为一种实现方式，所述比较所述参考时钟信号和所述工作时钟信号的延时差，包括：
采用所述高频信号采样所述参考时钟信号和所述工作时钟信号的相位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
作为一种实现方式，所述实现单芯片内多个通道的数据同步，包括：
通过第一同步信号使多个通道抽取的数据保持一致；
在所述抽取的数据传输过程中，使各通道同时读取所述数据。
作为一种实现方式，在所述抽取的数据传输过程中，使各通道同时读取所述数据，包括：
将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据。
与相关技术相比，本公开实施例的实现数据同步的装置包括多射频芯片间同步电路，和/或，单芯片内多通道同步电路；其中，所述多射频芯片间同步电路，用于实现多个射频芯片间的工作时钟同步；所述单芯片内多通道同步电路，用于实现单芯片内多个通道的数据同步。本公开实施例能够满足数据同步输入输出的要求，保证数据传递速度一致。
本公开实施例的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开实施例而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特 别指出的结构来实现和获得。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的实现数据同步的装置组成模块图；
图2为本公开实施例提供的单芯片内多通道同步电路中每个通道的组成模块图；
图3为本公开应用示例所示的多射频芯片间同步电路组成模块图；
图4为本公开应用示例所示的单芯片内多通道同步电路组成模块图；
图5为本公开应用示例所示的多射频芯片间同步方法流程图；
图6为本公开应用示例所示的单芯片内多通道同步方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
本公开实施例提供了一种实现数据同步的装置，如图1所示，所述装置包括：
多射频芯片间同步电路，和/或，单芯片内多通道同步电路；
其中，所述多射频芯片间同步电路，用于实现多个射频芯片间的工作时钟同步；所述单芯片内多通道同步电路，用于实现单芯片内多个通道的数据同步。
考虑到多个射频芯片之间的时钟相位差异可以由四部分造成，一是时钟芯片到不同射频芯片有不同的路径；二是射频芯片中时钟信号到各自的锁相环有不同的路径；三是锁相环生成分频时钟的分频器延时不同；四是时钟信号在传输数据链路中的路径不同。这些造成时钟相位不同步的问题可以通过印制电路板(Printed Circuit Board，PCB)的设计和系统校准来解决，但出于对系统资源的考虑，本公开实施例提供的多射频芯片间的同步电路主要用于解决芯片内由锁相环造成的时钟相位不同步的问题，作为一种实现方式，所述多射频芯片间同步电路，可以包括：
锁相环电路，用于接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；分频器电路，用于对锁相环电路输出的高频信号分频，得到芯片所需频率的工作时钟信号；相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差；相位同步控制电路，用于将所述延迟差与预设延迟阈值比较，若延迟差大于所述预设延迟阈值，控制锁相环电路调整输出的高频信号相位。
作为一种实现方式，上述相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差，可以包括：
采用所述锁相环电路输出的高频信号采样所述参考时钟信号和所述工作时钟信号的相位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
本公开实施例提供的多射频芯片间同步电路通过将多个射频芯片的锁相环电路的输出时钟信号与参考时钟信号同步，实现了同步多个射频芯片的时钟相位的目的。
作为一种实现方式，如图2所示，所述单芯片内多通道同步电路针对每个通道设置：
第一同步单元，用于通过第一同步信号使从多个通道抽取的数据保持一致；所述第一同步信号可以为系统同步信号sys_ref，该系统同步信号是 一个同时达到单芯片内多通道的脉冲信号；
第二同步单元，用于在数据从第一同步单元传输到第二同步单元时，使各通道同时读取数据；
第三同步单元，用于在数据从第二同步单元传输到第三同步单元时，使各通道同时读取数据。
其中，所述第二同步单元、所述第三同步单元，用于使各通道同时读取数据，包括：
将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据，所述第一同步信号、第二同步信号可以相同。
上述第一同步单元可以为ADC时钟域，所述第二同步单元可以为校准时钟域，所述第三同步单元可以为204B时钟域。
上述单芯片内多通道同步电路可以做到使各通道在同一时刻打拍流入数据，在同一时刻打拍流出数据。
下面以具体的应用示例对上述实施例提到的多射频芯片间同步电路、单芯片内多通道同步电路进行说明。
图3为本公开应用示例所示的多射频芯片间同步电路组成模块图。
如图3所示，所述多射频芯片间同步电路包括：
锁相环电路，包括：鉴频鉴相器，电荷泵、低通滤波器、压控振荡器VCO，延时控制电路以及N分频器；该锁相环电路用于接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；其中，
所述鉴频鉴相器，用于鉴别参考时钟信号和反馈时钟信号之间的相位差，如果参考时钟信号相位超前，输出一个正脉冲信号；如果反馈时钟信号相位超前，输出一个负脉冲信号；
电荷泵，用于根据正脉冲信号和负脉冲信号分别控制电荷泵中的两个 电流镜对一个电容充放电：其中，正脉冲信号对电容充电使电压升高；负脉冲信号对电容放电使电压降低；
所述低通滤波器，用于保留代表相位差信息的低频电压信号，过滤掉高频噪声；
VCO，用于根据代表相位差信息的低频电压信号控制输出时钟频率变大或变小；
N分频器，用于产生一个频率是参考时钟频率N倍的反馈时钟信号。
所述锁相环电路通过这样的一个反馈过程，逐渐使参考时钟信号和反馈时钟信号完全同频同相。
本振LO分频器电路，用于对锁相环电路输出的高频信号分频，得到芯片所需频率的工作时钟信号；
相位差计算电路(即图3中的鉴相器)，用于比较所述参考时钟信号和所述工作时钟信号的延时差；
相位同步控制电路，用于将所述延迟差与预设延迟阈值比较，若延迟差大于所述预设延迟阈值，向锁相环电路的延时控制模块发出控制信号；若延迟差小于或等于所述预设延迟阈值，可不做处理；
延时控制电路，用于接收相位同步控制电路的控制，增大或减小VCO输出信号的相位，作为一种实现方式，当延迟差大于180°时，增大VCO输出信号的相位；当延迟差小于180°且大于所述预设延迟阈值时，减小VCO输出信号的相位。
图4为本公开应用示例所示的单芯片内多通道同步电路组成模块图，如图所示，每个通道主要包括：
ADC时钟域，用于通过第一同步信号使从多个通道抽取的数据保持一致；所述ADC时钟域包括：半带滤波器、FIR滤波器；所述半带滤波器，用于对数据进行抽取时进行同步处理，例如当四个通道中传输的数据是abababab时，在用半带滤波器做二倍抽取时，通过所述第一同步信号使 得每个通道获取的数据都是aaaa或bbbb；FIR滤波器，用于对进行同步处理后的数据滤波；
校准时钟域，用于在数据从第一同步单元传输到第二同步单元时，使各通道同时读取数据；所述校准时钟域包括：QEC校准、HD2校准、DIG增益；所述QEC校准是指IQ不平衡校准，由于IQ两路信号之间存在增益、相位以及平坦度方面的差异，需要对IQ两路进行补偿，降低失真；所述HD2校准用以消除接收信号的谐波分量；所述DIG增益是指数字增益控制模块，控制信号增益趋于稳定；
204B时钟域,用于在数据从第二同步单元传输到第三同步单元时，使各通道同时读取数据；
上述ADC时钟域和校准时钟域之间、校准时钟域和204B时钟域之间使用双端口RAM(即图3中的跨时钟域模块)传递数据，所述双端口用于对不同时钟域使用的不同时钟信号的频率做跨时钟域处理；以及通过使用RAM完成跨时钟域功能，从而使各通道间在此位置处数据同步。
本公开实施例还提供了一种实现数据同步的方法，所述方法包括：
实现多个射频芯片间的工作时钟同步；和/或，实现单芯片内多个通道的数据同步。
作为一种实现方式，所述实现多个射频芯片间的工作时钟同步，包括：
接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
对所述高频信号分频，得到芯片所需频率的工作时钟信号；
比较所述参考时钟信号和所述工作时钟信号的延时差，若延迟差大于所述预设延迟阈值，调整输出的高频信号相位。
作为一种实现方式，所述比较所述参考时钟信号和所述工作时钟信号的延时差，包括：
采用所述高频信号采样所述参考时钟信号和所述工作时钟信号的相 位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
本公开实施例提供的多射频芯片间同步方法通过将多个射频芯片的锁相环电路的输出时钟信号与参考时钟信号同步，实现了同步多个射频芯片的时钟相位的目的。
作为一种实现方式，所述实现单芯片内多个通道的数据同步，包括：
通过第一同步信号使多个通道抽取的数据保持一致；
在所述抽取的数据传输过程中，使各通道同时读取所述数据。
作为一种实现方式，在所述抽取的数据传输过程中，使各通道同时读取所述数据，包括：将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据。
本公开实施例提供的单芯片内多通道同步方法可以做到使各通道在同一时刻打拍流入数据，在同一时刻打拍流出数据。
下面以具体的应用示例对上述实施例提到的多射频芯片间同步方法、单芯片内多通道同步方法进行说明。
图5为本公开应用示例所示的多射频芯片间同步方法流程图，如图所示，所述方法包括：
接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
对所述高频信号分频，得到芯片所需频率的工作时钟信号；
判断是否收到同步校准指令，如果接收到，对射频芯片所需频率的工作时钟即分频时钟，和参考时钟的相位差高频采样，判断所得的延迟差是否最小；如果最小，根据所述延时差进行同步控制：当延时差大于预设阈值时，增大或减小分频时钟的延时；当延时差小于或等于预设阈值时，不做处理，本次校准过程结束。
图6为本公开应用示例所示的单芯片内多通道同步电路工作流程图，如图所示，所述流程包括：
ADC时钟域接收到同步校准指令后，由ADC时钟域中的半带滤波器开始数据抽取，FIR滤波器进行滤波，将数据写入双端口RAM；
反馈时钟域接收到同步校准指令后，同步读取双端口RAM中的数据，对数据链路进行失真校准，校准后数据同步写入双端口RAM；
204B时钟域接收到同步校准指令后，同步读取双端口RAM中的数据。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (10)

  1. 一种实现数据同步的装置，包括：
    多射频芯片间同步电路，和/或，单芯片内多通道同步电路；
    其中，所述多射频芯片间同步电路，用于实现多个射频芯片间的工作时钟同步；
    所述单芯片内多通道同步电路，用于实现单芯片内多个通道的数据同步。
  2. 根据权利要求1所述的实现数据同步的装置，其中，所述多射频芯片间同步电路，包括：
    锁相环电路，用于接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
    分频器电路，用于对锁相环电路输出的高频信号分频，得到芯片所需频率的工作时钟信号；
    相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差；
    相位同步控制电路，用于将所述延迟差与预设延迟阈值比较，若延迟差大于所述预设延迟阈值，控制锁相环电路调整输出的高频信号相位。
  3. 根据权利要求2所述的实现数据同步的装置，其中，所述相位差计算电路，用于比较所述参考时钟信号和所述工作时钟信号的延时差，包括：
    采用所述锁相环电路输出的高频信号采样所述参考时钟信号和所述工作时钟信号的相位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
  4. 根据权利要求1至3中任一项所述的实现数据同步的装置，其中，
    所述单芯片内多通道同步电路针对每个通道设置：
    第一同步单元，用于通过第一同步信号使多个通道抽取的数据保持一致；
    第二同步单元，用于在数据从第一同步单元传输到第二同步单元时，使各通道同时读取数据；
    第三同步单元，用于在数据从第二同步单元传输到第三同步单元时，使各通道同时读取数据。
  5. 根据权利要求4所述的实现数据同步的装置，其中，
    所述第二同步单元、所述第三同步单元，用于使各通道同时读取数据，包括：
    将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据。
  6. 一种实现数据同步的方法，包括：
    实现多个射频芯片间的工作时钟同步；和/或
    实现单芯片内多个通道的数据同步。
  7. 根据权利要求6所述的实现数据同步的方法，其中，所述实现多个射频芯片间的工作时钟同步，包括：
    接收参考时钟信号，以及输出频率是所述参考时钟信号频率n倍的高频信号，n大于或等于2；
    对所述高频信号分频，得到芯片所需频率的工作时钟信号；
    比较所述参考时钟信号和所述工作时钟信号的延时差，若延迟差大于所述预设延迟阈值，调整输出的高频信号相位。
  8. 根据权利要求7所述的实现数据同步的方法，其中，所述比较所述参考时钟信号和所述工作时钟信号的延时差，包括：
    采用所述高频信号采样所述参考时钟信号和所述工作时钟信号的相位差，得到参考时钟沿与工作时钟沿之间的最小差值后，将这一差值乘以用于采样的所述高频信号的时钟周期即得到所述参考时钟信号和所述工作时钟信号的延时差。
  9. 根据权利要求6至8中任一项所述的实现数据同步的方法，其中， 所述实现单芯片内多个通道的数据同步，包括：
    通过第一同步信号使多个通道抽取的数据保持一致；
    在所述抽取的数据传输过程中，使各通道同时读取所述数据。
  10. 根据权利要求9所述的实现数据同步的方法，其中，在所述抽取的数据传输过程中，使各通道同时读取所述数据，包括：
    将数据写入双端口随机存储器RAM中，通过第二同步信号使各通道在同一时刻读取所述RAM中的数据。
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