WO2023236398A1 - 锁相环、信号处理设备及信号处理的方法 - Google Patents

锁相环、信号处理设备及信号处理的方法 Download PDF

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WO2023236398A1
WO2023236398A1 PCT/CN2022/123554 CN2022123554W WO2023236398A1 WO 2023236398 A1 WO2023236398 A1 WO 2023236398A1 CN 2022123554 W CN2022123554 W CN 2022123554W WO 2023236398 A1 WO2023236398 A1 WO 2023236398A1
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phase
reference clock
signal
locked loop
crystal oscillator
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PCT/CN2022/123554
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English (en)
French (fr)
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邓伟
刘鸿倬
贾海昆
池保勇
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清华大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, integrated circuit technology, and in particular, to a phase-locked loop, a signal processing device, and a signal processing method.
  • phase noise of the phase-locked loop can be roughly divided into two parts: in-band and out-of-band; among them, the out-of-band phase noise is mainly determined by the voltage controlled oscillator (VCO, Voltage Controlled Oscillator), and the in-band phase noise is mainly determined by the reference clock; in order To minimize phase-locked loop phase noise, the phase-locked loop bandwidth is generally adjusted to balance the ratio of in-band phase noise and out-of-band phase noise.
  • the modulation result is generally the contribution ratio of in-band phase noise and out-of-band phase noise to the total noise. Much the same.
  • the theoretical limit (lower limit) of in-band phase noise is the reference clock noise + log (N div ) dBc/Hertz (Hz); where N div represents the ratio of the phase-locked loop (PLL) output frequency to the reference clock frequency; dBc is expressed in The difference between the power at the frequency and the power at the reference in decibels (dB).
  • N div represents the ratio of the phase-locked loop (PLL) output frequency to the reference clock frequency
  • dBc is expressed in The difference between the power at the frequency and the power at the reference in decibels (dB).
  • a smaller bandwidth needs to be designed to reduce the in-band phase noise contributed by the reference clock, which leads to the need to design a lower-noise VCO to avoid excessive out-of-band phase noise.
  • phase noise and power consumption are interchangeable. To achieve lower phase noise, more power consumption is required.
  • phase noise and power consumption of the phase-locked loop are difficult to further modulate and optimize.
  • Embodiments of the present disclosure provide a phase-locked loop, including: a reference clock unit, a feedback unit, a correction unit, a phase detection unit and a weighting unit; wherein,
  • the reference clock unit is set to: output two or more frequency-adjustable reference clock signals to the phase detection unit, and the two or more reference clock signals are synchronized;
  • the feedback unit is set to: perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
  • the phase detection unit is configured to: for each reference clock signal, determine the corresponding error signal for output voltage signal correction based on the phase difference between the reference clock signal and the feedback signal;
  • the weighting unit is set to: perform weighted calculation on the determined error signal to obtain a weighted error signal;
  • the correction unit is configured to: correct the output voltage signal of the second period according to the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
  • the first period and the second period are two adjacent periods for outputting the output voltage signal.
  • the phase locked loop further includes a filter, which is set to:
  • the weighted error signal obtained by the weighting unit is filtered.
  • the reference clock unit includes more than two first crystal oscillators; wherein,
  • the first crystal oscillator is configured to output one of the reference clock signals.
  • the reference clock unit includes a second crystal oscillator and more than one third crystal oscillator; wherein,
  • the second crystal oscillator is configured to: output one of the reference clock signals
  • the third crystal oscillator is configured to: output one of the reference clock signals
  • the frequency of the reference clock signal output by the second crystal oscillator is greater than the frequency of the reference clock signal output by the third crystal oscillator.
  • the number of the third crystal oscillators is 8 or 16.
  • the frequency of the third crystal oscillator is 0.1n kilohertz
  • n is a positive integer.
  • An embodiment of the present disclosure also provides a signal processing device, which includes the phase-locked loop according to the above.
  • An embodiment of the present disclosure also provides a signal processing method, including:
  • the first period and the second period are two adjacent periods for outputting the output voltage signal; the two or more reference clock signals are synchronized.
  • the method before correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal, the method further includes:
  • the obtained weighted error signal is filtered.
  • the method before determining the corresponding error signal according to the phase difference between the reference clock signal and the feedback signal, the method further includes:
  • the two or more frequency-adjustable reference clock signals are generated through two or more first crystal oscillators.
  • Figure 1 is a structural block diagram of a phase-locked loop according to an embodiment of the present disclosure
  • Figure 2A is an example diagram of a phase-locked loop according to an embodiment of the present disclosure
  • Figure 2B is an example diagram of a reference clock unit according to an embodiment of the present disclosure.
  • Figure 2C is an example diagram of another reference clock unit according to an embodiment of the present disclosure.
  • FIG. 3 is a flow chart of a signal processing method according to an embodiment of the present disclosure.
  • FIG. 1 is a structural block diagram of a phase-locked loop provided by an embodiment of the present disclosure.
  • the phase-locked loop may include: a reference clock unit, a feedback unit, a correction unit, a phase detection unit and a weighting unit; wherein,
  • the reference clock unit is set to: output two or more frequency-adjustable reference clock signals to the phase detection unit, and the two or more reference clock signals are synchronized;
  • the feedback unit is set to: perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
  • the phase detection unit is configured to: for each reference clock signal, determine the corresponding error signal for output voltage signal correction based on the phase difference between the reference clock signal and the feedback signal;
  • the weighting unit is set to: perform weighted calculation on the determined error signal to obtain a weighted error signal;
  • the correction unit is configured to: correct the output voltage signal of the second period according to the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
  • the first period and the second period are two adjacent periods for outputting the above-mentioned output voltage signal.
  • Embodiments of the present disclosure determine multi-channel error signals by using more than two reference clock signals, and by weighting the error signals, the phase domain average of the reference clock noise of the phase-locked loop is achieved, and the in-band phase noise of the reference clock is avoided from affecting the phase locking. It affects the loop power consumption and reduces the power consumption of the phase-locked loop.
  • the feedback signal of the embodiment of the present disclosure may include: the frequency and/or phase of the output voltage signal.
  • the output voltage signal in the initial stage may be set to 0.
  • the phase-locked loop may also include other auxiliary circuits, and the initial stage of the phase-locked loop may also output other voltage signals provided by the auxiliary circuits.
  • the phase-locked loop of the embodiment of the present disclosure may further include a filter, which is connected between the weighting unit and the correction unit and is configured as:
  • the error signal in the embodiment of the present disclosure may be a digital signal or a voltage signal.
  • the phase detection unit of this embodiment of the present disclosure may include a plurality of first phase detectors or frequency phase detectors.
  • the weighting unit of this embodiment of the present disclosure may be an adder.
  • the phase detection unit of the embodiment of the present disclosure may include the same number of first phase detectors (or frequency phase detectors) as the number of reference clock signals, and each first phase detector (or phase frequency detector) A phase detector (or frequency phase detector) is configured to determine an error signal corresponding to the reference clock signal based on the phase difference between one of the two or more reference clock signals and the feedback signal.
  • the phase detection unit contains N first phase detectors (or frequency detectors), where N is a natural number greater than or equal to 2, according to Corresponding relationship, each crystal oscillator is connected to a first phase detector (or frequency detector), and the first phase detector (or frequency detector) detects the reference clock signal from the crystal oscillator connected to itself, according to the reference The phase difference between the clock signal and the feedback signal determines the error signal corresponding to the reference clock signal.
  • the reference clock unit includes N crystal oscillators and (N-1) synchronization modules, N is a natural number greater than or equal to 2, and the N crystal oscillators include a main Crystal oscillator and (N-1) slave crystal oscillators, each synchronization module includes a second phase detector and a second filter;
  • One input terminal of the i-th second phase detector is connected to the output terminal of the master crystal oscillator, and the other input terminal of the i-th second phase detector is connected to the output terminal of the i-th slave crystal oscillator.
  • the output terminal of the phase filter is connected to the input terminal of the i-th second filter, and the output terminal of the i-th second filter is connected to the input terminal of the i-th slave crystal oscillator.
  • i is a natural number between 1 and N-1. .
  • the phase detector unit includes N first phase detectors
  • One input terminal of the jth first phase detector is connected to the output terminal of the jth crystal oscillator, the other input terminal of the jth first phase detector is connected to the output terminal of the feedback unit, and the jth first phase detector is connected to the output terminal of the feedback unit.
  • the output terminal of the device is connected to an input terminal of the weighting unit, and j is a natural number between 1 and N.
  • the reference clock unit of the embodiment of the present disclosure may include more than two first crystal oscillators; wherein,
  • the first crystal oscillator is set to output a reference clock signal.
  • the reference clock unit of the embodiment of the present disclosure may include: a synchronization circuit configured to synchronize the reference clock signal.
  • the embodiment of the present disclosure numbers multiple first crystal oscillators, which are numbered first crystal oscillator 1, first crystal oscillator 2, first crystal oscillator 3... first crystal oscillator n. ;
  • a set of second phase detectors and a second filter configured to synchronize the reference clock signal are connected to the output end of the first crystal oscillator 1 to filter the second
  • the output of the oscillator is connected to the input of the first crystal oscillator 2, and the output of the first crystal oscillator 2 is connected to the input of the second phase detector.
  • the first crystal oscillator 1 and Synchronization of the reference clock signal output by the first crystal oscillator 2 similarly, between the first crystal oscillator 1 and the first crystal oscillator 3, a set of second phase detectors and second filters are connected according to the above principles to realize the first crystal oscillator 1 and the synchronization of the reference clock signal output by the first crystal oscillator 3; ...; between the first crystal oscillator 1 and the first crystal oscillator n, a set of second phase detectors and a second filter are connected according to the above principles to achieve the Synchronization of the reference clock signal output by a crystal oscillator 1 and the first crystal oscillator n.
  • the second phase detector and the second filter configured to synchronize the reference clock signal are subsequently defined as synchronization modules.
  • Multiple synchronization modules constitute a synchronization circuit.
  • the synchronization module can be understood as a narrowband lock Phase ring.
  • the reference clock unit may include a second crystal oscillator and more than one third crystal oscillator; wherein, the second crystal oscillator is configured to: output a reference clock signal; and the third crystal oscillator is configured to: : Output a reference clock signal;
  • the frequency of the reference clock signal output by the second crystal oscillator is greater than the frequency of the reference clock signal output by the third crystal oscillator.
  • the number of third crystal oscillators in this embodiment of the present disclosure may be eight.
  • the number of third crystal oscillators in this embodiment of the present disclosure may be 16.
  • the embodiment of the present disclosure numbers multiple third crystal oscillators, which are respectively numbered as third crystal oscillator 1, third crystal oscillator 2...third crystal oscillator m; determine the second crystal oscillator
  • a set of synchronization modules are connected between the second crystal oscillator and the third crystal oscillator 1 to synchronize the reference clock signals output by the second crystal oscillator and the third crystal oscillator 1; similarly, in the first A set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator 2, a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator 2,..., a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator m module to achieve synchronization of the reference clock signal output by the reference clock unit.
  • the frequency of the third crystal oscillator in the embodiment of the present disclosure may be 0.1n kilohertz; where n is a positive integer.
  • the correction unit in the phase-locked loop of the embodiment of the present disclosure may be an oscillator.
  • the feedback unit in the phase-locked loop of the embodiment of the present disclosure may be a frequency divider.
  • the above-mentioned oscillator in the embodiment of the present disclosure may be a voltage-controlled oscillator.
  • correction unit and the feedback unit in the embodiment of the present disclosure can be replaced with other components based on the results of the phase-locked loop.
  • the first crystal oscillator in the embodiment of the present disclosure may be a voltage-controlled crystal oscillator (VCXO) or a numerically controlled crystal oscillator; in an illustrative example, the second crystal oscillator in the embodiment of the present disclosure may be It can be a voltage-controlled crystal oscillator, or it can be a numerically controlled crystal oscillator; in an exemplary example, the third crystal oscillator in the embodiment of the present disclosure can be a voltage-controlled crystal oscillator, or it can be a numerically controlled crystal oscillator.
  • VXO voltage-controlled crystal oscillator
  • the second crystal oscillator in the embodiment of the present disclosure may be It can be a voltage-controlled crystal oscillator, or it can be a numerically controlled crystal oscillator
  • the third crystal oscillator in the embodiment of the present disclosure can be a voltage-controlled crystal oscillator, or it can be a numerically controlled crystal oscillator.
  • the first crystal oscillator, the second crystal oscillator and the third crystal oscillator are all voltage-controlled crystal oscillators.
  • the first crystal oscillator is a voltage-controlled crystal oscillator
  • the second crystal oscillator is a voltage-controlled crystal oscillator
  • it is expressed as the second VCXO.
  • VCXO when the third crystal oscillator is a voltage-controlled crystal oscillator, it is expressed as the third VCXO.
  • the reference clock unit includes a second VCXO and more than one third VCXO, and is configured to output N reference clock signals.
  • the phase detection unit includes Nth A phase detector, the weighting unit is an adder, and the filter, correction unit and feedback unit in the phase-locked loop are connected in sequence for explanation;
  • Figure 2A is an example diagram of a phase-locked loop according to an embodiment of the present disclosure, as shown in Figure 2A
  • the VCXO in the embodiment of the present disclosure is the second VCXO, it can be determined as the master crystal oscillator (Master VCXO).
  • the N-1 third VCXOs can be regarded as N-1 slave crystal oscillators ( Slave VCXO), each slave crystal oscillator is controlled by a synchronization module to synchronize it with the master crystal oscillator;
  • the phase-locked loop in the embodiment of the present disclosure includes 1 master phase-locked loop and N-1 (N-1 is greater than or equal to 1 , can be 8 or 16) synchronous phase-locked loops, where the main phase-locked loop includes a first phase detector, adder, filter, oscillator and frequency divider, and the synchronous phase-locked loop includes a second phase detector and The second filter; among them, the bandwidth of the synchronous phase-locked loop is much smaller than the bandwidth of the main phase-locked loop, because the frequency range of the main phase-locked loop bandwidth is higher than the frequency range of the synchronous phase-locked loop bandwidth, and the phase noise of each crystal oscillator is uncorrelated.
  • the output of each crystal oscillator is phase-detected with the output of the feedback unit, and there are a total of N first phase detectors.
  • the output of the first phase detector is averaged to achieve phase domain averaging of the reference clock noise, that is, an equivalent reference clock whose equivalent noise is 1/(N) of a single crystal oscillator is achieved. It achieves noise averaging in the phase domain, reduces the noise of the equivalent reference clock of the phase-locked loop, and avoids the noise and power consumption limitations of the traditional phase-locked loop; it is conducive to reducing the overall noise and power consumption of the phase-locked loop.
  • An embodiment of the present disclosure also provides a signal processing device.
  • the signal processing device includes the phase-locked loop described in any embodiment of the present disclosure.
  • the signal processing device of the embodiment of the present disclosure may further include a receiver, a clock circuit, a frequency sweep circuit or a local oscillator circuit.
  • Figure 3 is a flow chart of a signal processing method according to an embodiment of the present disclosure. As shown in Figure 3, the method may include:
  • Step 301 Perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal
  • Step 302 For each of the two or more frequency-adjustable reference clock signals, determine the corresponding error signal based on the phase difference between the reference clock signal and the feedback signal;
  • Step 303 Perform weighted calculation on the determined error signal to obtain a weighted error signal
  • Step 304 Correct the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
  • the first period and the second period are the periods of two adjacent output voltage signals; two or more reference clock signals are synchronized.
  • Embodiments of the present disclosure determine multi-channel error signals by using more than two reference clock signals, and by weighting the error signals, the phase domain average of the reference clock noise of the phase-locked loop is achieved, and the in-band phase noise of the reference clock is avoided from affecting the phase locking. It affects the loop power consumption and reduces the power consumption of the phase-locked loop.
  • the method of the embodiment of the present disclosure may further include:
  • the method of the embodiment of the present disclosure may further include:
  • More than two reference clock signals are generated through two or more first crystal oscillators.
  • the method of the embodiment of the present disclosure may further include:
  • More than two reference clock signals are generated through one second crystal oscillator and more than one third crystal oscillator.
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种锁相环、信号处理设备及信号处理的方法，锁相环中：参考时钟单元向鉴相单元输出两个以上频率可调的同步的参考时钟信号；反馈单元对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；鉴相单元对各参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的误差信号；加权单元对确定的误差信号进行加权计算，获得加权误差信号；校正单元设置为：根据加权误差信号对锁相环在第二周期输出的输出电压信号进行校正。

Description

锁相环、信号处理设备及信号处理的方法
本申请要求于2022年6月6日提交中国专利局、申请号为CN202210634606.5、发明名称为“一种锁相环、信号处理设备及信号处理的方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于集成电路技术，尤指一种锁相环、信号处理设备及信号处理的方法。
背景技术
近年来，不断进步的无线通信技术对所用频率源的相位噪声提出越来越高的要求。更低的相位噪声往往需要更高的功耗，在锁相环设计过程中，相位噪声与功耗的设计，成为日益重要的问题。
锁相环的相位噪声大致可分为带内和带外两部分；其中，带外相位噪声主要由压控振荡器(VCO，Voltage Controlled Oscillator)决定，带内相位噪声主要由参考时钟决定；为了实现锁相环相位噪声的最小化，一般通过调整锁相环带宽以平衡带内相位噪声和带外相位噪声的比例，调制结果一般为带内相位噪声和带外相位噪声对总噪声的贡献比例大致相同。带内相位噪声的理论极限(下限)为参考时钟噪声+log(N div)dBc/赫兹(Hz)；其中，N div表示锁相环(PLL)输出频率与参照时钟频率的比值；dBc是以分贝(dB)为单位的该频率处功率与基准处功率的差值。为了降低锁相环的相位噪声，需要设计更小的带宽，以降低参考时钟所贡献的带内相位噪声，这就导致需要设计更低噪声的VCO以避免带外相位噪声过大。在VCO设计中，相位噪声与功耗是互换的，为实现更低的相位噪声，需要更多功耗。
综上，受限于参考时钟的带内相位噪声，锁相环的相位噪声与功耗难以进一步调制优化。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种锁相环，包括：参考时钟单元、反馈单元、校正单元、鉴相单元和加权单元；其中，
参考时钟单元设置为：向鉴相单元输出两个以上频率可调的参考时钟信号，两个以上参考时钟信号同步；
反馈单元设置为：对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
鉴相单元设置为：对每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的用于输出电压信号校正的误差信号；
加权单元设置为：对确定的误差信号进行加权计算，以获得加权误差信号；
校正单元设置为：根据加权误差信号对第二周期的输出电压信号进行校正，以获得锁相环在第二周期输出的输出电压信号；
其中，所述第一周期和所述第二周期为相邻的两个输出所述输出电压信号的周期。
在一种示例性实例中，所述锁相环还包括滤波器，设置为：
对所述加权单元获得的所述加权误差信号进行滤波处理。
在一种示例性实例中，所述参考时钟单元包括两个以上第一晶振；其中，
所述第一晶振设置为：输出一个所述参考时钟信号。
在一种示例性实例中，所述参考时钟单元包括一个第二晶振和一个以上第三晶振；其中，
所述第二晶振设置为：输出一个所述参考时钟信号；
所述第三晶振设置为：输出一个所述参考时钟信号；
其中，所述第二晶振输出的所述参考时钟信号的频率，大于所述第三晶 振输出的所述参考时钟信号的频率。
在一种示例性实例中，所述第三晶振的个数为8个或16个。
在一种示例性实例中，所述第三晶振的频率为0.1n千赫兹；
其中，所述n为正整数。
本公开实施例还提供一种信号处理设备，所述信号处理设备包括根据上述的锁相环。
本公开实施例还提供一种信号处理的方法，包括：
对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
对两个以上频率可调的参考时钟信号中的每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的误差信号；
对确定的误差信号进行加权计算，以获得加权误差信号；
根据获得的加权误差信号对锁相环在第二周期的输出电压信号进行校正，以获得锁相环在第二周期输出的输出电压信号；
其中，所述第一周期和所述第二周期为相邻的两个输出所述输出电压信号的周期；所述两个以上参考时钟信号同步。
在一种示例性实例中，所述根据获得的加权误差信号对锁相环在第二周期的输出电压信号进行校正之前，所述方法还包括：
对获得的所述加权误差信号进行滤波处理。
在一种示例性实例中，所述根据参考时钟信号和反馈信号的相位差确定相应的误差信号之前，所述方法还包括：
通过两个以上第一晶振，生成所述两个以上频率可调的参考时钟信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开实施例的技术方案，并不构成对本公开实施例技术方案的限制。
图1为本公开实施例一种锁相环的结构框图；
图2A为本公开实施例一种锁相环的示例图；
图2B为本公开实施例一种参考时钟单元的示例图；
图2C为本公开实施例另一种参考时钟单元的示例图
图3为本公开实施例一种信号处理的方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
图1为本公开实施例提供的一种锁相环的结构框图，如图1所示，该锁相环可以包括：参考时钟单元、反馈单元、校正单元、鉴相单元和加权单元；其中，
参考时钟单元设置为：向鉴相单元输出两个以上频率可调的参考时钟信号，两个以上参考时钟信号同步；
反馈单元设置为：对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
鉴相单元设置为：对每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的用于输出电压信号校正的误差信号；
加权单元设置为：对确定的误差信号进行加权计算，以获得加权误差信号；
校正单元设置为：根据加权误差信号对第二周期的输出电压信号进行校正，以获得锁相环在第二周期输出的输出电压信号；
其中，第一周期和第二周期为相邻的两个输出上述输出电压信号的周期。
本公开实施例通过两个以上参考时钟信号确定多路误差信号，通过对误 差信号进行加权，实现了锁相环的参考时钟噪声的相位域平均，避免了参考时钟的带内相位噪声对锁相环功耗造成影响，降低了锁相环的功耗。
在一种示例性实例中，本公开实施例的反馈信号可以包括：输出电压信号的频率和/或相位。
在一种示例性实例中，初始阶段的输出电压信号可以设置为0。在另一种示例性实例中，该锁相环还可以包含其他辅助电路，锁相环初始阶段也可以输出由辅助电路提供的其他电压信号。
在一种示例性实例中，本公开实施例的锁相环还可以包括滤波器，滤波器连接在加权单元和校正单元之间，设置为：
对加权单元获得的加权误差信号进行滤波处理。
在一种示例性实例中，本公开实施例的误差信号可以是数字信号，也可以是电压信号。
在一种示例性实例中，如图2A所示，本公开实施例鉴相单元可以包括多个第一鉴相器或鉴频鉴相器。
在一种示例性实例中，如图2A所示，本公开实施例加权单元可以为加法器。
在一种示例性实例中，如图2A所示，本公开实施例的鉴相单元可以包括数量与参考时钟信号个数相同的第一鉴相器(或鉴频鉴相器)，每一个第一鉴相器(或鉴频鉴相器)被配置为：根据两个以上参考时钟信号的其中之一和反馈信号的相位差，确定该参考时钟信号相应的误差信号。换句话说，当锁相环中包含N个晶振时，鉴相单元中包含N个第一鉴相器(或鉴频鉴相器)，其中，N为大于或等于2的自然数，按照一一对应关系，每一个晶振连接一个第一鉴相器(或鉴频鉴相器)，第一鉴相器(或鉴频鉴相器)对来自与自身连接的晶振的参考时钟信号，根据该参考时钟信号和反馈信号的相位差，确定该参考时钟信号对应的误差信号。
在一种示例性实例中，结合图2A、2B和2C所示，参考时钟单元包括N个晶振和(N-1)个同步模块，N为大于或等于2的自然数，N个晶振包括一个主晶振和(N-1)个从晶振，每个同步模块包括一个第二鉴相器和一个第 二滤波器；
第i个第二鉴相器的一个输入端与主晶振的输出端连接，第i个第二鉴相器的另一个输入端与第i个从晶振的输出端连接，第i个第二鉴相器的输出端与第i个第二滤波器的输入端连接，第i个第二滤波器的输出端与第i个从晶振的输入端连接，i为1至N-1之间的自然数。
在一种示例性实例中，结合图1和图2A所示，鉴相单元包括N个第一鉴相器；
第j个第一鉴相器的一个输入端与第j个晶振的输出端连接，第j个第一鉴相器的另一个输入端与反馈单元的输出端连接，第j个第一鉴相器的输出端与加权单元的一个输入端连接，j为1至N之间的自然数。
在一种示例性实例中，如图2B所示，本公开实施例的参考时钟单元可以包括两个以上第一晶振；其中，
第一晶振设置为：输出一个参考时钟信号。
在一种示例性实例中，本公开实施例的参考时钟单元可以包括：配置为同步参考时钟信号的同步电路。
在一种示例性实例中，如图2B所示，本公开实施例对多个第一晶振进行编号，分别编号为第一晶振1、第一晶振2、第一晶振3……第一晶振n；确定第一晶振1的参考时钟信号作为标准参考时钟后，采用在第一晶振1的输出端连接一组配置为同步参考时钟信号的第二鉴相器和第二滤波器，将第二滤波器的输出与第一晶振2的输入连接，将第一晶振2的输出与第二鉴相器的输入端连接，通过连接的第二鉴相器和第二滤波器，进行第一晶振1和第一晶振2输出的参考时钟信号的同步；同理，在第一晶振1和第一晶振3之间，参照上述原理连接一组第二鉴相器和第二滤波器，可以实现第一晶振1和第一晶振3输出的参考时钟信号的同步；……；在第一晶振1和第一晶振n之间，参照上述原理连接一组第二鉴相器和第二滤波器，可以实现第一晶振1和第一晶振n输出的参考时钟信号的同步。为便于陈述，后续将配置为同步参考时钟信号的第二鉴相器和第二滤波器定义为同步模块，多个同步模块组成同步电路，在一些示例性示例中，同步模块可以理解为窄带锁相环。
在另一种示例性实例中，如图2C所示，参考时钟单元可以包括一个第二晶振和一个以上第三晶振；其中，第二晶振设置为：输出一个参考时钟信号；第三晶振设置为：输出一个参考时钟信号；
其中，第二晶振输出的参考时钟信号的频率，大于第三晶振输出的参考时钟信号的频率。
在一种示例性实例中，本公开实施例的第三晶振的个数可以为8个。
在另一种示例性实例中，本公开实施例的第三晶振的个数可以为16个。
在一种示例性实例中，如图2C所示，本公开实施例对多个第三晶振进行编号，分别编号为第三晶振1、第三晶振2……第三晶振m；确定第二晶振的参考时钟信号作为标准参考时钟后，采用在第二晶振和第三晶振1之间连接一组同步模块，进行第二晶振和第三晶振1输出的参考时钟信号的同步；同理，在第二晶振和第三晶振2之间连接一组同步模块，在第二晶振和第三晶振2之间连接一组同步模块，……，在第二晶振和第三晶振m之间连接一组同步模块，以此实现参考时钟单元输出的参考时钟信号的同步。
在一种示例性实例中，本公开实施例的第三晶振的频率可以为0.1n千赫兹；其中，n为正整数。
在一种示例性实例中，本公开实施例的锁相环中的校正单元可以是振荡器。
在一种示例性实例中，本公开实施例的锁相环中的反馈单元可以是分频器。
在一种示例性实例中，本公开实施例中的上述振荡器可以是压控振荡器。
在一种示例性实例中，本公开实施例中的校正单元和反馈单元可以根据锁相环的结果，采用其他组成进行替换。
在一种示例性实例中，本公开实施例中的第一晶振可以是压控晶振(VCXO)，也可以是数控晶振；在一种示例性实例中，本公开实施例中的第二晶振可以是压控晶振，也可以是数控晶振；在一种示例性实例中，本公开实施例中的第三晶振可以是压控晶振，也可以是数控晶振。
以下以第一晶振、第二晶振和第三晶振均为压控晶振为例进行示例说明， 第一晶振为压控晶振时表示为第一VCXO，第二晶振为压控晶振时表示为第二VCXO，第三晶振为压控晶振时表示为第三VCXO，本示例以参考时钟单元包括一个第二VCXO和一个以上第三VCXO，配置为输出N个参考时钟信号，鉴相单元包含N个第一鉴相器，加权单元为加法器，锁相环中的滤波器、校正单元和反馈单元依次连接为例进行说明；图2A为本公开实施例一种锁相环的示例图，如图2A所示，本公开实施例VCXO为第二VCXO时，可以将其确定为主晶振(Master VCXO)，VCXO为第三VCXO时，N-1个第三VCXO可以视为N-1个从晶振(Slave VCXO)，每个从晶振都受到一个同步模块的控制，以使其与主晶振同步；本公开实施例锁相环包括1个主锁相环和N-1(N-1大于或等于1，可以为8或16)个同步锁相环，其中，主锁相环包括第一鉴相器、加法器、滤波器、振荡器和分频器，同步锁相环包括第二鉴相器和第二滤波器；其中，同步锁相环的带宽远小于主锁相环的带宽，因为主锁相环带宽的频率范围高于同步锁相环带宽的频率范围，各晶振的相位噪声不相关。本公开实施例每个晶振的输出都与反馈单元的输出做鉴相，共有N个第一鉴相器。对第一鉴相器的输出进行求平均，实现了参考时钟噪声的相位域平均，即实现了等效噪声为单个晶振1/(N)的等效参考时钟。实现了相位域的噪声平均，降低了锁相环的等效参考时钟的噪声，避免了传统锁相环的噪声与功耗的限制；有利于降低锁相环整体的噪声和功耗。
本公开实施例还提供一种信号处理设备，信号处理设备包括本公开任一实施例所述的锁相环。
在一种示例性实例中，本公开实施例的信号处理设备还可以包括接收机、时钟电路、扫频电路或本振电路。
图3为本公开实施例一种信号处理的方法的流程图，如图3所示，该方法可以包括：
步骤301、对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
步骤302、对两个以上频率可调的参考时钟信号中的每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的误差信号；
步骤303、对确定的误差信号进行加权计算，以获得加权误差信号；
步骤304、根据获得的加权误差信号对锁相环在第二周期的输出电压信号进行校正，以获得锁相环在第二周期输出的输出电压信号；
其中，第一周期和第二周期为相邻的两个输出电压信号的周期；两个以上参考时钟信号同步。
本公开实施例通过两个以上参考时钟信号确定多路误差信号，通过对误差信号进行加权，实现了锁相环的参考时钟噪声的相位域平均，避免了参考时钟的带内相位噪声对锁相环功耗造成影响，降低了锁相环的功耗。
在一种示例性实例中，根据获得的加权误差信号对振荡器产生的输出电压信号进行校正之前，本公开实施例方法还可以包括：
对获得的加权误差信号进行滤波处理。
在一种示例性实例中，分别根据每一个参考时钟信号和反馈信号的相位差确定相应的误差信号之前，本公开实施例方法还可以包括：
通过两个以上第一晶振，生成两个以上参考时钟信号。
在一种示例性实例中，分别根据每一个参考时钟信号和反馈信号的相位差确定相应的误差信号之前，本公开实施例方法还可以包括：
通过一个第二晶振和一个以上第三晶振，生成两个以上参考时钟信号。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或 其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (14)

  1. 一种锁相环，包括：参考时钟单元、反馈单元、校正单元、鉴相单元和加权单元；其中，
    所述参考时钟单元设置为：向所述鉴相单元输出两个以上频率可调的参考时钟信号，两个以上参考时钟信号同步；
    所述反馈单元设置为：对所述锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
    所述鉴相单元设置为：对每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的用于输出电压信号校正的误差信号；
    所述加权单元设置为：对确定的误差信号进行加权计算，以获得加权误差信号；
    所述校正单元设置为：根据加权误差信号对第二周期的输出电压信号进行校正，以获得所述锁相环在第二周期输出的输出电压信号；
    其中，所述第一周期和所述第二周期为相邻的两个输出所述输出电压信号的周期。
  2. 根据权利要求1所述的锁相环，所述锁相环还包括滤波器，设置为：
    对所述加权单元获得的所述加权误差信号进行滤波处理。
  3. 根据权利要求1或2所述的锁相环，其中，所述参考时钟单元包括两个以上第一晶振；其中，
    所述第一晶振设置为：输出一个所述参考时钟信号。
  4. 根据权利要求1或2所述的锁相环，其中，所述参考时钟单元包括一个第二晶振和一个以上第三晶振；其中，
    所述第二晶振设置为：输出一个所述参考时钟信号；
    所述第三晶振设置为：输出一个所述参考时钟信号；
    其中，所述第二晶振输出的所述参考时钟信号的频率，大于所述第三晶振输出的所述参考时钟信号的频率。
  5. 根据权利要求4所述的锁相环，其中，所述第三晶振的个数为8个或16个。
  6. 根据权利要求4所述的锁相环，其中，所述第三晶振的频率为0.1 n千赫兹；
    其中，所述n为正整数。
  7. 根据权利要求1或2所述的锁相环，其中，所述参考时钟单元包括N个晶振和(N-1)个同步模块，N为大于或等于2的自然数，N个晶振包括一个主晶振和(N-1)个从晶振，每个所述同步模块包括一个第二鉴相器和一个第二滤波器；
    第i个所述第二鉴相器的一个输入端与所述主晶振的输出端连接，第i个所述第二鉴相器的另一个输入端与第i个所述从晶振的输出端连接，第i个所述第二鉴相器的输出端与第i个所述第二滤波器的输入端连接，第i个所述第二滤波器的输出端与第i个所述从晶振的输入端连接，i为1至N-1之间的自然数。
  8. 根据权利要求7所述的锁相环，其中，所述鉴相单元包括N个第一鉴相器；
    第j个所述第一鉴相器的一个输入端与第j个所述晶振的输出端连接，第j个所述第一鉴相器的另一个输入端与所述反馈单元的输出端连接，第j个所述第一鉴相器的输出端与所述加权单元的一个输入端连接，j为1至N之间的自然数。
  9. 根据权利要求1所述的锁相环，其中，所述校正单元为压控振荡器。
  10. 根据权利要求1所述的锁相环，其中，所述反馈单元为分频器。
  11. 一种信号处理设备，所述信号处理设备包括根据权利要求1至10中任一项所述的锁相环。
  12. 一种信号处理的方法，包括：
    对锁相环在第一周期输出的输出电压信号进行分频处理，获得反馈信号；
    对两个以上频率可调的参考时钟信号中的每一个参考时钟信号，根据参考时钟信号和反馈信号的相位差确定相应的误差信号；
    对确定的误差信号进行加权计算，以获得加权误差信号；
    根据获得的加权误差信号对所述锁相环在第二周期的输出电压信号进行校正，以获得所述锁相环在第二周期输出的输出电压信号；
    其中，所述第一周期和所述第二周期为相邻的两个输出所述输出电压信号的周期；所述两个以上参考时钟信号同步。
  13. 根据权利要求12所述的方法，所述根据获得的加权误差信号对所述锁相环在第二周期的输出电压信号进行校正之前，所述方法还包括：
    对获得的所述加权误差信号进行滤波处理。
  14. 根据权利要求12或13所述的方法，所述根据参考时钟信号和反馈信号的相位差确定相应的误差信号之前，所述方法还包括：
    通过两个以上第一晶振，或者通过一个第二晶振和一个以上第三晶振，生成所述两个以上频率可调的参考时钟信号，所述第二晶振输出的所述参考时钟信号的频率大于所述第三晶振输出的所述参考时钟信号的频率。
PCT/CN2022/123554 2022-06-06 2022-09-30 锁相环、信号处理设备及信号处理的方法 WO2023236398A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090015338A1 (en) * 2007-07-13 2009-01-15 Frey Douglas R Dividerless pll architecture
CN202949409U (zh) * 2012-08-15 2013-05-22 中国航天科工集团第三研究院第八三五七研究所 基于双vco的超宽带频率合成器
CN103959653A (zh) * 2011-12-07 2014-07-30 瑞典爱立信有限公司 具有增强的捕获的模拟锁相环
CN111277262A (zh) * 2019-11-22 2020-06-12 合肥大唐存储科技有限公司 一种时钟数据恢复电路
CN111953345A (zh) * 2020-07-06 2020-11-17 南京熊猫电子股份有限公司 一种高稳定低相噪标频处理方法及系统
CN115037294A (zh) * 2022-06-06 2022-09-09 清华大学 一种锁相环、信号处理设备及信号处理的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090015338A1 (en) * 2007-07-13 2009-01-15 Frey Douglas R Dividerless pll architecture
CN103959653A (zh) * 2011-12-07 2014-07-30 瑞典爱立信有限公司 具有增强的捕获的模拟锁相环
CN202949409U (zh) * 2012-08-15 2013-05-22 中国航天科工集团第三研究院第八三五七研究所 基于双vco的超宽带频率合成器
CN111277262A (zh) * 2019-11-22 2020-06-12 合肥大唐存储科技有限公司 一种时钟数据恢复电路
CN111953345A (zh) * 2020-07-06 2020-11-17 南京熊猫电子股份有限公司 一种高稳定低相噪标频处理方法及系统
CN115037294A (zh) * 2022-06-06 2022-09-09 清华大学 一种锁相环、信号处理设备及信号处理的方法

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