WO2020124836A1 - 一种阵列基板 - Google Patents

一种阵列基板 Download PDF

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Publication number
WO2020124836A1
WO2020124836A1 PCT/CN2019/079049 CN2019079049W WO2020124836A1 WO 2020124836 A1 WO2020124836 A1 WO 2020124836A1 CN 2019079049 W CN2019079049 W CN 2019079049W WO 2020124836 A1 WO2020124836 A1 WO 2020124836A1
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Prior art keywords
line
voltage compensation
array substrate
common electrode
common voltage
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PCT/CN2019/079049
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English (en)
French (fr)
Inventor
田新斌
徐向阳
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深圳市华星光电技术有限公司
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Publication of WO2020124836A1 publication Critical patent/WO2020124836A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate.
  • pixel Array Com pixel array common electrode
  • gate line gate line
  • the prior art will add an Acom (array substrate common voltage) compensation function to the liquid crystal display device to compensate for Acom and ensure the stability of the array substrate common voltage.
  • Acom array substrate common voltage
  • the Acom potential of the entire panel is completely unified, so the same Acom is not applicable to all areas of the entire panel, and the potential of a certain area cannot be compensated separately.
  • the Acom potential of the entire panel is completely unified, so the same Acom is not applicable to all areas of the entire panel, and the potential of a certain area cannot be compensated separately.
  • An array substrate including:
  • the pixel unit array includes a plurality of pixel units distributed in the array
  • At least two common electrode lines each of the common electrode lines corresponding to one row of the pixel units;
  • At least two data lines are electrically connected to the flip-chip film board and the pixel unit;
  • the array substrate further includes a common voltage compensation line electrically connected to the flip chip film, the common voltage compensation line is electrically connected to the flip chip film; the common voltage compensation line and the common electrode The lines are located in different layers, and the common voltage compensation line is electrically connected to the common electrode line through the through hole; the common voltage compensation line and the data line are in the same layer; the common voltage compensation line is The common electrode line is vertical.
  • the common voltage compensation line is used to receive the compensation signal from the flip chip film and transmit the compensation signal to a common electrode line connected to the common voltage compensation line.
  • the compensation signal is used to compensate the potential of the common electrode line connected to the common voltage compensation line, so that the potential of the common electrode line at any position of the array substrate is constant.
  • the flip chip film board includes at least two independent data driving units.
  • the common voltage compensation line includes at least two sets of voltage compensation lines, and each set of the voltage compensation lines is in one-to-one correspondence with the data driving unit and is electrically connected.
  • each common voltage compensation line is electrically connected to all common electrode lines.
  • each set of the voltage compensation line corresponds to the common electrode line in one-to-one correspondence and is electrically connected.
  • the data driving unit includes a first signal output terminal and a second signal output terminal, the first signal output terminal is electrically connected to the data line, and the second signal output terminal and the common voltage compensation Wire electrical connection.
  • An array substrate including:
  • the pixel unit array includes a plurality of pixel units distributed in the array
  • At least two common electrode lines each of the common electrode lines corresponding to one row of the pixel units;
  • At least two data lines are electrically connected to the flip-chip film board and the pixel unit;
  • the array substrate further includes a common voltage compensation line electrically connected to the flip chip film, the common voltage compensation line is electrically connected to the flip chip film; the common voltage compensation line and the common electrode The lines are located in different layers, and the common voltage compensation line is electrically connected to the common electrode line through a through hole.
  • the common voltage compensation line is used to receive the compensation signal from the flip chip film and transmit the compensation signal to a common electrode line connected to the common voltage compensation line.
  • the compensation signal is used to compensate the potential of the common electrode line connected to the common voltage compensation line, so that the potential of the common electrode line at any position of the array substrate is constant.
  • the common voltage compensation line and the data line are at the same layer.
  • the common voltage compensation line is perpendicular to the common electrode line.
  • the flip chip film board includes at least two independent data driving units.
  • the common voltage compensation line includes at least two sets of voltage compensation lines, and each set of the voltage compensation lines is in one-to-one correspondence with the data driving unit and is electrically connected.
  • each common voltage compensation line is electrically connected to all common electrode lines.
  • each set of the voltage compensation line corresponds to the common electrode line in one-to-one correspondence and is electrically connected.
  • the data driving unit includes a first signal output terminal and a second signal output terminal, the first signal output terminal is electrically connected to the data line, and the second signal output terminal and the common voltage compensation Wire electrical connection.
  • the common electrode line effectively matches the charge and discharge of the pixel electrode, and has less influence on the charge and discharge of the pixel electrode.
  • FIG. 1 is a schematic diagram of the distribution of common electrode lines and pixel cell arrays in a specific embodiment of the present invention
  • FIG. 2 is a schematic diagram of connection between a common voltage compensation line and a common electrode line in Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of the distribution of the first metal layer and the second metal layer on the array substrate in the specific embodiment of the invention.
  • FIG. 4 is a schematic diagram of the connection between the first metal layer and the second metal layer in a specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of connection of a common voltage compensation line and a common electrode line in Embodiment 2 of the present invention.
  • the present invention is directed to the existing array substrates, in which the common voltage potential of the array substrate of the entire substrate is completely uniform, so the common voltage of the same array substrate is not applicable to all areas of the entire panel, and the potential of a certain area cannot be compensated.
  • the present invention can solve the above problems.
  • the array substrate includes a pixel unit array 10, at least two common electrode lines 20 and at least two data lines 51.
  • the pixel unit array 10 includes a plurality of pixel units 11 distributed in an array, and each of the common electrode lines 20 corresponds to a row of the pixel units 11.
  • the array substrate further includes a flip-chip film 30 for generating data signals and compensation signals, and a common voltage compensation line 52 electrically connected to the flip-chip film 30; the common voltage compensation line 52 and the common electrode line 20 are located at different layers, and the common voltage compensation line 52 is electrically connected to the common electrode line 20 through a via 70.
  • the common voltage compensation line 52 is used to receive the compensation signal from the flip chip film 30 and transmit the compensation signal to the common electrode line 20 connected to the common voltage compensation line 52.
  • the compensation signal is used to compensate the potential of the common electrode line 20 connected to the common voltage compensation line 52 to make the potential of the common electrode line 20 at any position of the array substrate constant;
  • the flip-chip film 30 provides a compensation signal, which is transmitted to the common electrode line 20 through the common voltage compensation line 52, thereby achieving potential compensation.
  • the common voltage compensation line 52 is perpendicular to the common electrode line 20.
  • the flip chip film 30 includes at least two independent data driving units 31.
  • the common voltage compensation line 52 includes at least two sets of voltage compensation lines, and each set of the voltage compensation lines corresponds to the data driving unit 31 in one-to-one correspondence and is electrically connected.
  • connection lines correspond to the data driving unit 31 one-to-one and are electrically connected.
  • Each common voltage compensation line 52 is electrically connected to all common electrode lines 20.
  • the pixel unit 11 is divided into a plurality of regions, and the compensation signals of each region are individually controlled by a plurality of independent data driving units 31 and voltage compensation lines, so as to realize partition potential compensation and ensure that the common electrode line 20 of each region is effectively matched
  • the charging and discharging of the pixel electrode have less influence on the charging and discharging of the pixel electrode.
  • FIG. 2 only shows the case where each group of voltage compensation lines includes two voltage compensation lines; in one embodiment, the number of voltage compensation lines in each group of voltage compensation lines and each The number of pixel units 11 corresponding to the common electrode line 20 is the same, thereby reducing the influence of signal delay on the charging and discharging of the pixel electrode.
  • the data driving unit 31 includes a first signal output terminal 311 and a second signal output terminal 312, the first signal output terminal 311 is electrically connected to the data line 51, and the second signal output terminal 312 is The connection line is electrically connected.
  • the array substrate includes a stacked first metal layer 40, a transparent conductive metal layer 60 and a second metal layer 50.
  • the common electrode line 20 is located at the same layer as the scanning line and the gate, and both are formed on the first metal layer 40 through the same photomask process.
  • the common voltage compensation line 52 and the data line 51 are located at the same layer, and the common voltage compensation line 52 and the data line 51 are formed in the same mask process and the same etching process.
  • the common voltage compensation line 52 and the data line 51 are formed through one process, which reduces the process and production cost.
  • a through hole 70 is opened in the pixel unit 11 between the first metal layer 40 and the second metal layer 50, and a transparent conductive metal is filled in the through hole 70, so that the common voltage compensation line 52 and the The common electrode line 20 is electrically connected.
  • An array substrate, as shown in FIG. 5, is different from the first embodiment only in that the connection method of the common voltage compensation line 52 and the common electrode line 20 is different, wherein each group of the voltage compensation lines One-to-one correspondence with the common electrode line 20 is electrically connected.
  • the beneficial effects of the present invention are: providing a compensation signal through an independent data driving unit 31, and using a common voltage compensation line 52 to transmit the compensation signal to the common electrode line 20, thereby achieving individual control of the compensation signal for the common voltage of the array substrate in each area
  • the partition potential compensation is realized to ensure that the common electrode line 20 of each area effectively matches the pixel electrode charge and discharge, and the influence on the pixel electrode charge and discharge is smaller.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板，包括多个像素单元（11）、覆晶薄膜板（30）、至少两条公共电极线（20）和至少两条公共电压补偿线（52）。每一条公共电极线（20）与一行像素单元（11）对应设置，公共电压补偿线（52）与覆晶薄膜板（30）电性连接，公共电压补偿线（52）与公共电极线（20）位于不同层别，公共电压补偿线（52）通过通孔（70）与公共电极线（20）电性连接。

Description

一种阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板。
 背景技术
在TFT-LCD（Liquid Crysral Display，液晶显示器件）中，pixel Array Com（像素阵列公共电极）起到储存电容的作用。在现有的像素阵列设计中，pixel Array Com与gate line（栅极线）的方向是一致的。
随着LCD技术的发展，大尺寸面板需求日益增加，而因尺寸较大，负载都会比小尺寸大，导致面板信号延迟，电容耦合效应严重，面板均一性较差，这些会导致大尺寸面板的显示品质下降，如产生水平串扰等一些面板问题。为了解决上述问题，现有技术会在液晶显示器件中增设Acom（阵列基板公共电压）补偿功能，来对Acom补偿，保证阵列基板公共电压的稳定性。
但是在现有设计中，整个面板的Acom的电位是完全统一的，所以同一个Acom并不适用于整个面板所有区域，无法单独进行某一区域的电位的补偿。
 技术问题
在现有设计中，整个面板的Acom的电位是完全统一的，所以同一个Acom并不适用于整个面板所有区域，无法单独进行某一区域的电位的补偿。
 技术解决方案
一种阵列基板，包括：
像素单元阵列，包括阵列分布的多个像素单元；
至少两条公共电极线，每一条所述公共电极线与一行所述像素单元对应设置；
覆晶薄膜板，用于生成数据信号以及补偿信号；
至少两条数据线，所述数据线与所述覆晶薄膜板和所述像素单元电性连接；
其中，所述阵列基板还包括与覆晶薄膜板电性连接的公共电压补偿线，所述公共电压补偿线与所述覆晶薄膜板电性连接；所述公共电压补偿线与所述公共电极线位于不同层别，并且，所述公共电压补偿线通过通孔与所述公共电极线电性连接；所述公共电压补偿线与所述数据线位于同一层别；所述公共电压补偿线与所述公共电极线垂直。
进一步的，所述公共电压补偿线用于从所述覆晶薄膜板接收所述补偿信号，并将所述补偿信号传输至与所述公共电压补偿线相连的公共电极线。
进一步的，所述补偿信号用于对与所述公共电压补偿线相连的所述公共电极线的电位进行补偿，以使所述公共电极线在所述阵列基板的任意位置处的电位恒定。
进一步的，所述覆晶薄膜板包括至少两个相互独立的数据驱动单元。
进一步的，所述公共电压补偿线包括至少两组电压补偿线，每组所述电压补偿线与所述数据驱动单元一一对应且电性连接。
进一步的，每条公共电压补偿线均与所有公共电极线电性连接。
进一步的，每组所述电压补偿线与所述公共电极线一一对应且电性连接。
进一步的，所述数据驱动单元包括第一信号输出端和第二信号输出端，所述第一信号输出端与所述数据线电性连接，所述第二信号输出端与所述公共电压补偿线电性连接。
一种阵列基板，包括：
像素单元阵列，包括阵列分布的多个像素单元；
至少两条公共电极线，每一条所述公共电极线与一行所述像素单元对应设置；
覆晶薄膜板，用于生成数据信号以及补偿信号；
至少两条数据线，所述数据线与所述覆晶薄膜板和所述像素单元电性连接；
其中，所述阵列基板还包括与覆晶薄膜板电性连接的公共电压补偿线，所述公共电压补偿线与所述覆晶薄膜板电性连接；所述公共电压补偿线与所述公共电极线位于不同层别，并且，所述公共电压补偿线通过通孔与所述公共电极线电性连接。
进一步的，所述公共电压补偿线用于从所述覆晶薄膜板接收所述补偿信号，并将所述补偿信号传输至与所述公共电压补偿线相连的公共电极线。
进一步的，所述补偿信号用于对与所述公共电压补偿线相连的所述公共电极线的电位进行补偿，以使所述公共电极线在所述阵列基板的任意位置处的电位恒定。
进一步的，所述公共电压补偿线与所述数据线位于同一层别。
进一步的，所述公共电压补偿线与所述公共电极线垂直。
进一步的，所述覆晶薄膜板包括至少两个相互独立的数据驱动单元。
进一步的，所述公共电压补偿线包括至少两组电压补偿线，每组所述电压补偿线与所述数据驱动单元一一对应且电性连接。
进一步的，每条公共电压补偿线均与所有公共电极线电性连接。
进一步的，每组所述电压补偿线与所述公共电极线一一对应且电性连接。
进一步的，所述数据驱动单元包括第一信号输出端和第二信号输出端，所述第一信号输出端与所述数据线电性连接，所述第二信号输出端与所述公共电压补偿线电性连接。
有益效果
通过独立的数据驱动单元提供补偿信号，利用公共电压补偿线传输补偿信号给公共电极线，从而实现对每个区域阵列基板公共电压的补偿信号的单独控制，从而实现分区电位补偿，保证每块区域公共电极线有效匹配像素电极充放电，对像素电极充放电的影响更小。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中公共电极线和像素单元阵列的分布示意图；
图2为本发明实施例一中公共电压补偿线与公共电极线的连接示意图；
图3为本发明具体实施方式中阵列基板上的第一金属层和第二金属层的分布示意图；
图4为本发明具体实施方式中第一金属层和第二金属层的连接示意图；
图5为本发明实施例二中公共电压补偿线与公共电极线的连接示意图。
附图标记：10、像素单元阵列；11、像素单元；20、公共电极线；30、覆晶薄膜板；31、数据驱动单元；311、第一信号输出端；312、第二信号输出端；40、第一金属层；50、第二金属层；51、数据线；52、公共电压补偿线；60、透明导体金属层；70、通孔。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的阵列基板中，整个基板的阵列基板公共电压的电位是完全统一的，所以同一个阵列基板公共电压并不适用于整个面板所有区域，无法进行某一区域的电位的补偿。本发明能解决上述问题。
实施例一：
一种阵列基板，如图1和图2所示，所述阵列基板包括像素单元阵列10、至少两条公共电极线20以及至少两条数据线51。
其中，所述像素单元阵列10包括阵列分布的多个像素单元11，每一条所述公共电极线20与一行所述像素单元11对应设置。
进一步的，所述阵列基板还包括用于生成数据信号和补偿信号的覆晶薄膜板30，以及，与所述覆晶薄膜板30电性连接的公共电压补偿线52；所述公共电压补偿线52与所述公共电极线20位于不同层别，并且，所述公共电压补偿线52通过通孔70与所述公共电极线20电性连接。
具体的，所述公共电压补偿线52用于从所述覆晶薄膜板30接收所述补偿信号，并将所述补偿信号传输至与所述公共电压补偿线52相连的公共电极线20。
所述补偿信号用于对与所述公共电压补偿线52相连的所述公共电极线20的电位进行补偿，以使所述公共电极线20在所述阵列基板的任意位置处的电位恒定；利用覆晶薄膜板30提供补偿信号，通过公共电压补偿线52传输给公共电极线20，从而实现电位补偿。
具体的，所述公共电压补偿线52与所述公共电极线20垂直。
进一步的，所述覆晶薄膜板30包括至少两个相互独立的数据驱动单元31。
进一步的，所述公共电压补偿线52包括至少两组电压补偿线，每组所述电压补偿线与所述数据驱动单元31一一对应且电性连接。
其中，每组所述电压补偿线中的所有电压补偿线均与一连接线电性连接，所述连接线与所述数据驱动单元31一一对应且电性连接。
其中，每条公共电压补偿线52均与所有公共电极线20电性连接。
将像素单元11划分为多个区域，通过多个独立的数据驱动单元31和电压补偿线对每个区域的补偿信号进行单独控制，从而实现分区电位补偿，保证每块区域公共电极线20有效匹配像素电极充放电，对像素电极充放电的影响更小。
需要说明的是，图2中仅示出了每组电压补偿线中包含两条电压补偿线的情况；在一实施方式中，每组所述电压补偿线中的电压补偿线的数量与每条公共电极线20对应的像素单元11的数量相同，从而减小信号延迟对像素电极充放电的影响。
其中，所述数据驱动单元31包括第一信号输出端311和第二信号输出端312，所述第一信号输出端311与所述数据线51电性连接，所述第二信号输出端312与所述连接线电性连接。
需要说明的是，如图3和图4所示，所述阵列基板包括层叠设置的第一金属层40、透明导电金属层60以及第二金属层50。
其中，所述公共电极线20与扫描线和栅极位于同一层别，且均通过同一道光罩制程在第一金属层40上形成。
其中，所述公共电压补偿线52与所述数据线51位于同一层别，且所述公共电压补偿线52与所述数据线51是在同一道光罩制程和同一道蚀刻制程中形成的。
通过一道工序形成公共电压补偿线52和数据线51，减少工艺制程，降低生产成本。
其中，通过在所述第一金属层40与第二金属层50之间的像素单元11上开设通孔70，通过向通孔70中填充透明导电金属，从而实现公共电压补偿线52与所述公共电极线20的电性连接。
实施例二：
一种阵列基板，如图5所示，其与实施例一的不同之处仅在于所述公共电压补偿线52与所述公共电极线20的连接方式不同，其中，每组所述电压补偿线与所述公共电极线20一一对应且电性连接。
本发明的有益效果为：通过独立的数据驱动单元31提供补偿信号，利用公共电压补偿线52传输补偿信号给公共电极线20，从而实现对每个区域阵列基板公共电压的补偿信号的单独控制，从而实现分区电位补偿，保证每块区域公共电极线20有效匹配像素电极充放电，对像素电极充放电的影响更小。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其中，所述阵列基板包括：
    像素单元阵列，包括阵列分布的多个像素单元；
    至少两条公共电极线，每一条所述公共电极线与一行所述像素单元对应设置；
    覆晶薄膜板，用于生成数据信号以及补偿信号；
    至少两条数据线，所述数据线与所述覆晶薄膜板和所述像素单元电性连接；
    其中，所述阵列基板还包括与覆晶薄膜板电性连接的公共电压补偿线，所述公共电压补偿线与所述覆晶薄膜板电性连接；所述公共电压补偿线与所述公共电极线位于不同层别，并且，所述公共电压补偿线通过通孔与所述公共电极线电性连接；所述公共电压补偿线与所述数据线位于同一层别；所述公共电压补偿线与所述公共电极线垂直。
  2. 根据权利要求1所述的阵列基板，其中，所述公共电压补偿线用于从所述覆晶薄膜板接收所述补偿信号，并将所述补偿信号传输至与所述公共电压补偿线相连的公共电极线。
  3. 根据权利要求2所述的阵列基板，其中，所述补偿信号用于对与所述公共电压补偿线相连的所述公共电极线的电位进行补偿，以使所述公共电极线在所述阵列基板的任意位置处的电位恒定。
  4. 根据权利要求1所述的阵列基板，其中，所述覆晶薄膜板包括至少两个相互独立的数据驱动单元。
  5. 根据权利要求4所述的阵列基板，其中，所述公共电压补偿线包括至少两组电压补偿线，每组所述电压补偿线与所述数据驱动单元一一对应且电性连接。
  6. 根据权利要求5所述的阵列基板，其中，每条公共电压补偿线均与所有公共电极线电性连接。
  7. 根据权利要求5所述的阵列基板，其中，每组所述电压补偿线与所述公共电极线一一对应且电性连接。
  8. 根据权利要求4所述的阵列基板，其中，所述数据驱动单元包括第一信号输出端和第二信号输出端，所述第一信号输出端与所述数据线电性连接，所述第二信号输出端与所述公共电压补偿线电性连接。
  9. 一种阵列基板，其中，所述阵列基板包括：
    像素单元阵列，包括阵列分布的多个像素单元；
    至少两条公共电极线，每一条所述公共电极线与一行所述像素单元对应设置；
    覆晶薄膜板，用于生成数据信号以及补偿信号；
    至少两条数据线，所述数据线与所述覆晶薄膜板和所述像素单元电性连接；
    其中，所述阵列基板还包括与覆晶薄膜板电性连接的公共电压补偿线，所述公共电压补偿线与所述覆晶薄膜板电性连接；所述公共电压补偿线与所述公共电极线位于不同层别，并且，所述公共电压补偿线通过通孔与所述公共电极线电性连接。
  10. 根据权利要求9所述的阵列基板，其中，所述公共电压补偿线用于从所述覆晶薄膜板接收所述补偿信号，并将所述补偿信号传输至与所述公共电压补偿线相连的公共电极线。
  11. 根据权利要求10所述的阵列基板，其中，所述补偿信号用于对与所述公共电压补偿线相连的所述公共电极线的电位进行补偿，以使所述公共电极线在所述阵列基板的任意位置处的电位恒定。
  12. 根据权利要求9所述的阵列基板，其中，所述公共电压补偿线与所述数据线位于同一层别。
  13. 根据权利要求9所述的阵列基板，其中，所述公共电压补偿线与所述公共电极线垂直。
  14. 根据权利要求13所述的阵列基板，其中，所述覆晶薄膜板包括至少两个相互独立的数据驱动单元。
  15. 根据权利要求14所述的阵列基板，其中，所述公共电压补偿线包括至少两组电压补偿线，每组所述电压补偿线与所述数据驱动单元一一对应且电性连接。
  16. 根据权利要求15所述的阵列基板，其中，每条公共电压补偿线均与所有公共电极线电性连接。
  17. 根据权利要求15所述的阵列基板，其中，每组所述电压补偿线与所述公共电极线一一对应且电性连接。
  18. 根据权利要求14所述的阵列基板，其中，所述数据驱动单元包括第一信号输出端和第二信号输出端，所述第一信号输出端与所述数据线电性连接，所述第二信号输出端与所述公共电压补偿线电性连接。
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