WO2020124730A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2020124730A1
WO2020124730A1 PCT/CN2019/072501 CN2019072501W WO2020124730A1 WO 2020124730 A1 WO2020124730 A1 WO 2020124730A1 CN 2019072501 W CN2019072501 W CN 2019072501W WO 2020124730 A1 WO2020124730 A1 WO 2020124730A1
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WIPO (PCT)
Prior art keywords
layer
display area
data line
insulating layer
display panel
Prior art date
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Ceased
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PCT/CN2019/072501
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English (en)
French (fr)
Inventor
向明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/349,265 priority Critical patent/US20210183894A1/en
Publication of WO2020124730A1 publication Critical patent/WO2020124730A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the invention relates to the field of displays, in particular to a display panel and a manufacturing method thereof.
  • the data lines 11 are arranged in a manner that bypasses the holes to prevent the data line 11 from being cut off by the hole 10.
  • the spacing between the data lines 11 or the width of the data lines 11 needs to be reduced, which results in the generation of non-display areas (such as the surrounding area between the two broken lines 12 and 13 in FIG. 14), but affect the user's visual experience.
  • the present invention provides a display panel and a manufacturing method thereof to reduce the area of the non-display area, thereby improving the user's visual experience.
  • the main object of the present invention is to provide a display panel and a method for manufacturing the same, which reduces the area of the non-display area by changing the data lines in the non-display area by layers.
  • an embodiment of the present invention provides a display panel including a display area and a non-display area, wherein the display panel includes: a substrate, a first insulating layer, and a first metal layer , A second insulating layer, a second metal layer, a dielectric layer and a plurality of data lines.
  • the first insulating layer is provided on the substrate, and a buffer layer is provided between the first insulating layer and the substrate.
  • the first metal layer is disposed on the first insulating layer, wherein the first metal layer includes: a first gate layer and a first trace layer.
  • the first gate layer is provided on the first insulating layer located in the display area.
  • the first trace layer is provided on the first insulating layer located in the non-display area.
  • the second insulating layer is provided on the first metal layer.
  • the second metal layer is provided on the second insulating layer, wherein the second metal layer includes: a second gate layer and a second trace layer.
  • the second gate layer is provided on the second insulating layer located in the display area.
  • the second trace layer is provided on the second insulating layer located in the non-display area.
  • the dielectric layer is provided on the second metal layer.
  • the plurality of data lines are provided on the dielectric layer and include: the plurality of data lines located in the display area, electrically connected to the first gate layer; and located in the non-display area At least two of the plurality of data lines are respectively bent toward the first wiring layer and the second wiring layer in a height direction to electrically connect the first wiring layer and In the second wiring layer, there is a height difference between the adjacent data lines in the non-display area.
  • the length of the first trace layer is greater than the length of the second trace layer.
  • an embodiment of the invention provides a display panel including a display area and a non-display area, wherein the display panel includes: a plurality of data lines, phases in the non-display area There is a height difference between the adjacent data lines.
  • the display panel includes: a substrate, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a dielectric layer and the multi-layer Data lines.
  • the first insulating layer is provided on the substrate.
  • the first metal layer is disposed on the first insulating layer, wherein the first metal layer includes: a first gate layer and a first trace layer.
  • the first gate layer is provided on the first insulating layer located in the display area.
  • the first trace layer is provided on the first insulating layer located in the non-display area.
  • the second insulating layer is provided on the first metal layer.
  • the second metal layer is provided on the second insulating layer, wherein the second metal layer includes: a second gate layer and a second trace layer.
  • the second gate layer is provided on the second insulating layer located in the display area.
  • the second trace layer is provided on the second insulating layer located in the non-display area.
  • the dielectric layer is provided on the second metal layer.
  • the plurality of data lines are provided on the dielectric layer and include: the plurality of data lines located in the display area, electrically connected to the first gate layer; and located in the non-display area At least two of the plurality of data lines are respectively bent toward the first wiring layer and the second wiring layer in a height direction to electrically connect the first wiring layer and The second trace layer.
  • the length of the first trace layer is greater than the length of the second trace layer.
  • the plurality of data lines include a first data line, a second data line, and a third data line
  • the display panel includes: a substrate, an insulating layer, a first A dielectric layer, the first data line, a second dielectric layer, the second data line, a third dielectric layer and the third data line.
  • the insulating layer is provided on the substrate.
  • the first dielectric layer is provided on the insulating layer in the non-display area.
  • the first data line is provided on the first dielectric layer in the non-display area.
  • the second dielectric layer is provided on the first data line in the non-display area.
  • the second data line is provided on the second dielectric layer in the non-display area.
  • the third dielectric layer is provided on the second data line in the non-display area.
  • the third data line is provided on the third dielectric layer in the non-display area.
  • the length of the first data line is smaller than the length of the second data line and the length of the second data line is smaller than the length of the third data line length.
  • the length of the first data line is greater than the length of the second data line and the length of the second data line is greater than the length of the third data line length.
  • another embodiment of the present invention provides a method of manufacturing a display panel, the display panel including a display area and a non-display area, wherein the method of manufacturing the display panel includes: forming a plurality of data lines, wherein There is a height difference between the adjacent data lines in the non-display area.
  • the method for manufacturing the display panel further includes the steps of: providing a substrate; forming a first insulating layer on the substrate; forming a first metal layer on the first insulating layer , wherein the first metal layer includes: a first gate layer formed on the first insulating layer located in the display area; and a first trace layer formed on the non-display area Forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer, wherein the second metal layer includes: a second A gate layer formed on the second insulating layer in the display area; and a second trace layer formed on the second insulating layer in the non-display area; forming a dielectric layer On the second metal layer; and forming the plurality of data lines on the dielectric layer, including: the plurality of data lines located in the display area, electrically connected to the first gate Layer; and at least two of the plurality of data lines in the non-display area and are respectively bent toward the first wiring layer and the second
  • the dielectric layer and before the plurality of data lines after forming the dielectric layer and before the plurality of data lines, it further includes patterning the dielectric layer and the second insulating layer to form a first through hole And a second through hole, wherein at least two of the plurality of data lines are electrically connected to the first wiring layer and the second wiring through the first through hole and the second through hole, respectively Line layer.
  • the plurality of data lines include a first data line, a second data line, and a third data line
  • the method of manufacturing the display panel further includes the steps of: providing a substrate; Forming an insulating layer on the substrate; forming a first dielectric layer on the insulating layer in the non-display area; forming the first data line on the first in the non-display area On the dielectric layer; forming a second dielectric layer on the first data line in the non-display area; forming the second data line on the second media line in the non-display area On the electrical layer; forming a third dielectric layer on the second data line in the non-display area; and forming the third data line on the third dielectric line in the non-display area On the electric layer.
  • the display panel and the manufacturing method of the present invention reduce the area of the non-display area by changing the layer of the data line in the non-display area, thereby improving the user's visual experience.
  • FIG. 1 is a schematic diagram of a data line of a conventional display panel adjacent to an opening.
  • FIG. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.
  • FIG. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the invention.
  • FIG. 4 is a schematic flowchart of a method of manufacturing a display panel according to an embodiment of the invention.
  • FIG. 5 is a schematic flowchart of a method of manufacturing a display panel according to another embodiment of the invention.
  • a display panel 20 defines a display area 20A and a non-display area 20B, wherein the display panel 20 includes a substrate 21, a first insulating layer 22, and a first metal Layer 23, a second insulating layer 24, a second metal layer 25, a dielectric layer 26 and a plurality of data lines 27.
  • the substrate 21 can be used to carry the first insulating layer 22, the first metal layer 23, the second insulating layer 24, the second metal layer 25, the dielectric layer 26 and the plurality of Data line 27.
  • the substrate 21 is, for example, a soft substrate or a hard substrate.
  • the substrate 21 is, for example, a transparent substrate.
  • the first insulating layer 22 of the display panel 20 of the embodiment of the present invention is provided on the substrate 21.
  • the first insulating layer 22 mainly serves as an insulating medium for the subsequently formed first metal layer 23.
  • a buffer layer 28 may be provided between the first insulating layer 22 and the substrate 21.
  • the first metal layer 23 of the display panel 20 of the embodiment of the present invention is disposed on the first insulating layer 22, wherein the first metal layer 23 includes: a first gate layer 231 and a first trace layer 232 .
  • the first gate layer 231 is provided on the first insulating layer 22 in the display area 20A.
  • the first trace layer 232 is disposed on the first insulating layer 22 located in the non-display area 20B.
  • the first gate layer 231 mainly serves as the gate structure of the thin film transistor in the display area 20A.
  • the first gate layer 231 can be electrically connected through a scan line (not shown), so as to control the thin-film transistor on-off.
  • the first trace layer 232 and the first gate layer 231 are substantially at the same horizontal position, wherein the first trace layer 232 and the first gate layer 231 can be in the same process step at the same time form.
  • the first trace layer 232 may be electrically connected to one of the plurality of data lines 27, so that the data line 27 located in the non-display area 20B achieves a layer-changing effect, thereby reducing the non-display Area of area 20B.
  • the second insulating layer 24 of the display panel 20 of the embodiment of the present invention is provided on the first metal layer 23.
  • the second insulating layer 24 can serve as an insulating medium between the first metal layer 23 and the second metal layer 25.
  • the second metal layer 25 of the display panel 20 of the embodiment of the present invention is disposed on the second insulating layer 24, wherein the second metal layer 25 includes: a second gate layer 251 and a second trace layer 252 .
  • the second gate layer 251 is provided on the second insulating layer 24 located in the display area 20A.
  • the second trace layer 252 is disposed on the second insulating layer 24 located in the non-display area 20B.
  • the second gate layer 251 may form a storage capacitor with the first gate layer 231, or the second gate layer 251 may form a trench with the thin film transistor in the display area 20A
  • the overlap of the track area functions as a bleeder voltage signal.
  • the second trace layer 252 and the second gate layer 251 are substantially at the same horizontal position, wherein the second trace layer 252 and the second gate layer 251 can be simultaneously in the same process step form.
  • the second trace layer 252 can be electrically connected to the other one of the plurality of data lines 27, so that the data line 27 located in the non-display area 20B achieves a layer-changing effect, thereby reducing the non-linear The area of the display area 20B.
  • the length L1 of the first trace layer 232 is greater than the length L2 of the second trace layer 252.
  • the dielectric layer 26 of the display panel 20 of the embodiment of the present invention is disposed on the second metal layer 25.
  • the dielectric layer 26 can serve as an insulating medium between the plurality of data lines 27 and the second metal layer 25.
  • a plurality of data lines 27 of the display panel 20 of the embodiment of the present invention are provided on the dielectric layer 26 in the display area 20A, and the plurality of data lines 27 are respectively located in the display area 20A and the non- In the display area 20B, the plurality of data lines 27 located in the display area 20A are electrically connected to the first gate layer 231 and located in the plurality of data lines 27 in the non-display area 20B At least two of them are respectively bent toward the first wiring layer 232 and the second wiring layer 252 in a height direction to electrically connect the first wiring layer 232 and the second wiring ⁇ 252.
  • a flat layer 29 may be disposed on the plurality of data lines 27.
  • the dielectric layer 26 and the second insulating layer 24 may be patterned to form a first A through hole 261 and a second through hole 241, wherein at least two of the plurality of data lines 27 are electrically connected to the first circuit through the first through hole 261 and the second through hole 241, respectively The wire layer 232 and the second wiring layer 252.
  • the display panel 20 of the embodiment of the present invention performs layer change processing on the data line 27 located in the non-display area 20B (for example, in this embodiment, the data line 27 is changed to the first The wire layer 232 or the second wiring layer 252). It can be seen that there is a height difference between the adjacent data lines 27 in the non-display area 20B, wherein the height difference is, for example, through the thickness of the second insulating layer 24 or the The thickness of the dielectric layer 26 is provided.
  • the display of the embodiment of the present invention can be completed on the premise of maintaining the spacing between adjacent data lines (in this embodiment, the height difference can be regarded as the spacing) or the width of the data line
  • the panel 20 can reduce the area of the non-display area 20B.
  • the display panel 20 of the embodiment of the present invention shown in FIG. 2 has three data lines 27 overlapped in a vertical direction, so the area of the non-display area 20B can be reduced to roughly three-thirds of the original One.
  • the display panel 30 defines a display area 30A and a non-display area 30B.
  • the display panel 30 includes a plurality of data lines 301, a substrate 31, an insulating layer 32, a first dielectric layer 33, a second dielectric layer 35, and a third dielectric layer 37, wherein the multiple Each data line 301 includes a first data line 34, a second data line 36, and a third data line 38.
  • the substrate 30 may be used to carry the insulating layer 32, the first dielectric layer 33, the first data line 34, the second dielectric layer 35, the second data line 36, the first Three dielectric layers 37 and the third data line 38.
  • the substrate 31 is, for example, a soft substrate or a hard substrate. In another embodiment, the substrate 31 is, for example, a transparent substrate.
  • the insulating layer 32 of the display panel 30 of the embodiment of the present invention is provided on the substrate 31.
  • the insulating layer 32 serves as a gate insulating layer (the gate structure is not shown).
  • a buffer layer 39 may be provided between the insulating layer 32 and the substrate 31.
  • the insulating layer 32 may be a double-layer structure, for example, including a first gate insulating layer 321 and a second gate insulating layer 322, which may be used for the insulating layers of two gate structures, respectively .
  • the first dielectric layer 33 of the display panel 30 of the embodiment of the present invention is disposed on the insulating layer 32 in the non-display area 30B.
  • the first dielectric layer 33 can be formed on the insulating layer 32 by a general semiconductor process deposition method.
  • the first data line 34 of the display panel 30 of the embodiment of the present invention is disposed on the first dielectric layer 33 in the non-display area 30B.
  • the first data line 34 may be formed on the first dielectric layer 33 by a general semiconductor process deposition method.
  • the second dielectric layer 35 of the display panel 30 of the embodiment of the present invention is disposed on the first data line 34 in the non-display area 30B.
  • the second dielectric layer 35 may be formed on the first data line 34 by a general semiconductor process deposition method.
  • the second data line 36 of the display panel 30 of the embodiment of the present invention is disposed on the second dielectric layer 35 in the non-display area 30B.
  • the second data line 36 may be formed on the second dielectric layer 35 by a general semiconductor process deposition method.
  • the third dielectric layer 37 of the display panel 30 of the embodiment of the present invention is disposed on the second data line 36 in the non-display area 30B.
  • the third dielectric layer 37 may be formed on the second data line 36 by a general semiconductor process deposition method.
  • the third data line 38 of the display panel 30 of the embodiment of the present invention is disposed on the third dielectric layer 37 in the non-display area 30B.
  • the third data line 38 may be formed on the third dielectric layer 37 by a general semiconductor process deposition method.
  • a flat layer 391 can be disposed on the third data line 38.
  • the display panel 30 of the embodiment of the present invention performs layer change processing on the plurality of data lines 301 located in the non-display area 30B (for example, in this embodiment, the The first data line 34, the second data line 36, and the third data line 38 of the display area 30B are disposed on a layered structure of different heights (ie, the plurality of data lines 301 adjacent to the non-display area 30B have a Height difference).
  • the present invention can be completed on the premise of maintaining the distance between adjacent data lines (in this embodiment, the height difference can be regarded as the pitch) or the width of the data line
  • the display panel 30 of the embodiment can reduce the area of the non-display area 30B.
  • the display panel 30 of the embodiment of the present invention shown in FIG. 3 because the first data line 34 and the second data line 36
  • the third data lines 38 are arranged to overlap with each other in a vertical direction, so the area of the non-display area 30B can be reduced to roughly one third.
  • the length L3 of the first data line 34 is less than the length L4 of the second data line 36 and the length L4 of the second data line 36 is less than the length The length L5 of the third data line 38.
  • the length of the first data line 34 is greater than the length of the second data line 36 and the length of the second data line 36 is greater than the third The length of the data line 38.
  • the multiple data lines 301 described in the above embodiments may be located in the display area 30A and the non-display area 30B at the same time.
  • the plurality of data lines 301 located in the display area 30A can be used to electrically connect the drain (not shown) of the thin film transistors of the display panel 30; while many located in the non-display area 30B
  • Each data line 301 reduces the area of the non-display area 30B through the layer change process as described above.
  • the data line 301 located in the display area 30A may be disposed on the first dielectric layer 33 located in the display area 30A and located in the display area 30A according to the design.
  • the second dielectric layer 35 is located on the third dielectric layer 37 of the display area 30A.
  • another embodiment of the present invention provides a method 40 for manufacturing a display panel.
  • the display panel includes a display area and a non-display area.
  • the method for manufacturing a display panel includes steps 41 to 47: providing a Substrate (step 41); forming a first insulating layer on the substrate (step 42); forming a first metal layer on the first insulating layer, wherein the first metal layer includes: a first gate A polar layer formed on the first insulating layer in the display area; and a first wiring layer formed on the first insulating layer in the non-display area (step 43); forming a A second insulating layer on the first metal layer (step 44); forming a second metal layer on the second insulating layer, wherein the second metal layer includes: a second gate layer formed on Located on the second insulating layer in the display area; and a second trace layer formed on the second insulating layer in the non-display area (step 45); forming a dielectric layer on the On the second metal layer (step 41
  • each layer structure in steps 42 to 47 may be formed by, for example, a method (such as deposition, sputtering, etc.) used in a general semiconductor process.
  • the dielectric layer and before the plurality of data lines further includes patterning the dielectric layer and the second insulating layer to form a first through hole and a first Two through holes, wherein at least two of the plurality of data lines are electrically connected to the first wiring layer and the second wiring layer through the first through hole and the second through hole, respectively.
  • the display panel 20 of the embodiment of the present invention can be manufactured by the manufacturing method 40 of the display panel.
  • yet another embodiment of the present invention provides a method 50 for manufacturing a display panel.
  • the display panel includes a display area and a non-display area.
  • the method 50 for manufacturing a display panel includes steps 51 to 58: providing A substrate (step 51); forming an insulating layer on the substrate (step 52); forming a first dielectric layer on the insulating layer in the non-display area (step 53); forming a first The data line is on the first dielectric layer in the non-display area (step 54); a second dielectric layer is formed on the first data line in the non-display area (step 55) ; Forming a second data line on the second dielectric layer in the non-display area (step 56); forming a third dielectric layer, the second data in the non-display area Online (step 57); and forming a third data line on the third dielectric layer in the non-display area (step 58).
  • each layer structure in steps 52 to 58 may be formed by, for example, a method (such as deposition, sputtering, etc.) used in a general semiconductor process.
  • the display panel 30 of the embodiment of the present invention can be manufactured by the manufacturing method 50 of the display panel.
  • the present invention provides a display panel and a method for manufacturing the same.
  • the area of the non-display area is reduced, thereby improving the user's visual experience.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明公开一种显示面板及其制造方法，所述显示面板包含一显示区及一非显示区，其中所述显示面板包含：多个数据线，在所述非显示区中的相邻的所述多个数据线之间具有一高度差。所述显示面板通过将在非显示区的数据线换层的方式，可减少非显示区的面积。

Description

显示面板及其制造方法 技术领域
本发明是有关于显示器领域，特别是有关于一种显示面板及其制造方法。
 背景技术
如图1所示，对于在屏幕开孔的显示面板，数据线11会以绕过开孔的方式排列，以避免数据线11被孔洞10所截断。然而，在进行上述的排列方式时，需要缩小数据线11之间的间距或者数据线11的宽度，故导致非显示区的产生(如图1中的二个虚线12与13之间的围绕面积14处)，反而影响用户的视觉感受。
故，有必要提供一种显示面板及其制造方法，以解决现有技术所存在的问题。
 技术问题
有鉴于此，本发明提供一种显示面板及其制造方法，以减少非显示区的面积，进而改善用户的视觉感受。
 技术解决方案
本发明的主要目的在于提供一种显示面板及其制造方法，其通过将在非显示区的数据线换层的方式，以减少非显示区的面积。
为达成本发明的前述目的，本发明一实施例提供一种显示面板，包含一显示区及一非显示区，其中所述显示面板包含：一基板、一第一绝缘层、一第一金属层、一第二绝缘层、一第二金属层、一介电层及多个数据线。所述第一绝缘层设在所述基板上，其中一缓冲层设在所述第一绝缘层与所述基板之间。所述第一金属层设在所述第一绝缘层上，其中所述第一金属层包含：一第一栅极层及一第一走线层。所述第一栅极层设在位于所述显示区的所述第一绝缘层上。所述第一走线层设在位于所述非显示区的所述第一绝缘层上。所述第二绝缘层设在所述第一金属层上。所述第二金属层设在所述第二绝缘层上，其中所述第二金属层包含：一第二栅极层及一第二走线层。所述第二栅极层设在位于所述显示区的所述第二绝缘层上。所述第二走线层设在位于所述非显示区的所述第二绝缘层上。所述介电层设在所述第二金属层上。所述多个数据线设在所述介电层上，包含：位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层，其中在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
在本发明的一实施例中，在所述非显示区中，所述第一走线层的长度大于所述第二走线层的长度。
为达成本发明的前述目的，本发明一实施例提供一种显示面板，包含一显示区及一非显示区，其中所述显示面板包含：多个数据线，在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
在本发明的一实施例中，所述显示面板包含：一基板、一第一绝缘层、一第一金属层、一第二绝缘层、一第二金属层、一介电层及所述多个数据线。所述第一绝缘层设在所述基板上。所述第一金属层设在所述第一绝缘层上，其中所述第一金属层包含：一第一栅极层及一第一走线层。所述第一栅极层设在位于所述显示区的所述第一绝缘层上。所述第一走线层设在位于所述非显示区的所述第一绝缘层上。所述第二绝缘层设在所述第一金属层上。所述第二金属层设在所述第二绝缘层上，其中所述第二金属层包含：一第二栅极层及一第二走线层。所述第二栅极层设在位于所述显示区的所述第二绝缘层上。所述第二走线层设在位于所述非显示区的所述第二绝缘层上。所述介电层设在所述第二金属层上。所述多个数据线设在所述介电层上，包含：位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层。
在本发明的一实施例中，在所述非显示区中，所述第一走线层的长度大于所述第二走线层的长度。
在本发明的一实施例中，所述多个数据线包含一第一数据线、一第二数据线以及一第三数据线，以及所述显示面板包含：一基板、一绝缘层、一第一介电层、所述第一数据线、一第二介电层、所述第二数据线、一第三介电层及所述第三数据线。所述绝缘层设在所述基板上。所述第一介电层设在所述非显示区中的所述绝缘层上。所述第一数据线设在所述非显示区中的所述第一介电层上。所述第二介电层设在所述非显示区中的所述第一数据线上。所述第二数据线设在所述非显示区中的所述第二介电层上。所述第三介电层设在所述非显示区中的所述第二数据线上。所述第三数据线设在所述非显示区中的所述第三介电层上。
在本发明的一实施例中，在所述非显示区中，所述第一数据线的长度小于所述第二数据线的长度以及所述第二数据线的长度小于所述第三数据线的长度。
在本发明的一实施例中，在所述非显示区中，所述第一数据线的长度大于所述第二数据线的长度以及所述第二数据线的长度大于所述第三数据线的长度。
再者，本发明另一实施例提供一种显示面板的制造方法，所述显示面板包含一显示区及一非显示区，其中所述显示面板的制造方法包含：形成多个数据线，其中在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
在本发明的一实施例中，所述显示面板的制造方法还包含步骤：提供一基板；形成一第一绝缘层在所述基板上；形成一第一金属层在所述第一绝缘层上，其中所述第一金属层包含：一第一栅极层，形成在位于所述显示区的所述第一绝缘层上；及一第一走线层，形成在位于所述非显示区的所述第一绝缘层上；形成一第二绝缘层在所述第一金属层上；形成一第二金属层在所述第二绝缘层上，其中所述第二金属层包含：一第二栅极层，形成在位于所述显示区的所述第二绝缘层上；及一第二走线层，形成在位于所述非显示区的所述第二绝缘层上；形成一介电层在所述第二金属层上；及形成所述多个数据线在所述介电层上，包含:位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层。
在本发明的一实施例中，在形成所述介电层之后及所述多个数据线之前，还包含图案化所述介电层及所述第二绝缘层，以形成一第一通孔与一第二通孔，其中所述多个数据线中的至少二个通过所述第一通孔与所述第二通孔分别电性连接所述第一走线层与所述第二走线层。
在本发明的一实施例中，所述多个数据线包含一第一数据线、一第二数据线以及一第三数据线，以及所述显示面板的制造方法还包含步骤：提供一基板；形成一绝缘层在所述基板上；形成一第一介电层在所述非显示区中的所述绝缘层上；形成所述第一数据线在所述非显示区中的所述第一介电层上；形成一第二介电层，在所述非显示区中的所述第一数据线上；形成所述第二数据线，在所述非显示区中的所述第二介电层上；形成一第三介电层，在所述非显示区中的所述第二数据线上；及形成所述第三数据线，在所述非显示区中的所述第三介电层上。
 有益效果
与现有技术相比较，本发明的显示面板及其制造方法，通过把在非显示区的数据线换层的方式，以减少非显示区的面积，进而改善用户的视觉感受。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
 附图说明
图1是一现有显示面板在邻近开孔处的数据线的示意图。
图2是本发明一实施例的显示面板的剖面示意图。
图3是本发明另一实施例的显示面板的剖面示意图。
图4是本发明一实施例的显示面板的制造方法的流程示意图。
图5是本发明另一实施例的显示面板的制造方法的流程示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图2所示，本发明一实施例的显示面板20定义有一显示区20A及一非显示区20B，其中所述显示面板20包含一基板21、一第一绝缘层22、一第一金属层23、一第二绝缘层24、一第二金属层25、一介电层26及多个数据线27。所述基板21可用于承载所述第一绝缘层22、所述第一金属层23、所述第二绝缘层24、所述第二金属层25、所述介电层26及所述多个数据线27。在一实施例中，所述基板21例如是一软质基板或一硬质基板。在另一实施例中，所述基板21例如是一透光基板。
本发明实施例的显示面板20的第一绝缘层22设在所述基板21上。在一实施例中，所述第一绝缘层22主要作为后续形成的所述第一金属层23的绝缘介质。在一实施例中，所述第一绝缘层22与所述基板21之间可设有一缓冲层28。
本发明实施例的显示面板20的第一金属层23设在所述第一绝缘层22上，其中所述第一金属层23包含：一第一栅极层231及一第一走线层232。所述第一栅极层231设在位于所述显示区20A的所述第一绝缘层22上。所述第一走线层232设在位于所述非显示区20B的所述第一绝缘层22上。所述第一栅极层231主要作为所述显示区20A中的薄膜晶体管的栅极结构。一般而言，可通过扫描线(未绘示)电性连接所述第一栅极层231，进而对所述薄膜晶体管进行开关(on-off)的控制。所述第一走线层232与所述第一栅极层231大致上位在同一水平位置，其中所述第一走线层232可与所述第一栅极层231在相同的制程步骤中同时形成。所述第一走线层232可电性连接于所述多个数据线27中的一个，以使位在所述非显示区20B中的数据线27达成换层效果，进而减少所述非显示区20B的面积。
本发明实施例的显示面板20的第二绝缘层24设在所述第一金属层23上。所述第二绝缘层24可作为所述第一金属层23与所述第二金属层25之间的一绝缘介质。
本发明实施例的显示面板20的第二金属层25设在所述第二绝缘层24上，其中所述第二金属层25包含：一第二栅极层251及一第二走线层252。所述第二栅极层251设在位于所述显示区20A的所述第二绝缘层24上。所述第二走线层252设在位于所述非显示区20B的所述第二绝缘层24上。要提到的是，所述第二栅极层251可与所述第一栅极层231形成存储电容，或者所述第二栅极层251可与所述显示区20A中的薄膜晶体管的沟道区搭接起泄放电压信号的作用。所述第二走线层252与所述第二栅极层251大致上位在同一水平位置，其中所述第二走线层252可与所述第二栅极层251在相同的制程步骤中同时形成。所述第二走线层252可电性连接于所述多个数据线27中的另一个，以使位在所述非显示区20B中的数据线27达成换层效果，进而减少所述非显示区20B的面积。在一实施例中，在所述非显示区20B中，所述第一走线层232的长度L1大于所述第二走线层252的长度L2。
本发明实施例的显示面板20的介电层26设在所述第二金属层25上。所述介电层26可作为所述多个数据线27与所述第二金属层25之间的绝缘介质。
本发明实施例的显示面板20的多个数据线27设在所述显示区20A中的所述介电层26上，所述多个数据线27分别位在所述显示区20A与所述非显示区20B中，其中位在所述显示区20A的所述多个数据线27电性连接所述第一栅极层231，位在所述非显示区20B的所述多个数据线27中的至少二个且在一高度方向上分别朝向所述第一走线层232及所述第二走线层252弯折，以电性连接所述第一走线层232及所述第二走线层252。在一实施例中，一平坦层29可设置在所述多个数据线27上。
在一实施例中，在设置所述介电层26之后及所述多个数据线27之前，可对所述介电层26及所述第二绝缘层24进行图案化处理，以形成一第一通孔261与一第二通孔241，其中所述多个数据线27中的至少二个通过所述第一通孔261与所述第二通孔241分别电性连接所述第一走线层232与所述第二走线层252。
这边要提到的是，本发明实施例的显示面板20是通过把位在所述非显示区20B的数据线27进行换层处理(例如本实施例中把数据线27换到第一走线层232或第二走线层252)。由此可知，在所述非显示区20B中的相邻的所述多个数据线27之间具有一高度差，其中所述高度差例如是通过所述第二绝缘层24的厚度或所述介电层26的厚度所提供。通过这样的换层处理，可在维持相邻的数据线之间的间距(在本实施例，所述高度差可视为间距)或者数据线的宽度的前提下，完成本发明实施例的显示面板20，故可减少所述非显示区20B的面积。根据实际测量，如图2所示的本发明实施例的显示面板20，因为三个数据线27沿一垂直方向重叠排列，故所述非显示区20B的面积可大致减少为原来的三分之一。
请参照图3所示，本发明一实施例的显示面板30定义有一显示区30A及一非显示区30B。所述显示面板30包含有多个数据线301、一基板31、一绝缘层32、一第一介电层33、一第二介电层35及一第三介电层37，其中所述多个数据线301包含一第一数据线34、一第二数据线36及一第三数据线38。所述基板30可用于承载所述绝缘层32、所述第一介电层33、所述第一数据线34、所述第二介电层35、所述第二数据线36、所述第三介电层37及所述第三数据线38。在一实施例中，所述基板31例如是一软质基板或一硬质基板。在另一实施例中，所述基板31例如是一透光基板。
本发明实施例的显示面板30的绝缘层32设在所述基板31上。在一实施例中，所述绝缘层32例如作为一栅极绝缘层(栅极结构未绘示)。在一实施例中，所述绝缘层32与所述基板31之间可设有一缓冲层39。在另一实施例中，所述绝缘层32可以是双层结构，例如包含一第一栅极绝缘层321与一第二栅极绝缘层322，可分别用于二个栅极结构的绝缘层。
本发明实施例的显示面板30的第一介电层33设在所述非显示区30B中的所述绝缘层32上。在一实施例中，所述第一介电层33可通过一般半导体工艺的沉积方式形成在所述绝缘层32上。
本发明实施例的显示面板30的第一数据线34设在所述非显示区30B中的所述第一介电层33上。在一实施例中，所述第一数据线34可通过一般半导体工艺的沉积方式形成在所述第一介电层33上。
本发明实施例的显示面板30的第二介电层35设在所述非显示区30B中的所述第一数据线34上。在一实施例中，所述第二介电层35可通过一般半导体工艺的沉积方式形成在所述第一数据线34上。
本发明实施例的显示面板30的第二数据线36设在所述非显示区30B中的所述第二介电层35上。在一实施例中，所述第二数据线36可通过一般半导体工艺的沉积方式形成在所述第二介电层35上。
本发明实施例的显示面板30的第三介电层37设在所述非显示区30B中的所述第二数据线36上。在一实施例中，所述第三介电层37可通过一般半导体工艺的沉积方式形成在所述第二数据线36上。
本发明实施例的显示面板30的第三数据线38设在所述非显示区30B中的所述第三介电层37上。在一实施例中，所述第三数据线38可通过一般半导体工艺的沉积方式形成在所述第三介电层37上。在一实施例中，一平坦层391可设置在所述第三数据线38上。
这边要提到的是，本发明实施例的显示面板30是通过把位在所述非显示区30B的多个数据线301进行换层处理(例如本实施例中是把位在所述非显示区30B的第一数据线34、第二数据线36与第三数据线38设置在不同高度的层状结构上(即在非显示区30B的相邻的所述多个数据线301具有一高度差)。通过这样的换层处理，可在维持相邻的数据线之间的间距(在本实施例，所述高度差可视为间距)或者数据线的宽度的前提下，完成本发明实施例的显示面板30，故可减少所述非显示区30B的面积。根据实际测量，如图3所示的本发明实施例的显示面板30，因为第一数据线34、第二数据线36与第三数据线38沿一垂直方向重叠排列，故所述非显示区30B的面积可大致减少为原来的三分之一。
在一实施例中，在所述非显示区30B中，所述第一数据线34的长度L3小于所述第二数据线36的长度L4以及所述第二数据线36的长度L4小于所述第三数据线38的长度L5。在另一实施例中，在所述非显示区30B中，所述第一数据线34的长度大于所述第二数据线36的长度以及所述第二数据线36的长度大于所述第三数据线38的长度。
要提到的是，上述实施例介绍的多个数据线301可以同时位在所述显示区30A及所述非显示区30B。具体而言，位在所述显示区30A的多个数据线301可用于电性连接所述显示面板30的薄膜晶体管的漏极(未绘示)；而位在所述非显示区30B的多个数据线301则是如上述通过换层处理来减少所述非显示区30B的面积。在一实施例中，位在所述显示区30A的数据线301可根据设计而设置在位在所述显示区30A的所述第一介电层33上、位在所述显示区30A的所述第二介电层35上或位在所述显示区30A的所述第三介电层37上。
请参照图4，本发明另一实施例提出一种显示面板的制造方法40，所述显示面板包含一显示区及一非显示区，所述显示面板的制造方法包含步骤41至47：提供一基板(步骤41)；形成一第一绝缘层在所述基板上(步骤42)；形成一第一金属层在所述第一绝缘层上，其中所述第一金属层包含：一第一栅极层，形成在位于所述显示区的所述第一绝缘层上；及一第一走线层，形成在位于所述非显示区的所述第一绝缘层上(步骤43)；形成一第二绝缘层在所述第一金属层上(步骤44)；形成一第二金属层在所述第二绝缘层上，其中所述第二金属层包含：一第二栅极层，形成在位于所述显示区的所述第二绝缘层上；及一第二走线层，形成在位于所述非显示区的所述第二绝缘层上(步骤45)；形成一介电层在所述第二金属层上(步骤46)；及形成所述多个数据线在所述介电层上，包含:位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层(步骤47)。
在一实施例中，步骤42至47中各个层状结构的形成方式，可通过例如一般半导体工艺所使用的方式(例如沉积、溅镀等)来形成。
在一实施例中，在形成所述介电层之后及所述多个数据线之前，还包含图案化所述介电层及所述第二绝缘层，以形成一第一通孔与一第二通孔，其中所述多个数据线中的至少二个通过所述第一通孔与所述第二通孔分别电性连接所述第一走线层与所述第二走线层。
在一实施例中，本发明实施例的显示面板20可通过所述显示面板的制造方法40来制得。
请参照图5，本发明又一实施例提出一种显示面板的制造方法50，所述显示面板包含一显示区及一非显示区，所述显示面板的制造方法50包含步骤51至58：提供一基板(步骤51)；形成一绝缘层在所述基板上(步骤52)；形成一第一介电层在所述非显示区中的所述绝缘层上(步骤53)；形成一第一数据线在所述非显示区中的所述第一介电层上(步骤54)；形成一第二介电层，在所述非显示区中的所述第一数据线上(步骤55)；形成一第二数据线，在所述非显示区中的所述第二介电层上(步骤56)；形成一第三介电层，在所述非显示区中的所述第二数据线上(步骤57)；及形成一第三数据线，在所述非显示区中的所述第三介电层上(步骤58)。
在一实施例中，步骤52至58中各个层状结构的形成方式，可通过例如一般半导体工艺所使用的方式(例如沉积、溅镀等)来形成。
在一实施例中，本发明实施例的显示面板30可通过所述显示面板的制造方法50来制得。
综上所述，本发明提供一种显示面板及其制造方法，通过将在非显示区的数据线换层的方式，以减少非显示区的面积，进而改善用户的视觉感受。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (12)

  1. 一种显示面板，包含一显示区及一非显示区，其中所述显示面板包含：
    一基板；
    一第一绝缘层，设在所述基板上，其中一缓冲层设在所述第一绝缘层与所述基板之间；
    一第一金属层，设在所述第一绝缘层上，其中所述第一金属层包含：
    一第一栅极层，设在位于所述显示区的所述第一绝缘层上；及
    一第一走线层，设在位于所述非显示区的所述第一绝缘层上；
    一第二绝缘层，设在所述第一金属层上；
    一第二金属层，设在所述第二绝缘层上，其中所述第二金属层包含：
    一第二栅极层，设在位于所述显示区的所述第二绝缘层上；及
    一第二走线层，设在位于所述非显示区的所述第二绝缘层上；
    一介电层，设在所述第二金属层上；及
    多个数据线，设在所述介电层上，包含：
    位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及
    在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层，其中在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
  2. 如权利要求1所述的显示面板，其中在所述非显示区中，所述第一走线层的长度大于所述第二走线层的长度。
  3. 一种显示面板，包含一显示区及一非显示区，其中所述显示面板包含：多个数据线，在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
  4. 如权利要求3所述的显示面板，其中所述显示面板包含：
    一基板；
    一第一绝缘层，设在所述基板上；
    一第一金属层，设在所述第一绝缘层上，其中所述第一金属层包含：
    一第一栅极层，设在位于所述显示区的所述第一绝缘层上；及
    一第一走线层，设在位于所述非显示区的所述第一绝缘层上；
    一第二绝缘层，设在所述第一金属层上；
    一第二金属层，设在所述第二绝缘层上，其中所述第二金属层包含：
    一第二栅极层，设在位于所述显示区的所述第二绝缘层上；及
    一第二走线层，设在位于所述非显示区的所述第二绝缘层上；
    一介电层，设在所述第二金属层上；及
    所述多个数据线，设在所述介电层上，包含：
    位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及
    位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层。
  5. 如权利要求4所述的显示面板，其中在所述非显示区中，所述第一走线层的长度大于所述第二走线层的长度。
  6. 如权利要求3所述的显示面板，其中所述多个数据线包含一第一数据线、一第二数据线以及一第三数据线，以及所述显示面板包含：
    一基板；
    一绝缘层，设在所述基板上；
    一第一介电层，设在所述非显示区中的所述绝缘层上；
    所述第一数据线，设在所述非显示区中的所述第一介电层上；
    一第二介电层，设在所述非显示区中的所述第一数据线上；
    所述第二数据线，设在所述非显示区中的所述第二介电层上；
    一第三介电层，设在所述非显示区中的所述第二数据线上；及
    所述第三数据线，设在所述非显示区中的所述第三介电层上。
  7. 如权利要求6所述的显示面板，其中在所述非显示区中，所述第一数据线的长度小于所述第二数据线的长度以及所述第二数据线的长度小于所述第三数据线的长度。
  8. 如权利要求6所述的显示面板，其中在所述非显示区中，所述第一数据线的长度大于所述第二数据线的长度以及所述第二数据线的长度大于所述第三数据线的长度。
  9. 一种显示面板的制造方法，所述显示面板包含一显示区及一非显示区，其中所述显示面板的制造方法包含：形成多个数据线，其中在所述非显示区中的相邻的所述多个数据线之间具有一高度差。
  10. 如权利要求9所述的显示面板的制造方法，还包含步骤：
    提供一基板；
    形成一第一绝缘层在所述基板上；
    形成一第一金属层在所述第一绝缘层上，其中所述第一金属层包含：
    一第一栅极层，形成在位于所述显示区的所述第一绝缘层上；及
    一第一走线层，形成在位于所述非显示区的所述第一绝缘层上；；
    形成一第二绝缘层在所述第一金属层上；
    形成一第二金属层在所述第二绝缘层上，其中所述第二金属层包含：
    一第二栅极层，形成在位于所述显示区的所述第二绝缘层上；及
    一第二走线层，形成在位于所述非显示区的所述第二绝缘层上；
    形成一介电层在所述第二金属层上；及
    形成所述多个数据线在所述介电层上，包含:
    位在所述显示区的所述多个数据线，电性连接所述第一栅极层；及
    位在所述非显示区的所述多个数据线中的至少二个且在一高度方向上分别朝向所述第一走线层及所述第二走线层弯折，以电性连接所述第一走线层及所述第二走线层。
  11. 如权利要求10所述的显示面板的制造方法，其中在形成所述介电层之后及所述多个数据线之前，还包含图案化所述介电层及所述第二绝缘层，以形成一第一通孔与一第二通孔，其中所述多个数据线中的至少二个通过所述第一通孔与所述第二通孔分别电性连接所述第一走线层与所述第二走线层。
  12. 如权利要求9所述的显示面板的制造方法，其中所述多个数据线包含一第一数据线、一第二数据线以及一第三数据线，以及所述显示面板的制造方法还包含步骤：
    提供一基板；
    形成一绝缘层在所述基板上；
    形成一第一介电层在所述非显示区中的所述绝缘层上；
    形成所述第一数据线在所述非显示区中的所述第一介电层上；
    形成一第二介电层，在所述非显示区中的所述第一数据线上；
    形成所述第二数据线，在所述非显示区中的所述第二介电层上；
    形成一第三介电层，在所述非显示区中的所述第二数据线上；及
    形成所述第三数据线，在所述非显示区中的所述第三介电层上。
PCT/CN2019/072501 2018-12-17 2019-01-21 显示面板及其制造方法 Ceased WO2020124730A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427748A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及显示方法
CN107634086A (zh) * 2017-09-15 2018-01-26 京东方科技集团股份有限公司 一种柔性阵列基板及制备方法、显示装置
CN107994055A (zh) * 2017-11-10 2018-05-04 武汉华星光电半导体显示技术有限公司 可弯折显示面板及其制作方法
US20180247993A1 (en) * 2017-02-24 2018-08-30 Japan Display Inc. Display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427748A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及显示方法
US20180247993A1 (en) * 2017-02-24 2018-08-30 Japan Display Inc. Display device
CN107634086A (zh) * 2017-09-15 2018-01-26 京东方科技集团股份有限公司 一种柔性阵列基板及制备方法、显示装置
CN107994055A (zh) * 2017-11-10 2018-05-04 武汉华星光电半导体显示技术有限公司 可弯折显示面板及其制作方法

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