WO2020119738A1 - 忆阻器及其制作方法 - Google Patents

忆阻器及其制作方法 Download PDF

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WO2020119738A1
WO2020119738A1 PCT/CN2019/124682 CN2019124682W WO2020119738A1 WO 2020119738 A1 WO2020119738 A1 WO 2020119738A1 CN 2019124682 W CN2019124682 W CN 2019124682W WO 2020119738 A1 WO2020119738 A1 WO 2020119738A1
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electrode
functional layer
memristor
layer
substrate
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English (en)
French (fr)
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王恒
戴阳
陶华露
易成汉
李文杰
钟国华
杨春雷
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深圳先进技术研究院
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes

Definitions

  • the invention belongs to the field of semiconductor devices, in particular, it relates to a memristor and a manufacturing method thereof.
  • Synaptic plasticity is an important molecular basis for learning and memory, so synaptic bionics and synaptic plasticity simulation are considered to be the first step in achieving an efficient brain-like artificial neural network.
  • Memristor as the fourth basic circuit component, has unique non-synaptic non-linear electrical transmission characteristics. Its emergence and development provide the possibility to achieve this goal. Synapses and memristors have very similar transmission characteristics. A single memristor may simulate the basic function of a synapse; it is simulated with a complementary metal oxide semiconductor (CMOS) that is traditionally combined by multiple transistors and capacitors. Compared to a synapse, a memristor reduces a lot of energy consumption and also reduces the complexity of an integrated circuit.
  • CMOS complementary metal oxide semiconductor
  • a memristor is a non-linear, passive, double-ended electrical device that has or exhibits a transient resistance level as a function of bias history. Its greatest characteristic is that its resistance value is not constant, but varies with applied voltage or The magnitude and polarity of the current change, and these changes are non-volatile and can be retained for a long period of time.
  • the traditional memristor usually adopts a sandwich structure of top electrode, intermediate dielectric layer and bottom electrode in order from top to bottom. It is usually prepared by vacuum vapor deposition such as electron beam evaporation, thermal evaporation and magnetron sputtering. The voltage between the metal electrode layers changes the resistance to achieve a low resistance state and a high resistance state, and the preparation process is relatively complicated.
  • the research of memristors is mainly based on the system of oxide materials, and its working mechanism mainly depends on the migration and aggregation of ions and oxygen vacancies under the action of an electric field.
  • the process based on ion and oxygen vacancy migration is slow, it is difficult to form a conductive wire between the top electrode and the bottom electrode, which hinders the realization of the low resistance state, and the high switching ratio cannot be obtained.
  • the large set voltage causes large power consumption, and is affected by thermal effects, which results in poor stability, great randomness, difficult to control, and easy to be affected by the external environment, which limits the development of memristors.
  • the present invention provides a memristor and a manufacturing method thereof.
  • the memristor is provided with two parts of electrode functional layers on the same plane, and uses nanowires or nanoribbons to achieve both
  • the electronic conduction between can enable the memristor to switch between high resistance and low resistance under the positive and negative voltages of the cycle, and obtain a high HRS/LRS (high resistance value/low resistance value) value.
  • a memristor includes a substrate and a spaced first electrode functional layer and second electrode functional layer disposed on the substrate; wherein, the first electrode functional layer and the second electrode functional layer Connected by nanowires or nanoribbons to achieve electronic conduction.
  • the minimum width between the first electrode functional layer and the second electrode functional layer is 50 nm to 50 ⁇ m.
  • the top surface of the first electrode functional layer away from the substrate and the top surface of the second electrode functional layer away from the substrate are flush, and the top surface of the nanowire or nanoribbon Not lower than the top surfaces of the first electrode functional layer and the second electrode functional layer.
  • the thickness of the first electrode functional layer and the second electrode functional layer are both 1 nm to 600 nm; the thickness of the nanowire or nanoribbon is 1 nm to 1000 nm.
  • the material of the nanowires or nanoribbons is Ge 2 Sb 2-x Bi x Te 5 ; wherein, 0 ⁇ x ⁇ 2.
  • the materials of the first electrode functional layer and the second electrode functional layer are all selected from any one of Ag, Cu, Al, Zn, Fe, Mg, Na, Sn.
  • the memristor further includes a first conductive electrode disposed between the substrate and the first electrode functional layer, and a substrate disposed between the substrate and the second electrode functional layer Of the second conductive electrode.
  • the materials of the first conductive electrode and the second conductive electrode are selected from Pt, Ni, Mn, Mo, Nb, Pd, Ru, RuO 2 , Ta, TaN, W, WN, Ti, and titanium Any one of the oxides; and/or, the thickness of the first conductive electrode and the second conductive electrode are both 1 nm to 600 nm.
  • the memristor further includes a first electrode adsorption layer disposed between the substrate and the first conductive electrode, and a substrate disposed between the substrate and the second conductive electrode The second electrode adsorption layer.
  • materials of the first electrode adsorption layer and the second electrode adsorption layer are selected from any one of Cr, Ti, and Ni; and/or, the first electrode adsorption layer and the first The thickness of the two-electrode adsorption layer is 0.1 nm to 100 nm.
  • the memristor further includes a resistance change layer disposed around the first electrode functional layer and the second electrode functional layer.
  • the material of the resistance change layer is Ge 2 Sb 2-x Bi x Te 5 ; wherein, 0 ⁇ x ⁇ 2.
  • the top surface of the resistance change layer away from the substrate is flush with the top surface of the nanowire or nanoribbon.
  • Another object of the present invention is to provide a method for manufacturing a memristor as described above, which includes the steps of:
  • a femtosecond laser is used to scribe the resistive source layer between the first electrode functional layer and the second electrode functional layer, and the first electrode functional layer and the second electrode functional layer Between the formation of nanowires or nanoribbons;
  • the switching ratio of the memristor is required to be not less than 1000, remove the resistive source layer in the non-scribed area;
  • the switching ratio of the memristor is required to be less than 1000, the resistive source layer in the non-scribed area is not removed or partially removed.
  • the present invention can ensure that the memristor is under a positive and negative voltage of the cycle by providing two partly spaced electrode functional layers on the same plane on the substrate and using nanowires or nanoribbons to achieve electronic conduction between the two The high resistance and low resistance are switched, and a high HRS/LRS (high resistance value/low resistance value) value is obtained.
  • the memristor of the present invention changes the traditional "sandwich structure" memristor.
  • the manufacturing method of the memristor with a brand-new structure of the invention simplifies the process and also makes the testing of the device more convenient.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first memristor according to the present invention
  • FIG. 2 is a schematic cross-sectional structure diagram of a second memristor according to the present invention.
  • FIG. 3 is a schematic cross-sectional structure diagram of a third memristor according to the present invention.
  • 4 to 6 are process flow diagrams of the first method for manufacturing a memristor according to the present invention.
  • 7-8 are partial process flow diagrams of the second method for manufacturing a memristor according to the present invention.
  • 9-11 are partial process flow diagrams of the third method of manufacturing a memristor according to the present invention.
  • FIG. 13 is a current-voltage characteristic curve of a memristor according to Embodiment 2 of the present invention.
  • the present invention provides a specific new structure memristor.
  • the present invention provides a memristor of a first structure, which includes a substrate 1 and spaced first electrode functional layers 21 and second electrode functional layers 22 disposed on the substrate 1; wherein, The first electrode functional layer 21 and the second electrode functional layer 22 are connected by the nano-function part 3 to realize electronic conduction.
  • the materials of the first electrode functional layer 21 and the second electrode functional layer 22 may be specifically selected from any one of Ag, Cu, Al, Zn, Fe, Mg, Na, and Sn.
  • the metal ions in the first electrode functional layer 21 and the second electrode functional layer 22 can better form a conductive path through the nano-functional portion 3, thereby speeding up the formation of the low resistance state of the memristor and enhancing the device Cyclic stability greatly improves the resistance change rate (that is, the switching ratio) and improves the performance of the memristor.
  • the present invention also provides a second structure memristor.
  • the memristor of the second structure on the basis of the memristor of the first structure shown in FIG. 1, further includes a substrate disposed between the substrate 1 and the first electrode functional layer 21 The first conductive electrode 41 and the second conductive electrode 42 provided between the substrate 1 and the second electrode functional layer 22.
  • the materials of the first conductive electrode 41 and the second conductive electrode 42 may be specifically selected from Pt, Ni, Mn, Mo, Nb, Pd, Ru, RuO 2 , Ta, TaN, W, WN, Ti, and titanium Any one of oxides.
  • the thickness of the first conductive electrode 41 and the second conductive electrode 42 may be controlled to be 1 nm to 600 nm.
  • the present invention also provides a third structure of the memristor.
  • the third structure of the memristor is based on the second structure of the memristor shown in FIG. 2 and further includes a third structure disposed between the substrate 1 and the first conductive electrode 41.
  • the materials of the first electrode adsorption layer 51 and the second electrode adsorption layer 52 may be specifically selected from any one of Cr, Ti, and Ni.
  • the thickness of the first electrode adsorption layer 51 and the second electrode adsorption layer 52 may be controlled to be 0.1 nm to 100 nm.
  • the memristor of the present invention forms two parts of the conductive functional layer separated and unconnected on the substrate 1.
  • the conductive functional layer is specifically an electrode functional layer 21, 22; or specifically, conductive electrodes 41, 42 and electrode functional layers 21, 22 that are sequentially stacked, or electrode adsorption layers 51, 52 and conductive electrodes that are sequentially stacked. 41, 42 and electrode functional layers 21, 22.
  • the memristors of the above three structures further include a resistance change layer 6 surrounding the electrode functional layers 21 and 22.
  • the nano-functional part 3 specifically refers to a nano wire or a nano ribbon.
  • the electrode functional layers 21 and 22 need not limit the specific shape, but the minimum width between the two is controlled to be 50 nm to 50 ⁇ m. This is because if the distance between the two is too close, it is easy to cause a short circuit, but if the distance between the two is too far, a large voltage needs to be applied during use, which affects the performance of the device.
  • the electrode functional layers 21 and 22 are simultaneously fabricated, the conductive electrodes 41 and 42 are simultaneously fabricated, and the electrode adsorption layers 51 and 52 are simultaneously fabricated; therefore, the first electrode functional layer 21 is far away
  • the top surface of the substrate 1 and the top surface of the second electrode functional layer 22 away from the substrate 1 are flush, and the top surface of the nano-functional portion 3 is not lower than the top surfaces of the electrode functional layers 21 and 22.
  • control electrode functional layers 21 and 22 may be 1 nm to 600 nm, and the thickness of the nano-functional portion 3 may be 1 nm to 1000 nm.
  • the material of the nano-functional part 3 is Ge 2 Sb 2-x Bi x Te 5 (0 ⁇ x ⁇ 2).
  • the resistance change layer 6 and the portion for forming the nano-function part 3 are manufactured at the same time, so the material of the resistance change layer 6 and the nano-function part 3 are also the same, which is Ge 2 Sb 2-x Bi x Te 5 (0 ⁇ x ⁇ 2).
  • the top surface of the resistance change layer 6 away from the substrate 1 is flush with the top surface of the nano-function portion 3.
  • the manufacturing method of the first structure memristor of the present invention includes the following steps:
  • step S1 a spaced first electrode functional layer 21 and second electrode functional layer 22 are formed on the substrate 1; as shown in FIG. 4.
  • the substrate 1 is first pretreated to ensure the cleanliness of its surface; and then the electrode functional layers 21 and 22 are formed on it.
  • the substrate 1 is ultrasonically cleaned with acetone, ethanol and deionized water in sequence for about 15 minutes, and then the surface is blown dry with nitrogen.
  • the substrate 1 may be glass or a silicon wafer containing a silicon dioxide layer; it is not specifically limited in the present invention.
  • the production of the electrode functional layers 21 and 22 can be first patterned using photoresist and mask to form a patterned area for manufacturing the electrode functional layers 21 and 22, and the periphery of the patterned area is also coated There is photoresist; then it is deposited in the patterned area, so that the electrode functional layers 21, 22 are formed on the substrate 1; finally, the photoresist around the electrode functional layers 21, 22 can be removed.
  • step S2 a resistive material is deposited at least between the first electrode functional layer 21 and the second electrode functional layer 22 to form a resistive source layer 6a; as shown in FIG. 5.
  • a resistive material is deposited on the electrode functional layers 21 and 22 to form a resistive source layer 6a between the two, preferably surrounding the two; and the top surface of the resistive source layer 6a is preferably controlled to be higher than the electrode The top surfaces of the functional layers 21, 22 to completely cover the two.
  • step S3 a femtosecond laser is used to scribe the resistive source layer 6a between the first electrode functional layer 21 and the second electrode functional layer 22, and the first electrode functional layer 21 and the second electrode functional layer 22 The nano function part 3 is formed between them; as shown in FIG. 6.
  • the switching ratio of the memristor is required to selectively remove the resistive source layer in the non-scribed area. Specifically, if the switching ratio of the memristor is required to be not less than 1000, the resistive source layer of the non-scribed area is removed; and if the switching ratio of the memristor is required to be less than 1000, the non-scribed line is not removed or partially removed Regional resistance source layer.
  • the scribe line of the femtosecond laser causes the resistive source layer 6a between the electrode functional layers 21 and 22 to form one or more nanowires or nanoribbon nanofunctions 3, thereby ensuring the electrode functional layers 21 and 22
  • the metal ions inside can better form a conductive path through the nano-function part 3, thereby accelerating the formation of the low resistance state of the memristor, and enhancing the cycle stability of the device, greatly improving the resistance change rate (ie, the switching ratio), Improve the performance of the memristor.
  • the scribing operation of the femtosecond laser also irradiates the resistive source layer 6a with ultraviolet light to provide energy for the resistive source layer 6a to obtain better device performance.
  • step S1 it specifically includes first forming spaced first conductive electrodes 41 and second conductive electrodes 42 on the substrate 1 ; As shown in Figure 7. Then, a first electrode functional layer 21 is formed on the first conductive electrode 41, and a second electrode functional layer 22 is formed on the second conductive electrode 42; as shown in FIG.
  • step S1 in order to fabricate the above-mentioned third structure of the memristor of the present invention, it specifically includes first forming a spaced first electrode adsorption layer 51 and second electrode on the substrate 1 Adsorption layer 52; as shown in Figure 9. Then, a first conductive electrode 41 is formed on the first electrode adsorption layer 51, and a second conductive electrode 42 is formed on the second electrode adsorption layer 52; as shown in FIG. Finally, a first electrode functional layer 21 is formed on the first conductive electrode 41, and a second electrode functional layer 22 is formed on the second conductive electrode 42; as shown in FIG.
  • the rest of the steps refer to the above-mentioned method of manufacturing the first structure of the memristor, and different structures of memristors can be obtained respectively.
  • the source material of each structural layer involved in the above steps corresponds to the material of each structural layer; if the material of the first electrode functional layer 21 in a memristor is Mg, that is, its first electrode functional layer During the production process of 21, Mg can be deposited.
  • This embodiment provides a memristor as shown in FIG. 3.
  • the material of the substrate 1 is a silicon wafer with a single polished single oxide layer with a size of about 4 inches.
  • the first electrode adsorption layer 51 and the second electrode adsorption layer 52 are both 5 nm thick chromium thin films; the first conductive electrode 41 and the second conductive electrode 42 are both 50 nm thick gold thin films, the first electrode functional layer 21 and the second electrode
  • the functional layer 22 is a 20-nm-thick silver thin film; the resistive layer 6 and the nano-functional portion 3 are both 100-nm-thick Ge 2 Sb 2 Te 5 .
  • the narrowest distance between the first electrode functional layer 21 and the second electrode functional layer 22 is 5 ⁇ m.
  • the electron beam evaporation process is used to prepare a 5 nm thick chromium film as the electrode adsorption layer 51, 52; then, the thermal evaporation process is used to prepare a 50 nm thick gold film on the electrode adsorption layer 51, 52 as Conductive electrodes 41, 42; again, using a thermal evaporation process to prepare a 20 nm thick silver film on the conductive electrodes 41, 42 as the electrode functional layers 21, 22; the working pressure of electron beam evaporation in this embodiment is controlled to 5 ⁇ 10 -3 Pa; Finally, immerse in acetone for 15 min to remove the photoresist covering the other areas except the patterned area.
  • a magnetron sputtering method is used to deposit a resistive material Ge 2 Sb 2 Te 5 with a thickness of 100 nm on the electrode functional layers 21 and 22 as the resistive source layer 6a; specifically, the resistive material Ge 2 Sb 2 Te 5 was used as the sputtering target, argon gas was used as the sputtering atmosphere, the substrate temperature was room temperature, the sputtering power was 40 W, and the time was 10 minutes; it was sufficient to perform the sputtering treatment under vacuum oxygen-free atmosphere at room temperature.
  • the shortest gap between the electrode functional layers 21 and 22 formed in this embodiment is 5 ⁇ m; it is placed under a femtosecond laser with a laser power of 0.47 mW.
  • a parameter with a scanning step size of 0.1 ⁇ m scribes a 10 ⁇ m nanowire across the resistive source layer 6 a between the electrode functional layers 21 and 22 on the electrode functional layers 21 and 22 to obtain the memristor in this embodiment.
  • the performance of the memristor of this embodiment is tested. Specifically, the memristor is tested in a glove box. The current-voltage characteristic curve is shown in FIG. 12.
  • the memristor of this embodiment starts from -4V to 3.8V.
  • its resistance exhibits a low resistance state; while the voltage starts from 3.8V, as When the voltage decreases, the resistance increases sharply, and the high impedance state is maintained until the voltage drops to -4V. Therefore, the memristor of this embodiment has excellent performance such as high resistance change rate (switching ratio can reach 8000), high cycle stability (switching ratio fluctuates little with the increase of cycle number), and fast operation speed.
  • Embodiment 2 differs from Embodiment 1 in that in the memristor of Embodiment 2, the first conductive electrode 41 and the second conductive electrode 42 are both 100-nm-thick gold thin films, and the first electrode functional layer 21 and the first The two-electrode functional layer 22 is a 50-nm-thick copper thin film; and the narrowest distance between the first electrode functional layer 21 and the second electrode functional layer 22 is 10 ⁇ m.
  • the manufacturing method of the memristor in this embodiment is different from the manufacturing method in Embodiment 1 in that in step (5), the electrode is controlled by a parameter with a laser power of 0.62 mW and a scanning step of 0.1 ⁇ m.
  • the resistive source layer 6a between the functional layers 21 and 22 is scribed with a 20 ⁇ m nanowire overlapping on the electrode functional layers 21 and 22; for the rest, refer to the description in Embodiment 1 to obtain the memristor in this embodiment.
  • the performance of the memristor provided in this embodiment is tested. Specifically, first, the memristor is immersed in a 25% (wt%) tetramethylammonium hydroxide solution (TMAH) for 50 min to remove the other resistance source layer 6a around the nano-functional part 3; then The surface of the memristor away from the substrate 1 is coated with a layer of 100 nm Al 2 O 3 as an isolation layer to prevent it from oxidizing during the test; finally, the above test is performed in the glove box, and its current-voltage characteristic curve As shown in Figure 13.
  • TMAH tetramethylammonium hydroxide solution
  • the memristor of this embodiment starts from -5.9V to 5.8V.
  • its resistance exhibits a low resistance state; while the voltage starts from 3.8V, as When the voltage decreases, the resistance increases sharply, and the high resistance state is maintained until the voltage drops to -5.9V. Therefore, the memristor of this embodiment has excellent performance such as high resistance change rate (switching ratio can reach 5000), high cycle stability (switching ratio fluctuates little with the increase of cycle number), and fast operation speed.

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Abstract

一种忆阻器及其制备方法，忆阻器包括衬底（1）以及设置在衬底上的间隔的第一电极功能层（21）和第二电极功能层（22）；其中，第一电极功能层和第二电极功能层之间通过纳米线或纳米带连接以实现电子导通。该结构的忆阻器改变了传统的"三明治结构"的忆阻器，通过在衬底上的同一平面上设置两部分间隔的电极功能层，并利用纳米线或纳米带实现二者之间的电子导通，能够保证该忆阻器在循环的正负电压下进行高电阻和低电阻切换，并且得到高电阻值/低电阻值(HRS/LRS)。该忆阻器的制作方法简化了工艺，也使器件的测试更为便利。

Description

忆阻器及其制作方法 技术领域
本发明属于半导体器件领域，具体来讲，涉及一种忆阻器及其制作方法。
背景技术
突触可塑性是学习与记忆的重要分子基础，因此突触仿生和突触可塑性模拟被认为是实现高效类脑人工神经网络的第一步。忆阻器作为第四种基本电路元件，拥有独特的类神经突触非线性电学传输特性，它的出现和发展为实现这一目标提供了可能。突触和忆阻器有着十分相似的传输特性，单个忆阻器便可能模拟一个突触的基本功能；与传统使用的由多个晶体管和电容器相结合的互补金属氧化物半导体(CMOS)来模拟一个突触相比，忆阻器减少了很多能耗，也降低了集成电路的复杂性。
忆阻器是非线性、无源、双端电学器件，其具有或展现作为偏置历史的函数的瞬态电阻水平，其最大的特点为：它的电阻值非恒定，而是随着外加电压或电流的大小、极性而发生变化，并且这些变化具有非易失性，可以在很长一段时间内被保留下来。
传统的忆阻器通常是采用从上至下依次为顶电极、中间介质层、底电极的三明治结构，通常采用电子束蒸发、热蒸发、磁控溅射等真空气相沉积制备，通过调节两个金属电极层之间的电压来改变电阻，实现低阻态和高阻态，制备工艺较为复杂。目前忆阻器的研究主要基于氧化物材料的体系，其工作机理主要依赖离子、氧空位在电场作用下迁移和聚集。然而，基于离子、氧空位迁移的过程速度较慢，很难在顶电极和底电极之间形成导电丝，给低阻态的实现造成了阻碍，得不到很高的开关比，所需偏置电压很大造成功耗大，且受到热效应的影响而使得稳定性较差，随机性很大，难以控制，且很容易受到外界环境的影响，这些都限制了忆阻器的发展。
发明内容
为解决上述现有技术存在的问题，本发明提供了一种忆阻器及其制作方法，该忆阻器通过设置同一平面上的两部分电极功能层，并利用纳米线或纳米带实 现二者之间的电子导通，能够使该忆阻器在循环的正负电压下进行高电阻和低电阻切换，并且得到高HRS/LRS(高电阻值/低电阻值)值。
为了达到上述发明目的，本发明采用了如下的技术方案：
一种忆阻器，包括衬底以及设置在所述衬底上的间隔的第一电极功能层和第二电极功能层；其中，所述第一电极功能层和所述第二电极功能层之间通过纳米线或纳米带连接以实现电子导通。
可选地，所述第一电极功能层和所述第二电极功能层之间的最小宽度为50nm～50μm。
可选地，所述第一电极功能层远离所述衬底的顶面和所述第二电极功能层的远离所述衬底的顶面齐平，并且所述纳米线或纳米带的顶面不低于所述第一电极功能层及所述第二电极功能层的顶面。
可选地，所述第一电极功能层和所述第二电极功能层的厚度均为1nm～600nm；所述纳米线或纳米带的厚度为1nm～1000nm。
可选地，所述纳米线或纳米带的材料为Ge 2Sb 2-xBi xTe 5；其中，0≤x≤2。
可选地，所述第一电极功能层和所述第二电极功能层的材料均选自Ag、Cu、Al、Zn、Fe、Mg、Na、Sn中的任意一种。
可选地，所述忆阻器还包括设置在所述衬底和所述第一电极功能层之间的第一导电电极、以及设置在所述衬底和所述第二电极功能层之间的第二导电电极。
可选地，所述第一导电电极和所述第二导电电极的材料均选自Pt、Ni、Mn、Mo、Nb、Pd、Ru、RuO 2、Ta、TaN、W、WN、Ti及钛的氧化物中的任意一种；和/或，所述第一导电电极和所述第二导电电极的厚度均为1nm～600nm。
可选地，所述忆阻器还包括设置在所述衬底和所述第一导电电极之间的第一电极吸附层、以及设置在所述衬底和所述第二导电电极之间的第二电极吸附层。
可选地，所述第一电极吸附层和所述第二电极吸附层的材料均选自Cr、Ti、Ni中的任意一种；和/或，所述第一电极吸附层和所述第二电极吸附层的 厚度均为0.1nm～100nm。
可选地，所述忆阻器还包括环绕设置于所述第一电极功能层和所述第二电极功能层周围的阻变层。
可选地，所述阻变层的材料为Ge 2Sb 2-xBi xTe 5；其中，0≤x≤2。
可选地，所述阻变层的远离所述衬底的顶面与所述纳米线或纳米带的顶面齐平。
本发明的另一目的还在于提供了一种如上任一所述的忆阻器的制作方法，其包括步骤：
S1、在衬底上制作间隔的第一电极功能层和第二电极功能层；
S2、至少在所述第一电极功能层和所述第二电极功能层之间沉积阻变材料，以形成阻变源层；
S3、采用飞秒激光于所述第一电极功能层和所述第二电极功能层之间的阻变源层上进行划线，在所述第一电极功能层和所述第二电极功能层之间形成纳米线或纳米带；其中，
若要求所述忆阻器的开关比不低于1000，则去除非划线区域的阻变源层；
若要求所述忆阻器的开关比小于1000，则不去除或部分去除非划线区域的阻变源层。
本发明通过在衬底上的同一平面上设置两部分间隔的电极功能层，并利用纳米线或纳米带实现二者之间的电子导通，能够保证该忆阻器在循环的正负电压下进行高电阻和低电阻切换，并且得到高HRS/LRS(高电阻值/低电阻值)值。本发明的忆阻器改变了传统的“三明治结构”的忆阻器。本发明的具有全新结构的忆阻器的制作方法简化了工艺，也使器件的测试更为便利。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的第一种忆阻器的剖面结构示意图；
图2是根据本发明的第二种忆阻器的剖面结构示意图；
图3是根据本发明的第三种忆阻器的剖面结构示意图；
图4-图6是根据本发明的第一种忆阻器的制作方法的工艺流程图；
图7-图8是根据本发明的第二种忆阻器的制作方法的局部工艺流程图；
图9-图11是根据本发明的第三种忆阻器的制作方法的局部工艺流程图；
图12是根据本发明的实施例1的忆阻器电流-电压特性曲线；
图13是根据本发明的实施例2的忆阻器电流-电压特性曲线。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，为了清楚起见，可以夸大元件的形状和尺寸，并且相同的标号将始终被用于表示相同或相似的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
基于现有技术中忆阻器一般所具有的“三明治结构”，其将导致难以在顶电极和底电极之间形成导电丝，从而给低阻态的实现造成阻碍，得不到很高的开关比，所需偏置电压很大造成功耗大，且受到热效应的影响而使得稳定性较差，随机性很大，难以控制，且很容易受到外界环境的影响。为此，本发明提供了具体全新结构的忆阻器。
具体参阅图1，本发明提供了第一种结构的忆阻器，其包括衬底1以及设置在该衬底1上的间隔的第一电极功能层21和第二电极功能层22；其中，第一电极功能层21和第二电极功能层22之间通过纳米功能部3连接以实现电子导通。
在该忆阻器中，第一电极功能层21和第二电极功能层22的材料可具体选自Ag、Cu、Al、Zn、Fe、Mg、Na、Sn中的任意一种。
如此，该第一电极功能层21和第二电极功能层22内的金属离子能够更好地通过纳米功能部3形成导电通路，从而加快了该忆阻器低阻态的形成、并增强了器件循环稳定性，大大提高了电阻变化率(即开关比)，提升了该忆阻器的性能。
根据第一电极功能层21及第二电极功能层22的具体材料选择，为了获得更好的导电效果，本发明还提供了第二种结构的忆阻器。
具体参阅图2，该第二种结构的忆阻器在与图1所示的第一种结构的忆阻器的基础上，还包括设置在衬底1和第一电极功能层21之间的第一导电电极41、以及设置在衬底1和第二电极功能层22之间的第二导电电极42。
可选择地，第一导电电极41和第二导电电极42的材料可具体选自Pt、Ni、Mn、Mo、Nb、Pd、Ru、RuO 2、Ta、TaN、W、WN、Ti及钛的氧化物中的任意一种。
可选择地，控制第一导电电极41和第二导电电极42的厚度均为1nm～600nm即可。
进一步地，根据第一导电电极41和第二导电电极42的具体材料选择，为了防止二者与衬底1的附着力不够、易于脱落，本发明还提供了第三种结构的忆阻器。
具体参阅图3，该第三种结构的忆阻器在与图2所示的第二种结构的忆阻器的基础上，还包括设置在衬底1和第一导电电极41之间的第一电极吸附层51、以及设置在衬底1和第二导电电极42之间的第二电极吸附层52。
可选择地，第一电极吸附层51和第二电极吸附层52的材料可具体选自Cr、Ti、Ni中的任意一种。
可选择地，控制第一电极吸附层51和第二电极吸附层52的厚度均为0.1nm～100nm即可。
换句话说，本发明的忆阻器在衬底1上形成了相互分隔不连接的两部分导电功能层。该导电功能层具体为电极功能层21、22；或具体为依次叠层的导电电极41、42和电极功能层21、22，或具体为依次叠层的电极吸附层51、52，以及导电电极41、42和电极功能层21、22。
可选择地，在上述三种结构的忆阻器中，还包括环绕设置在电极功能层21、 22周围的阻变层6。
具体来讲，参阅图1-图3，本发明提供的上述三种不同结构的忆阻器中，纳米功能部3具体指纳米线或纳米带。
并且，上述电极功能层21、22无需限制具体的形状，但二者之间的最小宽度控制为50nm～50μm。这是因为，若二者之间距离太近，则易导致短路，但若二者之间距离太远，则在使用过程中需要施加较大的电压，影响器件性能。
进一步地，考虑该忆阻器的制作工艺的方便，电极功能层21、22同时制作，导电电极41、42同时制作，电极吸附层51、52同时制作；因此，第一电极功能层21的远离衬底1的顶面和第二电极功能层22的远离衬底1的顶面齐平，并且纳米功能部3的顶面不低于电极功能层21、22的顶面。
进一步地，控制电极功能层21、22的厚度均为1nm～600nm、纳米功能部3的厚度为1nm～1000nm即可。
在本发明的忆阻器中，纳米功能部3的材料为Ge 2Sb 2-xBi xTe 5(0≤x≤2)。
基于本发明的忆阻器的制作工艺的方便，优选阻变层6与用于形成纳米功能部3的部分同时制作，因此阻变层6的材料与纳米功能部3的材料也相同，为Ge 2Sb 2-xBi xTe 5(0≤x≤2)。由此，阻变层6的远离衬底1的顶面即与纳米功能部3的顶面齐平。
以下将参照附图对本发明的上述忆阻器的制作方法进行详细的描述。
本发明的上述第一种结构的忆阻器的制作方法包括下述步骤：
在步骤S1中，在衬底1上制作间隔的第一电极功能层21和第二电极功能层22；如图4所示。
优选对衬底1首先进行预处理，以保证其表面的清洁；然后再在其上方制作电极功能层21、22。
一般来讲，依次使用丙酮、乙醇和去离子水分别超声清洗该衬底1大约15min，再用氮气吹干其表面即可。
所述衬底1可以是玻璃，也可以是含二氧化硅层的硅片；本发明中不作具体限定。
电极功能层21、22的制作可以首先采用光刻胶及掩膜版进行图形化处理， 以形成用于制作电极功能层21、22的图形化区域，而该图形化区域的周边均还涂布有光刻胶；然后在图形化区域沉积，从而在衬底1上形成了电极功能层21、22；最后去除电极功能层21、22周边的光刻胶即可。
在步骤S2中，至少在第一电极功能层21和第二电极功能层22之间沉积阻变材料，以形成阻变源层6a；如图5所示。
具体来讲，在电极功能层21、22上沉积阻变材料，以在二者之间、优选环绕二者的阻变源层6a；并优选控制该阻变源层6a的顶面高于电极功能层21、22的顶面，以将二者完全覆盖。
在步骤S3中，采用飞秒激光于第一电极功能层21和第二电极功能层22之间的阻变源层6a上进行划线，在第一电极功能层21和第二电极功能层22之间形成纳米功能部3；如图6所示。
需要说明的是，当进行飞秒激光的划线之后，会形成划线区域和非划线区域；其中，划线区域即所述纳米功能部3，而针对非划线区域，则根据所要制作的忆阻器的开关比要求，来选择性地去除非划线区域的阻变源层。具体来讲，若要求忆阻器的开关比不低于1000，则去除非划线区域的阻变源层；而若要求忆阻器的开关比小于1000，则不去除或部分去除非划线区域的阻变源层。
如此，即通过飞秒激光的划线使得电极功能层21、22之间的阻变源层6a形成了一条或多条纳米线或纳米带的纳米功能部3，从而保证电极功能层21、22内的金属离子能够更好地通过纳米功能部3形成导电通路，从而加快了该忆阻器低阻态的形成、并增强了器件循环稳定性，大大提高了电阻变化率(即开关比)，提升了该忆阻器的性能。与此同时，飞秒激光的划线操作还对阻变源层6a照射了紫外光，为阻变源层6a提供了能量，以获得更好的器件性能。
在上述步骤的基础上，为了制作本发明的上述第二种结构的忆阻器，其在步骤S1中，具体包括首先在衬底1上制作间隔的第一导电电极41和第二导电电极42；如图7所示。然后在第一导电电极41上制作第一电极功能层21，在第二导电电极42上制作第二电极功能层22；如图8所示。
进一步在上述步骤的基础上，为了制作本发明的上述第三种结构的忆阻器，其在步骤S1中，具体包括首先在衬底1上制作间隔的第一电极吸附层51和第二电极吸附层52；如图9所示。然后在第一电极吸附层51上制作第一导电电 极41，在第二电极吸附层52上制作第二导电电极42；如图10所示。最后在第一导电电极41上制作第一电极功能层21，在第二导电电极42上制作第二电极功能层22；如图11所示。
在上述第二种结构和第三种结构的忆阻器的制作方法中，其余步骤参照上述第一种结构的忆阻器的制备方法所述，可分别对应获得不同结构的忆阻器。
进一步地，上述步骤中所涉及的各结构层的源材料均与每一结构层的材料对应相同；如某忆阻器中第一电极功能层21的材料为Mg，即其第一电极功能层21的制作过程中，即沉积Mg即可。
以下将通过具体的实施例来说明本发明的上述忆阻器及其制作方法，但本发明并不限制于此；下述实施例仅是本发明所要求保护的忆阻器及其制作方法的具体示例。
实施例1
本实施例提供了一种如图3所示的忆阻器。
在本实施例的忆阻器中，衬底1的材料为尺寸规格为4英寸左右的单抛单氧化层的硅片。第一电极吸附层51和第二电极吸附层52均为5nm厚的铬薄膜；第一导电电极41和第二导电电极42均为50nm厚的金薄膜，第一电极功能层21和第二电极功能层22均为20nm厚的银薄膜；阻变层6和纳米功能部3均为100nm厚的Ge 2Sb 2Te 5。
在本实施例的忆阻器中，其第一电极功能层21和第二电极功能层22之间的最窄间距为5μm。
以下具体描述本实施例的忆阻器的制作方法。
(1)提供一衬底1，并对该衬底1进行预处理；具体为依次使用丙酮、酒精和去离子水分别对衬底1进行约15min的超声清洗，并用氮气吹干。
(2)在衬底1上旋涂光刻胶NR9-1000p，于150℃下前烘3min，选择对称电极掩模板，利用光刻机紫外曝光40s，于100℃下后烘3min，然后于DPD-200中显影10s～15s，利用剥离工艺形成用于形成两部分导电功能层的图形化区域。
(3)首先，利用电子束蒸发工艺在图形化区域上制备5nm厚的铬薄膜作 为电极吸附层51、52；然后，利用热蒸发工艺在电极吸附层51、52上制备50nm厚的金薄膜作为导电电极41、42；再次，利用热蒸发工艺在导电电极41、42上制备20nm厚的银薄膜作为电极功能层21、22；本实施例中电子束蒸发的工作压强控制为5×10 -3Pa；最后，利用丙酮浸泡15min以去除覆盖图形化区域外其他区域的光刻胶。
(4)采用磁控溅射的方法，在电极功能层21、22上沉积100nm厚的阻变材料Ge 2Sb 2Te 5以作为阻变源层6a；具体来讲，以阻变材料Ge 2Sb 2Te 5作为溅射靶材，以氩气作为溅射气氛、衬底温度为室温、溅射功率为40W、时间10min；在真空无氧气氛中室温条件下进行溅射处理即可。
(5)依据选定的对称电极掩膜版的尺寸，本实施例形成的电极功能层21、22之间的最短间隙为5μm；将其置于飞秒激光器下，用激光功率为0.47mW、扫描步长0.1μm的参数将电极功能层21、22之间的阻变源层6a划一条10μm的纳米线搭接在电极功能层21、22上，即获得本实施例中的忆阻器。
对本实施例的忆阻器的性能进行测试，具体来讲，将该忆阻器于手套箱中进行上述测试，其电流-电压特性曲线如图12所示。
从图12中可以看出，本实施例的忆阻器从-4V开始一直到3.8V，在有电压施加在该器件上时，其电阻呈现低阻态；而电压从3.8V开始，随着电压的减小其电阻骤增，并一直保持高阻态直到电压减到-4V。因此，本实施例的忆阻器具有高电阻变化率(开关比可达到8000)、高循环稳定性(开关比随着循环次数增加波动很小)和操作速度快等优异性能。
实施例2
在实施例2的描述中，与实施例1的相同之处在此不再赘述，只描述与实施例1的不同之处。实施例2与实施例1的不同之处在于，在实施例2的忆阻器中，第一导电电极41和第二导电电极42均为100nm厚的金薄膜，第一电极功能层21和第二电极功能层22均为50nm厚的铜薄膜；且第一电极功能层21和第二电极功能层22之间的最窄间距为10μm。
在本实施例的忆阻器的制作方法中，与实施例1中的制作方法的不同之处在于，在步骤(5)中，控制激光功率为0.62mW、扫描步长0.1μm的参数将电极功能层21、22之间的阻变源层6a划一条20μm的纳米线搭接在电极功能 层21、22上；其余参照实施例1中所述，即获得本实施例中的忆阻器。
对本实施例提供的忆阻器的性能进行测试。具体来讲，首先，将该忆阻器先浸泡于25％(wt％)的四甲基氢氧化铵溶液(TMAH)中50min，以去除纳米功能部3周围的其他阻变源层6a；然后在该忆阻器的远离衬底1的表面镀一层100nm的Al 2O 3作为隔离层，以防止其在测试过程中发生氧化；最后于手套箱中进行上述测试，其电流-电压特性曲线如图13所示。
从图13中可以看出，本实施例的忆阻器从-5.9V开始一直到5.8V，在有电压施加在器件上时，其电阻呈现低阻态；而电压从3.8V开始，随着电压的减小其电阻骤增，并一直保持高阻态直到电压减到-5.9V。因此，本实施例的忆阻器具有高电阻变化率(开关比可达到5000)、高循环稳定性(开关比随着循环次数增加波动很小)和操作速度快等优异性能。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (20)

  1. 一种忆阻器，其中，包括衬底以及设置在所述衬底上的间隔的第一电极功能层和第二电极功能层；其中，所述第一电极功能层和所述第二电极功能层之间通过纳米线或纳米带连接以实现电子导通。
  2. 根据权利要求1所述的忆阻器，其中，所述第一电极功能层和所述第二电极功能层之间的最小宽度为50nm～50μm。
  3. 根据权利要求1所述的忆阻器，其中，所述第一电极功能层和所述第二电极功能层的远离所述衬底的顶面齐平，并且所述纳米线或纳米带的顶面不低于所述第一电极功能层及所述第二电极功能层的顶面。
  4. 根据权利要求3所述的忆阻器，其中，所述第一电极功能层和所述第二电极功能层的厚度均为1nm～600nm；所述纳米线或纳米带的厚度为1nm～1000nm。
  5. 根据权利要求1所述的忆阻器，其中，所述纳米线或纳米带的材料为Ge 2Sb 2-xBi xTe 5；其中，0≤x≤2。
  6. 根据权利要求1所述的忆阻器，其中，所述第一电极功能层和所述第二电极功能层的材料均选自Ag、Cu、Al、Zn、Fe、Mg、Na、Sn中的任意一种。
  7. 根据权利要求6所述的忆阻器，其中，所述忆阻器还包括设置在所述衬底和所述第一电极功能层之间的第一导电电极、以及设置在所述衬底和所述第二电极功能层之间的第二导电电极。
  8. 根据权利要求7所述的忆阻器，其中，所述第一导电电极和所述第二导电电极的材料均选自Pt、Ni、Mn、Mo、Nb、Pd、Ru、RuO 2、Ta、TaN、W、WN、Ti及钛的氧化物中的任意一种；所述第一导电电极和所述第二导电电极的厚度均为1nm～600nm。
  9. 根据权利要求7所述的忆阻器，其中，所述忆阻器还包括设置在所述衬底和所述第一导电电极之间的第一电极吸附层、以及设置在所述衬底和所述第二导电电极之间的第二电极吸附层。
  10. 根据权利要求9所述的忆阻器，其中，所述第一电极吸附层和所述第 二电极吸附层的材料均选自Cr、Ti、Ni中的任意一种；所述第一电极吸附层和所述第二电极吸附层的厚度均为0.1nm～100nm。
  11. 一种如权利要求1所述的忆阻器的制作方法，其中，包括步骤：
    S1、在衬底上制作间隔的第一电极功能层和第二电极功能层；
    S2、至少在所述第一电极功能层和所述第二电极功能层之间沉积阻变材料，以形成阻变源层；
    S3、采用飞秒激光于所述第一电极功能层和所述第二电极功能层之间的阻变源层上进行划线，在所述第一电极功能层和所述第二电极功能层之间形成纳米线或纳米带；其中，
    若要求所述忆阻器的开关比不低于1000，则去除非划线区域的阻变源层；
    若要求所述忆阻器的开关比小于1000，则不去除或部分去除非划线区域的阻变源层。
  12. 根据权利要求11所述的忆阻器的制作方法，其中，所述第一电极功能层和所述第二电极功能层之间的最小宽度为50nm～50μm。
  13. 根据权利要求11所述的忆阻器的制作方法，其中，所述第一电极功能层和所述第二电极功能层的远离所述衬底的顶面齐平，并且所述纳米线或纳米带的顶面不低于所述第一电极功能层及所述第二电极功能层的顶面。
  14. 根据权利要求13所述的忆阻器的制作方法，其中，所述第一电极功能层和所述第二电极功能层的厚度均为1nm～600nm；所述纳米线或纳米带的厚度为1nm～1000nm。
  15. 根据权利要求11所述的忆阻器的制作方法，其中，所述纳米线或纳米带的材料为Ge2Sb2-xBixTe5；其中，0≤x≤2。
  16. 根据权利要求11所述的忆阻器的制作方法，其中，所述第一电极功能层和所述第二电极功能层的材料均选自Ag、Cu、Al、Zn、Fe、Mg、Na、Sn中的任意一种。
  17. 根据权利要求16所述的忆阻器的制作方法，其中，所述忆阻器还包括设置在所述衬底和所述第一电极功能层之间的第一导电电极、以及设置在所述衬底和所述第二电极功能层之间的第二导电电极。
  18. 根据权利要求17所述的忆阻器的制作方法，其中，所述第一导电电极和所述第二导电电极的材料均选自Pt、Ni、Mn、Mo、Nb、Pd、Ru、RuO2、Ta、TaN、W、WN、Ti及钛的氧化物中的任意一种；所述第一导电电极和所述第二导电电极的厚度均为1nm～600nm。
  19. 根据权利要求17所述的忆阻器的制作方法，其中，所述忆阻器还包括设置在所述衬底和所述第一导电电极之间的第一电极吸附层、以及设置在所述衬底和所述第二导电电极之间的第二电极吸附层。
  20. 根据权利要求19所述的忆阻器的制作方法，其中，所述第一电极吸附层和所述第二电极吸附层的材料均选自Cr、Ti、Ni中的任意一种；所述第一电极吸附层和所述第二电极吸附层的厚度均为0.1nm～100nm。
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