WO2020118774A1 - 驱动装置及其驱动方法 - Google Patents

驱动装置及其驱动方法 Download PDF

Info

Publication number
WO2020118774A1
WO2020118774A1 PCT/CN2018/123849 CN2018123849W WO2020118774A1 WO 2020118774 A1 WO2020118774 A1 WO 2020118774A1 CN 2018123849 W CN2018123849 W CN 2018123849W WO 2020118774 A1 WO2020118774 A1 WO 2020118774A1
Authority
WO
WIPO (PCT)
Prior art keywords
image data
data signal
signal
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/123849
Other languages
English (en)
French (fr)
Inventor
王明良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,454 priority Critical patent/US11195486B2/en
Publication of WO2020118774A1 publication Critical patent/WO2020118774A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present application relates to the field of display technology, in particular to a driving device and a driving method thereof.
  • the current TV display architecture includes a TV motherboard and a control board.
  • the TV motherboard is set to receive input signals, such as the input of an antenna or a set-top box, processed by a system-on-chip (Single On Chip, SOC), and then pass the signal to the control board
  • SOC System-on-chip
  • TCON Timing Controller
  • the signal originally received from the antenna or the set-top box is processed by the system-level chip and the timing control board, the signal will be modified relatively large.
  • the display data in the same position is theoretically unchanged, but after processing by the system-level chip and the timing control board, the display data before and after the same display position may be different, and After this long series of process processing, the signal difference will become larger and larger, leading to the problem of flickering pictures.
  • a driving device and a driving method thereof are provided.
  • a driving device respectively connected to a signal output circuit and a display panel, includes:
  • a system-level chip connected to the signal output circuit, is configured to store image data signals of each frame to be transmitted output by the signal output circuit, and process the image data signals to output a first image data signal;
  • the system-level chip is further configured to output a difference signal according to the signal difference between the image data signal of any current frame and the image data signal of the previous frame of the current frame;
  • the timing control board connected to the display panel, is configured to receive the first image data signal and the difference signal, and according to the first image data signal and the difference signal, to the first image data signal After processing, the second image data signal is output;
  • the timing control board is configured to:
  • the second image data signal of the previous frame is output;
  • the second image data signal of the current frame is output.
  • a driving device includes a system-level chip and a timing control board.
  • the system-level chip includes:
  • the first buffer circuit is connected to the signal output circuit, and is configured to store and output the image data signals of each frame to be transmitted output by the signal output circuit;
  • a data comparison circuit an input end of the data comparison circuit is connected to the signal output circuit and the first buffer circuit, and is set to be based on the image data signal of any current frame and the image of the previous frame of the current frame
  • the signal difference of the data signal outputs the difference signal
  • a first processing circuit connected to the first buffer circuit, configured to receive the image data signal, and output the first image data signal after processing the image data signal;
  • An encoding circuit an input end of the encoding circuit is connected to the data comparison circuit and the first processing circuit, an output end of the encoding circuit is connected to the timing control board, and the encoding circuit is configured to receive the difference A signal and the first image data signal, and encode and output the difference signal and the first image data signal;
  • the timing control board includes:
  • a decoding circuit connected to the encoding circuit and configured to decode and output the difference signal encoded by the encoding circuit and the first image data signal;
  • a second processing circuit connected to the decoding circuit, configured to receive the decoded first image data signal, and process the first image data signal to output a second image data signal;
  • a second buffer circuit connected to the second processing circuit, configured to store the second image data signal and output the second image data signal
  • a selection circuit an input terminal of the selection circuit is connected to the decoding circuit, the second processing circuit and the second buffer circuit, an output terminal of the selection circuit is connected to the display panel, and is configured to receive the difference signal, The second image data signal of the current frame and the second image data signal of the previous frame, the selection circuit is configured when the signal difference is lower than a first set value, and the When the signal difference between the second image data signal and the second image data signal of the previous frame is higher than the second set value, the second image data signal of the previous frame is output; when the signal difference is lower than the The first set value, and when the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame is lower than the second set value, the first Two image data signals.
  • a driving method including the following steps:
  • the system-level chip receives the image data signals of each frame to be transmitted, and processes the image data signals to output the first image data signal; and is also set to be based on the image data signal of any current frame and the previous one of the current frame
  • the signal difference of the image data signal of the frame outputs the difference signal;
  • the timing control board is configured to output the second image data signal after reprocessing the first image data signal according to the difference signal and the first image data signal;
  • the timing The control board outputs the second image data signal of the current frame
  • the timing control board outputs the second image data signal of the previous frame.
  • the above-mentioned driving device solves the problem that the image data signal in the driving device is greatly changed after being processed by the system-level chip and the timing control board, thereby causing the static picture to flicker.
  • FIG. 1 is a schematic structural diagram of a driving device according to an embodiment
  • FIG. 2 is a schematic structural diagram of a driving device in another embodiment
  • FIG. 3 is the encoding principle of the encoding circuit in another embodiment
  • FIG. 5 is a schematic structural diagram of a second processing circuit in an embodiment
  • FIG. 6 is a schematic structural diagram of a timing control board in an embodiment.
  • FIG. 1 is a schematic structural diagram of a driving device according to an embodiment.
  • a driving device respectively connected to the signal output circuit 10 and the display panel 40, includes:
  • the system-on-chip 20 is connected to the signal output circuit 10, and is configured to store the image data signal 101 of each frame to be transmitted output by the signal output circuit 10, and process the image data signal 101 to output the first image data signal 201;
  • the system-on-chip 20 is further configured to output a difference signal 202 according to the signal difference between the image data signal of any current frame and the image data signal of the previous frame of the current frame;
  • the timing control board 30 is connected to the display panel 40, and is configured to receive the first image data signal 201 and the difference signal 202, and process the first image data signal 201 according to the first image data signal 201 and the difference signal 202 and output the first Two image data signals 301;
  • the timing control board 30 is configured to:
  • the second image data signal of the current frame is output.
  • the above-mentioned driving device includes a system-level chip 20 and a timing control board 30.
  • the system-level chip 20 is set to receive the image data signal 101 of each frame to be transmitted output by the receiving signal output circuit 10, and outputs the image data signal 101 after processing The first image data signal 201; also set to output a difference signal 202 according to the signal difference of the image data signal of any current frame and the image data signal of the previous frame of the current frame, wherein the signal output circuit 10 may be an antenna or a set-top box;
  • the timing control board 30 processes the first image data signal 201 according to the first image data signal 201 and the difference signal 202, and outputs a second image data signal 301.
  • the timing control board 30 when the signal difference is lower than the first set value, and the current When the signal difference between the second image data signal of the frame and the second image data signal of the previous frame is higher than the second set value, the timing control board 30 outputs the second image data signal of the previous frame; when the signal difference is lower than the second At a set value, and the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame is lower than the second set value, the timing control board 30 outputs the second image data signal of the current frame.
  • FIG. 2 is a schematic structural diagram of a driving device in another embodiment.
  • the system-on-chip 20 includes:
  • the first buffer circuit 210 is connected to the signal output circuit 10, and is configured to store and output image data signals of each frame to be transmitted output by the signal output circuit 10;
  • the data comparison circuit 220 the input end of the data comparison circuit 220 is connected to the signal output circuit 10 and the first buffer circuit 210, and is set according to the image data signal 102 of any current frame and the image data signal 2101 of the previous frame of the current frame
  • the first processing circuit 230 connected to the first buffer circuit 210, is configured to receive the image data signal, and output the first image data signal 201 after processing the image data signal;
  • system-on-chip 20 further includes:
  • the encoding circuit 240 the input terminal of the encoding circuit 240 is connected to the data comparison circuit 220 and the first processing circuit 230, the output terminal of the encoding circuit 240 is connected to the timing control board 30, and the encoding circuit 240 is configured to receive the difference signal 202 and the first image data Signal 201, and outputs the difference signal 202 and the first image data signal 201 after encoding.
  • the encoding circuit 240 is a low-voltage differential signal encoder.
  • the timing control board 30 includes:
  • the second processing circuit 320 is connected to the first processing circuit 230, and is configured to receive the first image data signal 201 and process the first image data signal 201 to output a second image data signal 301;
  • the second buffer circuit 330 is connected to the second processing circuit 320, and is configured to store and output the second image data signal 301;
  • the selection circuit 340 the input terminal of the selection circuit 340 is connected to the data comparison circuit 220, the second processing circuit 320 and the second buffer circuit 330, the output terminal of the selection circuit 340 is connected to the display panel 40, and is set to receive the difference signal 202, the current frame
  • the second image data signal and the second image data signal of the previous frame the selection circuit 340 is configured when the signal difference is lower than the first set value, and the second image data signal of the current frame and the second frame of the previous frame When the signal difference of the image data signal is higher than the second set value, the second image data signal of the previous frame is output; when the signal difference is lower than the first set value, and the second image data signal of the current frame and the previous frame When the signal difference of the second image data signal is lower than the second set value, the second image data signal of the current frame is output.
  • timing control board 30 further includes:
  • the decoding circuit 310 is connected to the encoding circuit 240, and is configured to decode and output the difference signal 202 and the first image data signal 201 encoded by the encoding circuit 310.
  • the decoding circuit 310 is a low-voltage differential signal decoder.
  • a data comparison circuit 220 is newly added to the system-on-chip 20 to compare the difference between the original input signal, that is, the image data signal 102 of the current frame and the image data signal 2101 of the previous frame. Difference, when the signal difference is lower than the first set value, it is marked as 0, when the signal difference is higher than the first set value, it is marked as 1, and then the protocol is encoded by the encoding circuit 240, the difference flag is also encoded Going in is equivalent to adding a new code to the existing protocol.
  • FIG. 3 is the coding principle of the coding circuit 240 in this embodiment, which uses a low voltage differential signal (Low Voltage Differential Signal, LVDS) encoder, in which P and N are a pair, a total of 0 ⁇ 3 A total of 4 pairs of differential signals.
  • the image data signals include red data signals, green data signals, and blue data signals.
  • the new transmission protocol includes the difference signal 202
  • it is transmitted to the timing control board 30.
  • the timing control board 30 performs a new protocol decoding on the encoded signal 200.
  • the decoded first image data signal 201 and the difference signal 202 are still Reprocessing is required, and the decoded difference signal 202 needs to be given to the selection circuit 340 as a basis for data determination.
  • the selection circuit 340 will then determine the difference between the second image data signal of the previous frame and the second image data signal of the current frame , And finally decided to output the data.
  • FIG. 4 is an example of the encoding circuit 240 in this embodiment, in which the difference signals of the red data signal, the green data signal, and the blue data signal are placed at position 530, position 510, and position 520 respectively, when the previous frame
  • the signal difference between the red data signal and the red data signal of the current frame the signal difference between the blue data signal of the previous frame and the blue data signal of the current frame is lower than the first set value
  • the corresponding position 530 and position 520 are The code is 0, which means that the timing control board 30 needs to be discriminated.
  • the corresponding position 510 is coded as 1, representing The timing control board 30 does not need to perform discrimination processing.
  • the difference between the red data signal and the blue data signal is 0.
  • the selection circuit 340 determines that the signal difference between the second image data signal of the previous frame and the second image data signal of the current frame is higher than the second set value, It is believed that the input of the signal from the source has caused a large difference to the terminal and may cause problems. Then, the second image data signal of the previous frame is selected for output. If the selection circuit 340 determines the second image data signal of the previous frame When the signal difference from the second image data signal of the current frame is lower than the second set value, then the second image data signal of the current frame may be selected to be output.
  • the first processing circuit 230 includes:
  • the expansion circuit is connected to the first buffer circuit, and is configured to receive the image data signal and expand the image data signal to output the first image data signal.
  • the expansion circuit includes:
  • the line expansion circuit is connected to the first buffer circuit, and is configured to extract each line data signal in the image data signal and perform line expansion on each line of data;
  • the column expansion circuit is connected to the row expansion circuit, and is configured to extract each column data signal of the image data signal after row processing expansion, and perform column expansion on each column of data.
  • the expansion circuit includes a row expansion circuit and a column expansion circuit, mainly for adjusting the received full-definition image data signal to an ultra-high-definition image data signal to adapt to display on an ultra-high-definition display panel.
  • FIG. 5 is a schematic structural diagram of a second processing circuit 320 in an embodiment.
  • the second processing circuit 320 includes:
  • the color processing circuit 321 is connected to the first processing circuit 230, and is configured to receive the first image data signal 201, and to correct the first image data signal 201 by querying a look-up table stored in the color processing circuit 321, the look-up table being an input Signal correction table for the first image data signal 201 and the output first image data signal 3211.
  • the color processing circuit 321 performs data replacement on the decoded first image data signal 201, and outputs the corrected first image data signal 3211 by looking up the corresponding relationship between the input/output data in the look-up table, mainly to enhance the vividness of the picture degree.
  • the second processing circuit 321 further includes:
  • the digital gamma circuit 322 is connected to the color processing circuit 321, and is configured to receive the first image data signal 3211 corrected by the color processing circuit 321, and convert the original bit number of the corrected first image data signal 3211 to convert The number of subsequent bits is greater than the original number of bits;
  • the jitter processing circuit 323 is connected to the digital gamma circuit 322, and is configured to receive the first image data signal 3221 converted by the digital gamma circuit 322, and output the converted first image data signal 3221 by dithering the original bits number.
  • the digital gamma circuit 322 replaces the number of bits of the first image data signal 3211 after correction.
  • the number of bits after replacement is larger than the original number of bits, which is mainly to ensure the smoothness of the gamma curve, where the gamma curve
  • the brightness displayed by the liquid crystal display is different from the brightness perceived by the human eye.
  • the gray scale rate of the human eye will enlarge the pupil and the brightness will be collected more. Therefore, in order to match the characteristics of the human eye,
  • the displayed data needs to be modified to meet the requirements of the gamma curve, so that all orders in the process of the picture from all black to all white are uniformly transitioned, and will not be bright or sudden.
  • the jitter processing circuit 323 outputs the original bit number data signal using the jitter method because the replaced bit number output by the digital gamma circuit 322, because the back-end timing control board 30 can only recognize the original bit number data signal, so the jitter
  • the processing circuit 323 will generate new original bit number data for output according to the converted data. Since different new original bit number data will be output at different times, it will cause a mixed effect of the human eye, which looks like real The converted bit number effect can display more gray scale numbers.
  • FIG. 6 is a schematic structural diagram of a timing control board 30 in an embodiment.
  • the timing control board 30 further includes:
  • the overdrive circuit 350 the input end of the overdrive circuit 350 is connected to the selection circuit 340 and the second buffer circuit 330, the output end of the overdrive circuit 350 is connected to the display panel 40, and is set to receive the second image data signal of the current frame and the previous one
  • the second image data signal of the frame and through the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame, enhances the ability of the selection circuit 340 to output a signal.
  • the newly added overdrive circuit 350 is to speed up the charging speed of the liquid crystal and reduce the smearing phenomenon of the dynamic picture. For example, it normally outputs 16 gray levels, which may not be charged within a certain charging time.
  • the overdrive circuit 350 can be set to directly output 20 gray levels, which is equivalent to charging the liquid crystal with a larger voltage, then at the same time Within 16 gray levels.
  • a driving device includes a system-level chip 20 and a timing control board 30.
  • the system-level chip 20 includes:
  • the first buffer circuit 210 is connected to the signal output circuit 10, and is configured to store and output image data signals of each frame to be transmitted output by the signal output circuit 10;
  • the data comparison circuit 220 the input end of the data comparison circuit 220 is connected to the signal output circuit 10 and the first buffer circuit 210, and is set according to the image data signal 102 of any current frame and the image data signal 2101 of the previous frame of the current frame
  • the first processing circuit 230 connected to the first buffer circuit 210, is configured to receive the image data signal, and output the first image data signal 201 after processing the image data signal;
  • the encoding circuit 240 the input terminal of the encoding circuit 240 is connected to the data comparison circuit 220 and the first processing circuit 230, the output terminal of the encoding circuit 240 is connected to the timing control board 30, and the encoding circuit 240 is configured to receive the difference signal 202 and the first image data Signal 201, and outputs the difference signal 202 and the first image data signal 201 after encoding.
  • the timing control board 30 includes:
  • the decoding circuit 310 is connected to the encoding circuit 240, and is configured to decode and output the difference signal 202 and the first image data signal 201 encoded by the encoding circuit 310;
  • the second processing circuit 320 is connected to the decoding circuit 310, and is configured to receive the decoded first image data signal 201 and process the first image data signal 201 to output a second image data signal 301;
  • the second buffer circuit 330 is connected to the second processing circuit 320, is configured to store the second image data signal 301, and outputs the second image data signal 301;
  • the selection circuit 340 the input terminal of the selection circuit 340 is connected to the decoding circuit 310, the second processing circuit 320, and the second buffer circuit 330, the output terminal of the selection circuit 340 is connected to the display panel 40, and is set to receive the difference signal 202, the first frame of the current frame
  • the second image data signal and the second image data signal of the previous frame the selection circuit 340 is configured when the signal difference is lower than the first set value, and the second image data signal of the current frame and the second image data of the previous frame When the signal difference of the signal is higher than the second set value, the second image data signal of the previous frame is output; when the signal difference is lower than the first set value, and the second image data signal of the current frame and the second frame of the previous frame When the signal difference between the two image data signals is lower than the second set value, the second image data signal of the current frame is output.
  • the above-mentioned driving device solves the problem that the image data signal in the driving device is greatly changed after being processed by the system-level chip and the timing control board, thereby causing the static picture to flicker.
  • a driving method including the following steps:
  • the system-level chip receives the image data signals of each frame to be transmitted and processes the image data signals to output the first image data signal; and is also configured to output the difference signal according to the signal difference between the current frame image data signal and the previous frame image data signal ;
  • the timing control board is configured to output the second image data signal after reprocessing the first image data signal according to the difference signal and the first image data signal;
  • the timing control board If the signal difference is lower than the first set value, and the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame is lower than the second set value, the timing control board outputs the second image data signal of the current frame ;
  • the timing control board If the signal difference is lower than the first set value, and the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame is higher than the second set value, the timing control board outputs the second image data of the previous frame signal.
  • the system-level chip is not only configured to receive the image data signals of each frame to be transmitted, and to process the image data signals to output the first image data signal; it is also set to be based on the image data signal of any current frame and the current
  • the signal difference of the image data signal of the previous frame of the frame outputs a difference signal
  • the timing control board processes the first image data signal according to the first image data signal and the difference signal, and outputs a second image data signal, if the signal difference is lower than The first set value, and the signal difference between the second image data signal of the current frame and the second image data signal of the previous frame is lower than the second set value, the timing control board outputs the second image data signal of the current frame;
  • the signal difference is lower than the first set value, and the signal difference of the second image data signal of the current frame and the second image data signal of the previous frame is higher than the second set value, the timing control board outputs the second of the previous frame Image data signal. Therefore, the problem that the image data signal in the driving device is modified greatly after being
  • system-level chip receives the image data signals of each frame to be transmitted, and processes the image data signals to output the first image data signal, which specifically includes:
  • the system-level chip receives the image data signals of each frame to be transmitted, and expands the image data signals to output the first image data signal.
  • the system-level chip receives each frame of image data signal to be transmitted, and expands the image data signal to output the first image data signal, which specifically includes:
  • the system-level chip When the system-level chip receives the image data signals of each frame to be transmitted, it extracts each row of data of the image data signal, expands each row of data by two times, and extracts each column of data of the processed image data signal, and extracts each column of data Output after double expansion processing.
  • the image data signal of each row is expanded twice, and the image data signal of each column is expanded twice, so that the full HD image data signal is converted into the ultra high definition data signal to adapt to the display panel displayed in the ultra high definition .
  • timing control board is configured to output the second image data signal after reprocessing the first image data signal according to the difference signal and the first image data signal, including:
  • the timing control board is configured to output the second image data signal after correcting the first image data signal according to the difference signal and the first image data signal.
  • the first image data signal is corrected mainly through the color processing module in the timing control board, and the first image data signal is corrected by querying the look-up table stored in the color processing circuit, the look-up table is the input first image data
  • the signal and the signal correction table of the output first image data signal the main purpose of correcting the first image data signal is to enhance the vividness of the picture.
  • outputting the second image data signal after reprocessing the first image data signal further includes:
  • the timing control board converts the original bit number of the corrected first image data signal, and outputs the original bit number in a dithering manner.
  • the number of original bits of the first image data signal after the conversion is converted and replaced by the digital gamma circuit in the timing control board is greater than the number of original bits, which is mainly to ensure the smoothness of the gamma curve
  • the gamma curve is an optical curve
  • the brightness displayed by the liquid crystal display is different from the brightness perceived by the human eye.
  • the gray scale rate of the human eye to the dark the pupil will be enlarged, the brightness will be collected more, so in order to
  • the displayed data needs to be modified to meet the requirements of the gamma curve, so that all the orders in the process of the picture from all black to all white are uniformly transitioned, and will not be bright or sudden.
  • the jitter processing circuit in the timing control board the number of replaced bits output by the digital gamma circuit is output by the method of dithering the original bit number data signal, because the back-end timing control board can only recognize the original bit number data Signal, so the jitter processing circuit will generate new original bit number data according to the converted data for output. Since different new original bit number data will be output at different times, it will cause a mixed effect of the human eye. Like the real converted bit effect, you can display more gray levels.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动装置及其驱动方法。该驱动装置包括系统级芯片和时序控制板；系统级芯片，设置为接收并处理待传输的各帧图像数据信号，并输出第一图像数据信号和当前帧与上一帧的图像数据信号的差异信号；时序控制板，设置将第一图像数据信号进行处理后输出第二图像数据信号，并根据差异信号和当前帧与上一帧的第二图像数据信号输出。

Description

驱动装置及其驱动方法
本申请要求于2018年12月13日提交中国专利局，申请号为2018115243729，申请名称为“驱动装置及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种驱动装置及其驱动方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示范性技术。
目前电视的显示架构，包括电视机主板与控制板，电视主板设置为接收输入信号，例如天线或机顶盒的输入，通过系统级芯片(Single On Chip，SOC)处理后，再将信号传递给控制板上的时序控制板(Timing Controller，TCON)进行再次处理，最后再通过数据驱动芯片去驱动液晶面板。
然而原始从天线或机顶盒接收到的信号，经过系统级芯片和时序控制板的处理之后，信号会被改动的比较大。对于静态画面显示来说，理论上同一个位置的显示数据是不变的，可是经过系统级芯片和时序控制板处理后，同一个显示位置的前后两次显示数据就有可能会不一样，且经过这一长串的流程处理，信号差异会越来越大，导致画面闪烁的问题。
发明内容
根据本申请的各种实施例，提供了一种驱动装置及其驱动方法。
一种驱动装置，分别与信号输出电路、显示面板连接，包括：
系统级芯片，与所述信号输出电路连接，设置为存储所述信号输出电路输出的待传输的各帧图像数据信号，并将所述图像数据信号处理后输出第一图像数据信号；
所述系统级芯片还设置为根据任一当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
时序控制板，与所述显示面板连接，设置为接收所述第一图像数据信号和所述差异信号，并根据所述第一图像数据信号和所述差异信号，对所述第一图像数据信号进行处理后输出第二图像数据信号；
若所述信号差异低于第一设定值，所述时序控制板被配置为：
当所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于第二设定值时，输出所述上一帧的第二图像数据信号；
当所述当前帧的第二图像数据信号和所述上一帧第二图像数据信号的信号差异低于所述第二设定值时，输出所述当前帧的第二图像数据信号。
一种驱动装置，包括系统级芯片和时序控制板，所述系统级芯片包括：
第一缓冲电路，与信号输出电路连接，设置为存储并输出所述信号输出电路输出的待传输的各帧图像数据信号；
数据比对电路，所述数据比对电路的输入端连接所述信号输出电路和所述第一缓冲电路，设置为根据任一当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
第一处理电路，与所述第一缓冲电路连接，设置为接收所述图像数据信号，并对所述图像数据信号处理后输出第一图像数据信号；
编码电路，所述编码电路的输入端连接所述数据比对电路和所述第一处理电路，所述编码电路的输出端与所述时序控制板连接，所述编码电路设置为接收所述差异信号和所述第一图像数据信号，并将所述差异信号和所述第一图像数据信号编码后输出；
所述时序控制板包括：
解码电路，与编码电路连接，设置为将所述编码电路编码后的所述差异信号和所述第一图像数据信号解码后输出；
第二处理电路，与所述解码电路连接，设置为接收解码后的所述第一图像数据信号，并将所述第一图像数据信号处理后输出第二图像数据信号；
第二缓冲电路，与所述第二处理电路连接，设置为存储所述第二图像数据信号，并输出所述第二图像数据信号；
选择电路，所述选择电路的输入端连接所述解码电路、所述第二处理电路和所述第二缓冲电路，所述选择电路的输出端与显示面板连接，设置为接收所述差异信号、所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号，所述选择电路被配置为当所述信号差异低于第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于第二设定值时，输出所述上一帧的第二图像数据信号；当所述信号差异低于所述第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异低于所述第二设定值时，输出所述当前帧的第二图像数据信号。
一种驱动方法，包括如下步骤：
系统级芯片接收待传输的各帧图像数据信号，并将所述图像数据信号处理后输出第一图像数据信号；及还设置为根据任一当前帧的图像数据信号和 所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
时序控制板设置为根据所述差异信号和所述第一图像数据信号，对所述第一图像数据信号进行再处理后输出第二图像数据信号；
若所述信号差异低于第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异低于第二设定值，所述时序控制板输出所述当前帧的第二图像数据信号；
若所述信号差异低于所述第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于所述第二设定值，所述时序控制板输出所述上一帧的第二图像数据信号。
上述的驱动装置，解决了驱动装置中图像数据信号经过系统级芯片和时序控制板处理后被改动的较大，从而导致静态画面闪烁的问题。
附图说明
为了更清楚地说明本申请实施例或示范例技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例驱动装置的结构示意图；
图2为另一实施例中驱动装置的结构示意图；
图3为另一实施例中编码电路的编码原理；
图4为另一实施例中编码电路的举例说明；
图5为一实施例中第二处理电路的结构示意图；
图6为一实施例中时序控制板的结构示意图。
具体实施方式
当一个元件被认为与另一个元件“相连”时，它可以是直接连接到另一个元件或者可能同时存在居中元件。除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
参见图1，图1为一实施例驱动装置的结构示意图。
一种驱动装置，分别与信号输出电路10、显示面板40连接，包括：
系统级芯片20，与信号输出电路10连接，设置为存储信号输出电路10输出的待传输的各帧图像数据信号101，并将图像数据信号101处理后输出第一图像数据信号201；
系统级芯片20还设置为根据任一当前帧的图像数据信号和当前帧的上一帧的图像数据信号的信号差异输出差异信号202；
时序控制板30，与显示面板40连接，设置为接收第一图像数据信号201和差异信号202，并根据第一图像数据信号201和差异信号202，对第一图像数据信号201进行处理后输出第二图像数据信号301；
若信号差异低于第一设定值，时序控制板30被配置为：
当当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异高于第二设定值时，输出上一帧的第二图像数据信号；
当当前帧的第二图像数据信号和上一帧第二图像数据信号的信号差异低于第二设定值时，输出当前帧的第二图像数据信号。
上述的驱动装置，包括系统级芯片20和时序控制板30，系统级芯片20 除了设置为接收信号输出电路10输出的待传输的各帧图像数据信号101，并对图像数据信号101进行处理后输出第一图像数据信号201；还设置为根据任一当前帧的图像数据信号和当前帧的上一帧的图像数据信号的信号差异输出差异信号202，其中，信号输出电路10可以为天线或机顶盒；时序控制板30根据第一图像数据信号201和差异信号202，对第一图像数据信号201进行处理后输出第二图像数据信号301，具体地，当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异高于第二设定值时，时序控制板30输出上一帧的第二图像数据信号；当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异低于第二设定值时，时序控制板30输出当前帧的第二图像数据信号。从而更加有效地有效解决了驱动装置中图像数据信号101经过系统级芯片20和时序控制板30处理后被改动的较大，从而导致静态画面闪烁的问题。
在一个实施例中，参见图2，图2为另一实施例中驱动装置的结构示意图，系统级芯片20包括：
第一缓冲电路210，与信号输出电路10连接，设置为存储并输出信号输出电路10输出的待传输的各帧图像数据信号；
数据比对电路220，数据比对电路220的输入端连接信号输出电路10和第一缓冲电路210，设置为根据任一当前帧的图像数据信号102和当前帧的上一帧的图像数据信号2101的信号差异输出差异信号202；
第一处理电路230，与第一缓冲电路210连接，设置为接收图像数据信号，并对图像数据信号处理后输出第一图像数据信号201；
进一步地，系统级芯片20还包括：
编码电路240，编码电路240的输入端连接数据比对电路220和第一处理电路230，编码电路240的输出端与时序控制板30连接，编码电路240设置为接收差异信号202和第一图像数据信号201，并将差异信号202和第一图像数据信号201编码后输出。
具体地，编码电路240为低电压差分信号编码器。
在本实施例中，时序控制板30包括：
第二处理电路320，与第一处理电路230连接，设置为接收第一图像数据信号201，并将第一图像数据信号201处理后输出第二图像数据信号301；
第二缓冲电路330，与第二处理电路320连接，设置为存储并输出第二图像数据信号301；
选择电路340，选择电路340的输入端连接数据比对电路220、第二处理电路320和第二缓冲电路330，选择电路340的输出端与显示面板40连接，设置为接收差异信号202、当前帧的第二图像数据信号和上一帧的第二图像数据信号，选择电路340被配置为当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异高于第二设定值时，输出上一帧的第二图像数据信号；当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异低于第二设定值时，输出当前帧的第二图像数据信号。
进一步地，时序控制板30还包括：
解码电路310，与编码电路240连接，设置为将编码电路310编码后的差异信号202和第一图像数据信号201解码后输出。
具体地，解码电路310为低电压差分信号解码器。
在本实施例中，在系统级芯片20中新增了一个数据比对电路220，通过 比对原始输入信号的差异，即当前帧的图像数据信号102和上一帧的图像数据信号2101的信号差异，当信号差异低于第一设定值时，标识为0，当信号差异高于第一设定值时，标识为1，然后通过编码电路240进行协议编码时，将这个差异标记也编码进去，相当于对现有协议增加新的编码。
参见图3，图3为本实施例中编码电路240的编码原理，采用的是低电压差分信号(Low Voltage Differential Signal，LVDS)编码器，其中，P和N为一对，总共有0～3共4对差分信号，图像数据信号包括红色数据信号、绿色数据信号和蓝色数据信号，这三种颜色的数据信号就包藏在这4对差分信号中，其中AR0～AR7为红色数据信号，AG0～AG7为绿色数据信号，AB0～AB7为蓝色数据信号，其中有3个预留位置REV目前并没有使用，本方案利用这3个预留位置REV放置差异信号，具体红色数据差异信号、绿色数据差异信号和蓝色数据差异信号的位置不限，只需要在这3个预留位置REV内即可。
当新的传输协议包含了差异信号202之后，传输给时序控制板30，时序控制板30要对编码后的信号200进行新的协议解码，解码后的第一图像数据信号201和差异信号202仍需要进行再处理，而解码后的差异信号202需要给到选择电路340作为数据判定的基准，选择电路340会再去判断上一帧的第二图像数据信号与当前帧的第二图像数据信号差异，最后决定输出数据。
参见图4，图4为本实施例中编码电路240的举例说明，其中，红色数据信号、绿色数据信号和蓝色数据信号的差异信号分别放置位置530、位置510和位置520，当上一帧的红色数据信号和当前帧的红色数据信号的信号差异、上一帧的蓝色数据信号和当前帧的蓝色数据信号的信号差异低于第一设定值时，对应位置530和位置520就编码为0，代表需要时序控制板30进行 判别处理，相反当前帧的绿色数据信号和上一帧的绿色数据信号的信号差异高于第一设定值时，对应位置510就编码为1，代表不需要时序控制板30进行判别处理。
红色数据信号和蓝色数据信号差异标识为0，当选择电路340判定上一帧的第二图像数据信号和当前帧的第二图像数据信号的信号差异高于第二设定值时，就可以认为信号从源头的输入，到现在终端已经造成了较大差异，可能会造成问题，那么就选择输出上一帧的第二图像数据信号，如果选择电路340判定上一帧的第二图像数据信号和当前帧的第二图像数据信号的信号差异低于第二设定值时，那么可以选择输出当前帧的第二图像数据信号。
进一步地，第一处理电路230包括：
扩展电路，与第一缓冲电路连接，设置为接收图像数据信号，并对图像数据信号进行扩展后输出第一图像数据信号。
具体地，扩展电路包括：
行扩展电路，与第一缓冲电路连接，设置为提取图像数据信号中的每行数据信号，并将每行数据进行行扩展；
列扩展电路，与行扩展电路连接，设置为提取进行行处理扩展后的图像数据信号的每列数据信号，并将每列数据进行列扩展。
扩展电路包括行扩展电路和列扩展电路，主要是为了将接收到的全高清的图像数据信号调整为超高清的图像数据信号，来适应显示在超高清的显示面板。
进一步地，参见图5，图5为一实施例中第二处理电路320的结构示意图，第二处理电路320包括：
颜色处理电路321，与第一处理电路230连接，设置为接收第一图像数 据信号201，并通过查询存储在颜色处理电路321中的查找表对第一图像数据信号201进行修正，查找表为输入的第一图像数据信号201与输出的第一图像数据信号3211的信号修正表。
颜色处理电路321把解码后的第一图像数据信号201进行数据替换，通过查询查找表中输入/输出数据的对应关系，输出修正后的第一图像数据信号3211，其主要是为了提升画面的鲜艳度。
进一步地，第二处理电路321还包括：
数字伽马电路322，与颜色处理电路321连接，设置为接收经过颜色处理电路321修正后的第一图像数据信号3211，并将修正后的第一图像数据信号3211的原始比特数进行转换，转换后的比特数大于原始比特数；
抖动处理电路323，与数字伽马电路322连接，设置为接收经过数字伽马电路322转换后的第一图像数据信号3221，并将转换后的第一图像数据信号3221采用抖动的方式输出原始比特数。
数字伽马电路322将修正后的第一图像数据信号3211进行比特数的替换，替换后的比特数比原始比特数要大，其主要是为了保证伽马曲线的平滑度，其中，伽马曲线为光学曲线，液晶显示器呈现出来的亮度与人眼感受的亮度是有所差别的，一般人眼对暗的灰阶率，瞳孔会放大，采集到亮度会比较多，因此为了配合人眼的特性，需修正显示的数据满足伽马曲线的要求，使画面从全黑到全白这一过程中的所有阶数是均匀过渡的，不会突亮或突灭。
抖动处理电路323将数字伽马电路322输出的替换后的比特数，采用抖动的方法进行输出原始比特数的数据信号，因为后端的时序控制板30只能识别原始比特数的数据信号，因此抖动处理电路323会根据转换后的数据，再产生新的原始比特数的数据进行输出，由于不同时间会输出不同新的原始比 特数的数据，会造成人眼的混合效应，看起来就像是真实的转换后的比特数效果，就可以显示更多的灰阶数。
进一步地，参见图6，图6为一实施例中时序控制板30的结构示意图，时序控制板30还包括：
过驱动电路350，过驱动电路350的输入端连接选择电路340和第二缓冲电路330，过驱动电路350的输出端与显示面板40连接，设置为接收当前帧的第二图像数据信号和上一帧的第二图像数据信号，并通过当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异，对选择电路340输出信号的能力进行加强。
新增加的过驱动电路350是为了加快液晶的充电速度，减少动态画面的拖尾现象。例如正常要输出16灰阶，在一定的充电时间内可能充不到，过驱动电路350就可以设置直接输出20灰阶，相当于用一个更大的电压对液晶进行充电，那么在同等的时间内就可以达到16灰阶。
在另一个实施例中，参见图2，一种驱动装置，包括系统级芯片20和时序控制板30，系统级芯片20包括：
第一缓冲电路210，与信号输出电路10连接，设置为存储并输出信号输出电路10输出的待传输的各帧图像数据信号；
数据比对电路220，数据比对电路220的输入端连接信号输出电路10和第一缓冲电路210，设置为根据任一当前帧的图像数据信号102和当前帧的上一帧的图像数据信号2101的信号差异输出差异信号202；
第一处理电路230，与第一缓冲电路210连接，设置为接收图像数据信号，并对图像数据信号处理后输出第一图像数据信号201；
编码电路240，编码电路240的输入端连接数据比对电路220和第一处 理电路230，编码电路240的输出端与时序控制板30连接，编码电路240设置为接收差异信号202和第一图像数据信号201，并将差异信号202和第一图像数据信号201编码后输出。
时序控制板30包括：
解码电路310，与编码电路240连接，设置为将编码电路310编码后的差异信号202和第一图像数据信号201解码后输出；
第二处理电路320，与解码电路310连接，设置为接收解码后的第一图像数据信号201，并将第一图像数据信号201处理后输出第二图像数据信号301；
第二缓冲电路330，与第二处理电路320连接，设置为存储第二图像数据信号301，并输出第二图像数据信号301；
选择电路340，选择电路340的输入端连接解码电路310、第二处理电路320和第二缓冲电路330，选择电路340的输出端与显示面板40连接，设置为接收差异信号202、当前帧的第二图像数据信号和上一帧的第二图像数据信号，选择电路340被配置为当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异高于第二设定值时，输出上一帧的第二图像数据信号；当信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异低于第二设定值时，输出当前帧的第二图像数据信号。
上述的驱动装置，解决了驱动装置中图像数据信号经过系统级芯片和时序控制板处理后被改动的较大，从而导致静态画面闪烁的问题。
一种驱动方法，包括如下步骤：
系统级芯片接收待传输的各帧图像数据信号，并将图像数据信号处理后 输出第一图像数据信号；及还设置为根据当前帧图像数据信号和上一帧图像数据信号的信号差异输出差异信号；
时序控制板设置为根据差异信号和第一图像数据信号，对第一图像数据信号进行再处理后输出第二图像数据信号；
若信号差异低于第一设定值，且当前帧第二图像数据信号和上一帧第二图像数据信号的信号差异低于第二设定值，时序控制板输出当前帧第二图像数据信号；
若信号差异低于第一设定值，且当前帧第二图像数据信号和上一帧第二图像数据信号的信号差异高于第二设定值，时序控制板输出上一帧第二图像数据信号。
上述的驱动方法，系统级芯片除了设置为接收待传输的各帧图像数据信号，并对图像数据信号进行处理后输出第一图像数据信号；还设置为根据任一当前帧的图像数据信号和当前帧的上一帧的图像数据信号的信号差异输出差异信号；时序控制板根据第一图像数据信号和差异信号，对第一图像数据信号进行处理后输出第二图像数据信号，若信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异低于第二设定值，时序控制板输出当前帧的第二图像数据信号；若信号差异低于第一设定值，且当前帧的第二图像数据信号和上一帧的第二图像数据信号的信号差异高于第二设定值，时序控制板输出上一帧的第二图像数据信号。从而有效解决了驱动装置中图像数据信号经过系统级芯片和时序控制板处理后被改动的较大，从而导致静态画面闪烁的问题。
进一步地，系统级芯片接收待传输的各帧图像数据信号，并将图像数据信号处理后输出第一图像数据信号，具体包括：
系统级芯片接收待传输的各帧图像数据信号，并将图像数据信号进行扩展后输出第一图像数据信号。
具体地，系统级芯片接收待传输的各帧图像数据信号，并将图像数据信号进行扩展后输出第一图像数据信号，具体包括：
系统级芯片接收待传输的各帧图像数据信号时，提取图像数据信号的每行数据，将每行数据进行扩展两倍处理，并提取处理后的图像数据信号的每列数据，将每列数据进行扩展两倍处理后输出。
为了达到扩展的效果，将每行图像数据信号扩展两倍，将每列图像数据信号扩展两倍，从而实现将全高清图像数据信号转换为超高清数据信号，以适应显示在超高清的显示面板。
进一步地，时序控制板设置为根据差异信号和第一图像数据信号，对第一图像数据信号进行再处理后输出第二图像数据信号，包括：
时序控制板设置为根据差异信号和第一图像数据信号，对第一图像数据信号进行修正后输出第二图像数据信号。其中，对第一图像数据信号进行修正主要通过时序控制板中的颜色处理模块，通过查询存储在颜色处理电路中的查找表对第一图像数据信号进行修正，查找表为输入的第一图像数据信号与输出的第一图像数据信号的信号修正表，对第一图像数据信号进行修正的主要目的是为了提升画面的鲜艳度。
进一步地，对第一图像数据信号进行再处理后输出第二图像数据信号，还包括：
时序控制板将修正后的第一图像数据信号的原始比特数进行转换，并采用抖动的方式输出原始比特数。
其中，通过时序控制板中的数字伽马电路将修正后的第一图像数据信号 的原始比特数进行转换替换后的比特数比原始比特数要大，其主要是为了保证伽马曲线的平滑度，其中，伽马曲线为光学曲线，液晶显示器呈现出来的亮度与人眼感受的亮度是有所差别的，一般人眼对暗的灰阶率，瞳孔会放大，采集到亮度会比较多，因此为了配合人眼的特性，需修正显示的数据满足伽马曲线的要求，使画面从全黑到全白这一过程中的所有阶数是均匀过渡的，不会突亮或突灭。
再通过时序控制板中的抖动处理电路将数字伽马电路输出的替换后的比特数，采用抖动的方法进行输出原始比特数的数据信号，因为后端的时序控制板只能识别原始比特数的数据信号，因此抖动处理电路会根据转换后的数据，再产生新的原始比特数的数据进行输出，由于不同时间会输出不同新的原始比特数的数据，会造成人眼的混合效应，看起来就像是真实的转换后的比特数效果，就可以显示更多的灰阶数。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种驱动装置，分别与信号输出电路、显示面板连接，包括：
    系统级芯片，与所述信号输出电路连接，设置为存储所述信号输出电路输出的待传输的各帧图像数据信号，并将所述图像数据信号处理后输出第一图像数据信号；所述系统级芯片还设置为根据任一当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
    时序控制板，与所述显示面板连接，设置为接收所述第一图像数据信号和所述差异信号，并根据所述第一图像数据信号和所述差异信号，对所述第一图像数据信号进行处理后输出第二图像数据信号；
    若所述信号差异低于第一设定值，所述时序控制板被配置为：
    当所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于第二设定值时，输出所述上一帧的第二图像数据信号；
    当所述当前帧的第二图像数据信号和所述上一帧第二图像数据信号的信号差异低于所述第二设定值时，输出所述当前帧的第二图像数据信号。
  2. 根据权利要求1所述的驱动装置，其中，所述系统级芯片包括：
    第一缓冲电路，与所述信号输出电路连接，设置为存储并输出所述信号输出电路输出的待传输的所述各帧图像数据信号；
    数据比对电路，所述数据比对电路的输入端连接所述信号输出电路和所述第一缓冲电路，设置为根据任一所述当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出所述差异信号；
    第一处理电路，分别与所述第一缓冲电路、时序控制板连接，设置为接收所述图像数据信号，并对所述图像数据信号处理后输出所述第一图像数据信号。
  3. 根据权利要求2所述的驱动装置，其中，所述系统级芯片还包括：
    编码电路，所述编码电路的输入端连接所述数据比对电路和所述第一处理电路，所述编码电路的输出端与所述时序控制板连接，所述编码电路设置为接收所述差异信号和所述第一图像数据信号，并将所述差异信号和所述第一图像数据信号编码后输出。
  4. 根据权利要求3所述的驱动装置，其中，所述编码电路为低电压差分信号编码器。
  5. 根据权利要求2所述的驱动装置，其中，所述时序控制板包括：
    第二处理电路，与所述第一处理电路连接，设置为接收所述第一图像数据信号，并将所述第一图像数据信号处理后输出第二图像数据信号；
    第二缓冲电路，与所述第二处理电路连接，设置为存储并输出所述第二图像数据信号；
    选择电路，所述选择电路的输入端连接所述数据比对电路、所述第二处理电路和所述第二缓冲电路，所述选择电路的输出端与显示面板连接，设置为接收所述差异信号、所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号，所述选择电路被配置为当所述信号差异低于第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于第二设定值时，输出所述上一帧的第二图像数据信号；当所述信号差异低于所述第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异低于所述第二设定值时，输出所述当前帧的第二图像数据信号。
  6. 根据权利要求3所述的驱动装置，其中，所述时序控制板还包括：
    解码电路，与所述编码电路连接，设置为将所述编码电路编码后的所述 差异信号和所述第一图像数据信号解码后输出。
  7. 根据权利要求6所述的驱动装置，其中，所述解码电路为低电压差分信号解码器。
  8. 根据权利要求2所述的驱动装置，其中，所述第一处理电路包括：
    扩展电路，与所述第一缓冲电路连接，设置为接收所述图像数据信号，并对所述图像数据信号进行扩展后输出所述第一图像数据信号。
  9. 根据权利要求8所述的驱动装置，其中，所述扩展电路包括：
    行扩展电路，与所述第一缓冲电路连接，设置为提取所述图像数据信号中的每行数据信号，并将所述每行数据进行行扩展；
    列扩展电路，与所述行扩展电路连接，设置为提取所述进行行处理扩展后的图像数据信号的每列数据信号，并将所述每列数据进行列扩展。
  10. 根据权利要求5所述的驱动装置，其中，所述第二处理电路包括：
    颜色处理电路，与所述第一处理电路连接，设置为接收经过所述第一图像数据信号，并通过查询存储在所述颜色处理电路中的查找表对所述第一图像数据信号进行修正，所述查找表为输入的所述第一图像数据信号与输出的所述第一图像数据信号的信号修正表。
  11. 根据权利要求10所述的驱动装置，其中，所述第二处理电路还包括：
    数字伽马电路，与所述颜色处理电路连接，设置为接收经过所述颜色处理电路修正后的第一图像数据信号，并将所述修正后的第一图像数据信号的原始比特数进行转换，转换后的比特数大于所述原始比特数；
    抖动处理电路，与所述数字伽马电路连接，设置为接收经过所述数字伽马电路转换后的第一图像数据信号，并将所述转换后的第一图像数据信号采用抖动的方式输出所述原始比特数。
  12. 根据权利要求5所述的驱动装置，其中，所述时序控制板还包括：
    过驱动电路，所述过驱动电路的输入端连接所述选择电路和所述第二缓冲电路，所述过驱动电路的输出端与所述显示面板连接，设置为接收所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号，并通过所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异，对所述选择电路输出信号的能力进行加强。
  13. 一种驱动装置，包括系统级芯片和时序控制板，所述系统级芯片包括：
    第一缓冲电路，与信号输出电路连接，设置为存储并输出所述信号输出电路输出的待传输的各帧图像数据信号；
    数据比对电路，所述数据比对电路的输入端连接所述信号输出电路和所述第一缓冲电路，设置为根据任一当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
    第一处理电路，与所述第一缓冲电路连接，设置为接收所述图像数据信号，并对所述图像数据信号处理后输出第一图像数据信号；
    编码电路，所述编码电路的输入端连接所述数据比对电路和所述第一处理电路，所述编码电路的输出端与所述时序控制板连接，所述编码电路设置为接收所述差异信号和所述第一图像数据信号，并将所述差异信号和所述第一图像数据信号编码后输出；
    所述时序控制板包括：
    解码电路，与编码电路连接，设置为将所述编码电路编码后的所述差异信号和所述第一图像数据信号解码后输出；
    第二处理电路，与所述解码电路连接，设置为接收解码后的所述第一图 像数据信号，并将所述第一图像数据信号处理后输出第二图像数据信号；
    第二缓冲电路，与所述第二处理电路连接，设置为存储所述第二图像数据信号，并输出所述第二图像数据信号；
    选择电路，所述选择电路的输入端连接所述解码电路、所述第二处理电路和所述第二缓冲电路，所述选择电路的输出端与显示面板连接，设置为接收所述差异信号、所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号，所述选择电路被配置为当所述信号差异低于第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于第二设定值时，输出所述上一帧的第二图像数据信号；当所述信号差异低于所述第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异低于所述第二设定值时，输出所述当前帧的第二图像数据信号。
  14. 一种驱动方法，基于权利要求1的驱动装置，包括如下步骤：
    系统级芯片接收待传输的各帧图像数据信号，并将所述图像数据信号处理后输出第一图像数据信号；及还设置为根据任一当前帧的图像数据信号和所述当前帧的上一帧的图像数据信号的信号差异输出差异信号；
    时序控制板设置为根据所述差异信号和所述第一图像数据信号，对所述第一图像数据信号进行再处理后输出第二图像数据信号；
    若所述信号差异低于第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异低于第二设定值，所述时序控制板输出所述当前帧的第二图像数据信号；
    若所述信号差异低于所述第一设定值，且所述当前帧的第二图像数据信号和所述上一帧的第二图像数据信号的信号差异高于所述第二设定值，所述 时序控制板输出所述上一帧的第二图像数据信号。
  15. 根据权利要求14所述的驱动方法，其中，所述系统级芯片接收待传输的各帧图像数据信号，并将所述图像数据信号处理后输出第一图像数据信号，具体包括：
    所述系统级芯片接收待传输的各帧图像数据信号，并将所述图像数据信号进行扩展后输出第一图像数据信号。
  16. 根据权利要求15所述的驱动方法，其中，所述系统级芯片接收待传输的各帧图像数据信号，并将所述图像数据信号进行扩展后输出第一图像数据信号，具体包括：
    所述系统级芯片接收待传输的各帧图像数据信号时，提取所述图像数据信号的每行数据，将所述每行数据进行扩展两倍处理，并提取所述处理后的图像数据信号的每列数据，将所述每列数据进行扩展两倍处理后输出。
  17. 根据权利要求14所述的驱动方法，其中，所述时序控制板设置为根据所述差异信号和所述第一图像数据信号，对所述第一图像数据信号进行再处理后输出第二图像数据信号，包括：
    所述时序控制板设置为根据所述差异信号和所述第一图像数据信号，对所述第一图像数据信号进行修正后输出第二图像数据信号。
  18. 根据权利要求17所述的驱动方法，其中，对所述第一图像数据信号进行再修正后输出第二图像数据信号，还包括：
    所述时序控制板将修正后的所述第一图像数据信号的原始比特数进行转换，并采用抖动的方式输出所述原始比特数。
PCT/CN2018/123849 2018-12-13 2018-12-26 驱动装置及其驱动方法 Ceased WO2020118774A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/042,454 US11195486B2 (en) 2018-12-13 2018-12-26 Driving device and driving method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811524372.9 2018-12-13
CN201811524372.9A CN109493828B (zh) 2018-12-13 2018-12-13 驱动装置及其驱动方法、显示装置

Publications (1)

Publication Number Publication Date
WO2020118774A1 true WO2020118774A1 (zh) 2020-06-18

Family

ID=65710124

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/123849 Ceased WO2020118774A1 (zh) 2018-12-13 2018-12-26 驱动装置及其驱动方法

Country Status (3)

Country Link
US (1) US11195486B2 (zh)
CN (1) CN109493828B (zh)
WO (1) WO2020118774A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111402785B (zh) * 2020-03-12 2021-10-01 安徽建德基文化传媒有限公司 分led显示屏抗干扰的视频显示方法、装置及存储介质
CN112164360A (zh) * 2020-09-24 2021-01-01 合肥维信诺科技有限公司 显示驱动电路和显示装置
CN115206226B (zh) * 2022-09-07 2023-01-24 惠科股份有限公司 显示驱动电路和显示面板
CN116486753B (zh) * 2023-04-20 2025-06-24 硅谷数模(苏州)半导体股份有限公司 过驱动补偿方法、过驱动补偿装置和液晶显示系统
CN117079616B (zh) * 2023-10-12 2023-12-15 惠科股份有限公司 补偿电路与显示设备
CN117095654B (zh) * 2023-10-12 2023-12-29 惠科股份有限公司 补偿电路与显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006123706A1 (ja) * 2005-05-20 2006-11-23 Kabushiki Kaisha Toyota Jidoshokki 液晶表示装置及びその駆動方法
CN101232573A (zh) * 2007-01-24 2008-07-30 佳能株式会社 图像处理设备及其方法
CN102006423A (zh) * 2010-11-15 2011-04-06 无锡中星微电子有限公司 一种消除摄像头闪烁现象的方法、装置及一种摄像头
CN102103841A (zh) * 2009-12-21 2011-06-22 乐金显示有限公司 液晶显示设备及其视频处理方法
CN105761695A (zh) * 2016-05-13 2016-07-13 京东方科技集团股份有限公司 驱动电路及其驱动方法和显示装置
CN106547396A (zh) * 2016-10-14 2017-03-29 南京仁光电子科技有限公司 一种提高光学触控系统抗瞬时强光干扰的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4719429B2 (ja) * 2003-06-27 2011-07-06 株式会社 日立ディスプレイズ 表示装置の駆動方法及び表示装置
JP4232114B2 (ja) * 2006-02-17 2009-03-04 ソニー株式会社 データ処理装置およびデータ処理方法、並びにプログラム
US7414795B2 (en) * 2006-05-15 2008-08-19 Eastman Kodak Company Method for driving display with reduced aging
JP2008070783A (ja) * 2006-09-15 2008-03-27 Seiko Epson Corp プロジェクタ、画像表示装置および液晶駆動方法
KR101407295B1 (ko) * 2007-10-19 2014-06-13 엘지디스플레이 주식회사 액정 표시 장치의 구동 장치 및 방법
CN107886916B (zh) * 2009-12-18 2021-09-21 株式会社半导体能源研究所 液晶显示装置及其驱动方法
CN102158633B (zh) * 2011-01-24 2012-12-26 广东威创视讯科技股份有限公司 一种图像信号同步处理方法
TW201234334A (en) * 2011-02-15 2012-08-16 Novatek Microelectronics Corp Driving method for bistable display device and driving device thereof
US10082860B2 (en) * 2011-12-14 2018-09-25 Qualcomm Incorporated Static image power management
CN102903348B (zh) * 2012-09-25 2015-02-04 苏州佳世达光电有限公司 具有判断静态画面功能的显示装置及其判断方法
KR102105410B1 (ko) * 2013-07-25 2020-04-29 삼성전자주식회사 Ddi, 상기 ddi를 포함하는 장치들, 및 이의 동작 방법
KR20160033549A (ko) * 2014-09-18 2016-03-28 삼성전자주식회사 디스플레이 구동회로, 디스플레이 구동회로의 동작방법 및 시스템 온 칩
KR20160089932A (ko) * 2015-01-20 2016-07-29 삼성디스플레이 주식회사 표시장치 및 표시장치의 구동방법
KR102299574B1 (ko) * 2015-01-23 2021-09-07 삼성전자주식회사 디스플레이 잡음을 개선하는 디스플레이 컨트롤러, 이를 포함하는 반도체 집적회로 장치 및 상기 디스플레이 컨트롤러의 동작 방법
JP6513298B2 (ja) * 2016-09-16 2019-05-15 三菱電機株式会社 制御試験装置及び制御試験方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006123706A1 (ja) * 2005-05-20 2006-11-23 Kabushiki Kaisha Toyota Jidoshokki 液晶表示装置及びその駆動方法
CN101232573A (zh) * 2007-01-24 2008-07-30 佳能株式会社 图像处理设备及其方法
CN102103841A (zh) * 2009-12-21 2011-06-22 乐金显示有限公司 液晶显示设备及其视频处理方法
CN102006423A (zh) * 2010-11-15 2011-04-06 无锡中星微电子有限公司 一种消除摄像头闪烁现象的方法、装置及一种摄像头
CN105761695A (zh) * 2016-05-13 2016-07-13 京东方科技集团股份有限公司 驱动电路及其驱动方法和显示装置
CN106547396A (zh) * 2016-10-14 2017-03-29 南京仁光电子科技有限公司 一种提高光学触控系统抗瞬时强光干扰的方法

Also Published As

Publication number Publication date
US20210125573A1 (en) 2021-04-29
CN109493828A (zh) 2019-03-19
CN109493828B (zh) 2020-08-04
US11195486B2 (en) 2021-12-07

Similar Documents

Publication Publication Date Title
WO2020118774A1 (zh) 驱动装置及其驱动方法
US7307644B2 (en) Method and system for efficient interfacing to frame sequential display devices
KR100943278B1 (ko) 액정 표시 장치와 이의 구동 장치 및 방법
WO2017028381A1 (zh) 一种激光电视的图像处理方法、系统及激光电视
US20170034450A1 (en) Data processing method and device for led television, and led television
CN101102487A (zh) 基于vga和hdmi两种显示模式的视频传输系统及方法
US8854289B2 (en) Intra-system interface unit of flat panel display
CN115604409B (zh) 一种显示设备及其驱动方法
US11100682B2 (en) Image processing device and image processing method
US11637964B2 (en) Image processing apparatus, image display system, image processing method having a time dithering process
KR102371823B1 (ko) 디스플레이 장치에서의 데이터송수신방법 및 디스플레이 패널구동장치
US9898993B2 (en) Method for controlling message signal within timing controller integrated circuit, timing controller integrated circuit and display panel
US7573534B2 (en) Digital display appliance and method for outputting video data
JPH01272280A (ja) 画像データ伝送方式及び表示方法
US11308899B2 (en) Method and device for driving a display panel, and a display device
US10778946B1 (en) Active screen for large venue and dome high dynamic range image projection
CN116343707B (zh) 一种场序显示装置、控制方法及显示设备
CN103024319A (zh) 控制电视机一屏多显的方法和装置
CN107846588B (zh) 电视中串口记录信息的获取方法和装置
US20050212969A1 (en) Apparatus and method of image display with real-time compression
US11315474B2 (en) Method and device for driving display panel, and display device
TWI526060B (zh) 用於在未壓縮的視訊互連上傳輸之影像資料的感知無損壓縮
CN109391791B (zh) 用于单片lcd投影设备的mipi视频信号转换方法及其装置
KR20060036953A (ko) 액정표시장치 및 그 구동방법
KR20130118178A (ko) 표시장치와 그 데이터 압축 전송 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18942780

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.11.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18942780

Country of ref document: EP

Kind code of ref document: A1