WO2020113599A1 - 主动开关及其制作方法、显示装置 - Google Patents

主动开关及其制作方法、显示装置 Download PDF

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WO2020113599A1
WO2020113599A1 PCT/CN2018/120136 CN2018120136W WO2020113599A1 WO 2020113599 A1 WO2020113599 A1 WO 2020113599A1 CN 2018120136 W CN2018120136 W CN 2018120136W WO 2020113599 A1 WO2020113599 A1 WO 2020113599A1
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layer
electrode
substrate
gate
active switch
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French (fr)
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宋振莉
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular, to an active switch, a manufacturing method thereof, and a display device.
  • LCD Liquid Crystal
  • LCD Liquid Crystal
  • the FFS liquid crystal display device commonly used at present may generally include an upper substrate, a lower substrate, and a liquid crystal layer between the upper and lower substrates.
  • the lower substrate is generally provided with a pixel electrode and a common electrode.
  • the pixel electrode and the common electrode may be planar or have a slit structure; in order to increase the transmittance, the common electrode and the pixel electrode are generally made in different layers.
  • a layer of metal is generally used to connect the pixels of the same gate line, and the layer of metal is input with a COM signal, and then connected to the common electrode by directly contacting the common electrode or by digging a hole In order to ensure the stability of the potential of the common electrode.
  • the aperture ratio will be lost.
  • an active switch that can reduce the loss of aperture ratio is provided.
  • An active switch including:
  • a gate insulating layer formed on the substrate and covering the gate
  • Source electrode and drain electrode are formed on both sides of the oxide semiconductor layer
  • An electrode stabilization layer is formed on the common electrode; wherein, the projection of the electrode stabilization layer on the substrate overlaps with the projection of the grid on the substrate.
  • An active switch manufacturing method is set to manufacture an active switch.
  • the active switch includes:
  • a gate insulating layer formed on the substrate and covering the gate
  • Source electrode and drain electrode are formed on both sides of the oxide semiconductor layer
  • the method includes:
  • a display device includes an array substrate.
  • the array substrate includes a display area, a peripheral area, and a switch tube area.
  • the switch tube area is provided with an active switch.
  • the active switch includes:
  • a gate insulating layer formed on the substrate and covering the gate
  • Source electrode and drain electrode are formed on both sides of the oxide semiconductor layer
  • An electrode stabilization layer is formed on the common electrode; wherein, the projection of the electrode stabilization layer on the substrate overlaps with the projection of the grid on the substrate.
  • the potential of the common electrode can be stabilized;
  • the projection on the substrate overlaps, that is to say, when the light is emitted from the backlight board, the grid will block a part of the light. Because the electrode stabilization layer and the grid overlap in the vertical direction, the grid The blocked light and the light blocked by the electrode stabilization layer will overlap, so this arrangement (the projection of the electrode stabilization layer on the substrate and the projection of the grid on the substrate overlap) can make the electrode stabilization layer not too much Affects the transmission of light, thereby reducing the loss of aperture ratio.
  • FIG. 1 is a schematic structural diagram of an active switch in an embodiment
  • FIG. 2 is a schematic flowchart of a method for manufacturing an active switch in an embodiment
  • FIG. 3 is a schematic diagram of a part of the structure formed according to step S10 in FIG. 2;
  • FIG. 4 is a schematic diagram of a part of the structure formed according to step S20 in FIG. 2;
  • FIG. 5 is a partial structural diagram formed according to step S30 in FIG. 2;
  • FIG. 6 is a schematic diagram of a part of the structure formed according to step S40 in FIG. 2;
  • FIG. 7 and 8 are schematic diagrams of partial structures formed according to step S50 in FIG. 2;
  • FIG. 9 is a schematic diagram of a part of the structure formed according to step S60 in FIG. 2;
  • FIG. 10 is a schematic diagram of a part of the structure formed according to step S70 in FIG. 2;
  • FIG. 11 is a schematic structural diagram of an array substrate in an embodiment.
  • the active switch may include: a substrate 10, a gate 20, a gate insulating layer 30, an oxide semiconductor layer 40, a source 510, and a drain 520, The first protective layer 60, the flat layer 70, the common electrode 80 and the electrode stabilization layer 90.
  • the gate 20 is formed on the substrate 10; the gate insulating layer 30 is formed on the substrate 10 and covers the gate 20; the oxide semiconductor layer 40 is formed on the gate insulating layer 30 corresponding to the gate; the source 510 The drain 520 is formed on both sides of the oxide semiconductor layer 40; the first protective layer 60 is formed on the source 510 and the drain 520; the flat layer 70 is formed on the first protective layer 60; the common electrode 80 is formed on The flat layer 70 corresponds to the top of the gate electrode 20; the electrode stabilizing layer 90 is formed on the common electrode 80; wherein, the projection of the electrode stabilizing layer 90 on the substrate 10 overlaps with the projection of the gate electrode 20 on the substrate 10.
  • the potential of the common electrode can be stabilized, on the other hand, due to the projection of the electrode stabilization layer on the substrate
  • the projection on the substrate overlaps, that is to say, when the light is emitted from the backlight board, the grid will block a part of the light. Because the electrode stabilization layer and the grid overlap in the vertical direction, the grid The blocked light and the light blocked by the electrode stabilization layer will overlap, so this arrangement (the projection of the electrode stabilization layer on the substrate and the projection of the grid on the substrate overlap) can make the electrode stabilization layer not too much Affects the transmission of light, thereby reducing the loss of aperture ratio.
  • the substrate 10 may be a glass substrate or a plastic substrate, wherein the glass substrate may be alkali-free borosilicate ultra-thin glass, and the alkali-free borosilicate glass has higher physical characteristics, better corrosion resistance, and higher Thermal stability and lower density and higher modulus of elasticity.
  • the grid 20 is formed on the substrate 10, wherein the formation process of the grid 20 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • the material of the gate 20 may be one or more of a stack combination of molybdenum, titanium, aluminum, and copper; selecting molybdenum, titanium, aluminum, and copper as the material of the gate 20 can ensure good conductivity. It can be understood that the material of the gate 20 can be selected and adjusted according to the actual application situation and product performance, and is not further limited herein.
  • the gate insulating layer 30 is formed on the substrate 10.
  • the formation process of the gate insulating layer 30 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate insulating layer 30 may be one or a combination of silicon oxide and silicon nitride, that is, the gate insulating layer 30 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen Silicone mixture.
  • the material of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the thickness of the gate insulating layer 30 may be 1000 angstroms-4000 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 1000 angstroms-2500 angstroms. Further, the thickness of the gate insulating layer 30 may be 2500 angstroms-4000 angstroms. Egypt. It can be understood that the thickness of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the oxide semiconductor layer 40 is formed above the gate insulating layer 30 corresponding to the gate 20, that is, the oxide semiconductor layer 40 is formed only above the gate 20.
  • the formation process of the oxide semiconductor layer 40 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the oxide semiconductor layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the oxide semiconductor layer 40 is indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), and the use of metal oxide as the active layer material of the thin film transistor has the following two advantages: (1) Forbidden bandwidth ( >3.0eV), which can bring very good light stability, so unlike amorphous silicon thin film transistors, metal oxide thin film transistors can be made into fully transparent devices, thereby significantly increasing the aperture ratio of the display panel, thereby reducing the display device Power consumption; (2) high mobility (about 10cm2/V ⁇ s). In short, metal oxide thin film transistors can have both the technical advantages of amorphous silicon thin film transistors and polycrystalline silicon thin film transistors, and are feasible in mass production.
  • Forbidden bandwidth >3.0eV
  • metal oxide thin film transistors can be made into fully transparent devices, thereby significantly increasing the aperture ratio of the display panel, thereby reducing the display device Power consumption
  • high mobility about 10cm2/V ⁇ s.
  • metal oxide thin film transistors can have both the technical advantages of amorphous
  • the thickness of the oxide semiconductor layer 40 may be 200 angstroms-1000 angstroms. Alternatively, the thickness of the oxide semiconductor layer 40 may be 200 angstroms-600 angstroms. Further, the thickness of the oxide semiconductor layer 40 may be 600 angstroms-1000 angstroms. Egypt. It can be understood that the thickness of the oxide semiconductor layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the source electrode 510 and the drain electrode 520 are formed on both sides of the oxide semiconductor layer 40.
  • the formation process of the source electrode 510 and the drain electrode 520 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the source electrode 510 and the drain electrode 520 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the materials of the source electrode 510 and the drain electrode 520 can be one or more of a stack combination of molybdenum, titanium, aluminum, and copper; choosing molybdenum, titanium, aluminum, and copper as the source electrode 510 and the drain electrode 520 materials can ensure good Conductive properties. It can be understood that the materials of the source electrode 510 and the drain electrode 520 can be selected and adjusted according to actual application conditions and product performance, and are not further limited herein.
  • the first protective layer 60 is formed on the source electrode 510 and the drain electrode 520.
  • the forming process of the first protective layer 60 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the first protective layer 60 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the first protective layer 60 may be one of silicon oxide, silicon nitride, or a combination of the two, that is, the first protective layer 60 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen. Silicone mixture. It can be understood that the material of the first protective layer 60 can be selected and adjusted according to the actual application situation and product performance, which is not further limited herein.
  • the flat layer 70 is formed on the first protective layer 60.
  • the formation process of the flat layer 70 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the flat layer 70 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the thickness of the flat layer 70 may be 2000 nm-3000 nm; alternatively, the thickness of the flat layer 70 may be 2000 nm-2500 nm; alternatively, the thickness of the flat layer 70 may be 2500 nm-3000 nm. It can be understood that the thickness of the flat layer 70 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the common electrode 80 is formed above the flat layer 70 corresponding to the gate electrode 20.
  • the forming process of the common electrode 80 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the common electrode 80 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the common electrode 80 may be a transparent metal oxide, and the transparent metal oxide may be one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, and indium germanium zinc oxide.
  • the electrode stabilization layer 90 is formed on the common electrode 80; wherein, the projection of the electrode stabilization layer 90 on the substrate 10 overlaps with the projection of the grid 20 on the substrate 10.
  • the grid 20 is made of opaque metal, so it will block part of the light.
  • the electrode stabilizing layer 90 and the grid 20 are perpendicular to the substrate There is an overlap in the direction, so the light blocked by the grid 20 and the light blocked by the electrode stabilization layer 90 will overlap, then, this arrangement (the projection of the electrode stabilization layer on the substrate overlaps the projection of the grid on the substrate ), the electrode stabilization layer 90 will not affect the light transmission too much, thereby reducing the loss of aperture ratio.
  • the material of the electrode stabilizing layer 90 may be one or more of a stack combination of molybdenum, titanium, aluminum, and copper; selecting molybdenum, titanium, aluminum, and copper as the material of the gate electrode 20 can ensure good conductivity. It can be understood that the material of the electrode stabilization layer 90 can be selected and adjusted according to the actual application situation and product performance, and is not further limited herein.
  • the thickness of the electrode stabilizing layer 90 may range from 1000 angstroms to 6000 angstroms. Alternatively, the thickness of the electrode stabilizing layer 90 may range from 1000 angstroms to 3500 angstroms. Further, the thickness of the electrode stabilizing layer 90 may range from 3500 angstroms to 6000 angstroms.
  • the thickness of the electrode stabilizing layer 90 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein. Since the flat layer 70 is sandwiched between the gate 20 and the electrode stabilizing layer 90, and the thickness of the flat layer 70 is 2000 nm-3000 nm, that is, the distance between the gate and the electrode stabilizing layer is very far, so the gate line The load on will not have much impact. Further, since the electrode stabilization layer 90 directly contacts the common electrode 80, the metal trace (COM signal) originally parallel to the gate electrode 20 can be omitted, and the aperture ratio can be increased.
  • FIG. 2 is a schematic flowchart of a method for manufacturing an active switch in an embodiment; the method is used to manufacture the active switch described above; the method may include steps S10-S70.
  • Step S10 providing a substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the glass substrate may be an alkali-free borosilicate ultra-thin glass.
  • the alkali-free borosilicate glass has higher physical characteristics Good corrosion resistance, higher thermal stability and lower density and higher elastic modulus.
  • a first metal layer (not shown in FIG. 3) is formed on the substrate 10.
  • the formation process of the first metal layer may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the first metal layer can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the first metal layer is patterned to form the gate 20.
  • a photoresist layer (not shown in FIG. 3) may be coated on the first metal layer, and then a photomask process is used to pattern the photoresist layer to obtain a photoresist with a preset pattern ( (Not shown in FIG. 3), on this basis, a wet etching process may be used to etch the first metal layer to form the gate electrode 20.
  • Step S20 forming a gate insulating layer on the gate.
  • a gate insulating layer 30 is formed on the gate 20.
  • the formed gate insulating layer 30 covers the gate electrode 20.
  • the forming process of the gate insulating layer 30 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • Step S30 a semiconductor layer is deposited on the gate insulating layer, and the semiconductor layer is etched to form an oxide semiconductor layer corresponding to the gate.
  • a semiconductor layer (not shown in FIG. 5) is formed on the gate insulating layer 30, and the semiconductor layer is etched to form an oxide semiconductor layer 40 corresponding to the gate 20.
  • a semiconductor layer can be formed on the gate insulating layer 30 by radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition processes, and then a photoresist layer is coated on the semiconductor layer ( Figure 5 is not Mark), and then use a photomask process to pattern the photoresist layer to obtain a photoresist with a preset pattern (not shown in FIG. 5). On this basis, a dry etching process is applied to the first metal layer Etching is performed to form the oxide semiconductor layer 40.
  • the material of the oxide semiconductor layer 40 may be indium gallium zinc oxide.
  • Step S40 a second metal layer is deposited on the oxide semiconductor layer, and the second metal layer is etched to form a source electrode and a drain electrode covering both sides of the oxide semiconductor layer.
  • the forming process of the second metal layer may include RF magnetron sputtering, thermal evaporation, and vacuum electrons. Beam evaporation and plasma enhanced chemical vapor deposition processes. It can be understood that the forming process of the second metal layer can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the second metal layer is etched to form the source electrode 510 and the drain electrode 520 covering both sides of the oxide semiconductor layer 40. Specifically, a photoresist layer (not shown in FIG.
  • the second metal layer may be coated on the second metal layer, and then a photomask process is used to pattern the photoresist layer to obtain a photoresist with a predetermined pattern ( (Not shown in FIG. 6), on this basis, the second metal layer is etched by a wet etching process to form the source electrode 510 and the drain electrode 520, wherein the source electrode 510 and the oxide semiconductor layer 40 are realized on one side
  • the drain 520 is electrically connected to the other side of the oxide semiconductor layer 40.
  • Step S50 a first protective layer and a flat layer are sequentially formed on the source electrode and the drain electrode.
  • the first protective layer 60 and the flat layer 70 may be sequentially deposited on the source electrode 510 and the drain electrode 520.
  • the deposition process may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming processes of the first protective layer 60 and the flat layer 70 can be selected and adjusted according to actual application conditions and product performance, and are not further limited herein.
  • Step S60 a third metal layer is deposited on the flat layer, and the third metal layer is etched to form a common electrode corresponding to the gate.
  • FIG. 9 deposit and form a third metal layer on the flat layer 70 (not shown in FIG. 9 ).
  • the forming process of the third metal layer may include RF magnetron sputtering, thermal evaporation, and vacuum electron beam evaporation And plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the third metal layer can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the third metal layer is etched to form a common electrode 80 corresponding to the gate 20. Specifically, a photoresist layer (not shown in FIG.
  • a photomask process is used to pattern the photoresist layer to obtain a photoresist with a preset pattern ( 9 is not marked), on this basis, the third metal layer is etched using a wet etching process to form a common electrode 80 corresponding to the gate 20.
  • Step S70 depositing a fourth metal layer on the common electrode, and etching the fourth metal layer to form an electrode stabilizing layer; wherein, the projection of the electrode stabilizing layer on the substrate and the gate The projections on the substrate overlap.
  • a fourth metal layer (not shown in FIG. 10) on the common electrode 80.
  • the formation process of the fourth metal layer may include RF magnetron sputtering, thermal evaporation, and vacuum electron beam evaporation And plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the fourth metal layer can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the fourth metal layer is etched to form an electrode stabilizing layer 90, wherein the projection of the electrode stabilizing layer 90 on the substrate 10 overlaps with the projection of the gate electrode 20 on the substrate 10.
  • a photoresist layer (not shown in FIG.
  • the fourth metal layer may be coated on the fourth metal layer, and then a photomask process is used to pattern the photoresist layer to obtain a photoresist with a predetermined pattern ( (Not shown in FIG. 10), on this basis, the fourth metal layer is etched using a wet etching process to form the electrode stabilizing layer 90.
  • the projection of the electrode stabilization layer 90 on the substrate 10 overlaps with the projection of the grid 20 on the substrate 10. In other words, when light is emitted from the backlight, the grid 20 is made of opaque metal, so it will block part of the light.
  • the electrode stabilizing layer 90 and the grid 20 are perpendicular to the substrate There is an overlap in the direction, so the light blocked by the grid 20 and the light blocked by the electrode stabilization layer 90 will overlap, then, this arrangement (the projection of the electrode stabilization layer on the substrate overlaps the projection of the grid on the substrate ), the electrode stabilization layer 90 will not affect the light transmission too much, thereby reducing the loss of aperture ratio.
  • the manufacturing method of the above active switch because the manufactured active switch forms a common electrode on a flat layer and makes the electrode stabilizing layer directly contact with the common electrode, on the one hand, the potential of the common electrode can be stabilized, on the other hand, because the electrode is stable
  • the projection of the layer on the substrate overlaps with the projection of the grid on the substrate, that is to say, when the light is emitted from the backlight board, the grid will block part of the light, because the electrode stabilizing layer and the grid are perpendicular There is an overlap in the direction, so the light blocked by the grid and the light blocked by the electrode stabilization layer will overlap. Then, this arrangement (the projection of the electrode stabilization layer on the substrate overlaps the projection of the grid on the substrate) The electrode stabilization layer will not affect the light transmission too much, thereby reducing the loss of aperture ratio.
  • FIG. 11 is a schematic structural diagram of an array substrate in an embodiment
  • the array substrate may include a switch region 1, a display region 2 and a peripheral region 3, wherein the switch region 1 is provided with the aforementioned active switches.
  • the active switch may further include a second protective layer 100 and a pixel electrode 110; wherein, the second protective layer 100 is formed on the electrode stabilizing layer 90; the pixel electrode 110 is formed on the second protective layer 100
  • the pixel electrode 110 is connected to the drain 520 through a via H1 penetrating the second protective layer 100, the flat layer 70, and the first protective layer 60.
  • the second protective layer 100 may be one of silicon oxide, silicon nitride, or a combination of the two, that is, the protective insulating layer 90 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen. Silicone mixture.
  • the material of the second protective layer 100 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the formation process of the pixel electrode 100 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the pixel electrode 100 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the pixel electrode 100 may be one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide.
  • the pixel electrode 110 and the drain 520 are electrically connected through a via H1 that penetrates the second protective layer 100, the flat layer 70 and the first protective layer 60.
  • "Through" can be formed by a photolithography or etching process. Specifically, photolithography refers to the use of a reticle with a certain layer of design graphics. After exposure and development, the photosensitive photoresist forms a three-dimensional relief on the substrate Graphics. Etching means that under the masking of photoresist, different microlayer patterns are formed as required, and different etching substances and methods are used to selectively etch the film layers. In this way, after removing the photoresist, the three-dimensional design pattern is transferred to the relevant film layer of the substrate.
  • the above-mentioned array substrate adopts the aforementioned active switch.
  • the potential of the common electrode can be stabilized, on the other hand,
  • the projection of the electrode stabilization layer on the substrate overlaps with the projection of the grid on the substrate, that is to say, when light is emitted from the backlight board, the grid will block a part of the light, because the electrode stabilization layer and the grid The electrodes overlap in the vertical direction, so the light blocked by the grid and the light blocked by the electrode stabilization layer will overlap. Then, this configuration (the projection of the electrode stabilization layer on the substrate and the projection of the grid on the substrate overlap Stacking), the electrode stabilization layer will not affect the light transmission too much, thereby reducing the loss of aperture ratio.
  • a display device which includes the aforementioned array substrate. Since the array substrate uses the aforementioned active switch, the active switch forms a common electrode on a flat layer, and the electrode stabilizing layer directly contacts the common electrode. On the one hand, the potential of the common electrode can be stabilized; on the other hand, because the projection of the electrode stabilization layer on the substrate overlaps with the projection of the grid on the substrate, that is, when light is emitted from the backlight, the grid It will block a part of the light, because the electrode stabilization layer and the grid overlap in the vertical direction, so the light blocked by the grid and the light blocked by the electrode stabilization layer will overlap. Then, set this (the electrode stabilization layer is in The projection on the substrate overlaps with the projection of the grid on the substrate), so that the electrode stabilization layer will not affect the transmission of light too much, thereby reducing the loss of aperture ratio.

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Abstract

本申请涉及一种主动开关及其制作方法、显示装置。该主动开关包括基板；栅极，形成于基板上；栅极绝缘层，形成于栅极上；氧化物半导体层，形成于栅极绝缘层对应于栅极的上方；源极、漏极，形成于氧化物半导体层的两侧边沿上；第一保护层，形成于源极、漏极上；平坦层，形成于第一保护层上；公共电极，形成于平坦层对应于栅极的上方；电极稳定层，形成于公共电极上；其中，电极稳定层在基板上的投影与栅极在基板上的投影有交叠。

Description

主动开关及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2018年12月03日提交中国专利局、申请号为201811465751.5、申请名称为“主动开关及其制作方法、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种主动开关及其制作方法、显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
目前LCD(Liquid Crystal Display,液晶显示器)面板作为最广泛使用的显示器之一，可为各种电子设备如移动电话、个人数字助理(PDA)、数字相机以及计算机等提供高分辨率彩色屏幕。其中FFS(Fringe Field Switching，边缘场开关技术)液晶显示装置以及其广视角、高开口率等特点受到广大用户的喜爱。
目前普遍采用的FFS液晶显示装置，通常可以包括上基板、下基板以及上下基板之间的液晶层。其中下基板上一般设置有像素电极和公共电极，像素电极和公共电极可分别为平面状或者具有狭缝结构；为了增大穿透率，一般公共电极和像素电极制作在不同层别。当前设计为了稳定公共电极上的电位，一般会采用一层金属串联同一条栅极线的像素，同时使该层金属输入 COM信号，然后通过直接接触公共电极或者通过挖孔的方式连接至公共电极，以此来保证公共电极的电位稳定。但是不管上述哪种接触方式，都会损失开口率。
申请内容
根据本申请的各种实施例，提供一种可以减小开口率损失的主动开关。
此外，还提供一种主动开关的制作方法、显示装置。
一种主动开关，包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
第一保护层，形成于所述源极、漏极上；
平坦层，形成于所述第一保护层上；
公共电极，形成于所述平坦层对应于所述栅极的上方；及
电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
一种主动开关的制作方法，设置为制造主动开关，所述主动开关包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
第一保护层，形成于所述源极、漏极上；
平坦层，形成于所述第一保护层上；
公共电极，形成于所述平坦层对应于所述栅极的上方；及
电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠；
所述方法包括：
提供一基板，并在所述基板上沉积第一金属层，对所述第一金属层进行图案化处理形成栅极；
在所述栅极上形成栅极绝缘层；
在所述栅极绝缘层上沉积半导体层、并对所述半导体层进行刻蚀以形成对应于所述栅极上方的氧化物半导体层；
在所述氧化物半导体层上沉积第二金属层，对所述第二金属层进行刻蚀以形成覆盖于所述氧化物半导体层两侧边沿的源极、漏极；
在所述源极、漏极上依次形成第一保护层、平坦层；
在所述平坦层上沉积第三金属层，对所述第三金属层进行刻蚀以形成对应于所述栅极上方的公共电极；及
在所述公共电极上沉积第四金属层，对所述第四金属层进行刻蚀以形成电极稳定层；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
一种显示装置，包括阵列基板，所述阵列基板包括显示区域、外围区域和开关管区域，所述开关管区域设置有主动开关，所述主动开关包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
第一保护层，形成于所述源极、漏极上；
平坦层，形成于所述第一保护层上；
公共电极，形成于所述平坦层对应于所述栅极的上方；及
电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
上述主动开关，通过在平坦层上形成公共电极，并且使电极稳定层直接与公共电极接触，一方面可以保证公共电极的电位稳定，另一方面，由于电极稳定层在基板上的投影与栅极在基板上的投影有交叠，也即是说，当光线由背光板发射出来时，栅极会遮挡住一部分的光线，由于电极稳定层和栅极在垂直方向上有交叠，所以栅极遮挡的光线和电极稳定层遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交叠)就可以让电极稳定层不会过多的影响光线的透过，从而减小开口率的损失。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的 附图。
图1为一实施例中的主动开关的结构示意图；
图2为一实施例中的主动开关的制作方法流程示意图；
图3为根据图2中步骤S10形成的部分结构示意图；
图4为根据图2中步骤S20形成的部分结构示意图；
图5为根据图2中步骤S30形成的部分结构示意图；
图6为根据图2中步骤S40形成的部分结构示意图；
图7、图8为根据图2中步骤S50形成的部分结构示意图；
图9为根据图2中步骤S60形成的部分结构示意图；
图10为根据图2中步骤S70形成的部分结构示意图；
图11为一实施例中的阵列基板的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的可选的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于申请的技术领域的技术人员通常理解的含义相同。本文中在申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参照图1，为一实施例中的主动开关的结构示意图；该主动开关可以包括：基板10，栅极20，栅极绝缘层30，氧化物半导体层40，源极510、 漏极520，第一保护层60，平坦层70，公共电极80及电极稳定层90。其中，栅极20形成于基板10上；栅极绝缘层30形成于基板10上、并覆盖栅极20；氧化物半导体层40形成于栅极绝缘层30对应于栅极的上方；源极510、漏极520形成于氧化物半导体层40的两侧边沿上；第一保护层60形成于源极510、漏极520上；平坦层70形成于第一保护层60上；公共电极80形成于平坦层70对应于栅极20的上方；电极稳定层90形成于公共电极80上；其中，电极稳定层90在基板10上的投影与栅极20在基板10上的投影有交叠。
上述实施例，通过在平坦层上形成公共电极，并且使电极稳定层直接与公共电极接触，一方面可以保证公共电极的电位稳定，另一方面，由于电极稳定层在基板上的投影与栅极在基板上的投影有交叠，也即是说，当光线由背光板发射出来时，栅极会遮挡住一部分的光线，由于电极稳定层和栅极在垂直方向上有交叠，所以栅极遮挡的光线和电极稳定层遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交叠)就可以让电极稳定层不会过多的影响光线的透过，从而减小开口率的损失。
基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。
栅极20形成于基板10上，其中，栅极20的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极20的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极20的材料可以为钼、钛、铝和 铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为栅极20材料可以保证良好的导电性能。可以理解，栅极20的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
栅极绝缘层30形成于基板10上，栅极绝缘层30的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极绝缘层30的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的材料可以是氧化硅、氮化硅中的一种或者二者的组合，即栅极绝缘层30可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。可以理解，栅极绝缘层30的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的厚度可以为1000埃-4000埃，可选地，栅极绝缘层30的厚度可以为1000埃-2500埃，进一步地，栅极绝缘层30的厚度可以为2500埃-4000埃。可以理解，栅极绝缘层30的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
氧化物半导体层40形成于栅极绝缘层30对应栅极20的上方，也即是说，氧化物半导体层40仅形成在与栅极20相对的上方。氧化物半导体层40的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，氧化物半导体层40的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。进一步地，氧化物半导体层40的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)，使用金属氧化物作为薄膜晶体管的有源层材料具有以下两方面的优点：(1)禁带宽(＞3.0eV)，由此可带来非常好的 光照稳定性，所以与非晶硅薄膜晶体管不同，金属氧化物薄膜晶体管可以制作成全透明器件，从而显著增加显示面板的开口率，进而降低显示装置的功耗；(2)高迁移率(约为10cm2/V·s)。总而言之，金属氧化物薄膜晶体管可同时具备非晶硅薄膜晶体管和多晶硅薄膜晶体管的技术优势，且在大规模量产上具有可行性。氧化物半导体层40的厚度可以为200埃-1000埃，可选地，氧化物半导体层40的厚度可以为200埃-600埃，进一步地，氧化物半导体层40的厚度可以为600埃-1000埃。可以理解，氧化物半导体层40的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
源极510与漏极520形成于氧化物半导体层40的两侧边沿上。源极510与漏极520的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，源极510与漏极520的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。源极510与漏极520的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为源极510与漏极520材料可以保证良好的导电性能。可以理解，源极510与漏极520的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
第一保护层60形成于源极510、漏极520上，第一保护层60的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第一保护层60的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。第一保护层60的材料可以是氧化硅、氮化硅中的一种或者二者的组合，即第一保 护层60可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。可以理解，第一保护层60的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
平坦层70形成于第一保护层60上。平坦层70的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，平坦层70的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。平坦层70的厚度可以为2000纳米-3000纳米；可选地，平坦层70的厚度可以为2000纳米-2500纳米；可选地，平坦层70的厚度可以为2500纳米-3000纳米。可以理解，平坦层70的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
公共电极80形成于平坦层70对应于栅极20的上方。公共电极80的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，公共电极80的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。公共电极80可以为透明金属氧化物，透明金属氧化物可以为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
电极稳定层90形成于公共电极80上；其中，电极稳定层90在基板10上的投影与栅极20在基板10上的投影有交叠。换句话说，当光线由背光板发射出来时，栅极20由于采用的是不透光的金属制成，所以会遮挡住一部分的光线，由于电极稳定层90和栅极20在垂直于基板的方向上有交叠，所以栅极20遮挡的光线和电极稳定层90遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交 叠)就可以让电极稳定层90不会过多的影响光线的透过，从而减少开口率的损失。电极稳定层90的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为栅极20材料可以保证良好的导电性能。可以理解，电极稳定层90的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。电极稳定层90的厚度范围可以为1000埃-6000埃，可选地，电极稳定层90的厚度可以为1000埃-3500埃，进一步地，电极稳定层90的厚度可以为3500埃-6000埃。可以理解，电极稳定层90的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。由于栅极20与电极稳定层90之间夹有平坦层70，并且平坦层70的厚度为2000纳米-3000纳米，也即是栅极和电极稳定层之间的距离很远，所以栅极线上的负载不会有太大的影响。进一步地，由于电极稳定层90直接与公共电极80接触，所以可以将原先与栅极20平行的金属走线(COM信号)省去，增大开口率。
请参阅图2，为一实施例中的主动开关的制作方法流程示意图；该方法用于制造前述所述的主动开关；该方法可以包括步骤S10-S70。
步骤S10，提供一基板，并在所述基板上沉积第一金属层，对所述第一金属层进行图案化处理形成栅极。
具体地，请辅助参阅图3，基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。在基板10上形成第一金属层(图3未标示)，第一金属层的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第一金属层的形成工艺可以根据实际应用情 况以及产品性能进行选择和调整，在此不作进一步的限定。对第一金属层进行图案化处理形成栅极20。具体地，可在第一金属层的上方涂布一层光阻层(图3未标示)，然后采用一道光罩工艺对光阻层进行图案化处理，得到具有预设图案的光刻胶(图3未标示)，在此基础上，可采用湿法刻蚀工艺对第一金属层进行刻蚀以形成栅极20。
步骤S20，在所述栅极上形成栅极绝缘层。
具体地，请参阅图4，在栅极20上形成栅极绝缘层30。形成的栅极绝缘层30将栅极20覆盖住，栅极绝缘层30的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极绝缘层30的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
步骤S30，在所述栅极绝缘层上沉积半导体层、并对所述半导体层进行刻蚀以形成对应于所述栅极上方的氧化物半导体层。
具体地，请辅助参阅图5，在栅极绝缘层30上形成半导体层(图5未标示)，对半导体层进行刻蚀以形成对应于栅极20上方的氧化物半导体层40。可通过射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺在栅极绝缘层30上形成半导体层，然后在半导体层的上方涂布一层光阻层(图5未标示)，然后采用一道光罩工艺对光阻层进行图案化处理，得到具有预设图案的光刻胶(图5未标示)，在此基础上，采用干法刻蚀工艺对第一金属层进行刻蚀以形成氧化物半导体层40。氧化物半导体层40的材料可以为铟镓锌氧化物。
步骤S40，在所述氧化物半导体层上沉积第二金属层，对所述第二金属层进行刻蚀以形成覆盖于所述氧化物半导体层两侧边沿的源极、漏极。
具体地，请辅助参阅图6，在氧化物半导体层40上沉积形成第二金属层(图6未标示)，对第二金属层的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第二金属层的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。对第二金属层进行刻蚀以形成覆盖于氧化物半导体层40两侧边沿的源极510、漏极520。具体地，可在第二金属层的上方涂布一层光阻层(图6未标示)，然后采用一道光罩工艺对光阻层进行图案化处理，得到具有预设图案的光刻胶(图6未标示)，在此基础上，采用湿法刻蚀工艺对第二金属层进行刻蚀以形成源极510、漏极520，其中，源极510与氧化物半导体层40的一侧实现电连接，漏极520与氧化物半导体层40的另一侧实现电连接。
步骤S50，在所述源极、漏极上依次形成第一保护层、平坦层。
具体地，请辅助参阅图7、图8。可在源极510、漏极520上依次沉积形成第一保护层60和平坦层70，沉积工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第一保护层60和平坦层70的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
步骤S60，在所述平坦层上沉积第三金属层，对所述第三金属层进行刻蚀以形成对应于所述栅极上方的公共电极。
具体地，请辅助参阅图9，在平坦层70上沉积形成第三金属层(图9未标示)，对第三金属层的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第三金属层的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作 进一步的限定。对第三金属层进行刻蚀以形成对应于栅极20上方的公共电极80。具体地，可在第三金属层的上方涂布一层光阻层(图9未标示)，然后采用一道光罩工艺对光阻层进行图案化处理，得到具有预设图案的光刻胶(图9未标示)，在此基础上，采用湿法刻蚀工艺对第三金属层进行刻蚀以形成对应于栅极20上方的公共电极80。
步骤S70，在所述公共电极上沉积第四金属层，对所述第四金属层进行刻蚀以形成电极稳定层；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
具体地，请辅助参阅图10，在公共电极80上沉积形成第四金属层(图10未标示)，对第四金属层的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，第四金属层的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。对第四金属层进行刻蚀以形成电极稳定层90，其中，电极稳定层90在基板10上的投影与栅极20在基板10上的投影有交叠。具体地，可在第四金属层的上方涂布一层光阻层(图10未标示)，然后采用一道光罩工艺对光阻层进行图案化处理，得到具有预设图案的光刻胶(图10未标示)，在此基础上，采用湿法刻蚀工艺对第四金属层进行刻蚀以形成电极稳定层90。电极稳定层90在基板10上的投影与栅极20在基板10上的投影有交叠。换句话说，当光线由背光板发射出来时，栅极20由于采用的是不透光的金属制成，所以会遮挡住一部分的光线，由于电极稳定层90和栅极20在垂直于基板的方向上有交叠，所以栅极20遮挡的光线和电极稳定层90遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交叠)就可以让电极稳定层 90不会过多的影响光线的透过，从而减少开口率的损失。
上述主动开关的制作方法，由于制造出来的主动开关通过在平坦层上形成公共电极，并且使电极稳定层直接与公共电极接触，一方面可以保证公共电极的电位稳定，另一方面，由于电极稳定层在基板上的投影与栅极在基板上的投影有交叠，也即是说，当光线由背光板发射出来时，栅极会遮挡住一部分的光线，由于电极稳定层和栅极在垂直方向上有交叠，所以栅极遮挡的光线和电极稳定层遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交叠)就可以让电极稳定层不会过多的影响光线的透过，从而减小开口率的损失。
请参阅图11，为一实施例中的阵列基板的结构示意图；该阵列基板可以包括开关管区域1、显示区域2和外围区域3，其中，开关管区域1设置有前述所述的主动开关。
进一步地，请继续参阅图11，主动开关还可以包括第二保护层100以及像素电极110；其中，第二保护层100形成于电极稳定层90上；像素电极110形成于第二保护层100上，像素电极110通过贯穿第二保护层100、平坦层70及第一保护层60的过孔H1与漏极520连接。具体地，第二保护层100可以为氧化硅、氮化硅中的一种或者二者的组合，即保护绝缘层90可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。可以理解，第二保护层100的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。像素电极100的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，像素电极100的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。像素电极100可以为铟 锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。像素电极110与漏极520通过贯穿第二保护层100、平坦层70及第一保护层60的过孔H1电连接。“贯穿”可通过光刻或刻蚀工艺形成，具体的，光刻是指使用带有某一层设计图形的掩模版，经过曝光和显影，使光敏的光刻胶在衬底上形成三维浮雕图形。刻蚀是指在光刻胶掩蔽下，根据需要形成微图形的膜层不同，采用不同的刻蚀物质和方法在膜层上进行选择性刻蚀。这样，去掉光刻胶以后，三维设计图形就转移到了衬底的相关膜层上。
上述阵列基板，由于采用前述所述的主动开关，该主动开关通过在平坦层上形成公共电极，并且使电极稳定层直接与公共电极接触，一方面可以保证公共电极的电位稳定，另一方面，由于电极稳定层在基板上的投影与栅极在基板上的投影有交叠，也即是说，当光线由背光板发射出来时，栅极会遮挡住一部分的光线，由于电极稳定层和栅极在垂直方向上有交叠，所以栅极遮挡的光线和电极稳定层遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投影与栅极在基板上的投影有交叠)就可以让电极稳定层不会过多的影响光线的透过，从而减小开口率的损失。
还提供一种显示装置，包括前述所述的阵列基板，该阵列基板由于采用前述所述的主动开关，该主动开关通过在平坦层上形成公共电极，并且使电极稳定层直接与公共电极接触，一方面可以保证公共电极的电位稳定，另一方面，由于电极稳定层在基板上的投影与栅极在基板上的投影有交叠，也即是说，当光线由背光板发射出来时，栅极会遮挡住一部分的光线，由于电极稳定层和栅极在垂直方向上有交叠，所以栅极遮挡的光线和电极稳定层遮挡的光线就会有重合，那么，这样设置(电极稳定层在基板上的投 影与栅极在基板上的投影有交叠)就可以让电极稳定层不会过多的影响光线的透过，从而减小开口率的损失。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种主动开关，包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
    氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
    源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
    第一保护层，形成于所述源极、漏极上；
    平坦层，形成于所述第一保护层上；
    公共电极，形成于所述平坦层对应于所述栅极的上方；及
    电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
  2. 根据权利要求1所述的主动开关，其中，所述公共电极为透明金属氧化物。
  3. 根据权利要求1所述的主动开关，其中，所述公共电极包括铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的至少一种。
  4. 根据权利要求1所述的主动开关，其中，还包括：
    第二保护层，形成于所述电极稳定层上。
  5. 根据权利要求4所述的主动开关，其中，还包括：
    像素电极，形成于所述第二保护层上；其中，所述像素电极通过贯穿所述第二保护层、平坦层及第一保护层的过孔与所述漏极连接。
  6. 根据权利要求5所述的主动开关，其中，所述像素电极包括铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的至少一种。
  7. 根据权利要求1所述的主动开关，其中，所述氧化物半导体层的材料为氧化铟镓锌。
  8. 根据权利要求1所述的主动开关，其中，所述氧化物半导体层的厚度为200埃-1000埃。
  9. 根据权利要求1所述的主动开关，其中，所述电极稳定层的厚度为1000埃-6000埃。
  10. 根据权利要求1所述的主动开关，其中，所述电极稳定层包括钼、钛、铝和铜中的至少一种。
  11. 根据权利要求1所述的主动开关，其中，所述平坦层的厚度为2000纳米-3000纳米。
  12. 根据权利要求1所述的主动开关，其中，所述源极包括钼、钛、铝和铜中的至少一种；所述漏极包括钼、钛、铝和铜中的至少一种。
  13. 根据权利要求1所述的主动开关，其中，所述栅极绝缘层包括氧化硅。
  14. 根据权利要求1所述的主动开关，其中，所述栅极绝缘层包括氮化硅。
  15. 根据权利要求1所述的主动开关，其中，所述栅极绝缘层包括氧化硅和氮化硅。
  16. 根据权利要求1所述的主动开关，其中，所述栅极绝缘层的厚度为1000埃-4000埃。
  17. 根据权利要求1所述的主动开关，其中，所述基板为玻璃基板，所述玻璃基板为无碱硼硅酸盐超薄玻璃基板。
  18. 一种主动开关的制作方法，其中，设置为制造主动开关，所述主动 开关包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
    氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
    源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
    第一保护层，形成于所述源极、漏极上；
    平坦层，形成于所述第一保护层上；
    公共电极，形成于所述平坦层对应于所述栅极的上方；及
    电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠；
    所述方法包括：
    提供一基板，并在所述基板上沉积第一金属层，对所述第一金属层进行图案化处理形成栅极；
    在所述栅极上形成栅极绝缘层；
    在所述栅极绝缘层上沉积半导体层、并对所述半导体层进行刻蚀以形成对应于所述栅极上方的氧化物半导体层；
    在所述氧化物半导体层上沉积第二金属层，对所述第二金属层进行刻蚀以形成覆盖于所述氧化物半导体层两侧边沿的源极、漏极；
    在所述源极、漏极上依次形成第一保护层、平坦层；
    在所述平坦层上沉积第三金属层，对所述第三金属层进行刻蚀以形成对应于所述栅极上方的公共电极；及
    在所述公共电极上沉积第四金属层，对所述第四金属层进行刻蚀以形成 电极稳定层；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
  19. 根据权利要求18所述的主动开关的制作方法，其中，所述第一金属层的形成工艺包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺中的至少一种。
  20. 一种显示装置，其中，包括阵列基板，所述阵列基板包括显示区域、外围区域和开关管区域，所述开关管区域设置有主动开关，所述主动开关包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成于所述基板上、并覆盖所述栅极；
    氧化物半导体层，形成于所述栅极绝缘层对应于所述栅极的上方；
    源极、漏极，形成于所述氧化物半导体层的两侧边沿上；
    第一保护层，形成于所述源极、漏极上；
    平坦层，形成于所述第一保护层上；
    公共电极，形成于所述平坦层对应于所述栅极的上方；及
    电极稳定层，形成于所述公共电极上；其中，所述电极稳定层在所述基板上的投影与所述栅极在所述基板上的投影有交叠。
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