WO2020107528A1 - 检测电路和扫描驱动电路 - Google Patents

检测电路和扫描驱动电路 Download PDF

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Publication number
WO2020107528A1
WO2020107528A1 PCT/CN2018/120271 CN2018120271W WO2020107528A1 WO 2020107528 A1 WO2020107528 A1 WO 2020107528A1 CN 2018120271 W CN2018120271 W CN 2018120271W WO 2020107528 A1 WO2020107528 A1 WO 2020107528A1
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Prior art keywords
signal
input terminal
scan
output
stage buffer
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Ceased
Application number
PCT/CN2018/120271
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English (en)
French (fr)
Inventor
熊志
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HKC Co Ltd
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HKC Co Ltd
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Publication of WO2020107528A1 publication Critical patent/WO2020107528A1/zh
Priority to US17/105,560 priority Critical patent/US11328638B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the present application relates to the display field, in particular to a detection circuit and a scan driving circuit.
  • a scan chip is generally used as a panel scan driver in the display panel.
  • the scan chip is connected to the scan lines in the display panel.
  • the scanning working voltage includes a high-level voltage signal and a low-level voltage signal
  • a short circuit occurs, a circuit is conducted between the high-level voltage signal and the low-level voltage signal, causing the scan chip to be burned.
  • the present application provides a detection circuit and a scan driving circuit to improve the situation that the scan chip is burnt out due to the short circuit between the scan lines.
  • This application provides a detection circuit, including:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip, and the second input terminal is connected to the low-level voltage signal for receiving the low-level voltage signal and the n-th stage buffer
  • the scan output signal output by the output terminal of the, and generates a first intermediate signal according to the scan output signal and the low-level voltage signal
  • the first input terminal is connected to the output terminal of the comparison unit, and the second input terminal is connected to the input terminal of the n-th stage buffer of the scanning chip, for receiving the first output terminal of the comparison unit
  • a control signal is generated and output to the scanning chip to control the scanning chip to turn off the output when a short circuit occurs.
  • the comparison unit includes:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip
  • the second input terminal is connected to the low-level voltage signal
  • the output terminal is connected to the first input terminal of the judgment unit.
  • the judgment unit includes:
  • the input terminal is connected to the input terminal of the n-th stage buffer of the scanning chip, and is used to receive the scan input signal of the n-th stage buffer output from the input end of the n-th stage buffer of the scanning chip And reverse processing the scan input signal of the n-th level buffer;
  • the first input terminal is connected to the output terminal of the comparison branch, and the second input terminal is connected to the output terminal of the signal processing branch for receiving the first intermediate signal and the reverse
  • the processed scan input signal of the nth stage buffer generates the control signal according to the first intermediate signal and the reverse processed scan input signal of the nth stage buffer, and outputs the control signal to the scan chip .
  • the comparison branch includes a comparator, a positive input terminal of the comparator is connected to the output terminal of the nth stage buffer of the scanning chip, and a negative input terminal of the comparator is The low-level voltage signal is connected, and the output end of the comparator is connected to the first input end judged by the logic.
  • the logic determination branch includes an AND circuit device, a first input terminal of the AND circuit device is connected to an output terminal of the comparator, and a second input of the AND circuit device The terminal is connected to the output terminal of the inverter.
  • the comparison unit includes:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip, and the second input terminal is connected to a low-level voltage signal for receiving the low-level voltage signal and the n-th A scan output signal output from the output end of the stage buffer, and generate a comparison signal according to the scan output signal and the low-level voltage signal;
  • the input terminal is connected to the output terminal of the comparison branch, and the output terminal is connected to the first input terminal of the judgment unit, used for receiving the comparison signal, and performing reverse processing on the comparison signal to generate The first intermediate signal, and provide the first intermediate signal to the judgment sheet.
  • the judgment unit includes:
  • the first input terminal is connected to the output terminal of the signal processing branch, and the second input terminal is connected to the input terminal of the nth-stage buffer of the scanning chip, for receiving the first intermediate signal and
  • the scan input signal of the nth stage buffer generates the control signal according to the first intermediate signal and the scan input signal of the nth stage buffer, and outputs the control signal to the scan chip.
  • the comparison branch includes a comparator
  • the signal processing branch includes an inverter
  • the positive input terminal of the comparator is connected to the output terminal of the nth stage buffer of the scanning chip, the negative input terminal of the comparator is connected to a low-level voltage signal, and the output terminal of the comparator is connected to all The input terminal of the inverter is connected.
  • the logic judgment branch includes an AND circuit device, a first input terminal of the AND circuit device is connected to an output terminal of the inverter, and a second input of the AND circuit The terminal is connected to the input terminal of the nth stage buffer of the scanning chip.
  • the present application further provides a scan drive circuit, the scan drive circuit including at least one detection circuit.
  • the detection circuit includes:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip, and the second input terminal is connected to the low-level voltage signal for receiving the low-level voltage signal and the n-th stage buffer
  • the scan output signal output by the output terminal of the, and generates a first intermediate signal according to the scan output signal and the low-level voltage signal
  • the first input terminal is connected to the output terminal of the comparison unit, and the second input terminal is connected to the input terminal of the n-th stage buffer of the scanning chip, for receiving the first output terminal of the comparison unit
  • a control signal is generated and output to the scanning chip to control the scanning chip to turn off the output when a short circuit occurs.
  • the comparison unit includes:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip
  • the second input terminal is connected to the low-level voltage signal
  • the output terminal is connected to the first input terminal of the judgment unit.
  • the judgment unit includes:
  • the input terminal is connected to the input terminal of the n-th stage buffer of the scanning chip, and is used to receive the scan input signal of the n-th stage buffer output from the input end of the n-th stage buffer of the scanning chip And reverse processing the scan input signal of the n-th level buffer;
  • the first input terminal is connected to the output terminal of the comparison branch, and the second input terminal is connected to the output terminal of the signal processing branch for receiving the first intermediate signal and the reverse
  • the processed scan input signal of the nth stage buffer generates the control signal according to the first intermediate signal and the reverse processed scan input signal of the nth stage buffer, and outputs the control signal to the scan chip .
  • the comparison branch includes a comparator, a positive input terminal of the comparator is connected to the output terminal of the nth stage buffer of the scanning chip, and a negative input terminal of the comparator is The low-level voltage signal is connected, and the output end of the comparator is connected to the first input end judged by the logic.
  • the logic determination branch includes an AND circuit device, a first input terminal of the AND circuit device is connected to an output terminal of the comparator, and a second input of the AND circuit device The terminal is connected to the output terminal of the inverter.
  • the comparison unit includes:
  • the first input terminal is connected to the output terminal of the n-th stage buffer of the scanning chip, and the second input terminal is connected to a low-level voltage signal for receiving the low-level voltage signal and the n-th A scan output signal output from the output end of the stage buffer, and generate a comparison signal according to the scan output signal and the low-level voltage signal;
  • the input terminal is connected to the output terminal of the comparison branch, and the output terminal is connected to the first input terminal of the judgment unit, used for receiving the comparison signal, and performing reverse processing on the comparison signal to generate The first intermediate signal, and provide the first intermediate signal to the judgment sheet.
  • the judgment unit includes:
  • the first input terminal is connected to the output terminal of the signal processing branch, and the second input terminal is connected to the input terminal of the nth-stage buffer of the scanning chip, for receiving the first intermediate signal and
  • the scan input signal of the nth stage buffer generates the control signal according to the first intermediate signal and the scan input signal of the nth stage buffer, and outputs the control signal to the scan chip.
  • the comparison branch includes a comparator
  • the signal processing branch includes an inverter
  • the positive input terminal of the comparator is connected to the output terminal of the nth stage buffer of the scanning chip, the negative input terminal of the comparator is connected to a low-level voltage signal, and the output terminal of the comparator is connected to all The input terminal of the inverter is connected.
  • the logic judgment branch includes an AND circuit device, a first input terminal of the AND circuit device is connected to an output terminal of the inverter, and a second input of the AND circuit The terminal is connected to the input terminal of the nth stage buffer of the scanning chip.
  • the present application provides a detection circuit and a scan driving circuit.
  • the detection circuit includes a comparison unit and a determination unit.
  • the first input terminal of the comparison unit is connected to the output terminal of the nth stage buffer of the scanning chip, the second input terminal of the comparison unit is connected to the low-level voltage signal, and the comparison unit is used to receive the low power A flat voltage signal and a scan output signal output from the output terminal of the n-th stage buffer, and generate a first intermediate signal according to the scan output signal and the low-level voltage signal.
  • the first input terminal of the judgment unit is connected to the output terminal of the comparison unit, the second input terminal of the judgment unit is connected to the input terminal of the nth level buffer of the scanning chip, and the judgment unit is used to receive The first intermediate signal output from the output end of the comparison unit, and the scan input signal of the nth stage buffer output from the input end of the nth stage buffer of the scan chip, according to the first intermediate signal and The scan input signal of the n-th stage buffer generates a control signal and outputs it to the scan chip to control the scan chip to turn off the output when a short circuit occurs.
  • the first intermediate signal is generated by the comparison unit based on the low-level voltage signal and the scan output signal output from the output terminal of the n-th stage buffer, and the judgment unit is used according to the first
  • the intermediate signal and the scan input signal of the nth stage buffer generate a control signal and output it to the scan chip to control the scan chip to turn off the output when a short circuit occurs to avoid scanning caused by a short circuit between scan lines
  • the chip is burnt out.
  • Figure 1 is a schematic diagram of the connection method of the signal line in the display panel
  • FIG. 2 is a schematic diagram of a short circuit between adjacent scan lines in a display panel
  • Figure 3 is a schematic diagram of the connection mode of the scanning chip and the scanning line
  • FIG. 4 is a schematic structural diagram of a detection circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another detection circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the working principle of the scanning chip
  • FIG. 7 is a schematic structural diagram of yet another detection circuit provided by an embodiment of the present application.
  • the display uses a scanning chip as the panel scanning driver. Its internal structure is shown in Figure 3.
  • the scanning chip uses a buffer D4 formed by a 2-level (can also be set as required) inverter to connect to the panel display. Scan lines in the area.
  • the scan chip is connected to the scan line. When a short circuit occurs between adjacent scan lines, that is, there is a conduction path between the adjacent scan lines. Since the scan operating voltage is a high-level voltage signal VGH and a low-level voltage signal VGL, when When there is a short-circuit condition, the high-level voltage signal VGH and the low-level voltage signal VGL are turned on, resulting in the risk that the scanning chip is burned.
  • the present application provides a detection circuit.
  • the detection circuit includes a comparison unit 100 and a judgment unit 200.
  • the first input terminal of the comparison unit 100 is connected to the output terminal of the nth stage buffer D4 of the scanning chip, the second input terminal of the comparison unit 100 is connected to the low-level voltage signal VGL, and the comparison unit 100 is used to Receiving the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and generating a first intermediate signal according to the scan output signal G_out and the low-level voltage signal VGL .
  • the first input terminal of the judgment unit 200 is connected to the output terminal of the comparison unit 100, and the second input terminal of the judgment unit 200 is connected to the input terminal of the n-th stage buffer D4 of the scanning chip.
  • the unit 200 is configured to receive the first intermediate signal output from the output terminal of the comparison unit 100 and the scan input signal G_in of the n-th stage buffer D4 output from the input terminal of the n-th stage buffer D4 of the scan chip , Generating a control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 and outputting it to the scan chip to control the scan chip to turn off the output when a short circuit occurs.
  • the comparison unit 100 generates a first intermediate signal according to the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and the judgment unit 200 generates The first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 generate a control signal and output it to the scan chip to control the scan chip to turn off the output when a short circuit occurs, which can avoid the cause of The short circuit between the scan lines causes the scan chip to burn out.
  • the comparison unit 100 includes a comparison branch 110, and a first input terminal of the comparison branch 110 is connected to the output terminal of the nth stage buffer D4 of the scanning chip,
  • the second input terminal of the comparison branch 110 is connected to the low-level voltage signal VGL
  • the output terminal of the comparison branch 110 is connected to the first input terminal of the judgment unit 200
  • the comparison branch 110 is used to Receiving the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and generating a first intermediate signal according to the scan output signal G_out and the low-level voltage signal VGL .
  • the judgment unit 200 includes a signal processing branch 210 and a logic judgment branch 220.
  • the input terminal of the signal processing branch 210 is connected to the input terminal of the n-th stage buffer D4 of the scanning chip, and the signal processing branch 210 is used to receive the output terminal of the scanning chip n-th stage buffer D4
  • the scan input signal G_in of the nth stage buffer D4 and inversely process the scan input signal G_in of the nth stage buffer D4.
  • the first input terminal of the logic judgment branch 220 is connected to the output terminal of the comparison branch 110, and the second input terminal of the logic judgment branch 220 is connected to the output terminal of the signal processing branch 210.
  • the logic judgment branch 220 is used to receive the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 after the reverse processing, according to the first intermediate signal and the reverse processed
  • the scan input signal G_in of the n-th stage buffer D4 generates the control signal and outputs it to the scan chip.
  • the comparison branch 110 includes a comparator D1, a positive input terminal of the comparator D1 is connected to the output terminal of the nth stage buffer D4 of the scanning chip, and the comparator D1 The negative input terminal is connected to the low-level voltage signal VGL, and the output terminal of the comparator D1 is connected to the first input terminal judged by the logic.
  • the comparator D1 when the scan output signal G_out output from the output terminal of the n-th stage buffer D4 of the scan chip is at a high level, the comparator D1 is generated according to the scan output signal G_out and the low-level voltage signal VGL And output a high-level comparison signal, that is, the first intermediate signal is a high-level signal.
  • the comparator D1 When the scan output signal G_out output from the output terminal of the n-th stage buffer D4 of the scan chip is at a low level, the comparator D1 generates and outputs a low level according to the scan output signal G_out and the low-level voltage signal VGL
  • the level comparison signal that is, the first intermediate signal is a low-level voltage signal.
  • the signal processing branch 210 includes an inverter D2, an input terminal of the inverter D2 is connected to an input terminal of the nth stage buffer D4 of the scanning chip, and the inverter The output terminal of D2 is connected to the second input terminal of the logic judgment branch 220.
  • the logic judgment branch 220 includes an AND circuit device D3, a first input terminal of the AND circuit device D3 is connected to an output terminal of the comparator D1, and the AND circuit device The second input terminal of D3 is connected to the output terminal of the inverter D2.
  • the output terminal of the AND circuit device D3 When the input signals of the first input terminal and the second input terminal of the AND circuit device D3 are both high-level signals or both are low-level voltage signals, the output terminal of the AND circuit device D3 The output is 1, that is, the control signal is a high-level signal.
  • the signal input to the first input terminal of the AND circuit device D3 is a high-level signal
  • the signal input to the second input terminal is a low-level voltage signal
  • the signal input to the first input terminal is a low-level voltage signal
  • the output terminal of the AND circuit device D3 outputs 0, that is, the control signal is a low-level voltage signal.
  • the scanning chip includes an N-level buffer D4.
  • the scan input signal G_in at the input of the n-th stage buffer D4 is high Level signal
  • the first switch tube T1 for N-type field effect transistor
  • the second switch tube T2 for P-type field effect transistor
  • the first switching transistor T1 (which is an N-type field effect transistor) in the n-th stage buffer D4 is turned off, and the second switching transistor T2 (which is a P-type field effect transistor) is turned on, then
  • the scan output signal G_out output through the output terminal of the n-th stage buffer D4 in the scan chip is a low-level voltage signal VGL and is provided to the n-th row of scan lines.
  • the n-th line buffer D4 When a short circuit occurs between the scan lines (assuming a short circuit between the n-th scan line and the n+1-th scan line), when the scan chip needs to hit the n+1-th line, it should pass through the n-th line buffer D4 provides a low-level voltage signal VGL for the scan line in the n-th row, and provides a high-level signal VGH for the scan line in the n+1-th line through the buffer D4 in the n+1-th line. However, since the scan line of the n-th row and the scan line of the n+1-th row are short-circuited, the voltage at the output end of the buffer D4 of the n-th row approaches the high-level voltage signal VGH and the lower-level voltage signal VGL Too large.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH, and the comparator D1 according to the high power
  • the flat voltage signal VGH and the low-level voltage signal VGL the first intermediate signal generated is a high-level signal
  • the input terminal of the inverter D2 receives the high-level voltage signal VGH
  • the low-level voltage is obtained after reverse processing
  • Flat voltage signal that is, the high-level signal is input to the first input terminal of the AND circuit device D3, and the low-level voltage signal is input to the second input terminal of the AND circuit circuit, so the output of the AND circuit device D3 is O , That is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 When the scanning chip needs to turn on other scanning lines, the n-th stage buffer D4 outputs a high-level voltage signal VGL, and the first intermediate signal output by the comparator D1 is a low-level voltage signal.
  • the input terminal of the inverter D2 is a low-level voltage signal, and the inverter D2 outputs a high-level signal, that is, the first input terminal of the AND circuit device D3 inputs a low-level voltage signal, and the The second input terminal of the gate circuit has a high-level signal, so the output of the AND circuit device D3 is 0, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH
  • the comparator D1 is based on the high-level voltage signal VGH and the low-level voltage signal VGL
  • the first intermediate signal generated is a high-level signal
  • the input terminal of the inverter D2 receives the high-level voltage signal VGH
  • the low-level voltage signal is obtained after reverse processing, that is, the AND circuit
  • the first input terminal of the device D3 inputs a high-level signal
  • the second input terminal of the AND circuit has a low-level voltage signal. Therefore, the output of the AND circuit device D3 is O, that is, the control signal is a low-level voltage signal .
  • the n+1/n-1 stage buffer D4 When the scan chip needs to open the scan line in the n+1/n-1 row, the n+1/n-1 stage buffer D4 outputs a high-level voltage signal VGH, and the nth stage buffer D4 The high-level voltage signal VGL is output.
  • the voltage at the output end of the n-th stage buffer D4 approaches the high-level voltage signal VGH, and the lower level The voltage signal VGL is too large, so at this time, the first intermediate signal output from the comparator D1 is a high-level signal, and the input terminal of the inverter D2 is a low-level voltage signal, and the inverter D2 Output a high level signal, that is, a high level signal is input to the first input terminal of the AND circuit device D3, and a high level signal is input to the second input terminal of the AND circuit device, so the AND circuit device D3 outputs Is 1, that is, the control signal
  • the comparison unit 100 includes a comparison branch 110 and a signal processing branch 210.
  • the first input terminal of the comparison branch 110 is connected to the output terminal of the n-th stage buffer D4 of the scanning chip, and the second input terminal of the comparison branch 110 is connected to the low-level voltage signal VGL.
  • the branch 110 is used to receive the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and according to the scan output signal G_out and the low-level voltage signal VGL Generate comparison signals;
  • the input terminal of the signal processing branch 210 is connected to the output terminal of the comparison branch 110, the output terminal of the signal processing branch 210 is connected to the first input terminal of the judgment unit 200, and the signal processing branch
  • the path 210 is used to receive the comparison signal, perform reverse processing on the comparison signal to generate the first intermediate signal, and provide the first intermediate signal to the judgment sheet.
  • the judgment unit 200 includes a logic judgment branch 220, the first input terminal of the logic judgment branch 220 is connected to the output terminal of the signal processing branch 210, and the logic judgment branch 220 The second input terminal is connected to the input terminal of the nth stage buffer D4 of the scan chip, and the logic judgment branch 220 is used to receive the first intermediate signal and the scan input signal G_in of the nth stage buffer D4 , Generate the control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4, and output to the scan chip.
  • the comparison branch 110 includes a comparator D1
  • the signal processing branch 210 includes an inverter D2
  • the logic determination branch 220 includes an AND circuit device D3.
  • the positive input terminal of the comparator D1 is connected to the output terminal of the n-th stage buffer D4 of the scan chip, the negative input terminal of the comparator D1 is connected to the low-level voltage signal VGL, and the The output terminal is connected to the input terminal of the inverter D2.
  • the first input terminal of the AND circuit device D3 is connected to the output terminal of the inverter D2, and the second input terminal of the AND circuit is connected to the input terminal of the n-th stage buffer D4 of the scan chip.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH, and the comparator D1 according to the high power
  • the flat voltage signal VGH and the low-level voltage signal VGL generate a high-level signal comparison signal
  • the inverter D2 reversely processes the high-level comparison signal to generate a low-level first intermediate signal, That is, the first input terminal of the AND circuit device D3 is a low-level voltage signal, and the second input terminal of the AND circuit device D3 is a high-level signal, so the output of the AND circuit device D3 at this time is O, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 When the scanning chip needs to turn on other scanning lines, the n-th stage buffer D4 outputs a high-level voltage signal VGL, the comparison signal output by the comparator D1 is a low-level voltage signal, and the inversion After the reverse processing of the low-level comparison signal, the device D2 outputs a high-level first intermediate signal, that is, a high-level signal is input to the first input terminal of the AND circuit device D3, and the The second input terminal has a low-level voltage signal, so the output of the AND circuit device D3 is 0 at this time, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH
  • the comparator D1 is based on the high-level voltage signal VGH and the low-level voltage signal VGL
  • the generated comparison signal is a high-level signal
  • the inverter D2 reversely processes the high-level comparison signal to generate a low-level first intermediate signal, that is, the AND circuit device D3
  • a low-level voltage signal is input to the first input terminal of the device, and a high-level signal is input to the second input terminal of the AND circuit. Therefore, the output of the AND circuit device D3 is 0, that is, the control signal is a low-level voltage signal.
  • the n+1/n-1 stage buffer D4 When the scan chip needs to open the scan line in the n+1/n-1 row, the n+1/n-1 stage buffer D4 outputs a high-level voltage signal VGH, and the nth stage buffer D4 The high-level voltage signal VGL is output.
  • the voltage at the output end of the n-th stage buffer D4 approaches the high-level voltage signal VGH, and the lower level The voltage signal VGL is too large, so the comparison signal output by the comparator D1 is a high-level signal at this time, and the inverter D2 reversely processes the high-level comparison signal and outputs a low-level signal.
  • the first intermediate signal that is, the first input terminal of the AND circuit device D3 inputs a low-level voltage signal
  • the second input terminal of the AND circuit circuit inputs a low-level voltage signal
  • the AND circuit device D3 The output is 1, that is, the control signal is a high-level signal. Therefore, the scan chip can turn off the output when a short circuit occurs according to the control signal, to avoid the problem that the scan chip is burned out due to the short circuit between the scan lines.
  • the present application also provides a scan drive circuit, the scan drive circuit including the detection circuit in any of the above embodiments.
  • the scan driving circuit includes a buffer D4 and at least one detection circuit.
  • the detection circuit includes a comparison unit 100 and a determination unit 200.
  • the first input terminal of the comparison unit 100 is connected to the output terminal of the nth stage buffer D4 of the scanning chip, the second input terminal of the comparison unit 100 is connected to the low-level voltage signal VGL, and the comparison unit 100 is used to Receiving the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and generating a first intermediate signal according to the scan output signal G_out and the low-level voltage signal VGL .
  • the first input terminal of the judgment unit 200 is connected to the output terminal of the comparison unit 100, and the second input terminal of the judgment unit 200 is connected to the input terminal of the n-th stage buffer D4 of the scanning chip.
  • the unit 200 is configured to receive the first intermediate signal output from the output terminal of the comparison unit 100 and the scan input signal G_in of the n-th stage buffer D4 output from the input terminal of the n-th stage buffer D4 of the scan chip , Generating a control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 and outputting it to the scan chip to control the scan chip to turn off the output when a short circuit occurs.
  • the comparison unit 100 includes a comparison branch 110 whose first input terminal is connected to the output terminal of the nth stage buffer D4 of the scanning chip, and the comparison branch The second input terminal of 110 is connected to the low-level voltage signal VGL, the output terminal of the comparison branch 110 is connected to the first input terminal of the judgment unit 200, and the comparison branch 110 is used to receive the low power The level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and generate a first intermediate signal according to the scan output signal G_out and the low-level voltage signal VGL.
  • the judgment unit 200 includes a signal processing branch 210 and a logic judgment branch 220.
  • the input terminal of the signal processing branch 210 is connected to the input terminal of the n-th stage buffer D4 of the scanning chip, and the signal processing branch 210 is used to receive the output terminal of the scanning chip n-th stage buffer D4
  • the scan input signal G_in of the nth stage buffer D4 and inversely process the scan input signal G_in of the nth stage buffer D4.
  • the first input terminal of the logic judgment branch 220 is connected to the output terminal of the comparison branch 110, and the second input terminal of the logic judgment branch 220 is connected to the output terminal of the signal processing branch 210.
  • the logic judgment branch 220 is used to receive the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 after the reverse processing, according to the first intermediate signal and the reverse processed
  • the scan input signal G_in of the n-th stage buffer D4 generates the control signal and outputs it to the scan chip.
  • the comparison branch 110 includes a comparator D1, a positive input terminal of the comparator D1 is connected to the output terminal of the nth stage buffer D4 of the scanning chip, and the comparator D1 The negative input terminal is connected to the low-level voltage signal VGL, and the output terminal of the comparator D1 is connected to the first input terminal judged by the logic.
  • the signal processing branch 210 includes an inverter D2, an input terminal of the inverter D2 is connected to an input terminal of the nth stage buffer D4 of the scanning chip, and the inverter The output terminal of D2 is connected to the second input terminal of the logic judgment branch 220.
  • the logic judgment branch 220 includes an AND circuit device D3, a first input terminal of the AND circuit device D3 is connected to an output terminal of the comparator D1, and the AND circuit device The second input terminal of D3 is connected to the output terminal of the inverter D2.
  • the scanning chip includes an N-level buffer D4.
  • the scan input signal G_in at the input of the n-th stage buffer D4 is high Level signal
  • the first switch tube T1 for N-type field effect transistor
  • the second switch tube T2 for P-type field effect transistor
  • the scan output signal G_out output through the output terminal of the n-th stage buffer D4 in the scan chip is a low-level voltage signal VGL and is provided to the n-th row of scan lines.
  • the n-th line buffer D4 When a short circuit occurs between the scan lines (assuming a short circuit between the n-th scan line and the n+1-th scan line), when the scan chip needs to hit the n+1-th line, it should pass through the n-th line buffer D4 provides a low-level voltage signal VGL for the scan line in the n-th row, and provides a high-level signal VGH for the scan line in the n+1-th line through the buffer D4 in the n+1-th line. However, since the scan line of the n-th row and the scan line of the n+1-th row are short-circuited, the voltage at the output end of the buffer D4 of the n-th row approaches the high-level voltage signal VGH and the lower-level voltage signal VGL Too large.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH, and the comparator D1 according to the high power
  • the flat voltage signal VGH and the low-level voltage signal VGL the first intermediate signal generated is a high-level signal
  • the input terminal of the inverter D2 receives the high-level voltage signal VGH
  • the low-level voltage is obtained after reverse processing
  • Flat voltage signal that is, the high-level signal is input to the first input terminal of the AND circuit device D3, and the low-level voltage signal is input to the second input terminal of the AND circuit circuit, so the output of the AND circuit device D3 is O , That is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 When the scanning chip needs to turn on other scanning lines, the n-th stage buffer D4 outputs a high-level voltage signal VGL, and the first intermediate signal output by the comparator D1 is a low-level voltage signal.
  • the input terminal of the inverter D2 is a low-level voltage signal, and the inverter D2 outputs a high-level signal, that is, the first input terminal of the AND circuit device D3 inputs a low-level voltage signal, and the The second input terminal of the gate circuit has a high-level signal, so the output of the AND circuit device D3 is 0, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH
  • the comparator D1 is based on the high-level voltage signal VGH and the low-level voltage signal VGL
  • the first intermediate signal generated is a high-level signal
  • the input terminal of the inverter D2 receives the high-level voltage signal VGH
  • the low-level voltage signal is obtained after reverse processing, that is, the AND circuit
  • the first input terminal of the device D3 inputs a high-level signal
  • the second input terminal of the AND circuit has a low-level voltage signal. Therefore, the output of the AND circuit device D3 is O, that is, the control signal is a low-level voltage signal .
  • the n+1/n-1 stage buffer D4 When the scan chip needs to open the scan line in the n+1/n-1 row, the n+1/n-1 stage buffer D4 outputs a high-level voltage signal VGH, and the nth stage buffer D4 The high-level voltage signal VGL is output.
  • the voltage at the output end of the n-th stage buffer D4 approaches the high-level voltage signal VGH, and the lower level The voltage signal VGL is too large, so at this time, the first intermediate signal output from the comparator D1 is a high-level signal, and the input terminal of the inverter D2 is a low-level voltage signal, and the inverter D2 Output a high level signal, that is, a high level signal is input to the first input terminal of the AND circuit device D3, and a high level signal is input to the second input terminal of the AND circuit device, so the AND circuit device D3 outputs Is 1, that is, the control signal
  • the present application further provides another scan driving circuit. Please refer to FIG. 7.
  • the comparison unit 100 in the scan driving includes a comparison branch 110 and a signal processing branch 210.
  • the first input terminal of the comparison branch 110 is connected to the output terminal of the n-th stage buffer D4 of the scanning chip, and the second input terminal of the comparison branch 110 is connected to the low-level voltage signal VGL.
  • the branch 110 is used to receive the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and according to the scan output signal G_out and the low-level voltage signal VGL Generate comparison signals;
  • the input terminal of the signal processing branch 210 is connected to the output terminal of the comparison branch 110, the output terminal of the signal processing branch 210 is connected to the first input terminal of the judgment unit 200, and the signal processing branch
  • the path 210 is used to receive the comparison signal, perform reverse processing on the comparison signal to generate the first intermediate signal, and provide the first intermediate signal to the judgment sheet.
  • the judgment unit 200 includes a logic judgment branch 220, the first input terminal of the logic judgment branch 220 is connected to the output terminal of the signal processing branch 210, and the logic judgment branch 220 The second input terminal is connected to the input terminal of the nth stage buffer D4 of the scan chip, and the logic judgment branch 220 is used to receive the first intermediate signal and the scan input signal G_in of the nth stage buffer D4 , Generate the control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4, and output to the scan chip.
  • the comparison branch 110 includes a comparator D1
  • the signal processing branch 210 includes an inverter D2
  • the logic determination branch 220 includes an AND circuit device D3.
  • the positive input terminal of the comparator D1 is connected to the output terminal of the n-th stage buffer D4 of the scan chip, the negative input terminal of the comparator D1 is connected to the low-level voltage signal VGL, and the The output terminal is connected to the input terminal of the inverter D2.
  • the first input terminal of the AND circuit device D3 is connected to the output terminal of the inverter D2, and the second input terminal of the AND circuit is connected to the input terminal of the n-th stage buffer D4 of the scan chip.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH, and the comparator D1 according to the high power
  • the flat voltage signal VGH and the low-level voltage signal VGL generate a high-level signal comparison signal
  • the inverter D2 reversely processes the high-level comparison signal to generate a low-level first intermediate signal, That is, the first input terminal of the AND circuit device D3 is a low-level voltage signal, and the second input terminal of the AND circuit device D3 is a high-level signal, so the output of the AND circuit device D3 at this time is O, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 When the scan chip needs to turn on other scan lines, the n-th stage buffer D4 outputs a high-level voltage signal VGL, the comparison signal output by the comparator D1 is a low-level voltage signal, and the inversion After the reverse processing of the low-level comparison signal, the device D2 outputs a high-level first intermediate signal, that is, a high-level signal is input to the first input terminal of the AND circuit device D3, and the The second input terminal has a low-level voltage signal, so the output of the AND circuit device D3 is 0 at this time, that is, the control signal is a low-level voltage signal.
  • the n-th stage buffer D4 outputs a high-level voltage signal VGH
  • the comparator D1 is based on the high-level voltage signal VGH and the low-level voltage signal VGL
  • the generated comparison signal is a high-level signal
  • the inverter D2 reversely processes the high-level comparison signal to generate a low-level first intermediate signal, that is, the AND circuit device D3
  • a low-level voltage signal is input to the first input terminal of the device, and a high-level signal is input to the second input terminal of the AND circuit. Therefore, the output of the AND circuit device D3 is 0, that is, the control signal is a low-level voltage signal.
  • the n+1/n-1 stage buffer D4 When the scan chip needs to open the scan line in the n+1/n-1 row, the n+1/n-1 stage buffer D4 outputs a high-level voltage signal VGH, and the nth stage buffer D4 The high-level voltage signal VGL is output.
  • the voltage at the output end of the n-th stage buffer D4 approaches the high-level voltage signal VGH, and the lower level The voltage signal VGL is too large, so the comparison signal output by the comparator D1 is a high-level signal at this time, and the inverter D2 reversely processes the high-level comparison signal and outputs a low-level signal.
  • the first intermediate signal that is, the first input terminal of the AND circuit device D3 inputs a low-level voltage signal
  • the second input terminal of the AND circuit circuit inputs a low-level voltage signal
  • the AND circuit device D3 The output is 1, that is, the control signal is a high-level signal. Therefore, the scan chip can turn off the output when a short circuit occurs according to the control signal, to avoid the problem that the scan chip is burned out due to the short circuit between the scan lines.
  • the present application provides a detection circuit and a scan driving circuit.
  • the detection circuit includes a comparison unit 100 and a judgment unit 200.
  • the first input terminal of the comparison unit 100 is connected to the output terminal of the nth stage buffer D4 of the scanning chip, the second input terminal of the comparison unit 100 is connected to the low-level voltage signal VGL, and the comparison unit 100 is used to Receiving the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and generating a first intermediate signal according to the scan output signal G_out and the low-level voltage signal VGL .
  • the first input terminal of the judgment unit 200 is connected to the output terminal of the comparison unit 100, and the second input terminal of the judgment unit 200 is connected to the input terminal of the n-th stage buffer D4 of the scanning chip.
  • the unit 200 is configured to receive the first intermediate signal output from the output terminal of the comparison unit 100 and the scan input signal G_in of the n-th stage buffer D4 output from the input terminal of the n-th stage buffer D4 of the scan chip , Generating a control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4 and outputting it to the scan chip to control the scan chip to turn off the output when a short circuit occurs.
  • the comparison unit 100 generates a first intermediate signal according to the low-level voltage signal VGL and the scan output signal G_out output from the output terminal of the n-th stage buffer D4, and the judgment unit 200 Generate a control signal according to the first intermediate signal and the scan input signal G_in of the n-th stage buffer D4, and output it to the scan chip to control the scan chip to turn off the output when a short circuit occurs to avoid the cause The short circuit between the scan lines causes the scan chip to burn out.

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Abstract

一种检测电路和扫描驱动电路，检测电路包括比较单元（100）和判断单元（200）。比较单元（100）用于接收低电平电压信号和第n级缓冲器（D4）输出的扫描输出信号，并根据扫描输出信号和低电平电压信号生成第一中间信号。判断单元（200）用于接收第一中间信号，以及扫描芯片第n级缓冲器（D4）的输入端输出的第n级缓冲器（D4）的扫描输入信号，根据第一中间信号和扫描输入信号生成控制信号，并输出给扫描芯片，以控制扫描芯片在发生短路时关断输出。

Description

检测电路和扫描驱动电路
相关申请
本申请要求2018年11月29日申请的，申请号为201811443274.2，名称为“检测电路和扫描驱动电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示领域，尤其涉及一种检测电路和扫描驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着显示器朝向大型化、高解析度、高分辨率发展，以及对显示品质要求的提高，高PPI(Pixels Per Inch，每英寸所拥有的像素数)使得信号线越来越细、线间距越来越小，使得信号线之间发生短路的概率大幅提高。
显示面板中一般采用扫描芯片作为面板扫描驱动,扫描芯片与显示面板中的扫描线相连接，当相邻扫描线间发生短路时，则即相邻扫描线之间存在导通路径。由于扫描工作电压包括高电平电压信号和低电平电压信号，当其发生短路时则高电平电压信号和低电平电压信号之间导通电路，致使扫描芯片存在被烧坏的危险。
发明内容
基于此，本申请提供了一种检测电路和扫描驱动电路以改善因扫描线之间短路致使扫描芯片被烧坏的情况。
本申请提供了一种检测电路，包括：
比较单元，第一输入端与扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平 电压信号生成第一中间信号；以及
判断单元，第一输入端与所述比较单元的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述比较单元输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
在其中一个实施例中，所述比较单元包括：
比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，输出端与所述判断单元的第一输入端连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号。
在其中一个实施例中，所述判断单元包括：
信号处理支路，输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，并对所述第n级缓冲器的扫描输入信号进行反向处理；以及
逻辑判断支路，第一输入端与所述比较支路的输出端连接，第二输入端与所述信号处理支路的输出端连接，用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路包括比较器，所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述逻辑判断的第一输入端连接。
在其中一个实施例中，所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述比较器的输出端连接，所述与门电路器件的第二输入端与所述反相器的输出端连接。
在其中一个实施例中，所述比较单元包括：
比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成比较信号；
信号处理支路，输入端与所述比较支路的输出端连接，输出端与所述判断单元的第一输入端连接，用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。
在其中一个实施例中，所述判断单元包括：
逻辑判断支路，第一输入端与所述信号处理支路的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述第一中间信号以及所述第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路包括比较器，所述信号处理支路包括反相器；其中，
所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述反相器的输入端连接。
在其中一个实施例中，所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述反相器的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器的输入端连接。
基于同一发明构思，本申请还提供了扫描驱动电路，所述扫描驱动电路包括至少一个检测电路。
其中，所述检测电路，包括：
比较单元，第一输入端与扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号；以及
判断单元，第一输入端与所述比较单元的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述比较单元输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
在其中一个实施例中，所述比较单元包括：
比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，输出端与所述判断单元的第一输入端连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出 信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号。
在其中一个实施例中，所述判断单元包括：
信号处理支路，输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，并对所述第n级缓冲器的扫描输入信号进行反向处理；以及
逻辑判断支路，第一输入端与所述比较支路的输出端连接，第二输入端与所述信号处理支路的输出端连接，用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路包括比较器，所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述逻辑判断的第一输入端连接。
在其中一个实施例中，所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述比较器的输出端连接，所述与门电路器件的第二输入端与所述反相器的输出端连接。
在其中一个实施例中，所述比较单元包括：
比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成比较信号；
信号处理支路，输入端与所述比较支路的输出端连接，输出端与所述判断单元的第一输入端连接，用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。
在其中一个实施例中，所述判断单元包括：
逻辑判断支路，第一输入端与所述信号处理支路的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述第一中间信号以及所述第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路包括比较器，所述信号处理支路包括反相器；其中，
所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接， 所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述反相器的输入端连接。
在其中一个实施例中，所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述反相器的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器的输入端连接。
综上，本申请提供了一种检测电路和扫描驱动电路。所述检测电路包括比较单元和判断单元。所述比较单元的第一输入端与扫描芯片第n级缓冲器的输出端连接，所述比较单元的第二输入端与低电平电压信号连接，所述比较单元用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号。所述判断单元的第一输入端与所述比较单元的输出端连接，所述判断单元的第二输入端与所述扫描芯片第n级缓冲器的输入端连接，所述判断单元用于接收所述比较单元输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。本申请中，通过所述比较单元根据所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号生成第一中间信号，以及通过所述判断单元根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
附图说明
图1为显示面板中信号线的连接方式示意图；
图2为显示面板中相邻扫描线之间发生短路的示意图；
图3为扫描芯片与扫描线的连接方式示意图；
图4为本申请实施例提供的一种检测电路的结构示意图；
图5为本申请实施例提供的另一种检测电路的结构示意图；
图6为扫描芯片的工作原理结构示意图；
图7为本申请实施例提供的又一种检测电路的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施的限制。
随着显示器朝向大型化、高解析度、高分辨率发展，以及对显示品质要求的提高，高PPI(Pixels Per Inch，每英寸所拥有的像素数)使得信号线越来越细、线间距越来越小。一般显示器中数据线、扫描线与像素连接如图1所示，高PPI致使相邻信号线之间的间距越来越小，从而导致相邻信号线之间发生短路的概率大幅提高，请参见图2，图2中星号表示两个相邻的扫描线之间发生短路。
显示器采用扫描芯片作为面板扫描驱动,其内部部分结构如图3所示，所述扫描芯片使用由2级(亦可根据需要进行设置)反向器(Inverter)形成的缓冲器D4连接到面板显示区内扫描线。扫描芯片与扫描线相连接，当相邻扫描线间发生短路时，即相邻扫描线之间存在导通路径，由于扫描工作电压为高电平电压信号VGH和低电平电压信号VGL，当存在短路情况时，则高电平电压信号VGH与低电平电压信号VGL之间导通，导致所述扫描芯片存在被烧毁风险。
为解决上述问题，本申请提供了一种检测电路。请参见图4，所述检测电路包括比较单元100和判断单元200。
所述比较单元100的第一输入端与扫描芯片第n级缓冲器D4的输出端连接，所述比较单元100的第二输入端与低电平电压信号VGL连接，所述比较单元100用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成第一中间信号。
所述判断单元200的第一输入端与所述比较单元100的输出端连接，所述判断单元200的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述判断单元200用于接收所述比较单元100输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号和所述第n级缓冲器D4的扫描输入信号G_in生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
可以理解，通过所述比较单元100根据所述低电平电压信号VGL和所述 第n级缓冲器D4的输出端输出的扫描输出信号G_out生成第一中间信号，以及通过所述判断单元200根据所述第一中间信号和所述第n级缓冲器D4的扫描输入信号G_in生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出，可以避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
请参见图5，在其中一个实施例中，所述比较单元100包括比较支路110，所述比较支路110的第一输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较支路110的第二输入端与低电平电压信号VGL连接，所述比较支路110的输出端与所述判断单元200的第一输入端连接，所述比较支路110用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成第一中间信号。
在其中一个实施例中，所述判断单元200包括信号处理支路210和逻辑判断支路220。
所述信号处理支路210的输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述信号处理支路210用于接收所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in，并对所述第n级缓冲器D4的扫描输入信号G_in进行反向处理。
所述逻辑判断支路220的第一输入端与所述比较支路110的输出端连接，所述逻辑判断支路220的第二输入端与所述信号处理支路210的输出端连接，所述逻辑判断支路220用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号以及所述反向处理后的第n级缓冲器D4的扫描输入信号G_in生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路110包括比较器D1，所述比较器D1的正向输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较器D1的负向输入端与低电平电压信号VGL连接，所述比较器D1的输出端与所述逻辑判断的第一输入端连接。
可以理解，当所述扫描芯片第n级缓冲器D4的输出端输出的扫描输出信号G_out为高电平时，所述比较器D1根据所述扫描输出信号G_out和所述低电平电压信号VGL生成并输出高电平的比较信号，即所述第一中间信号为高电平信号。当所述扫描芯片第n级缓冲器D4的输出端输出的扫描输出信号G_out为低电平时，所述比较器D1根据所述扫描输出信号G_out和所述低电 平电压信号VGL生成并输出低电平的比较信号，即所述第一中间信号为低电平电压信号。
在其中一个实施例中，所述信号处理支路210包括反相器D2，所述反相器D2的输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述反相器D2的输出端与所述逻辑判断支路220的第二输入端连接。
可以理解，当所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in为高电平信号时，经所述反相器D2反向处理后，所述反相器D2输出的反向处理后的第n级缓冲器D4的扫描输入信号G_in为低电平电压信号。当所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in为低电平电压信号时，经所述反相器D2反向处理后，所述反相器D2输出的反向处理后的第n级缓冲器D4的扫描输入信号G_in为高电平信号。
在其中一个实施例中，所述逻辑判断支路220包括与门电路器件D3，所述与门电路器件D3的第一输入端与所述比较器D1的输出端连接，所述与门电路器件D3的第二输入端与所述反相器D2的输出端连接。
可以理解，当所述与门电路器件D3的第一输入端和第二输入端的输入的信号均为高电平信号或均为低电平电压信号时，所述与门电路器件D3的输出端输出为1，即所述控制信号为高电平信号。当所述与门电路器件D3的第一输入端输入的信号为高电平信号、第二输入端的输入的信号低电平电压信号，或者第一输入端输入的信号为低电平电压信号、第二输入端的输入的信号高电平信号时，所述与门电路器件D3的输出端输出为0，即所述控制信号为低电平电压信号。
请参见图6，所述扫描芯片包括N级缓冲器D4。当所述扫描芯片需要打开第n行扫描线时(其中n和N均为大于或等于1的整数，并且1≤n≤N)，第n级缓冲器D4的输入端的扫描输入信号G_in为高电平信号，第一开关管T1(为N型场效应管)导通，第二开关管T2(为P型场效应管)截止，则通过所述扫描芯片中第n级缓冲器D4输出高电平电压信号VGH给所述第n行扫描线。当扫描到下一行或其它行时，第n级缓冲器D4中的第一开关管T1(为N型场效应管)关闭，第二开关管T2(为P型场效应管)导通，则通过所述扫描芯片中第n级缓冲器D4的输出端输出的扫描输出信号G_out为低电平电压信号VGL，并提供给所述第n行扫描线。
当扫描线之间发生短路时(假设第n行扫描线与第n+1行扫描线发生短路)，当所述扫描芯片需要打第n+1行时，则应通过第n行的缓冲器D4为所 述第n行扫描线提供低电平电压信号VGL，通过第n+1行的缓冲器D4为所述第n+1行扫描线提供高电平信号VGH。但由于所述第n行扫描线与第n+1行扫描线发生短路，因此所述第n行缓冲器D4的输出端的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大。
本实施例中，正常工作状态下，当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的第一中间信号为高电平信号，所述反相器D2输入端接收所述高电平电压信号VGH，经反向处理后得到低电平电压信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。当所述扫描芯片需要打开其它行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGL，所述比较器D1的输出的第一中间信号为低电平电压信号，所述反相器D2输入端输入的为低电平电压信号，所述反相器D2输出高电平信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端高电平信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
若第n行扫描线和与之相邻的扫描线发生短路时，假设第n行扫描线与第n+1行扫描线发生短路。当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的第一中间信号为高电平信号，所述反相器D2输入端接收所述高电平电压信号VGH，经反向处理后得到低电平电压信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
当所述扫描芯片需要打开第n+1/n-1行扫描线时，所述第n+1/n-1级缓冲器D4输出高电平电压信号VGH，所述第n级缓冲器D4输出高电平电压信号VGL。但由于所述第n行扫描线与第n+1/n-1行扫描线短路，第所述第n级缓冲器D4输出端的的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大，因此此时所述比较器D1的输出的第一中间信号为高电平信号，所述反相器D2输入端输入的为低电平电压信号，所述反相器D2输出高电平信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端输入高电平信号，因此所述与门电路器件D3输出为1，即控制信号为高电平信号。因此所述扫描芯片可根据所述控制信号在发生短路时关 断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
在其中一个实施例中，请参见图7，所述比较单元100包括比较支路110和信号处理支路210。
所述比较支路110的第一输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较支路110的第二输入端与低电平电压信号VGL连接，所述比较支路110用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成比较信号；
所述信号处理支路210的输入端与所述比较支路110的输出端连接，所述信号处理支路210的输出端与所述判断单元200的第一输入端连接，所述信号处理支路210用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。
本实施例中，所述判断单元200包括逻辑判断支路220，所述逻辑判断支路220的第一输入端与所述信号处理支路210的输出端连接，所述逻辑判断支路220的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述逻辑判断支路220用于接收所述第一中间信号以及所述第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号以及所述第n级缓冲器D4的扫描输入信号G_in生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路110包括比较器D1，所述信号处理支路210包括反相器D2，所述逻辑判断支路220包括与门电路器件D3。
所述比较器D1的正向输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较器D1的负向输入端与低电平电压信号VGL连接，所述比较器的输出端与所述反相器D2的输入端连接。
所述与门电路器件D3的第一输入端与所述反相器D2的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接。
本实施例中，正常工作状态下，当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成高电平信号比较信号，所述反相器D2对所述高电平比较信号经反向处理后，生成低电平的第一中间信号，即所述与门电路器件D3的第一输入端为低电平电压信号，所述与门电路器件D3的第二输入端为高电平信号，因此此时所述与门电路器件D3输出为O，即控制信号为低电平电压信号。当所述扫描芯片需要打开其它行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGL，所述比较器D1的输 出的比较信号为低电平电压信号，所述反相器D2对所述低电平的比较信号反向处理后输出高电平的第一中间信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此此时所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
若第n行扫描线和与之相邻的扫描线发生短路时，假设第n行扫描线与第n+1行扫描线发生短路。当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的比较信号为高电平信号，所述反相器D2对所述高电平的比较信号反向处理后，生成低电平的第一中间信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端高电平信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
当所述扫描芯片需要打开第n+1/n-1行扫描线时，所述第n+1/n-1级缓冲器D4输出高电平电压信号VGH，所述第n级缓冲器D4输出高电平电压信号VGL。但由于所述第n行扫描线与第n+1/n-1行扫描线短路，第所述第n级缓冲器D4输出端的的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大，因此此时所述比较器D1的输出的比较信号为高电平信号，所述反相器D2对所述高电平的比较信号反向处理后，输出低电平的第一中间信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端输入低电平电压信号，因此所述与门电路器件D3输出为1，即控制信号为高电平信号。因此所述扫描芯片可根据所述控制信号在发生短路时关断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
基于同一发明构思，本申请还提供了一种扫描驱动电路，所述扫描驱动电路包括上述任一实施例中的检测电路。
本实施例中，所述扫描驱动电路包括缓冲器D4以及至少一个检测电路。其中，检测电路包括比较单元100和判断单元200。
所述比较单元100的第一输入端与扫描芯片第n级缓冲器D4的输出端连接，所述比较单元100的第二输入端与低电平电压信号VGL连接，所述比较单元100用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成第一中间信号。
所述判断单元200的第一输入端与所述比较单元100的输出端连接，所述判断单元200的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连 接，所述判断单元200用于接收所述比较单元100输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号和所述第n级缓冲器D4的扫描输入信号G_in生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
在其中一个实施例中，所述比较单元100包括比较支路110，所述比较支路110的第一输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较支路110的第二输入端与低电平电压信号VGL连接，所述比较支路110的输出端与所述判断单元200的第一输入端连接，所述比较支路110用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成第一中间信号。
在其中一个实施例中，所述判断单元200包括信号处理支路210和逻辑判断支路220。
所述信号处理支路210的输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述信号处理支路210用于接收所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in，并对所述第n级缓冲器D4的扫描输入信号G_in进行反向处理。
所述逻辑判断支路220的第一输入端与所述比较支路110的输出端连接，所述逻辑判断支路220的第二输入端与所述信号处理支路210的输出端连接，所述逻辑判断支路220用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号以及所述反向处理后的第n级缓冲器D4的扫描输入信号G_in生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路110包括比较器D1，所述比较器D1的正向输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较器D1的负向输入端与低电平电压信号VGL连接，所述比较器D1的输出端与所述逻辑判断的第一输入端连接。
在其中一个实施例中，所述信号处理支路210包括反相器D2，所述反相器D2的输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述反相器D2的输出端与所述逻辑判断支路220的第二输入端连接。
在其中一个实施例中，所述逻辑判断支路220包括与门电路器件D3，所述与门电路器件D3的第一输入端与所述比较器D1的输出端连接，所述与门 电路器件D3的第二输入端与所述反相器D2的输出端连接。
请参见图6，所述扫描芯片包括N级缓冲器D4。当所述扫描芯片需要打开第n行扫描线时(其中n和N均为大于或等于1的整数，并且1≤n≤N)，第n级缓冲器D4的输入端的扫描输入信号G_in为高电平信号，第一开关管T1(为N型场效应管)导通，第二开关管T2(为P型场效应管)截止，则通过所述扫描芯片中第n级缓冲器D4输出高电平电压信号VGH给所述第n行扫描线。当扫描到下一行或其它行时，第n级缓冲器D4中的第一开关管T1(为N型场效应管)关闭，第二开关管T2(为P型场效应管)导通，则通过所述扫描芯片中第n级缓冲器D4的输出端输出的扫描输出信号G_out为低电平电压信号VGL，并提供给所述第n行扫描线。
当扫描线之间发生短路时(假设第n行扫描线与第n+1行扫描线发生短路)，当所述扫描芯片需要打第n+1行时，则应通过第n行的缓冲器D4为所述第n行扫描线提供低电平电压信号VGL，通过第n+1行的缓冲器D4为所述第n+1行扫描线提供高电平信号VGH。但由于所述第n行扫描线与第n+1行扫描线发生短路，因此所述第n行缓冲器D4的输出端的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大。
本实施例中，正常工作状态下，当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的第一中间信号为高电平信号，所述反相器D2输入端接收所述高电平电压信号VGH，经反向处理后得到低电平电压信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。当所述扫描芯片需要打开其它行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGL，所述比较器D1的输出的第一中间信号为低电平电压信号，所述反相器D2输入端输入的为低电平电压信号，所述反相器D2输出高电平信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端高电平信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
若第n行扫描线和与之相邻的扫描线发生短路时，假设第n行扫描线与第n+1行扫描线发生短路。当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的第一中间信号为高电平信号，所述反相器D2输入端接收所述高电平电压信号VGH，经反向处理后得到低 电平电压信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
当所述扫描芯片需要打开第n+1/n-1行扫描线时，所述第n+1/n-1级缓冲器D4输出高电平电压信号VGH，所述第n级缓冲器D4输出高电平电压信号VGL。但由于所述第n行扫描线与第n+1/n-1行扫描线短路，第所述第n级缓冲器D4输出端的的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大，因此此时所述比较器D1的输出的第一中间信号为高电平信号，所述反相器D2输入端输入的为低电平电压信号，所述反相器D2输出高电平信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端输入高电平信号，因此所述与门电路器件D3输出为1，即控制信号为高电平信号。因此所述扫描芯片可根据所述控制信号在发生短路时关断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
本申请还提供了另一种扫描驱动电路，请参见图7，所述扫描驱动中的所述比较单元100包括比较支路110和信号处理支路210。
所述比较支路110的第一输入端与所述扫描芯片第n级缓冲器D4的输出端连接，所述比较支路110的第二输入端与低电平电压信号VGL连接，所述比较支路110用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成比较信号；
所述信号处理支路210的输入端与所述比较支路110的输出端连接，所述信号处理支路210的输出端与所述判断单元200的第一输入端连接，所述信号处理支路210用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。本实施例中，所述判断单元200包括逻辑判断支路220，所述逻辑判断支路220的第一输入端与所述信号处理支路210的输出端连接，所述逻辑判断支路220的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述逻辑判断支路220用于接收所述第一中间信号以及所述第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号以及所述第n级缓冲器D4的扫描输入信号G_in生成所述控制信号，并输出给所述扫描芯片。
在其中一个实施例中，所述比较支路110包括比较器D1，所述信号处理支路210包括反相器D2，所述逻辑判断支路220包括与门电路器件D3。
所述比较器D1的正向输入端与所述扫描芯片第n级缓冲器D4的输出端 连接，所述比较器D1的负向输入端与低电平电压信号VGL连接，所述比较器的输出端与所述反相器D2的输入端连接。
所述与门电路器件D3的第一输入端与所述反相器D2的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接。
本实施例中，正常工作状态下，当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成高电平信号比较信号，所述反相器D2对所述高电平比较信号经反向处理后，生成低电平的第一中间信号，即所述与门电路器件D3的第一输入端为低电平电压信号，所述与门电路器件D3的第二输入端为高电平信号，因此此时所述与门电路器件D3输出为O，即控制信号为低电平电压信号。当所述扫描芯片需要打开其它行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGL，所述比较器D1的输出的比较信号为低电平电压信号，所述反相器D2对所述低电平的比较信号反向处理后输出高电平的第一中间信号，即所述与门电路器件D3的第一输入端输入高电平信号，所述与门电路的第二输入端低电平电压信号，因此此时所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
若第n行扫描线和与之相邻的扫描线发生短路时，假设第n行扫描线与第n+1行扫描线发生短路。当所述扫描芯片需要打开第n行扫描线时，所述第n级缓冲器D4输出高电平电压信号VGH，所述比较器D1根据所述高电平电压信号VGH和低电平电压信号VGL，生成的比较信号为高电平信号，所述反相器D2对所述高电平的比较信号反向处理后，生成低电平的第一中间信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端高电平信号，因此所述与门电路器件D3输出为O，即控制信号为低电平电压信号。
当所述扫描芯片需要打开第n+1/n-1行扫描线时，所述第n+1/n-1级缓冲器D4输出高电平电压信号VGH，所述第n级缓冲器D4输出高电平电压信号VGL。但由于所述第n行扫描线与第n+1/n-1行扫描线短路，第所述第n级缓冲器D4输出端的的电压向高电平电压信号VGH电压靠近，较低电平电压信号VGL偏大，因此此时所述比较器D1的输出的比较信号为高电平信号，所述反相器D2对所述高电平的比较信号反向处理后，输出低电平的第一中间信号，即所述与门电路器件D3的第一输入端输入低电平电压信号，所述与门电路的第二输入端输入低电平电压信号，因此所述与门电路器件D3输出为1，即控制信号为高电平信号。因此所述扫描芯片可根据所述控制信号在发生短 路时关断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
综上，本申请提供了一种检测电路和扫描驱动电路。所述检测电路包括比较单元100和判断单元200。所述比较单元100的第一输入端与扫描芯片第n级缓冲器D4的输出端连接，所述比较单元100的第二输入端与低电平电压信号VGL连接，所述比较单元100用于接收所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out，并根据所述扫描输出信号G_out和所述低电平电压信号VGL生成第一中间信号。所述判断单元200的第一输入端与所述比较单元100的输出端连接，所述判断单元200的第二输入端与所述扫描芯片第n级缓冲器D4的输入端连接，所述判断单元200用于接收所述比较单元100输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器D4的输入端输出的所述第n级缓冲器D4的扫描输入信号G_in，根据所述第一中间信号和所述第n级缓冲器D4的扫描输入信号G_in生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。本申请中，通过所述比较单元100根据所述低电平电压信号VGL和所述第n级缓冲器D4的输出端输出的扫描输出信号G_out生成第一中间信号，以及通过所述判断单元200根据所述第一中间信号和所述第n级缓冲器D4的扫描输入信号G_in生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出，避免产生因扫描线之间短路致使扫描芯片被烧坏的问题。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种检测电路，包括：
    比较单元，第一输入端与扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号；以及
    判断单元，第一输入端与所述比较单元的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述比较单元输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
  2. 如权利要求1所述的检测电路，其中所述比较单元包括：
    比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，输出端与所述判断单元的第一输入端连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号。
  3. 如权利要求2所述的检测电路，其中所述判断单元包括：
    信号处理支路，输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，并对所述第n级缓冲器的扫描输入信号进行反向处理；以及
    逻辑判断支路，第一输入端与所述比较支路的输出端连接，第二输入端与所述信号处理支路的输出端连接，用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
  4. 如权利要求3所述的检测电路，其中所述比较支路包括比较器，所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述逻辑判断的第一输入端连接。
  5. 如权利要求4所述的检测电路，其中所述信号处理支路包括反相器， 所述反相器的输入端与所述扫描芯片第n级缓冲器的输入端连接，所述反相器的输出端与所述逻辑判断支路的第二输入端连接。
  6. 如权利要求4所述的检测电路，其中所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述比较器的输出端连接，所述与门电路器件的第二输入端与所述反相器的输出端连接。
  7. 如权利要求1所述的检测电路，其中所述比较单元包括：
    比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成比较信号；
    信号处理支路，输入端与所述比较支路的输出端连接，输出端与所述判断单元的第一输入端连接，用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。
  8. 如权利要求7所述的检测电路，其中所述判断单元包括：
    逻辑判断支路，第一输入端与所述信号处理支路的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述第一中间信号以及所述第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
  9. 如权利要求8所述的检测电路，其中所述比较支路包括比较器，所述信号处理支路包括反相器；其中，
    所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述反相器的输入端连接。
  10. 如权利要求9所述的检测电路，其中所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述反相器的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器的输入端连接。
  11. 一种扫描驱动电路，所述扫描驱动电路包括至少一个检测电路；
    其中，所述检测电路包括：
    比较单元，第一输入端与扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号；以及
    判断单元，第一输入端与所述比较单元的输出端连接，第二输入端与所 述扫描芯片第n级缓冲器的输入端连接，用于接收所述比较单元输出端输出的所述第一中间信号，以及所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，根据所述第一中间信号和所述第n级缓冲器的扫描输入信号生成控制信号，并输出给所述扫描芯片，以控制所述扫描芯片在发生短路时关断输出。
  12. 如权利要求11所述的扫描驱动电路，其中所述比较单元包括：
    比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，输出端与所述判断单元的第一输入端连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低电平电压信号生成第一中间信号。
  13. 如权利要求12所述的扫描驱动电路，其中所述判断单元包括：
    信号处理支路，输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述扫描芯片第n级缓冲器的输入端输出的所述第n级缓冲器的扫描输入信号，并对所述第n级缓冲器的扫描输入信号进行反向处理；以及
    逻辑判断支路，第一输入端与所述比较支路的输出端连接，第二输入端与所述信号处理支路的输出端连接，用于接收所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述反向处理后的第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
  14. 如权利要求13所述的扫描驱动电路，其中所述比较支路包括比较器，所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述逻辑判断的第一输入端连接。
  15. 如权利要求14所述的扫描驱动电路，其中所述信号处理支路包括反相器，所述反相器的输入端与所述扫描芯片第n级缓冲器的输入端连接，所述反相器的输出端与所述逻辑判断支路的第二输入端连接。
  16. 如权利要求15所述的扫描驱动电路，其中所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述比较器的输出端连接，所述与门电路器件的第二输入端与所述反相器的输出端连接。
  17. 如权利要求11所述的扫描驱动电路，其中所述比较单元包括：
    比较支路，第一输入端与所述扫描芯片第n级缓冲器的输出端连接，第二输入端与低电平电压信号连接，用于接收所述低电平电压信号和所述第n级缓冲器的输出端输出的扫描输出信号，并根据所述扫描输出信号和所述低 电平电压信号生成比较信号；
    信号处理支路，输入端与所述比较支路的输出端连接，输出端与所述判断单元的第一输入端连接，用于接收所述比较信号，对所述比较信号进行反向处理生成所述第一中间信号，并将所述第一中间信号提供给所述判断单。
  18. 如权利要求17所述的扫描驱动电路，其中所述判断单元包括：
    逻辑判断支路，第一输入端与所述信号处理支路的输出端连接，第二输入端与所述扫描芯片第n级缓冲器的输入端连接，用于接收所述第一中间信号以及所述第n级缓冲器的扫描输入信号，根据所述第一中间信号以及所述第n级缓冲器的扫描输入信号生成所述控制信号，并输出给所述扫描芯片。
  19. 如权利要求18所述的扫描驱动电路，其中所述比较支路包括比较器，所述信号处理支路包括反相器；其中，
    所述比较器的正向输入端与所述扫描芯片第n级缓冲器的输出端连接，所述比较器的负向输入端与低电平电压信号连接，所述比较器的输出端与所述反相器的输入端连接。
  20. 如权利要求19所述的扫描驱动电路，其中所述逻辑判断支路包括与门电路器件，所述与门电路器件的第一输入端与所述反相器的输出端连接，所述与门电路的第二输入端与所述扫描芯片第n级缓冲器的输入端连接。
PCT/CN2018/120271 2018-11-29 2018-12-11 检测电路和扫描驱动电路 Ceased WO2020107528A1 (zh)

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110264925B (zh) * 2019-06-11 2021-11-05 惠科股份有限公司 显示装置及其短路检测方法
CN110444141B (zh) * 2019-06-27 2022-08-05 重庆惠科金渝光电科技有限公司 一种显示面板的栅极驱动电路和显示装置
CN115331644B (zh) * 2022-08-31 2024-10-18 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示装置
CN117978151B (zh) * 2024-03-29 2024-06-07 上海灵动微电子股份有限公司 毛刺防护电路和预驱动芯片

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104318880A (zh) * 2014-08-19 2015-01-28 友达光电股份有限公司 具有短路检测机制的电压移位电路及短路检测方法
CN106340264A (zh) * 2016-07-12 2017-01-18 友达光电股份有限公司 一种电位转换器及其输出端短路检测方法
CN106991988A (zh) * 2017-05-17 2017-07-28 深圳市华星光电技术有限公司 Goa电路的过电流保护系统及方法
US20170316728A1 (en) * 2016-04-27 2017-11-02 Samsung Display Co., Ltd. Display apparatus and driving method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008268615A (ja) * 2007-04-23 2008-11-06 Matsushita Electric Ind Co Ltd プラズマディスプレイ装置
TWI373022B (en) * 2007-10-31 2012-09-21 Chunghwa Picture Tubes Ltd Method for controlling a flat panel display and a signal controlling circuit thereof
JP5175142B2 (ja) * 2008-07-28 2013-04-03 ラピスセミコンダクタ株式会社 ショート検出回路
CN103106881A (zh) * 2013-01-23 2013-05-15 京东方科技集团股份有限公司 一种栅极驱动电路、阵列基板及显示装置
CN105304050B (zh) * 2015-11-20 2017-07-25 深圳市华星光电技术有限公司 一种过流保护电路和过流保护方法
CN105448260B (zh) * 2015-12-29 2017-11-03 深圳市华星光电技术有限公司 一种过流保护电路及液晶显示器
CN105632438B (zh) * 2016-01-08 2017-12-08 京东方科技集团股份有限公司 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路
JP2017181574A (ja) * 2016-03-28 2017-10-05 株式会社ジャパンディスプレイ 表示装置
US10374413B2 (en) * 2017-03-27 2019-08-06 Rohm Co., Ltd. Switching power supply and method of short-circuit-to-ground detection therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104318880A (zh) * 2014-08-19 2015-01-28 友达光电股份有限公司 具有短路检测机制的电压移位电路及短路检测方法
US20170316728A1 (en) * 2016-04-27 2017-11-02 Samsung Display Co., Ltd. Display apparatus and driving method thereof
CN106340264A (zh) * 2016-07-12 2017-01-18 友达光电股份有限公司 一种电位转换器及其输出端短路检测方法
CN106991988A (zh) * 2017-05-17 2017-07-28 深圳市华星光电技术有限公司 Goa电路的过电流保护系统及方法

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