WO2020107390A1 - 功率放大器电路 - Google Patents

功率放大器电路 Download PDF

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Publication number
WO2020107390A1
WO2020107390A1 PCT/CN2018/118500 CN2018118500W WO2020107390A1 WO 2020107390 A1 WO2020107390 A1 WO 2020107390A1 CN 2018118500 W CN2018118500 W CN 2018118500W WO 2020107390 A1 WO2020107390 A1 WO 2020107390A1
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Prior art keywords
amplifier
branch
matching network
power
coupling line
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PCT/CN2018/118500
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English (en)
French (fr)
Inventor
曾志雄
孙捷
索海雷
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880098138.6A priority Critical patent/CN112771778A/zh
Priority to EP18941683.7A priority patent/EP3855619A4/en
Priority to PCT/CN2018/118500 priority patent/WO2020107390A1/zh
Publication of WO2020107390A1 publication Critical patent/WO2020107390A1/zh
Priority to US17/333,299 priority patent/US20210288616A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • This application relates to the field of electricity, and in particular to a power amplifier circuit.
  • the peak of the signal is relatively high, generally above 8dB, and can even reach 10dB.
  • the peak-to-average ratio refers to the ratio between the amplitude of the waveform and the effective value. Since the signal works in the non-peak state most of the time, the power amplifier needs to work in the high power back-off state most of the time. For traditional class AB power amplifiers, the efficiency at power back-off will be much lower than the peak efficiency. The efficiency can refer to the ratio between the output power of the power amplifier and the input power. Therefore, as the signal peak-to-average ratio increases, the efficiency of the power amplifier will decrease accordingly.
  • Doherty power amplification technology, outphasing power amplification technology or Chireix power amplification technology are commonly used in the industry to improve the efficiency of power amplifiers under power back-off.
  • the current technology to improve the efficiency of power amplifiers can maintain high efficiency when the power back-off range is small (for example, about 6dB), but when the power amplifier achieves a larger power back-off range, an efficiency recession will appear, and the power The larger the back-off range, the greater the depression in the "efficiency depression region", resulting in an insignificant increase in the efficiency of the power amplifier.
  • the present application provides a power amplifier circuit, which can improve the efficiency of the power amplifier.
  • a power amplifier circuit in a first aspect, includes: a first branch including a cascaded first amplifier and a first matching network, and a first end of the first branch is a signal input of the first amplifier End, the second end of the first branch is connected to the first input end of the first coupling line; the second branch includes a cascaded second amplifier and a second matching network, and the second branch One end is the signal input end of the second amplifier, the second end of the second branch is connected to the second input end of the first coupling line, and the first coupling line makes the first branch Forming a first combined circuit with the second branch; the third branch includes a cascaded third amplifier and a third matching network, and the first end of the third branch is the signal input end of the third amplifier, The second end of the third branch is connected to the first input end of the second coupling line; the fourth branch includes a cascaded fourth amplifier and a fourth matching network, and the first end of the fourth branch Is the signal input terminal of the fourth amplifier, the second terminal of the fourth branch is
  • the power of the first combined circuit to the second combined circuit is the relationship of the series combined circuit, so the load impedance is presented to each branch after the combined network formed by the coupling lines The impedance becomes lower. Therefore, the power amplifier circuit proposed in the embodiments of the present application is easier to implement a high-power, large-bandwidth power amplifier.
  • the circuit further includes 2N branches, where N is an integer greater than 0, where the 2i+3 branch includes a cascaded 2i+3 amplifier and A 2i+3 matching network, the first end of the 2i+3 branch is the signal input terminal of the 2i+3 amplifier, and the second end of the 2i+3 branch is coupled to the i+2 coupling line
  • the 2i+4 branch including the cascaded 2i+4 amplifier and the 2i+4 matching network, the 2i+4 branch
  • One end is the signal input end of the 2i+4 amplifier
  • the second end of the 2i+4 branch is connected to the second input end of the i+2 coupling line
  • the i+2 coupling line makes
  • the second i+3 branch and the second i+4 branch form an i+2 combined circuit;
  • the first output end of the i+2 coupling line is connected to the second output end of the i+1 coupling line ,
  • the power amplifier circuit can obtain higher efficiency when the power back-off range is increased. Further, it also has a smaller load traction ratio and a smaller impedance, so a high-power, wide-bandwidth power amplifier can be realized.
  • the first matching network and the second matching network are configured such that the first amplifier and the second amplifier form a first Doherty power tube pair ,
  • the configuration of the third matching network and the fourth matching network is such that the third amplifier and the fourth amplifier form a second Doherty power tube pair, and the first coupling line and the second coupling
  • the configuration of the wires enables the first Doherty power tube pair and the second Doherty power tube pair to form a combined Shire amplifier.
  • the electrical length of the first coupling line and the electrical length of the second coupling line are used to determine the first back-off height of the combined circuit of the Shire amplifier Efficiency point.
  • the first matching network and the second matching network are configured such that the first amplifier and the second amplifier form a peak power tube pair, and the third matching
  • the configuration of the network and the fourth matching network makes the third amplifier and the fourth amplifier form a Shire power tube pair
  • the configuration of the first coupling line and the second coupling line makes the Shire power
  • the tube pair and the peak power tube pair to the peak power tube pair constitute a Doherty amplifier combination circuit.
  • the configuration of the first matching network and the second matching network is such that the first amplifier and the second amplifier form a first Shire power tube pair
  • the configuration of the third matching network and the fourth matching network is such that the third amplifier and the fourth amplifier form a second Shire power tube pair
  • the first coupling line and the second coupling line The configuration is such that the first Shire power tube pair and the second Shire power tube pair form a Shire amplifier combination circuit.
  • the first matching network and the second matching network are configured such that the first amplifier and the second amplifier form a first Doherty power tube pair ,
  • the configuration of the third matching network and the fourth matching network is such that the third amplifier and the fourth amplifier form a second Doherty power tube pair, and the first coupling line and the second coupling
  • the configuration of the wires makes the first Doherty power tube pair and the second Doherty power tube pair form a Doherty amplifier circuit.
  • an integrated circuit including the power amplifier circuit described in the first aspect or any possible implementation manner of the first aspect.
  • a chip system including the power amplifier circuit described in the first aspect or any possible implementation manner of the first aspect.
  • Figure 1 is a schematic diagram of the ideal Chireix power amplifier circuit.
  • Figure 2 is a schematic diagram of the relationship between the power amplifier efficiency and the back-off power of an ideal Chireix power amplifier circuit.
  • Figure 3 is a schematic diagram of the relationship between the load pull ratio (LPR
  • 4 is a schematic diagram of the impedance of the Chireix power amplifier circuit at different output powers.
  • FIG. 5 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a power amplifier circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of the relationship between the power amplifier efficiency and the back-off power of a power amplifier circuit according to yet another embodiment of the present application.
  • FIG. 8 is a schematic diagram of the relationship between the load pulling ratio and the back-off power of a power amplifier circuit according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of impedances of a power amplifier circuit according to yet another embodiment of the present application at different output powers.
  • FIG. 10 is a schematic diagram of a power amplifier efficiency curve of a power amplifier circuit according to an embodiment of the present application under input signals of different frequencies.
  • 11 is a schematic diagram of the relationship between the excitation signal amplitude and the back-off power of each branch of the power amplifier circuit of the embodiment of the present application.
  • FIG. 12 is a schematic diagram of impedance bandwidth characteristics of the power amplifier circuit of the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a power amplifier circuit according to another embodiment of the present application.
  • FIG. 14 is a schematic diagram of the relationship between power amplifier efficiency and back-off power of a power amplifier circuit according to yet another embodiment of the present application.
  • 15 is a schematic diagram of impedances of a power amplifier circuit according to yet another embodiment of the present application at different output powers.
  • 16 is a schematic structural diagram of a power amplifier circuit according to another embodiment of the present application.
  • 17 is a schematic structural diagram of a power amplifier circuit according to another embodiment of the present application.
  • the power amplifier may also be simply referred to as a power amplifier.
  • FIG. 1 shows a schematic diagram of the ideal Chireix power amplifier circuit.
  • the Chireix power amplifier may include power tubes PA1 and PA2.
  • the two power tubes are combined through two sections of transmission lines with different lengths. The position where the two branches are combined may be called a combining point.
  • the phases of the excitation signals of the power tubes PA1 and PA2 are expressed as with Z c represents the characteristic impedance of the transmission line, and ⁇ 1 and ⁇ 2 represent the phase of the transmission line.
  • the length and phase difference of the two transmission lines determine the frequency band where the Chireix power amplifier works and the location of the first back-off high-efficiency point.
  • the back-off high-efficiency point refers to the position where the power amplifier reaches the highest efficiency of the ideal power tube
  • the first back-off high-efficiency point refers to the first high-efficiency point that occurs when the maximum back-off power changes to the minimum back-off power.
  • Figure 2 shows a schematic diagram of the relationship between the power amplifier efficiency curve and the back-off power of an ideal Chireix power amplifier circuit.
  • the position of the first retraction high-efficiency point K is shown in FIG. 2.
  • the power back-off range is small, for example, when the back-off range is about 6dB, the Chireix power amplifier can maintain a relatively high efficiency.
  • a larger power back-off range is required, that is, the position of the first back-off high-efficiency point is smaller. For example, in FIG.
  • the power back-off range is about 11 dB
  • the first back-off high-efficiency point K is at a position where the back-off power is -10.7 dB and the efficiency is 75.81%.
  • an obvious "efficiency recessed area” will appear within the power back-off range, and the efficiency of the power amplifier will decrease in the "efficiency recessed area”.
  • the larger the range of power back-off the larger the depression of the "efficiency depression region”. Since the power amplifier generally has a higher probability of working in the "efficiency recessed area", for example, it operates within the range of 5dB-10dB of power back-off in FIG. 2. Therefore, the existence of the "efficiency depression region" will affect the efficiency improvement effect of the power amplifier's modulated signal.
  • FIG. 3 is a schematic diagram of the relationship between the load pull ratio (LPR
  • the abscissa in FIG. 3 represents the back-off power
  • the ordinate represents the load traction ratio LPR.
  • the load traction ratio refers to the standing wave ratio corresponding to the reflection coefficient of the load impedance relative to the maximum output power impedance of the power tube. In the case where the load pull ratio is too large, the peak efficiency of the power amplifier will drop sharply. Therefore, we expect the load traction ratio to remain within a relatively small range.
  • the load traction is also large, which leads to a decrease in the efficiency of the power amplifier.
  • the curve in FIG. 3 shows the relationship between the load traction ratio of PA1 and PA2 and the back-off power. It can be seen from Figure 3 that when the back-off power is -10.7dB, the load pull ratio of the power tube in the Chireix power amplifier circuit is about 10.7dB, so the load pull is relatively large.
  • FIG. 4 shows a schematic diagram of the impedance of the Chireix power amplifier circuit at different output powers.
  • 1.0 in FIG. 4 represents a normalization of 50 ohms ( ⁇ ).
  • Curve 1 in FIG. 4 shows the impedance of PA1 in the Chireix power amplifier circuit at different output powers
  • curve 2 shows the impedance of PA2 in the Chireix power amplifier circuit at different output powers.
  • the minimum impedance of PA1 and PA2 is about 50 ⁇
  • the maximum impedance of PA1 and PA2 is about 550 ⁇ . Therefore, as the output power increases, the impedance of the two load traction paths of the Chireix power amplifier circuit decreases from 550 ⁇ to 50 ⁇ .
  • the output impedance is usually relatively small, for example, between 1 and 10 ⁇ Of the order of magnitude. Therefore, the impedance conversion ratio from the high impedance of 50 ⁇ to 550 ⁇ at the junction to the order of 1 to 10 ⁇ at the position of the power tube is very large, which severely limits the bandwidth of the matching circuit.
  • the power amplifier circuit 30 includes:
  • the first branch A1 includes a cascaded first amplifier PA1 and a first matching network MN1, the first end of the first branch A1 is a signal input end of the first amplifier, the first branch A1 The second end of is connected to the first input end of the first coupling line M1.
  • the second branch A2 includes a cascaded second amplifier PA2 and a second matching network MN2, the first end of the second branch A2 is the signal input end of the second amplifier PA2, and the second branch The second end of A2 is connected to the second input end of the first coupling line, and the first coupling line M1 makes the first branch A1 and the second branch A2 form a first joint.
  • the first combined circuit may be a serial combined circuit or a parallel combined circuit.
  • the series-parallel mode of the first combination may depend on the specific form of the first coupling line.
  • the third branch A3 includes a cascaded third amplifier PA3 and a third matching network MN3, the first end of the third branch A3 is the signal input end of the third amplifier PA3, and the third branch The second terminal of A3 is connected to the first input terminal of the second coupling line M2.
  • the fourth branch A4 includes a cascaded fourth amplifier PA4 and a fourth matching network MN4, the first end of the fourth branch A4 is the signal input end of the fourth amplifier PA4, and the fourth branch The second end of A4 is connected to the second input end of the second coupling line M2, and the second coupling line M2 makes the third branch A3 and the fourth branch A4 form a second joint.
  • the second combined circuit may be a serial combined circuit or a parallel combined circuit.
  • the series-parallel mode of the second combination may depend on the specific form of the first coupling line.
  • the first output terminal of the first coupling line M1 is the signal output terminal of the power amplifier circuit 30, and the second output terminal of the first coupling line M1 is connected to the first output terminal of the second coupling line M2 , So that the first joint and the second joint form a series joint.
  • the foregoing matching networks for example, the first matching network MN1 to the fourth matching network MN4, are used to match each branch.
  • the matching network may be composed of transmission lines of different lengths and different phases. This embodiment of the present application does not limit this.
  • the two branches corresponding to each of the above-mentioned coupling lines may form a class AB combination, an out-phasing (Outphasing) combination, a Chireix combination, or a Doherty combination through the coupling lines.
  • the first branch A1 and the second branch A2 may form a class AB power tube pair, an outphasing power tube pair, a Chireix power tube pair, or a Doherty power tube pair through the first coupling line M1.
  • the third branch A3 and the fourth branch A4 may form a class AB power tube pair, an outphasing power tube pair, a Chireix power tube pair, or a Doherty power tube pair through the second coupling line M2.
  • the two networks respectively corresponding to the first coupling line and the second coupling line may be recombined to form a Class AB combination, Outphasing combination, Chireix combination or Doherty combination.
  • FIG. 6 shows a schematic diagram of a power amplifier circuit 40 according to another embodiment of the present application.
  • the configurations of the first matching network MN1 and the second matching network MN2 are such that the first amplifier PA1 and the second amplifier PA2 form a first Doherty power tube pair P1, the third matching network MN3 and the first
  • the configuration of the four matching networks MN4 makes the third amplifier PA3 and the fourth amplifier PA4 form a second Doherty power tube pair P2
  • the configuration of the first coupling line M1 and the second coupling line M2 makes the first A Doherty power tube pair P1 and the second Doherty power tube P2 pair form a Chireix amplifier combination.
  • the first matching network MN1 to the fourth matching network MN4 may be transmission lines with different lengths and phases.
  • the phases of the first matching network MN1 and the second matching network MN2 are 0° and 90°, respectively, so that PA1 and PA2 form a Doherty power tube pair.
  • the phases of the third matching network MN3 and the fourth matching network MN4 are 0° and 90°, respectively, so that PA3 and PA4 form a Doherty power tube pair.
  • the electrical lengths L1 and L2 of the first coupling line M1 and the second coupling line M2 can be used to determine the position of the first retracted high efficiency point of the Chireix amplifier combination.
  • FIG. 7 shows the relationship between the power amplifier efficiency and the back-off power of the power amplifier circuit 40 of FIG. 6 and the Chireix power amplifier circuit of FIG. 1.
  • the curve 1 corresponds to the power amplifier circuit 40
  • the curve 2 corresponds to the Chireix power amplifier circuit in FIG.
  • the power amplifier circuit 40 introduces more back-off high efficiency points into the efficiency curve.
  • Figure 7 shows three back-off high-efficiency points, where the first back-off high-efficiency point is at a position of about -10dB, the second back-off high-efficiency point is at a position of about -5dB, and the third The high-efficiency back-off point is at 0dB.
  • the "efficiency recessed area" has been significantly improved, so the power amplifier circuit 40 can still maintain a high efficiency under a large power back-off range.
  • FIG. 8 is a schematic diagram of the relationship between the load pulling ratio and the back-off power of a power amplifier circuit according to another embodiment of the present application.
  • curve 1 is a schematic diagram of the relationship between the load traction ratio of the power amplifier circuit 40 and the back-off power
  • curve 2 is a schematic diagram of the relationship between the load traction ratio and the back-off power of the Chireix power amplifier circuit in FIG. 1. It can be seen from FIG. 8 that at the first back-off high efficiency point, that is, at a position of about -11 dB, the load pulling ratio of the amplifiers PA1 and PA2 of the Chireix power amplifier circuit is about 11 dB.
  • the load traction ratio of the amplifiers PA1 and PA3 of the power amplifier circuit 40 is 8 dB, which is about 3 dB smaller than the Chireix power amplifier. It can be seen that the load pulling ratio of the power amplifier circuit 40 in the embodiment of the present application is smaller than that of the conventional power amplifier circuit, so a higher efficiency power amplifier circuit can be realized.
  • FIG. 9 is a schematic diagram of impedances of a power amplifier circuit according to yet another embodiment of the present application at different output powers.
  • Curves 1 and 2 in FIG. 9 show the impedances of the first amplifier PA1 and the third amplifier PA3 of the power amplifier circuit 40, respectively.
  • the first amplifier PA1 and the third amplifier PA3 are power amplifiers of the main circuit of the power amplifier circuit 40.
  • the three intersection points of curve 1 and curve 2 respectively correspond to the impedances of the three back-off high-efficiency points of the power amplifier circuit 40.
  • the load impedance changes from about 12.5 ⁇ to about 50 ⁇ .
  • the load impedance decreases from 50 ⁇ to 12.5 ⁇ . Therefore, the impedance at the junction point of the power amplifier circuit 40 is low, and it is easier to realize a high-power broadband power amplifier.
  • Curve 1 is an efficiency curve with an input signal frequency of 1.8 GHz
  • curve 2 is an efficiency curve with an input signal frequency of 2.0 GHz
  • curve 3 is an efficiency curve with an input signal frequency of 2.2 GHz.
  • the maximum efficiency of the power amplifier circuit 40 is about 78% when the input signal frequency is 1.8 GHz-2.2 GHz, that is, when the bandwidth is about 0.4 GHz, and the efficiency is high in the range of power retreat -10 dB At 70%. It can be seen that the power amplifier circuit in the embodiment of the present application has high power efficiency under a wide bandwidth and a large power back-off range.
  • FIG. 11 is a schematic diagram of the relationship between the excitation signal amplitude and the back-off power of each branch of the power amplifier circuit 40 of the embodiment of the present application. It can be seen from FIG. 11 that the amplitudes of the excitation signals of the second branch A2 and the fourth branch A4 are 0 when the back-off power range exceeds 5 dB. In other words, the second branch A2 and the fourth branch A4 are only in an operating state when the fallback power range is within 5 dB, which is the same as the peak mode of the Doherty power amplifier.
  • FIG. 12 is a schematic diagram of impedance bandwidth characteristics of the power amplifier circuit 40 of the embodiment of the present application.
  • FIG. 12 shows a schematic diagram of the impedance of the first amplifier PA1 to the fourth amplifier PA4 in the power amplifier circuit 40 when the input signal frequency changes from 1.8 GHz to 2.2 GHz.
  • FIG. 12 shows the impedances of the first amplifier PA1 to the fourth amplifier PA4 when the back-off power is about 0dB, -5dB, and -10dB, respectively. It can be seen from FIG. 11 that the second amplifier PA2 and the fourth amplifier PA4 do not work when the back-off power range is greater than 5 dB.
  • the impedances of the second amplifier PA2 and the fourth amplifier PA4 when the back-off power is -5dB and -10dB are not shown in FIG.
  • the impedance variation range of the first amplifier PA1 to the fourth amplifier PA4 is small, and the impedance convergence characteristic of the power amplifier circuit 40 is good.
  • FIG. 13 is a schematic structural diagram of a power amplifier circuit 50 according to another embodiment of the present application.
  • the configurations of the first matching network MN1 and the second matching network MN2 are such that the first amplifier PA1 and the second amplifier PA2 form a peak power tube pair P1, and the third matching network MN3 and the fourth matching network MN4
  • the configuration is such that the third amplifier PA3 and the fourth amplifier PA4 form a Chireix power tube pair P2, and the configuration of the first coupling line M1 and the second coupling line M2 makes the Chireix power tube pair P2 and the The peak power tube forms a Doherty amplifier combination with P1.
  • the peak power tube pair P1 constitutes the peak circuit of the Doherty amplifier combination
  • the Chireix power tube pair P2 constitutes the main circuit of the Doherty amplifier combination
  • the first matching network MN1 to the fourth matching network MN4 may be transmission lines with different lengths and phases.
  • the phases of the first matching network MN1 and the second matching network MN2 are both 90°, so that PA1 and PA2 form a peak power tube pair in which the Doherty amplifier is combined.
  • the phases of the third matching network MN3 and the fourth matching network MN4 are 192° and 168°, respectively, so that PA3 and PA4 form a Chireix power tube pair.
  • the electrical length of the transmission line of the third matching network MN3 is L3
  • the electrical length of the transmission line of the fourth matching network MN4 is L4.
  • L3, L4 and the maximum power output capability of the first amplifier PA1-fourth amplifier PA4 can be used together to determine the position of the back-off high efficiency point of the power amplifier circuit 50.
  • FIG. 14 is a schematic diagram of the relationship between the power amplifier efficiency and the back-off power of a power amplifier circuit 50 according to another embodiment of the present application. It can be seen from FIG. 14 that the power amplifier circuit 50 also introduces three back-off high-efficiency points in the efficiency curve. Among them, the position of the first back-off high efficiency point is about -13dB, the position of the second back-off high efficiency point is about -6.5dB, and the position of the third back-off high efficiency point is 0dB. And when the power back-off range is between 6.5dB-13dB, the power amplifier circuit 50 maintains a relatively high efficiency, which is about 76% or more.
  • the power back-off range is between 0dB-6.5dB, and the efficiency of the power amplifier circuit 50 is also above 70%.
  • the efficiency of the power amplifier when the power back-off range is large is improved, and the “efficiency recessed area” situation is improved.
  • FIG. 15 is a schematic diagram of impedances of a power amplifier circuit according to yet another embodiment of the present application at different output powers.
  • Curve 1 and curve 2 in FIG. 15 show the impedances of the third amplifier PA3 and the fourth amplifier PA4 of the power amplifier circuit 50, respectively.
  • the three intersection points of curve 1 and curve 2 respectively correspond to the three high-efficiency points of the power amplifier circuit 50.
  • the load impedance changes from about 12.5 ⁇ to about 100 ⁇ . It can be understood that as the output power of the power amplifier circuit 50 increases, the load impedance decreases from 100 ⁇ to 12.5 ⁇ . Therefore, compared with FIG. 4, the load impedance of the power amplifier circuit 50 is lower than that of the conventional Chireix power amplifier circuit, and it is easier to realize a high-power broadband power amplifier.
  • FIG. 16 is a schematic structural diagram of a power amplifier circuit 60 according to another embodiment of the present application.
  • the configurations of the first matching network MN1 and the second matching network MN2 are such that the first amplifier PA1 and the second amplifier PA2 form a first Chireix power tube pair P1, and the third matching network MN3 and the The configuration of the fourth matching network MN4 makes the third amplifier PA3 and the fourth amplifier PA4 form a second Chireix power tube pair P2, and the configuration of the first coupling line M1 and the second coupling line M2 makes the first Chireix power The tube pair P1 and the second Chireix power tube pair P2 form a Chireix amplifier combination.
  • the first matching network MN1 to the fourth matching network MN4 may be transmission lines with different lengths and phases.
  • the phases of the first matching network MN1 and the second matching network MN2 are 60 and 120°, respectively, so that PA1 and PA2 form a Chireix power tube pair.
  • the phases of the third matching network MN3 and the fourth matching network MN4 are 60 and 120°, respectively, so that PA3 and PA4 form a Chireix power tube pair.
  • the length of the first coupling line M1 is L1
  • the length of the second coupling line M2 is L2.
  • Z odd is used to indicate the odd-mode impedance of the coupled line, and Z even indicates the even-mode impedance of the coupled line.
  • the power amplifier in the embodiment of the present application may also form the power amplifier circuit in other ways.
  • the configuration of the first matching network MN1 and the second matching network MN2 is such that the first amplifier PA1 and the second amplifier PA2 form a first Doherty power tube pair, and the third matching network MN3 and the fourth matching network MN4
  • the configuration of the third amplifier PA3 and the fourth amplifier PA4 form a second Doherty power tube pair
  • the configuration of the first coupling line M1 and the second coupling line M2 make the first Doherty power tube pair P1 and the second Doherty power tube pair P2 Doherty amplifier is combined.
  • the power of the first combined circuit to the second combined circuit is the relationship of the series combined circuit, so the load impedance is presented to each branch after the combined network formed by the coupling lines The impedance becomes lower. Therefore, the power amplifier circuit proposed in the embodiments of the present application is easier to implement a high-power, large-bandwidth power amplifier.
  • the power amplifier circuit in the embodiment of the present application may further include more branches.
  • FIG. 17 is a schematic structural diagram of a power amplifier circuit 80 according to another embodiment of the present application. As shown in FIG. 17, the power amplifier circuit 80 may further include 2N branches, where N is an integer greater than 0.
  • the 2i+3 branch A (2i+3) includes a cascaded 2i+3 amplifier PA (2i+3) and a 2i+3 matching network MN (2i+3), the 2i+3 branch
  • the first end of the path is the signal input end of the 2i+3 amplifier
  • the 2i+4 branch A (2i+4) including the cascaded 2i+4 amplifier PA (2i+4) and the 2i+4 matching network MN (2i+4), the 2i+4 branch
  • the first terminal of A(2i+4) is the signal input terminal of the 2i+4 amplifier PA(2i+4)
  • the second terminal of the 2i+4 branch A(2i+4) is connected to the i+ 2 the second input end of the coupling line M(i+2) is connected, and the i+2 coupling line M(i+2) makes the 2i+3 branch A(2i+3) and the 2i
  • the +4 branch A (2i+4) forms the i+2 joint.
  • the first output terminal of the (i+2)th coupling line M(i+2) is connected to the second output terminal of the (i+1)th coupling line M(i+1), so that the first coupling circuit
  • the connection to the i+2th connection forms a series connection.
  • the first to N+2th connection forms a series connection.
  • the second output terminal of the N+2 coupling line M(N+2) may be connected to the corresponding matching network MN.
  • the power amplifier circuit can obtain higher efficiency when the power back-off range is increased. Further, it also has a smaller load traction ratio and a smaller impedance, so a high-power, wide-bandwidth power amplifier can be realized.
  • the power amplifier circuit can obtain higher efficiency when the power back-off range is increased. Further, it also has a smaller load traction ratio and a smaller impedance, so a high-power, wide-bandwidth power amplifier can be realized.
  • the power of the first combined circuit to the N+2 combined circuit is the relationship of the series combined circuit, so the load impedance is presented to each after the combined network formed by the coupling lines The impedance of the branch becomes lower. Therefore, the power amplifier circuit proposed in the embodiments of the present application is easier to implement a high-power, large-bandwidth power amplifier.
  • each coupling line in the embodiment of the present application may be a four-port coupling line.
  • the above four ports may include a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1 and a second output terminal OUT2, respectively.
  • (1)-(8) in FIG. 18 show schematic structural diagrams of different forms of coupling lines used in embodiments of the present application.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and both ends of the first microstrip line W1 are a first input terminal IN1 and a first output, respectively At the terminal OUT1, the two ends of the second microstrip line W2 are the second input terminal IN2 and the second output terminal OUT2, respectively.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other. Both ends of the first microstrip line W1 are respectively a first input terminal IN1 and a second input terminal IN2, and both ends of the second microstrip line W2 are respectively a second output terminal OUT1 and a second output terminal OUT2.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the first end and the second end of the first microstrip line W1 are a first input port IN1 and a first output port OUT1, respectively.
  • the first end of the third microstrip line W3 is the second input port IN2
  • the second end of the fourth microstrip line W4 is the second output port OUT2
  • the second end of the second microstrip line W2 It is connected to the second end of the third microstrip line W3, and the first end of the second microstrip line W2 and the first end of the fourth microstrip line W4 are respectively connected to corresponding matching networks MN.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the first end and the second end of the first microstrip line W1 are a first input port IN1 and a first output port OUT1, respectively.
  • the first end and the second end of the fourth microstrip line W4 are the second input port IN2 and the second output port OUT2, respectively.
  • the second end of the second microstrip line W2 is connected to the second end of the third microstrip line W3, the first end of the second microstrip line W2 and the third end of the third microstrip line W3 One end is respectively connected to the corresponding matching network MN.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the first end of the second microstrip line W2 is the first input port IN1
  • the second end of the first microstrip line W1 is the first output port OUT1.
  • the first end of the third microstrip line W3 is the second input port IN2, and the second end of the fourth microstrip line W4 is the second output port OUT2.
  • the second end of the second microstrip line W2 is connected to the second end of the third microstrip line W3, the first end of the first microstrip line W1 and the first end of the fourth microstrip line W4 One end is respectively connected to the corresponding matching network MN.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the first end of the first microstrip line W1 is a first input port IN1
  • the second end of the fourth microstrip line W4 is a second input port IN2.
  • the first end of the second microstrip line W2 is the first output port OUT1
  • the second end of the third microstrip line W3 is the second output port OUT2.
  • the second end of the second microstrip line W2 is connected to the first end of the third microstrip line W3, the second end of the first microstrip line W1 and the first end of the fourth microstrip line W4 One end is respectively connected to the corresponding matching network MN.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the second end of the first microstrip line W1 is a first input port IN1
  • the first end of the fourth microstrip line W4 is a second input port IN2.
  • the first end of the second microstrip line W2 is the first output port OUT1
  • the second end of the third microstrip line W3 is the second output port OUT2.
  • the second end of the second microstrip line W2 is connected to the first end of the third microstrip line W3, the first end of the first microstrip line W1 and the first end of the fourth microstrip line W4
  • the two ends are respectively connected to the corresponding matching network MN.
  • the coupling line may include a first microstrip line W1 and a second microstrip line W2 coupled to each other, and a third microstrip line W3 and a fourth microstrip line W4 coupled to each other.
  • the first end of the first microstrip line W1 is a first input port IN1
  • the first end of the fourth microstrip line W4 is a second input port IN2.
  • the first end of the second microstrip line W2 is the first output port OUT1
  • the second end of the third microstrip line W3 is the second output port OUT2.
  • the second end of the second microstrip line W2 is connected to the first end of the third microstrip line W3, the second end of the first microstrip line W1 and the first end of the fourth microstrip line W4
  • the two ends are respectively connected to the corresponding matching network MN.
  • microstrip lines in (1)-(8) of FIG. 18 can also be replaced by lumped elements such as inductors, capacitors, or resistors.

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Abstract

一种功率放大器电路，能够提高功率放大器的效率。该电路包括：第一支路，包括级联的第一放大器和第一匹配网络；第二支路，包括级联的第二放大器和第二匹配网络，第一耦合线使得第一支路和第二支路形成第一合路；第三支路，包括级联的第三放大器和第三匹配网络；第四支路，包括级联的第四放大器和第四匹配网络，第二耦合线使得第三支路和第四支路形成第二合路；第一耦合线的第一输出端为电路的信号输出端，第一耦合线的第二输出端与第二耦合线的第一输出端相连，使得第一合路和第二合路形成串联合路。

Description

功率放大器电路 技术领域
本申请涉及电学领域，尤其涉及一种功率放大器电路。
背景技术
在现代数字通信标准中，信号的峰均比较高，一般在8dB以上，甚至可以达到10dB。其中，峰均比指波形的振幅与有效值之间的比值。由于信号在大部分时间工作在非峰值状态，因此功率放大器在大部分时间需要工作在大功率回退状态下。对于传统的AB类功率放大器，在功率回退时的效率相比峰值时的效率将下降很多。其中效率可以指功率放大器的输出功率与输入功率之间的比值。因此，随着信号峰均比的增大，功率放大器的效率将随之下降。当前业界普遍使用多赫蒂(Doherty)功率放大技术、异相(outphasing)功率放大技术或者希雷(Chireix)功率放大技术提升功率放大器在功率回退下的效率。
当前提升功率放大器效率的技术在功率回退范围较小(例如6dB左右)的时候能够保持较高的效率，但是功率放大器在实现更大的功率回退范围时会出现一个效率凹陷区，并且功率回退的范围越大，“效率凹陷区”的凹陷越大，导致功率放大器的效率提升不明显。
发明内容
本申请提供一种功率放大器电路，能够提高功率放大器的效率。
第一方面，提供了一种功率放大器电路包括：第一支路，包括级联的第一放大器和第一匹配网络，所述第一支路的第一端为所述第一放大器的信号输入端，所述第一支路的第二端与第一耦合线的第一输入端相连；第二支路，包括级联的第二放大器和第二匹配网络，所述第二支路的第一端为所述第二放大器的信号输入端，所述第二支路的第二端与所述第一耦合线的第二输入端相连，所述第一耦合线使得所述第一支路和第二支路形成第一合路；第三支路，包括级联的第三放大器和第三匹配网络，所述第三支路的第一端为所述第三放大器的信号输入端，所述第三支路的第二端与第二耦合线的第一输入端相连；第四支路，包括级联的第四放大器和第四匹配网络，所述第四支路的第一端为所述第四放大器的信号输入端，所述第四支路的第二端与所述第二耦合线的第二输入端相连，所述第二耦合线使得所述第三支路和第四支路形成第二合路；所述第一耦合线的第一输出端为所述电路的信号输出端，所述第一耦合线的第二输出端与所述第二耦合线的第一输出端相连，使得所述第一合路和所述第二合路形成串联合路。
在本申请实施例中提出的功率放大器电路的方案中，相比于传统的功率放大器电路，可以在功率回退范围增大的情况下，获得更高的效率。进一步地，在第一个回退高效率点时，功率放大器电路的负载牵引比更低，因此更适合高效率的功率放大器。
本申请实施例提出的功率放大器电路的方案中，第一合路到第二合路的功率是串联合路的关系，因此负载阻抗在通过耦合线组成的合路网络之后，呈现给各支路的阻抗变低了， 因此，本申请实施例中提出的功率放大器电路更容易实现大功率、大宽带的功率放大器。
结合第一方面，在一种可能的实现方式中，所述电路还包括2N个支路，N为大于0的整数，其中，第2i+3支路，包括级联的第2i+3放大器和第2i+3匹配网络，所述第2i+3支路的第一端为所述第2i+3放大器的信号输入端，所述2i+3支路的第二端与第i+2耦合线的第一输入端相连，i＝1，2…,N；第2i+4支路，包括级联的第2i+4放大器和第2i+4匹配网络，所述第2i+4支路的第一端为所述第2i+4放大器的信号输入端，所述2i+4支路的第二端与第i+2耦合线的第二输入端相连，所述第i+2耦合线使得所述第2i+3支路和所述第2i+4支路形成第i+2合路；所述第i+2耦合线的第一输出端与第i+1耦合线的第二输出端相连，使得所述第一合路至所述第i+2合路形成串联合路。
在本申请实施例中，相比于传统的功率放大器电路，功率放大器电路可以在功率回退范围增大的情况下，获得更高的效率。进一步地，还具有更小的负载牵引比和更小的阻抗，因此能够实现大功率、宽带宽的功率放大器。
结合第一方面，在一种可能的实现方式中，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一多赫蒂功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二多赫蒂功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一多赫蒂功率管对和所述第二多赫蒂功率管对组成希雷放大器合路。
结合第一方面，在一种可能的实现方式中，所述第一耦合线的电长度和所述第二耦合线的电长度用于确定所述希雷放大器合路的第一个回退高效率点。
结合第一方面，在一种可能的实现方式中，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和第二放大器组成峰值功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成希雷功率管对，所述第一耦合线和所述第二耦合线的配置使得所述希雷功率管对和所述峰路的功率管对峰值功率管对组成多赫蒂放大器合路。
结合第一方面，在一种可能的实现方式中，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一希雷功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二希雷功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一希雷功率管对和所述第二希雷功率管对组成希雷放大器合路。
结合第一方面，在一种可能的实现方式中，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一多赫蒂功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二多赫蒂功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一多赫蒂功率管对和所述第二多赫蒂功率管对组成多赫蒂放大器合路。
第二方面，提供了一种集成电路，所述集成电路包括第一方面或第一方面的任一种可能的实现方式中所述的功率放大器电路。
第三方面，提供了一种芯片系统，所述芯片系统包括第一方面或第一方面的任一种可能的实现方式中所述的功率放大器电路。
附图说明
图1是理想的Chireix功率放大器电路原理示意图。
图2是理想的Chireix功率放大器电路的功放效率与回退功率之间的关系示意图。
图3是理想的Chireix功率放大器电路的负载牵引比(load pull ratio，LPR|)与回退功率之间的关系示意图。
图4是Chireix功率放大器电路在不同输出功率时的阻抗的示意图。
图5是本申请实施例的功率放大器电路的结构示意图。
图6是本申请又一实施例的功率放大器电路的结构示意图。
图7是本申请又一实施例的功率放大器电路的功放效率与回退功率之间的关系示意图。
图8是本申请又一实施例的功率放大器电路的负载牵引比与回退功率之间的关系示意图。
图9是本申请又一实施例的功率放大器电路在不同输出功率时的阻抗的示意图。
图10是本申请实施例的功率放大器电路在不同频率的输入信号下的功放效率曲线的示意图。
图11是本申请实施例的功率放大器电路的各支路的激励信号幅度与回退功率之间的关系示意图。
图12是本申请实施例的功率放大器电路的阻抗带宽特性示意图。
图13是本申请又一实施例的功率放大器电路的结构示意图。
图14是本申请又一实施例的功率放大器电路的功放效率与回退功率之间的关系示意图。
图15是本申请又一实施例的功率放大器电路在不同输出功率时的阻抗的示意图。
图16是本申请又一实施例的功率放大器电路的结构示意图。
图17是本申请又一实施例的功率放大器电路的结构示意图。
图18是本申请实施例中的耦合线的不同形式的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
为了便于理解，首先介绍功率放大技术提升的原理。需要说明的是，在本申请实施例中，功率放大器也可以简称为功放。
图1示出了理想的Chireix功率放大器电路原理示意图。如图1所示，Chireix功率放大器可以包括功率管PA1和PA2，两个功率管通过两段长度不同的传输线进行合路，两个支路合路的位置可以称为合路点。其中功率管PA1和PA2的激励信号相位分别表示为
Figure PCTCN2018118500-appb-000001
和
Figure PCTCN2018118500-appb-000002
Z c表示传输线的特性阻抗，θ 1、θ 2表示传输线的相位。两段传输线的长度和相位差确定了Chireix功率放大器工作的频段和第一个回退高效率点的位置。其中，回退高效率点是指功放达到理想功率管最高效率的位置，第一个回退高效率点是指从最大回退功率往最小回退功率变化时出现的第一个高效率点。
图2示出了理想的Chireix功率放大器电路的功放效率曲线与回退功率之间的关系示意图。图2中示出了第一个回退高效率点K的位置。通常情况下，在功率回退范围较小时， 例如，在回退范围为6dB左右时，Chireix功放可以保持相对较高的效率。但对于峰均比较大的信号，需要功率回退范围较大，即第一个回退高效率点的位置较小。例如，图2中功率回退范围为11dB左右，第一个回退高效率点K的位于回退功率为-10.7dB的位置，效率为75.81％的位置。在这种情况下，在功率回退范围内会出现一个明显的“效率凹陷区”，在“效率凹陷区”，功率放大器的效率下降。并且功率回退的范围越大，“效率凹陷区”的凹陷越大。由于通常情况下功率放大器在“效率凹陷区”工作的概率较大，例如，在图2中功率回退5dB-10dB的区间内工作。因此“效率凹陷区”的存在将影响功率放大器的调制信号的效率提升效果。
图3是理想的Chireix功率放大器电路的负载牵引比(load pull ratio，LPR|)与回退功率之间的关系示意图。图3中的横坐标表示回退功率，纵坐标表示负载牵引比LPR。其中，负载牵引比是指负载阻抗相对于功率管最大输出功率阻抗的反射系数所对应的驻波比。在负载牵引比过大的情况下，功率放大器的峰值效率将急剧下降。因此，我们期望负载牵引比维持在较小的范围。但是在Chireix功率放大器电路中，当功率回退范围较大时负载牵引也较大，这导致了功率放大器的效率下降。图3中的曲线示出了PA1和PA2的负载牵引比与回退功率的关系。由图3可见，在回退功率为-10.7dB时，Chireix功率放大器电路中的功率管的负载牵引比为10.7dB左右，因此负载牵引比较大。
图4示出了Chireix功率放大器电路在不同输出功率时的阻抗的示意图。其中，图4中的1.0表示50欧姆(Ω)的归一化。图4中的曲线1示出了Chireix功率放大器电路中的PA1在不同输出功率时的阻抗，曲线2示出了Chireix功率放大器电路中的PA2在不同输出功率时的阻抗。由图4可以看出，PA1和PA2的最小阻抗为50Ω左右，PA1和PA2的最大阻抗在550Ω左右。因此，随着输出功率的增加，Chireix功率放大器电路的两个负载牵引路径的阻抗从550Ω下降至50Ω，对于输出功率较大的场效应功率管，其输出阻抗通常比较小，例如在1～10Ω的数量级。因此从合路点的高阻抗50Ω～550Ω变换到功率管位置的1～10Ω的数量级，其阻抗变换比非常大，严重限制了匹配电路的带宽。
图5是本申请实施例的功率放大器电路30的结构示意图。如图5所示，该功率放大器电路30包括：
第一支路A1，包括级联的第一放大器PA1和第一匹配网络MN1，所述第一支路A1的第一端为所述第一放大器的信号输入端，所述第一支路A1的第二端与第一耦合线M1的第一输入端相连。
第二支路A2，包括级联的第二放大器PA2和第二匹配网络MN2，所述第二支路A2的第一端为所述第二放大器PA2的信号输入端，所述第二支路A2的第二端与所述第一耦合线的第二输入端相连，所述第一耦合线M1使得所述第一支路A1和第二支路A2形成第一合路。
可选地，所述第一合路可以是串联合路也可以是并联合路。例如，第一合路的串并联模式可以取决于第一耦合线的具体形式。
第三支路A3，包括级联的第三放大器PA3和第三匹配网络MN3，所述第三支路A3的第一端为所述第三放大器PA3的信号输入端，所述第三支路A3的第二端与第二耦合线M2的第一输入端相连。
第四支路A4，包括级联的第四放大器PA4和第四匹配网络MN4，所述第四支路A4 的第一端为所述第四放大器PA4的信号输入端，所述第四支路A4的第二端与所述第二耦合线M2的第二输入端相连，所述第二耦合线M2使得所述第三支路A3和第四支路A4形成第二合路。
可选地，所述第二合路可以是串联合路也可以是并联合路。例如，第二合路的串并联模式可以取决于第一耦合线的具体形式。
所述第一耦合线M1的第一输出端为所述功率放大器电路30的信号输出端，所述第一耦合线M1的第二输出端与所述第二耦合线M2的第一输出端相连，使得所述第一合路和所述第二合路形成串联合路。
可选地，上述各匹配网络，例如第一匹配网络MN1至第四匹配网络MN4，用于匹配各个支路。例如，根据不同的需求配置各支路的阻抗和相位等。在一个示例中，匹配网络可以由不同长度、不同相位的传输线组成。本申请实施例对此不做限定。
可选地，上述每个耦合线对应的两个支路可以通过耦合线形成AB类合路、异相(Outphasing)合路、Chireix合路或者Doherty合路。例如，第一支路A1和第二支路A2可以通过第一耦合线M1形成AB类功率管对、Outphasing功率管对、Chireix功率管对或者Doherty功率管对。或者，第三支路A3和第四支路A4可以通过第二耦合线M2形成AB类功率管对、Outphasing功率管对、Chireix功率管对或者Doherty功率管对。上述第一耦合线和第二耦合线分别对应的两个网络可以再结合，形成AB类合路、Outphasing合路、Chireix合路或者Doherty合路。
作为一个具体示例，图6示出了本申请又一实施例的功率放大器电路40的示意图。如图6所示，第一匹配网络MN1和第二匹配网络MN2的配置使得所述第一放大器PA1和所述第二放大器PA2组成第一Doherty功率管对P1，第三匹配网络MN3和所第四匹配网络MN4的配置使得所述第三放大器PA3和所述第四放大器PA4组成第二Doherty功率管对P2，所述第一耦合线M1和所述第二耦合线M2的配置使得所述第一Doherty功率管对P1和所述第二Doherty功率管P2对组成Chireix放大器合路。其中，第一匹配网络MN1～第四匹配网络MN4可以是不同长度和相位的传输线。例如，作为示例而非限定，第一匹配网络MN1和第二匹配网络MN2的相位分别为0°和90°，以使得PA1和PA2形成Doherty功率管对。类似地，第三匹配网络MN3和第四匹配网络MN4的相位分别为0°和90°，以使得PA3和PA4形成Doherty功率管对。第一耦合线M1和第二耦合线M2的电长度L1和L2可以用于确定Chireix放大器合路的第一个回退高效率点的位置。
图7示出了图6的功率放大器电路40以及图1中的Chireix功率放大器电路的功放效率和回退功率之间的关系。其中曲线1对应功率放大器电路40，曲线2对应图1中的Chireix功率放大器电路。相比于传统的Chireix功率放大器电路，功率放大器电路40为效率曲线中引入了更多个回退高效率点。例如，图7中示出了三个回退高效率点，其中第一个回退高效率点位于-10dB左右的位置，第二个回退高效率点位于-5dB左右的位置，第三个回退高效率点位于0dB位置。在增加了回退高效率点的情况下，“效率凹陷区”得到了明显改善，因此功率放大器电路40在大的功率回退范围下，依然可以保持较高的效率。
图8是本申请又一实施例的功率放大器电路的负载牵引比与回退功率之间的关系示意图。其中，曲线1是功率放大器电路40的负载牵引比与回退功率之间的关系示意图，曲线2是图1中的Chireix功率放大器电路的负载牵引比与回退功率之间的关系示意图。 由图8可以看出，在第一回退高效率点处，即-11dB左右的位置处，Chireix功率放大器电路的放大器PA1和PA2的负载牵引比大约为11dB左右。而功率放大器电路40的放大器PA1、PA3的负载牵引比为8dB，比Chireix功放小3dB左右。可见，本申请实施例中的功率放大器电路40的负载牵引比相比传统的功率放大器电路更小，因此可以实现更高效率的功率放大器电路。
图9是本申请又一实施例的功率放大器电路在不同输出功率时的阻抗的示意图。图9中的曲线1和曲线2分别示出了功率放大器电路40的第一放大器PA1和第三放大器PA3的阻抗。其中，第一放大器PA1和第三放大器PA3为功率放大器电路40的主路的功放。在图9中，曲线1和曲线2的三个交点分别对应功率放大器电路40的三个回退高效率点的阻抗。从图9可见，第一回退高效率点到第三回退高效率点之间，负载阻抗从12.5Ω左右变化到50Ω左右。可以理解为，随着功率放大器电路40的输出功率的增加，负载阻抗从50Ω下降至12.5Ω。因此功率放大器电路40的合路点位置的阻抗较低，更容易实现大功率的宽带功率放大器。
图10是是本申请实施例的功率放大器电路在不同频率的输入信号下的功放效率曲线的示意图。其中，假设第一耦合线M1和第二耦合线M2的偶模阻抗Z even＝220Ω。曲线1是输入信号频率为1.8GHz的效率曲线，曲线2是输入信号频率为2.0GHz的效率曲线，曲线3是输入信号频率为2.2GHz的效率曲线。可以看出，在输入信号频率1.8GHz-2.2GHz的情况下，即带宽为0.4GHz左右时，功率放大器电路40的最高效率为78％左右，且在功率回退-10dB范围内，效率均高于70％。可见本申请实施例中的功率放大器电路在宽带宽、大的功率回退范围下的功率效率也较高。
图11是本申请实施例的功率放大器电路40的各支路的激励信号幅度与回退功率之间的关系示意图。由图11可见，第二支路A2和第四支路A4的激励信号幅度在回退功率范围超过5dB的情形下为0。换句话说，第二支路A2和第四支路A4只有在回退功率范围5dB以内时处于工作状态，这与Doherty功率放大器的峰值(peak)路的工作模式相同。
图12是本申请实施例的功率放大器电路40的阻抗带宽特性示意图。图12示出了功率放大器电路40中的第一放大器PA1-第四放大器PA4在输入信号频率从1.8GHz-2.2GHz变化时的阻抗示意图。图12中的分别示出了回退功率为0dB、-5dB以及-10dB左右时第一放大器PA1-第四放大器PA4的阻抗。其中，由图11可知，第二放大器PA2和第四放大器PA4在回退功率范围大于5dB时不工作。因此，图12中未示出第二放大器PA2和第四放大器PA4在回退功率为-5dB以及-10dB时的阻抗。从图12可以看出，在宽带宽下，第一放大器PA1-第四放大器PA4的阻抗变化范围较小，功率放大器电路40的阻抗收敛特性较好。
作为一个具体示例，图13是本申请又一实施例的功率放大器电路50的结构示意图。如图13所示，第一匹配网络MN1和第二匹配网络MN2的配置使得所述第一放大器PA1和第二放大器PA2组成峰值功率管对P1，第三匹配网络MN3和第四匹配网络MN4的配置使得所述第三放大器PA3和所述第四放大器PA4组成Chireix功率管对P2，所述第一耦合线M1和所述第二耦合线M2的配置使得所述Chireix功率管对P2和所述峰值功率管对P1组成Doherty放大器合路。其中，所述峰值功率管对P1组成了所述Doherty放大器合路的峰值路，所述Chireix功率管对P2组成了所述Doherty放大器合路的主(main)路。 其中，第一匹配网络MN1～第四匹配网络MN4可以是不同长度和相位的传输线。例如，作为示例而非限定，第一匹配网络MN1和第二匹配网络MN2的相位均为90°，以使得PA1和PA2形成Doherty放大器合路的峰值功率管对。第三匹配网络MN3和第四匹配网络MN4的相位分别为192°和168°，以使得PA3和PA4形成Chireix功率管对。第三匹配网络MN3的传输线的电长度为L3，第四匹配网络MN4的传输线的电长度为L4。L3、L4以及第一放大器PA1-第四放大器PA4的最大功率输出能力可以共同用于确定功率放大器电路50的回退高效率点的位置。
图14是本申请又一实施例的功率放大器电路50的功放效率与回退功率之间的关系示意图。由图14可见，功率放大器电路50也在效率曲线中引入了三个回退高效率点。其中，第一个回退高效率点的位置约为-13dB左右，第二个回退高效率点的位置约为-6.5dB左右，第三个回退高效率点的位置为0dB。并且功率回退范围在6.5dB-13dB之间时，功率放大器电路50都维持着较高的效率，约76％以上。功率回退范围在0dB-6.5dB之间，功率放大器电路50的效率也在70％以上。与图2所示的传统的Chireix功率放大器电路相比，提高了功率放大器在功率回退范围较大时的效率，并且改善了“效率凹陷区”的情况。
图15是本申请又一实施例的功率放大器电路在不同输出功率时的阻抗的示意图。图15中的曲线1和曲线2分别示出了功率放大器电路50的第三放大器PA3和第四放大器PA4的阻抗。在图15中，曲线1和曲线2的三个交点分别对应功率放大器电路50的三个回退高效率点。从图15可见，第一回退高效率点到第三回退高效率点之间，负载阻抗从12.5Ω左右变化到100Ω左右。可以理解为，随着功率放大器电路50的输出功率的增加，负载阻抗从100Ω下降至12.5Ω。因此，与图4相比，功率放大器电路50的负载阻抗相对于传统的Chireix功率放大器电路更低，更容易实现大功率的宽带功率放大器。
作为一个具体示例，图16是本申请又一实施例的功率放大器电路60的结构示意图。如图16所示，第一匹配网络MN1和第二匹配网络MN2的配置使得所述第一放大器PA1和第二放大器PA2组成第一Chireix功率管对P1，所述第三匹配网络MN3和所述第四匹配网络MN4的配置使得第三放大器PA3和第四放大器PA4组成第二Chireix功率管对P2，所述第一耦合线M1和所述第二耦合线M2的配置使得所述第一Chireix功率管对P1和第二Chireix功率管对P2组成Chireix放大器合路。其中，第一匹配网络MN1～第四匹配网络MN4可以是不同长度和相位的传输线。例如，作为示例而非限定，第一匹配网络MN1和第二匹配网络MN2的相位分别为60和120°，以使得PA1和PA2形成Chireix功率管对。类似地，第三匹配网络MN3和第四匹配网络MN4的相位分别为60和120°，以使得PA3和PA4形成Chireix功率管对。第一耦合线M1的长度为L1，第二耦合线M2的长度为L2。Z odd用于表示耦合线的奇模阻抗，Z even表示耦合线的偶模阻抗。
上述图6、图13、图16所示的功率放大器电路的结构仅作为示例。可选地，在满足对图5中的功率放大器电路30的描述的情况下，本申请实施例中的功率放大器还可以采用其他方式形成功率放大器电路。例如，在一个具体示例中，第一匹配网络MN1和第二匹配网络MN2的配置使得第一放大器PA1和第二放大器PA2组成第一Doherty功率管对，第三匹配网络MN3和第四匹配网络MN4的配置使得第三放大器PA3和第四放大器PA4组成第二Doherty功率管对，第一耦合线M1和第二耦合线M2的配置使得第一Doherty功率管对P1和第二Doherty功率管对P2组成Doherty放大器合路。
在本申请实施例中提出的功率放大器电路的方案中，相比于传统的功率放大器电路，可以在功率回退范围增大的情况下，获得更高的效率。并且在第一个回退高效率点时，功率放大器电路的负载牵引比更低，因此更适合高效率的功率放大器。
本申请实施例提出的功率放大器电路的方案中，第一合路至第二合路的功率是串联合路的关系，因此负载阻抗在通过耦合线组成的合路网络之后，呈现给各支路的阻抗变低了，因此，本申请实施例中提出的功率放大器电路更容易实现大功率、大宽带的功率放大器。
可选地，在图5、图6、图13、图16所示的功率放大器电路或者其他功率放大器电路的基础上，本申请实施例中的功率放大器电路还可以包括更多个支路。
图17是本申请又一实施例的功率放大器电路80的结构示意图。如图17所示，所述功率放大器电路80还可以包括2N个支路，N为大于0的整数。
其中，第2i+3支路A(2i+3)包括级联的第2i+3放大器PA(2i+3)和第2i+3匹配网络MN(2i+3)，所述第2i+3支路的第一端为所述第2i+3放大器的信号输入端，所述2i+3支路的第二端与第i+2耦合线M(i+2)的第一输入端相连，i＝1，2…,N。
第2i+4支路A(2i+4)，包括级联的第2i+4放大器PA(2i+4)和第2i+4匹配网络MN(2i+4)，所述第2i+4支路A(2i+4)的第一端为所述第2i+4放大器PA(2i+4)的信号输入端，所述2i+4支路A(2i+4)的第二端与第i+2耦合线M(i+2)的第二输入端相连，所述第i+2耦合线M(i+2)使得所述第2i+3支路A(2i+3)和所述第2i+4支路A(2i+4)形成第i+2合路。
所述第(i+2)耦合线M(i+2)的第一输出端与第(i+1)耦合线M(i+1)的第二输出端相连，使得所述第一合路至第i+2合路形成串联合路。从而所述第一合路至第N+2合路形成了串联合路。
可选地，第N+2耦合线M(N+2)的第二输出端可以接相应的匹配网络MN。
在本申请实施例中，相比于传统的功率放大器电路，功率放大器电路可以在功率回退范围增大的情况下，获得更高的效率。进一步地，还具有更小的负载牵引比和更小的阻抗，因此能够实现大功率、宽带宽的功率放大器。
在本申请实施例中，相比于传统的功率放大器电路，功率放大器电路可以在功率回退范围增大的情况下，获得更高的效率。进一步地，还具有更小的负载牵引比和更小的阻抗，因此能够实现大功率、宽带宽的功率放大器。
本申请实施例提出的功率放大器电路的方案中，第一合路到第N+2合路的功率是串联合路的关系，因此负载阻抗在通过耦合线组成的合路网络之后，呈现给各支路的阻抗变低了，因此，本申请实施例中提出的功率放大器电路更容易实现大功率、大宽带的功率放大器。
可选地，在本申请实施例中的各耦合线，例如第一耦合线M1或第二耦合线M2可以是四端口的耦合线。上述四个端口可以分别包括第一输入端IN1、第二输入端IN2、第一输出端OUT1和第二输出端OUT2。作为示例，图18中的(1)-(8)示出了本申请实施例中使用的耦合线的不同形式的结构示意图。
在图18的(1)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，第一微带线W1的两端分别为第一输入端IN1和第一输出端OUT1，第二微带线W2的两端分别为第二输入端IN2和第二输出端OUT2。
在图18的(2)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2。 第一微带线W1的两端分别为第一输入端IN1和第二输入端IN2，第二微带线W2的两端分别为第二输出端OUT1和第二输出端OUT2。
在图18的(3)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第一微带线W1的第一端和第二端分别为第一输入端口IN1和第一输出端口OUT1。所述第三微带线W3的第一端为第二输入端口IN2，所述第四微带线W4的第二端为第二输出端口OUT2，所述第二微带线W2的第二端与所述第三微带线W3的第二端相连，所述第二微带线W2的第一端和所述第四微带线W4的第一端分别连接对应的匹配网络MN。
在图18的(4)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第一微带线W1的第一端和第二端分别为第一输入端口IN1和第一输出端口OUT1。所述第四微带线W4的第一端和第二端分别为第二输入端口IN2和第二输出端口OUT2。所述第二微带线W2的第二端与所述第三微带线W3的第二端相连，所述第二微带线W2的第一端和所述第三微带线W3的第一端分别连接对应的匹配网络MN。
在图18的(5)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第二微带线W2的第一端为第一输入端口IN1，所述第一微带线W1的第二端为第一输出端口OUT1。所述第三微带线W3的第一端为第二输入端口IN2,所述第四微带线W4的第二端为第二输出端口OUT2。所述第二微带线W2的第二端与所述第三微带线W3的第二端相连，所述第一微带线W1的第一端和所述第四微带线W4的第一端分别连接对应的匹配网络MN。
在图18的(6)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第一微带线W1的第一端为第一输入端口IN1，所述第四微带线W4的第二端为第二输入端口IN2。所述第二微带线W2的第一端为第一输出端口OUT1,所述第三微带线W3的第二端为第二输出端口OUT2。所述第二微带线W2的第二端与所述第三微带线W3的第一端相连，所述第一微带线W1的第二端和所述第四微带线W4的第一端分别连接对应的匹配网络MN。
在图18的(7)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第一微带线W1的第二端为第一输入端口IN1，所述第四微带线W4的第一端为第二输入端口IN2。所述第二微带线W2的第一端为第一输出端口OUT1,所述第三微带线W3的第二端为第二输出端口OUT2。所述第二微带线W2的第二端与所述第三微带线W3的第一端相连，所述第一微带线W1的第一端和所述第四微带线W4的第二端分别连接对应的匹配网络MN。
在图18的(8)中，耦合线可以包括相互耦合的第一微带线W1和第二微带线W2，以及相互耦合的第三微带线W3和第四微带线W4。所述第一微带线W1的第一端为第一输入端口IN1，所述第四微带线W4的第一端为第二输入端口IN2。所述第二微带线W2的第一端为第一输出端口OUT1,所述第三微带线W3的第二端为第二输出端口OUT2。所述第二微带线W2的第二端与所述第三微带线W3的第一端相连，所述第一微带线W1的第二端和所述第四微带线W4的第二端分别连接对应的匹配网络MN。
可选地，图18的(1)-(8)中的微带线也可以被电感、电容或电阻等集总元件替代。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (9)

  1. 一种功率放大器电路，其特征在于，包括：
    第一支路，包括级联的第一放大器和第一匹配网络，所述第一支路的第一端为所述第一放大器的信号输入端，所述第一支路的第二端与第一耦合线的第一输入端相连；
    第二支路，包括级联的第二放大器和第二匹配网络，所述第二支路的第一端为所述第二放大器的信号输入端，所述第二支路的第二端与所述第一耦合线的第二输入端相连，所述第一耦合线使得所述第一支路和第二支路形成第一合路；
    第三支路，包括级联的第三放大器和第三匹配网络，所述第三支路的第一端为所述第三放大器的信号输入端，所述第三支路的第二端与第二耦合线的第一输入端相连；
    第四支路，包括级联的第四放大器和第四匹配网络，所述第四支路的第一端为所述第四放大器的信号输入端，所述第四支路的第二端与所述第二耦合线的第二输入端相连，所述第二耦合线使得所述第三支路和第四支路形成第二合路；
    所述第一耦合线的第一输出端为所述电路的信号输出端，所述第一耦合线的第二输出端与所述第二耦合线的第一输出端相连，使得所述第一合路和所述第二合路形成串联合路。
  2. 如权利要求1所述的电路，其特征在于，所述电路还包括2N个支路，N为大于0的整数，其中，
    第2i+3支路，包括级联的第2i+3放大器和第2i+3匹配网络，所述第2i+3支路的第一端为所述第2i+3放大器的信号输入端，所述2i+3支路的第二端与第i+2耦合线的第一输入端相连，i＝1，2…,N；
    第2i+4支路，包括级联的第2i+4放大器和第2i+4匹配网络，所述第2i+4支路的第一端为所述第2i+4放大器的信号输入端，所述2i+4支路的第二端与第i+2耦合线的第二输入端相连，所述第i+2耦合线使得所述第2i+3支路和所述第2i+4支路形成第i+2合路；
    所述第i+2耦合线的第一输出端与第i+1耦合线的第二输出端相连，使得所述第一合路至所述第i+2合路形成串联合路。
  3. 如权利要求1或2所述的电路，其特征在于，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一多赫蒂功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二多赫蒂功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一多赫蒂功率管对和所述第二多赫蒂功率管对组成希雷放大器合路。
  4. 如权利要求3所述的电路，其特征在于，所述第一耦合线的电长度和所述第二耦合线的电长度用于确定所述希雷放大器合路的第一个回退高效率点。
  5. 如权利要求1或2所述的电路，其特征在于，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和第二放大器组成峰值功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成希雷功率管对，所述第一耦合线和所述第二耦合线的配置使得所述希雷功率管对和所述峰值功率管对组成多赫蒂放大器合路。
  6. 如权利要求1或2所述的电路，其特征在于，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一希雷功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二希雷功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一希雷功率管对和所述第二希雷功率管对组成希雷放大器合路。
  7. 如权利要求1或2所述的电路，其特征在于，所述第一匹配网络和所述第二匹配网络的配置使得所述第一放大器和所述第二放大器组成第一多赫蒂功率管对，所述第三匹配网络和所述第四匹配网络的配置使得所述第三放大器和所述第四放大器组成第二多赫蒂功率管对，所述第一耦合线和所述第二耦合线的配置使得所述第一多赫蒂功率管对和所述第二多赫蒂功率管对组成多赫蒂放大器合路。
  8. 一种集成电路，其特征在于，包括如权利要求1至7中任一项所述的功率放大器电路。
  9. 一种芯片系统，其特征在于，包括如权利要求1至7中任一项所述的功率放大器电路。
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