WO2020103774A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置

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Publication number
WO2020103774A1
WO2020103774A1 PCT/CN2019/118940 CN2019118940W WO2020103774A1 WO 2020103774 A1 WO2020103774 A1 WO 2020103774A1 CN 2019118940 W CN2019118940 W CN 2019118940W WO 2020103774 A1 WO2020103774 A1 WO 2020103774A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
electrodes
comb
pixel regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/118940
Other languages
English (en)
French (fr)
Inventor
宋文华
石博
颜莎宁
陈仕琦
王立苗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/763,565 priority Critical patent/US11215890B2/en
Publication of WO2020103774A1 publication Critical patent/WO2020103774A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display device.
  • the display panel usually includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the two substrates.
  • a pixel electrode and a common electrode may be provided on the array substrate, and the pixel electrode and the common electrode may form an electric field to control the deflection direction of the liquid crystal in the liquid crystal layer, thereby achieving the display function.
  • An array substrate in the related art includes a base substrate having a plurality of sub-pixel areas on the base substrate, and the sub-pixel areas are arranged on the base substrate in a row-column arrangement, on the left side of any sub-pixel area Each is provided with a data line corresponding to any one of the sub-pixel areas, and the data line is used to input electrical signals to other circuit structures in the sub-pixel area.
  • a pixel electrode and a common electrode are provided on each sub-pixel area.
  • the embodiments of the present disclosure provide an array substrate, a display panel, and a display device.
  • the technical solution is as follows:
  • an array substrate includes: a substrate substrate having a plurality of sub-pixel regions on the substrate substrate, the plurality of sub-pixel regions having multiple rows and columns on the substrate substrate Arrangement
  • each of the data lines corresponds to at least one sub-pixel area in any row of the sub-pixel areas, and any row of the sub-pixel areas Including a plurality of pairs of sub-pixel regions, each pair of sub-pixel regions includes two adjacent sub-pixel regions, and any two pairs of sub-pixel regions include sub-pixel regions that are different, and the two sub-pixel regions correspond The two data lines are located on different sides of the two sub-pixel regions in the row direction;
  • the common electrode and the plurality of pixel electrodes are located on the base substrate.
  • the plurality of pixel electrodes correspond one-to-one with the plurality of sub-pixel regions, and the orthographic projection of each pixel electrode on the base substrate is located in the sub-pixel region corresponding to each pixel electrode ,
  • the minimum distance between two pixel electrodes corresponding to the two sub-pixel regions is greater than or equal to a first specified distance, and the first specified distance is a minimum distance that the two pixel electrodes will not affect each other.
  • the common electrode includes a plurality of comb-shaped sub-electrodes, and the plurality of comb-shaped sub-electrodes correspond one-to-one to the plurality of sub-pixel regions, and the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions
  • the orthographic projection on the base substrate overlaps with the area between the two sub-pixel areas.
  • each of the comb-shaped sub-electrodes includes a plurality of mutually parallel strip-shaped structures, and the strip-shaped structures in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions form a first designated angle, the first A specified angle is greater than 90 degrees and less than 180 degrees.
  • each of the comb-shaped sub-electrodes includes two sets of strip-shaped structures, each set of strip-shaped structures includes a plurality of strip-shaped structures parallel to each other, and two comb-shaped elements corresponding to the two sub-pixel regions
  • the strip structures of the four strip structures in the electrode are arranged in an x-shape.
  • an orthographic projection of any comb-shaped sub-electrode on the base substrate of the plurality of comb-shaped sub-electrodes overlaps with a sub-pixel region corresponding to any comb-shaped sub-electrode.
  • the two comb-shaped sub-electrodes are electrically connected.
  • the distance between two data lines between any two adjacent pairs of the sub-pixel regions is greater than or equal to a second specified distance, and the second specified The distance is the minimum distance that the two data lines will not affect each other.
  • the distance between the two pixel electrodes on both sides of the two data lines is greater than or equal to a third specified distance, where the third specified distance is the second specified distance and the distance between the two data lines The sum of the width and twice the fourth specified distance, the fourth specified distance being the minimum distance that the pixel electrode on the base substrate and the data line will not affect each other.
  • the plurality of comb-shaped sub-electrodes are all composed of a transparent conductive material.
  • the plurality of pixel electrodes correspond one-to-one with the plurality of sub-pixel regions, and the orthographic projection of each pixel electrode on the base substrate is located in the sub-pixel region corresponding to each pixel electrode ,
  • the minimum distance between the two pixel electrodes corresponding to the two sub-pixel regions is greater than or equal to a first specified distance, and the first specified distance is the minimum distance that the two pixel electrodes will not affect each other;
  • the common electrode includes a plurality of comb-shaped sub-electrodes, and the plurality of comb-shaped sub-electrodes correspond one-to-one with the plurality of sub-pixel regions, and the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions There is overlap between the orthographic projection and the area between the two sub-pixel areas;
  • Each of the comb-shaped sub-electrodes includes a plurality of parallel strip-shaped structures, and the strip-shaped structures in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions form a first designated angle, and the first designated angle Greater than 90 degrees and less than 180 degrees, the two comb electrodes are electrically connected;
  • the orthographic projection of any comb-shaped sub-electrode on the base substrate overlaps with the sub-pixel area corresponding to the comb-shaped sub-electrode.
  • the display panel includes a color filter substrate, a liquid crystal layer, and the above-mentioned array substrate.
  • the array substrate includes a substrate substrate, and the substrate substrate has a plurality of sub-pixel regions. Multiple sub-pixel regions are arranged on the base substrate in multiple rows and multiple columns; multiple data lines, the multiple data lines are located on the base substrate, and each of the data lines is in any column At least one sub-pixel area in the sub-pixel area corresponds to, any row of the sub-pixel area includes multiple pairs of sub-pixel areas, each pair of sub-pixel areas includes two adjacent sub-pixel areas, and any two sub-pixel areas The sub-pixel regions are different from the sub-pixel regions included.
  • the two data lines corresponding to the two sub-pixel regions are respectively located on different sides of the two sub-pixel regions in the row direction; the common electrode and the plurality of pixel electrodes are located at On the base substrate.
  • the plurality of pixel electrodes correspond one-to-one with the plurality of sub-pixel regions, and the orthographic projection of each pixel electrode on the base substrate is located in the sub-pixel region corresponding to each pixel electrode ,
  • the color filter substrate has a first black matrix, and the orthographic projection of the region between the two pixel electrodes corresponding to the two sub-pixel regions on the base substrate is located on the first black matrix on the substrate Orthographic projection on the base substrate.
  • the color filter substrate has a second black matrix, and the orthographic projection of the area between two pixel electrodes on both sides of any one of the data lines on the base substrate is located on the second black matrix In an orthographic projection on the base substrate.
  • the plurality of pixel electrodes correspond one-to-one with the plurality of sub-pixel regions, and the orthographic projection of each pixel electrode on the base substrate is located in the sub-pixel region corresponding to each pixel electrode ,
  • the minimum distance between the two pixel electrodes corresponding to the two sub-pixel regions is greater than or equal to a first specified distance, and the first specified distance is the minimum distance that the two pixel electrodes will not affect each other;
  • the common electrode includes a plurality of comb-shaped sub-electrodes, and the plurality of comb-shaped sub-electrodes correspond one-to-one with the plurality of sub-pixel regions, and the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions are on the base substrate There is overlap between the orthographic projection and the area between the two sub-pixel areas;
  • Each of the comb-shaped sub-electrodes includes a plurality of parallel strip-shaped structures, and the strip-shaped structures in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions form a first designated angle, and the first designated angle Greater than 90 degrees and less than 180 degrees, the two comb electrodes are electrically connected;
  • the orthographic projection of any comb-shaped sub-electrode on the base substrate overlaps with the sub-pixel area corresponding to the comb-shaped sub-electrode.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate
  • FIG. 2 is a schematic diagram of black hatching of the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an array substrate shown in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a black hatching of the array substrate shown in FIG. 3;
  • FIG. 5 is a side view of the array substrate shown in FIG. 3;
  • FIG. 6 is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • FIG. 10 is another schematic structural diagram of the array substrate shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the brightness of the display panel shown in an embodiment of the present disclosure.
  • FIG. 13 is a partial schematic diagram in the schematic diagram shown in FIG. 12;
  • FIG. 14 is another partial schematic diagram in the schematic diagram shown in FIG. 12;
  • 15 is a trend diagram of the aperture ratio and contrast of the display panel shown in the embodiment of the present disclosure.
  • 16 is a schematic diagram of the aperture ratio and liquid crystal efficiency of a display panel shown in an embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of the contrast of each angle of the display panel shown in the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an array substrate.
  • the array substrate may include a base substrate 11, and the base substrate 11 may have a plurality of sub-pixel regions p, and each sub-pixel region p is provided with its corresponding data line D (the data line corresponding to any sub-pixel region In order to input an electrical signal to the pixel electrode in any one of the sub-pixel regions), each sub-pixel region p may be provided with various electrodes, such as a pixel electrode pe and a common electrode (not shown in FIG. 1).
  • the distance h can be equal to the width of the data line plus twice the anti-interference distance (the anti-interference distance is the minimum distance between the data line and the pixel electrode that does not affect each other.
  • the anti-interference distance can usually be determined by the data
  • the accuracy of the manufacturing process of the line and the pixel electrode is determined, that is, the interference prevention distance can be greater than or equal to the minimum distance that can be achieved by the manufacturing process.
  • the distance can be 3.0 ⁇ m to 3.5 ⁇ m). This may cause a large electric field-free region between the sub-pixel regions of the array substrate in the lateral direction. There may be no electric field in this region, or there may be no electric field that can control the liquid crystal layer.
  • a large black shadow line (English: Black Shadow Line) area between each two horizontal sub-pixel areas, as shown in FIG. 2
  • FIG. 2 It is a schematic structural diagram of an array substrate. The white area is the sub-pixel area, and the black area between the white areas is the black shadow. It can be seen that the black shadow line is wider, which may reduce the viewing angle contrast and transmittance of the display panel side, which seriously affects the display effect of the display panel.
  • the array substrate 10 may include: a base substrate 11 on which a plurality of sub-pixel regions p are provided, and the plurality of sub-pixel regions p are arranged on the base substrate in multiple rows and columns.
  • a plurality of data lines 12, the plurality of data lines 12 are located on the base substrate 11, and each data line 12 corresponds to at least one sub-pixel area p in any column of sub-pixel areas p.
  • Any row of sub-pixel regions p includes multiple pairs of sub-pixel regions, and each sub-pixel region pair includes two adjacent sub-pixel regions p (the two sub-pixel regions p shown in FIG. 3 belong to a pair of sub-pixel regions), and any two A pair of sub-pixel regions are different from each other (that is, any two pairs of sub-pixel regions will not include the same sub-pixel region), and the two data lines 12 corresponding to these two sub-pixel regions p are located in these two sub-pixel regions p Different sides in the row direction (the row direction is the lateral direction shown in FIG.
  • the data line 12 corresponding to the left sub-pixel region p is located on the left side
  • the data line 12 corresponding to the right sub-pixel region p is located on the right side.
  • the common electrode and the plurality of pixel electrodes are located on the base substrate 11.
  • FIG. 4 it is a schematic structural diagram of an array substrate shown in an embodiment of the present disclosure, where the white area is the sub-pixel area, and the black area between the white areas is the black hatching. It can be seen that since there is no data line between the white areas, the black shadow line between the white areas becomes significantly narrower (compared to the array substrate shown in FIG. 2).
  • FIG. 5 which is a cross-sectional view of the array substrate shown in FIG. 3, pixel electrodes 13 and a common electrode 14 are respectively provided in two sub-pixel regions p of the array substrate 11. Two data lines 12 are respectively provided on both sides of the two sub-pixel regions p. It can be seen that the distance between the pixel electrode 13 and the common electrode 14 in two adjacent sub-pixel regions p is relatively short.
  • an array substrate provided by an embodiment of the present disclosure, two data lines corresponding to two adjacent sub-pixel regions in the same row are respectively disposed on different sides of the two sub-pixel regions in the row direction, As a result, there is a structure in which no data lines are provided between two adjacent sub-pixel regions on the base substrate. In this structure, the distance between the pixel electrodes of the two adjacent sub-pixel regions can be closer, and thus an electric field cannot be generated. It will be smaller, so that the display panel made of the array substrate has a higher display effect. The problem of poor display effect of the display panel made of the array substrate in the related art is solved. The display effect of the display panel made of the array substrate is improved.
  • FIG. 6 is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • the array substrate has been adjusted on the basis of the array substrate shown in FIG. 6.
  • the common electrode 14 includes a plurality of comb-shaped sub-electrodes 141, and the plurality of comb-shaped sub-electrodes 141 correspond one-to-one with the plurality of sub-pixel regions p. Any one of the comb-shaped sub-electrodes 141 on the base substrate 11 The area where the orthographic projection is located overlaps with the sub-pixel area p corresponding to any comb-shaped sub-electrode. After the orthographic projection of the base substrate overlaps with the sub-pixel area, the comb-shaped sub-electrode can form a lateral electric field with the pixel electrode in the sub-pixel area to control the liquid crystal layer.
  • the comb-shaped sub-electrode 141 includes a plurality of strip-shaped voids, so that the comb-shaped sub-electrode 141 and the pixel electrode located below it can generate a lateral electric field and control the liquid crystal layer of the display panel.
  • no data line is provided between two adjacent sub-pixel areas p, and the common electrode does not interfere with the data line, so the common electrode can be provided between the two adjacent Above the area between the sub-pixel areas p, that is, the orthographic projection of the two comb-shaped sub-electrodes 141 corresponding to the two sub-pixel areas p of any one sub-pixel area pair on the base substrate 11 (not shown in FIG. 6) (Out) There is overlap with the area between these two sub-pixel areas p.
  • the above structure increases the area of the common electrode, reduces the area of the area where the common electrode is not provided between the sub-pixel areas, and further reduces the area of the electric field-free area between the sub-pixel areas.
  • the data line D is provided between two adjacent sub-pixel areas p
  • the comb-shaped sub-electrodes corresponding to the two adjacent sub-pixel areas p are connected by a trace
  • the trace It will inevitably cross the data line and affect the data line and the comb electrode.
  • the two comb-shaped sub-electrodes 141 can be electrically connected.
  • FIG. 6 shows a structure in which the two comb-shaped sub-electrodes 141 are electrically connected by wiring.
  • the two comb-shaped sub-electrodes 141 may be electrically connected in other ways.
  • FIG. 7 it is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the two comb-shaped sub-electrodes 141 are of an integrated structure.
  • the two comb-shaped sub-electrodes cover the area between their corresponding two sub-pixel areas, further reducing the area of the electric field-free area between the sub-pixel areas .
  • each comb-shaped sub-electrode 141 includes a plurality of parallel strip-shaped structures (that is, black strip-shaped portions in FIG. 7), and the comb-shaped sub-electrode 141 is composed of these strip-shaped structures.
  • the common electrode may include a frame for fixing the strip-shaped structure in the comb-shaped sub-electrode 141.
  • the strip-shaped structure in the two comb-shaped sub-electrodes 141 corresponding to the two sub-pixel regions p in each sub-pixel region pair forms a first designated angle x.
  • the first designated angle may be greater than 90 degrees and less than 180 degrees. In this angle range, the comb-shaped sub-electrode can apply a pretilt angle to the liquid crystal in the display panel to increase the deflection speed of the liquid crystal.
  • the common electrode in the array substrate shown in FIG. 7 is a common electrode with a dual-domain structure provided by an embodiment of the present disclosure, but the common electrode may also have other structures. As shown in FIG. 8, it is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • Each comb-shaped sub-electrode 141 includes two strip-shaped structure sets (the upper half of each comb-shaped sub-electrode 141 in FIG. 8 is a strip-shaped set and the lower half is another strip-shaped set),
  • Each strip structure set includes a plurality of strip structures parallel to each other (that is, the black strip portion in FIG. 8), and the strip structures in the two strip structure sets form a second designated angle y.
  • the second specified included angle y may be greater than 0 degrees and less than 90 degrees.
  • the strip-shaped structures in the four strip-shaped structure sets in the two comb-shaped sub-electrodes 141 corresponding to the two sub-pixel areas p in the sub-pixel area pair are arranged in an x-type arrangement.
  • the common electrode in the array substrate shown in FIG. 8 is a four-domain structure common electrode provided by an embodiment of the present disclosure.
  • FIG. 9 it is a schematic structural diagram of another array substrate shown in an embodiment of the present disclosure.
  • the plurality of pixel electrodes 13 correspond to the plurality of sub-pixel regions p one by one, and the orthographic projection of each pixel electrode 13 on the base substrate 11 is located in the sub-pixel region p corresponding to each pixel electrode 13, which is opposite to the sub-pixel region
  • the minimum distance s1 between the two pixel electrodes 13 corresponding to the two sub-pixel regions p in is greater than or equal to the first specified distance, which is the minimum distance at which the two pixel electrodes 13 will not affect each other.
  • the first specified distance may be the minimum distance between the two pixel electrodes 13 that will not turn on each other.
  • the first specified distance can generally be determined by the accuracy of the manufacturing process of the two pixel electrodes, that is, the first specified distance can be greater than or equal to the minimum distance that can be achieved by the manufacturing process.
  • the distance may be 3.0 microns to 3.5 microns. In this way, the two pixel electrodes will not affect each other. Compared with the distance h between pixel electrodes in two adjacent sub-pixel regions in the array substrate shown in FIG.
  • the distance between pixel electrodes in two adjacent sub-pixel regions in the embodiment of the present disclosure is obvious More recently, this can reduce the area of the non-electric field region between the sub-pixel regions, reduce the black hatching between the sub-pixel regions, and also improve the transmittance of the display panel.
  • the base substrate 11 may have multiple columns of sub-pixel regions, and multiple data lines correspond to the multiple columns of sub-pixel regions, that is, each data line corresponds to a column of sub-pixel regions.
  • two adjacent There may be two data lines between the pair of sub-pixel areas, and the distance s2 between the two data lines 12 is greater than or equal to the second specified distance, which is the minimum that the two data lines 12 will not affect each other. distance. In this way, the data lines arranged together can be prevented from affecting each other.
  • the second specified distance reference may be made to the first specified distance described above, and details are not described herein again.
  • FIG. 10 it is another schematic structural diagram of the array substrate shown in FIG.
  • the distance between the two pixel electrodes 13 on both sides of the two data lines 12 is greater than or equal to the third specified distance
  • the third specified distance is the second specified distance and the width of the two data lines 12 (that is, the two data lines The sum of the width of 12) and the twice the sum of the fourth specified distance s3, which is the minimum distance at which the pixel electrode on the base substrate and the data line will not affect each other.
  • the plurality of comb-shaped sub-electrodes 141 are all made of a transparent conductive material, so that the transmittance of the array substrate can be improved.
  • the transparent conductive material may include indium tin oxide (English: Indium tin oxide; ITO for short).
  • an array substrate provided by an embodiment of the present disclosure may further include structures such as a gate metal, a source metal, and various insulating layers. The embodiments of the present disclosure will not be repeated here.
  • the array substrate provided by the embodiment of the present disclosure can be applied to an advanced super-dimensional field conversion (English: Advanced Super Dimension Switch; abbreviation: ADS) display panel or a fringe field switching type (English: Fringe Field Switching; abbreviation: FFS) display panel.
  • ADS Advanced Super Dimension Switch
  • FFS Fringe Field Switching
  • an array substrate provided by an embodiment of the present disclosure, two data lines corresponding to two adjacent sub-pixel regions in the same row are respectively disposed on different sides of the two sub-pixel regions in the row direction, As a result, there is a structure in which no data lines are provided between two adjacent sub-pixel regions on the base substrate. In this structure, the distance between the pixel electrodes of the two adjacent sub-pixel regions can be closer, and thus an electric field cannot be generated. It will be smaller, so that the display panel made of the array substrate has a higher display effect. The problem of poor display effect of the display panel made of the array substrate in the related art is solved. The display effect of the display panel made of the array substrate is improved.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include a color filter substrate 20, a liquid crystal layer 30, and any array substrate 10 provided by the foregoing embodiment.
  • the plurality of pixel electrodes 13 correspond to the plurality of sub-pixel regions p
  • the orthographic projection of each pixel electrode 13 on the base substrate 11 is located in the sub-pixel region p corresponding to each pixel electrode 13 and corresponds to the sub-pixel
  • the minimum distance s1 between the two pixel electrodes 13 corresponding to the two sub-pixel regions p in the area pair is greater than or equal to the first specified distance, which is the minimum distance at which the two pixel electrodes will not affect each other.
  • the color filter substrate 20 has a first black matrix 21, and the orthographic projection of the area between the two pixel electrodes 13 (the data lines are not provided between the two pixel electrodes 13) on the base substrate 11 is located on the first black matrix 21 is in the orthographic projection on the base substrate 11. That is, the first black matrix can just block the area between the two pixel electrodes 13 and prevent the light emitted by the adjacent sub-pixel areas from affecting each other.
  • the width of the first black matrix and the width of the area between the two pixel electrodes 13 are positively correlated.
  • the minimum width of the first black matrix may be a width that can avoid cross-color and light leakage of adjacent sub-pixel areas.
  • the color filter substrate may also be provided with a flat layer, spacers, and indium tin oxide that shields the electric field. The embodiments of the present disclosure will not be repeated here.
  • the distance between two adjacent pixel electrodes (refer to the distance h shown in FIG. 1) is large, it is used to block between two sub-pixel regions
  • the black matrix of the area will also be wider, resulting in a wider black shadow between the sub-pixel areas, which in turn leads to a lower white state brightness of the display panel.
  • the display panel provided by the embodiments of the present disclosure due to the small black-shielding area of the black matrix, the brightness of the white state of the display panel is higher, the brightness of the black state is lower, and the contrast is higher, and the overall display effect is better.
  • the array substrate in the display panel is the array substrate shown in FIG. 7
  • optical simulation through software shows that the white brightness of the display panel increases by 5%
  • the dark state brightness decreases by 5%
  • the contrast increases by 10%
  • the array substrate in the display panel is the array substrate shown in FIG. 8
  • the black brightness of the display surface provided by the embodiment of the present disclosure decreases by 3%
  • the white brightness increases by 2.8%
  • the contrast increases by 6.5%.
  • a second black matrix 22 is further provided on the color filter substrate 20, and the orthographic projection of the area between the two pixel electrodes 13 on both sides of any one data line 12 on the base substrate 11 is located on the second black matrix 22 is in the orthographic projection on the base substrate 11. That is, the second black matrix 22 can block the area between the two pixel electrodes 13.
  • the width of the second black matrix 22 is higher than that of the display panel in the related art, the area of the overlapping area of the unshielded area of the black matrix and the pixel electrode is not reduced.
  • the display panel provided by the embodiments of the present disclosure improves the vertical contrast and the side viewing angle contrast of the display panel by reducing the size of the black hatching.
  • FIG. 12 it is a schematic diagram of the brightness of the display panel shown in an embodiment of the present disclosure.
  • the abscissa is the voltage (the voltage is the voltage loaded on the liquid crystal layer), the unit is volts, the ordinate is the relative percentage of brightness, the relative percentage is a display panel (such as the array substrate shown in Figure 1 is made The maximum brightness of the display panel is 100% brightness.
  • curve q1 is a brightness curve diagram of a display panel made of the array substrate shown in FIG. 1; curves q2 and curve q3 are display panels made of the array substrate shown in FIG.
  • curve q2 sets the distance of the pixel electrodes in the adjacent sub-pixel regions of the array substrate shown in FIG. 8 to be the same as the array substrate shown in FIG. 1
  • curve q3 is the case where the distance of the pixel electrode in the adjacent sub-pixel area is set to the first specified distance.
  • Curve q4 and curve q5 are the brightness curves of the display panel made of the array substrate shown in FIG. 7 according to an embodiment of the present disclosure.
  • Curve q4 is to set the distance of the pixel electrode in the adjacent sub-pixel region to be the same as that shown in FIG. 1 The same is true for the array substrate of FIG. 2; and curve q5 is the case where the distance of the pixel electrode in the adjacent sub-pixel area is set to the first specified distance. It can be seen that the maximum brightness shown by curve q5 is significantly higher than that of other display panels, which shows that the maximum brightness has been significantly improved.
  • FIG. 13 it is a graph in the graph shown in FIG. 12, with the abscissa ranging from 0 volts to 0.6 volts (this interval can be regarded as the brightness in the dark state).
  • the brightness of curve q3 and curve q5 are close (for ease of illustration in FIG. 13, curve q5 is made higher than curve q3, but this is not a limitation on curve q5 and curve q3), and the brightness of curve q2 and curve q4 is close to In FIG. 13, for the sake of convenience, curve q2 is higher than curve q4, but this is not a limitation on curve q2 and curve q4).
  • the brightness of curve q1 is about 3% higher than that of curve q3 and curve q5.
  • the brightness is about 5% higher than the curves q2 and q4.
  • the dark state brightness of the display panel provided by the embodiment of the present disclosure is significantly lower than that of the display panel made with the array substrate shown in FIG. 1.
  • FIG. 14 it is a brightness curve in the interval of 6 volts to 6.6 volts (this interval can be regarded as the maximum luminance interval) in the graph shown in FIG. 12.
  • the brightness of curve q2 is about 3% higher than curve q1
  • the brightness of curve q3 is about 2.5% higher than curve q1
  • the brightness of curve q5 is about 8% higher than curve q1
  • the brightness of curve q4 is The curve q1 is about 5% higher.
  • the maximum brightness of the display panel provided by the embodiments of the present disclosure is significantly higher than the maximum brightness of the display panel made of the array substrate shown in FIG. 1.
  • FIG. 15 it is a trend graph of the aperture ratio and contrast of the display panel corresponding to each curve in the graph shown in FIG.
  • the abscissa indicates the curve corresponding to each display panel, and the ordinate on the left is the contrast (English: Contrast Ratio).
  • the contrast is based on the contrast of the display panel corresponding to the curve q1 being 100%.
  • the ordinate on the right is the aperture ratio (English: Aperture Ratio) (the aperture ratio is the actual value).
  • the black circle symbol represents the aperture ratio, and the black square symbol represents contrast.
  • the aperture ratio of the display panel corresponding to the curve q1 is approximately between 65% and 66%, and the contrast ratio is 100%. It can be seen that the contrast of the display panel provided by the embodiments of the present disclosure is significantly higher than that of the display panel made of the array substrate shown in FIG. 1.
  • FIG. 16 it is a trend diagram of the aperture ratio and liquid crystal efficiency (English: liquid crystal efficiency) of the display panel corresponding to each curve in the graphs shown in FIG.
  • the abscissa indicates the curve corresponding to each display panel.
  • the ordinate on the left is the liquid crystal efficiency.
  • the liquid crystal efficiency is a parameter used to indicate the deflection ability of the liquid crystal layer for light. The higher the liquid crystal efficiency, the liquid crystal deflection of light The stronger the ability.
  • the ordinate on the right is the aperture ratio (the aperture ratio is the actual value).
  • the black circle symbol represents the aperture ratio, and the height of the rectangular frame represents the liquid crystal efficiency. It can be seen that the liquid crystal efficiency of the display panel made of the array substrate shown in FIG.
  • liquid crystal efficiency represented by curve q1 is between 80% and 82%, while the liquid crystal efficiency of the display panel provided by the embodiments of the present disclosure All are above 85%, which is significantly higher than the liquid crystal efficiency of the display panel made of the array substrate shown in FIG.
  • FIG. 17 is a schematic diagram of the contrast of each angle of the display panel corresponding to the curves q1, q4, and q5 in the graph shown in FIG. 12.
  • the interior of the circular chart is divided into multiple areas by multiple solid lines, and the closer the area is, the higher the contrast represented.
  • the outer edge of the circle chart indicates the angle of the orthographic projection of the sight line on the display surface of the display panel and an edge of the display panel.
  • the dotted circle inside indicates the angle of the sight line and the display surface of the display panel. 20 degrees, 40 degrees and 60 degrees.
  • the rectangular frame k represents the requirement for the contrast of the display panel.
  • the performance of the display panel provided by the embodiments of the present disclosure is superior to the display panel made of the array substrate shown in FIG. 1 in various aspects.
  • a display panel provided by an embodiment of the present disclosure includes an array substrate.
  • an array substrate By arranging two data lines corresponding to two adjacent sub-pixel regions in the same row in the two sub-pixel regions in the row direction
  • the distance between the pixel electrodes of the two adjacent sub-pixel regions can be closer, which makes it impossible
  • the area where the electric field is generated will be smaller, so that the display panel made of the array substrate has a higher display effect.
  • the problem of poor display effect of the display panel in the related art is solved. Improve the display effect of the display panel.

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Abstract

一种阵列基板（10）、显示面板和显示装置。该阵列基板（10）包括：通过将同一行且相邻的两个子像素区域（p）对应的两条数据线（12），分别设置在这两个子像素区域（p）在行向上的不同侧，使得衬底基板（11）上存在相邻的两个子像素区域（p）之间未设置数据线（12）的结构，这相邻的两个子像素区域（p）的像素电极（pe）的距离就可以较近，进而无法产生电场的区域就会较小，使得该阵列基板（10）制成的显示面板的显示效果较高。解决了相关技术中显示面板的显示效果较差的问题。提高了阵列基板（10）制成的显示面板的显示效果。

Description

阵列基板、显示面板和显示装置
本申请要求于2018年11月19日提交的申请号为201811376215.8、公开名称为“阵列基板、显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板、显示面板和显示装置。
背景技术
显示面板通常包括阵列基板、彩膜基板以及设置在这两块基板之间的液晶层。其中的阵列基板上可以设置有像素电极以及公共电极，该像素电极可以和公共电极形成电场，以控制液晶层中液晶的偏转方向，进而实现显示功能。
相关技术中的一种阵列基板包括衬底基板，该衬底基板上具有多个子像素区域，这些子像素区域以行列排布的方式在衬底基板上排布，任一子像素区域的左侧均设置有与该任一子像素区域对应的数据线，该数据线用于向该子像素区域中的其他电路结构输入电信号。每个子像素区域上设置有像素电极和公共电极。
发明内容
本公开实施例提供了一种阵列基板、显示面板和显示装置。所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：衬底基板，所述衬底基板上具有多个子像素区域，所述多个子像素区域在所述衬底基板上以多行多列的方式排布；
多条数据线，所述多条数据线位于所述衬底基板上，每条所述数据线均与任意一列所述子像素区域中的至少一个子像素区域对应，任意一行所述子像素区域包括多个子像素区域对，每个所述子像素区域对包括相邻的两个子像素区域，且任意两个所述子像素区域对包括的子像素区域均不相同，所述两个子像素区域对应的两条数据线分别位于所述两个子像素区域在行向上的不同侧；
公共电极和多个像素电极，位于所述衬底基板上。
可选地，所述多个像素电极与所述多个子像素区域一一对应，且每个所述像素电极在所述衬底基板的正投影位于每个所述像素电极对应的子像素区域中，与所述两个子像素区域对应的两个像素电极之间的最小距离大于或等于第一指定距离，所述第一指定距离为所述两个像素电极互相不会影响的最小距离。
可选地，所述公共电极包括多个梳状子电极，所述多个梳状子电极与所述多个子像素区域一一对应，所述两个子像素区域对应的两个梳状子电极在所述衬底基板上的正投影与所述两个子像素区域之间的区域存在重叠。
可选地，每个所述梳状子电极均包括多个互相平行的条状结构，所述两个子像素区域对应的两个梳状子电极中的条状结构成第一指定夹角，所述第一指定夹角大于90度且小于180度。
可选地，每个所述梳状子电极均包括两个条状结构集合，每个所述条状结构集合包括多个互相平行的条状结构，所述两个子像素区域对应的两个梳状子电极中的四个条状结构集合的条状结构成x型排列。
可选地，所述多个梳状子电极中任一梳状子电极在所述衬底基板上的正投影与所述任一梳状子电极对应的子像素区域存在重叠。
可选地，所述两个梳状子电极电连接。
可选地，任意一行所述子像素区域中，位于任意两个相邻的所述子像素区域对之间的两条数据线之间的距离大于或等于第二指定距离，所述第二指定距离为所述两条数据线互相不会影响的最小距离。
可选地，所述两条数据线两侧的两个像素电极之间的距离大于或等于第三指定距离，所述第三指定距离为所述第二指定距离、所述两条数据线的宽度以及2倍的第四指定距离的和，所述第四指定距离为所述衬底基板上的像素电极与数据线互相不会影响的最小距离。
可选地，所述多个梳状子电极均由透明导电材料构成。
可选地，所述多个像素电极与所述多个子像素区域一一对应，且每个所述像素电极在所述衬底基板的正投影位于每个所述像素电极对应的子像素区域中，与所述两个子像素区域对应的两个像素电极之间的最小距离大于或等于第一指定距离，所述第一指定距离为所述两个像素电极互相不会影响的最小距离；
所述公共电极包括多个梳状子电极，所述多个梳状子电极与所述多个子像素区域一一对应，所述两个子像素区域对应的两个梳状子电极在所述衬底基板 上的正投影与所述两个子像素区域之间的区域存在重叠；
每个所述梳状子电极均包括多个互相平行的条状结构，所述两个子像素区域对应的两个梳状子电极中的条状结构成第一指定夹角，所述第一指定夹角大于90度且小于180度，所述两个梳状子电极电连接；
所述多个梳状子电极中任一梳状子电极在所述衬底基板上的正投影与所述任一梳状子电极对应的子像素区域存在重叠。
另一方面，提供一种显示面板，所述显示面板包括彩膜基板、液晶层以及上述的阵列基板，所述阵列基板包括衬底基板，所述衬底基板上具有多个子像素区域，所述多个子像素区域在所述衬底基板上以多行多列的方式排布；多条数据线，所述多条数据线位于所述衬底基板上，每条所述数据线均与任意一列所述子像素区域中的至少一个子像素区域对应，任意一行所述子像素区域包括多个子像素区域对，每个所述子像素区域对包括相邻的两个子像素区域，且任意两个所述子像素区域对包括的子像素区域均不相同，所述两个子像素区域对应的两条数据线分别位于所述两个子像素区域在行向上的不同侧；公共电极和多个像素电极，位于所述衬底基板上。
可选地，所述多个像素电极与所述多个子像素区域一一对应，且每个所述像素电极在所述衬底基板的正投影位于每个所述像素电极对应的子像素区域中，所述彩膜基板上具有第一黑矩阵，所述两个子像素区域对应的两个像素电极之间的区域在所述衬底基板上的正投影位于所述第一黑矩阵在所述衬底基板上的正投影中。
可选地，所述彩膜基板上具有第二黑矩阵，任意一条所述数据线两侧的两个像素电极之间的区域在所述衬底基板上的正投影位于所述第二黑矩阵在所述衬底基板上的正投影中。
可选地，所述多个像素电极与所述多个子像素区域一一对应，且每个所述像素电极在所述衬底基板的正投影位于每个所述像素电极对应的子像素区域中，与所述两个子像素区域对应的两个像素电极之间的最小距离大于或等于第一指定距离，所述第一指定距离为所述两个像素电极互相不会影响的最小距离；
所述公共电极包括多个梳状子电极，所述多个梳状子电极与所述多个子像素区域一一对应，所述两个子像素区域对应的两个梳状子电极在所述衬底基板上的正投影与所述两个子像素区域之间的区域存在重叠；
每个所述梳状子电极均包括多个互相平行的条状结构，所述两个子像素区 域对应的两个梳状子电极中的条状结构成第一指定夹角，所述第一指定夹角大于90度且小于180度，所述两个梳状子电极电连接；
所述多个梳状子电极中任一梳状子电极在所述衬底基板上的正投影与所述任一梳状子电极对应的子像素区域存在重叠。
另一方面，提供一种显示装置，所述显示装置包括上述的显示面板。
附图说明
图1是一种阵列基板的结构示意图；
图2是图1所示的阵列基板的黑影线示意图；
图3是本公开实施例示出的一种阵列基板的结构示意图；
图4是图3所示的阵列基板的黑影线示意图；
图5是图3所示的阵列基板的侧视图；
图6是本公开实施例示出的另一种阵列基板的结构示意图；
图7是本公开实施例示出的另一种阵列基板的结构示意图；
图8是本公开实施例示出的另一种阵列基板的结构示意图；
图9是本公开实施例示出的另一种阵列基板的结构示意图；
图10是图9所示的阵列基板的另一种结构示意图；
图11是本公开实施例提供的一种显示面板的结构示意图；
图12是本公开实施例示出的显示面板的亮度示意图；
图13是图12所示的示意图中的一种部分示意图；
图14是图12所示的示意图中的另一种部分示意图；
图15是本公开实施例示出的显示面板的开口率和对比度的趋势图；
图16是本公开实施例示出的显示面板的开口率和液晶效率的示意图；
图17是本公开实施例示出的显示面板的各角度对比度示意图。
具体实施方式
下面将结合附图对本公开实施方式进行描述。
图1是一种阵列基板的结构示意图。该阵列基板可以包括衬底基板11，衬底基板11上可以具有多个子像素区域p，每个子像素区域p的左侧设置有其对应的数据线D(任意一个子像素区域对应的数据线用于向该任意一个子像素区域中的像素电极输入电信号)，每个子像素区域p中可以设置有各种电极，如像 素电极pe和公共电极(图1未示出)等。
为了避免数据线与电极过近导致互相影响，数据线两侧均存在未设置电极(例如像素电极和公共电极)的区域，数据线两侧的子像素区域中的像素电极pe之间的距离h也会较远，该距离h可以等于数据线的宽度加上两倍的防干扰距离(防干扰距离为数据线和像素电极之间不会互相影响的最小距离，该防干扰距离通常可以由数据线和像素电极的制造工艺的精度来决定，即该防干扰距离可以大于或等于制造工艺所能实现的最小距离。示例性的，该距离可以为3.0微米至3.5微米)。这会导致阵列基板在横向上的子像素区域之间会存在较大的无电场区域，该区域可能不存在电场，或不存在能够对液晶层进行控制的电场。进而导致该阵列基板制成的显示面板中，每两个横向的子像素区域之间会存在较大的无法进行显示的黑影线(英文：Black shadow Line)区域，如图2所示，其为一种阵列基板的结构示意图。其中的白色区域即为子像素区域，而白色区域之间的黑色区域即为黑影线。可以看出黑影线较宽，这可能会降低显示面板侧视角对比度以及透过率，严重影响了显示面板的显示效果。
图3是本公开实施例示出的一种阵列基板的结构示意图。该阵列基板10可以包括：衬底基板11，衬底基板11上设置有多个子像素区域p，多个子像素区域p在衬底基板上以多行多列的方式排布。
多条数据线12，多条数据线12位于衬底基板11上，每条数据线12均与任意一列子像素区域p中的至少一个子像素区域p对应。任意一行子像素区域p包括多个子像素区域对，每个子像素区域对包括相邻的两个子像素区域p(图3所示的两个子像素区域p即属于一个子像素区域对)，且任意两个子像素区域对包括的子像素区域均不相同(即任意两个子像素区域对不会包括同一个子像素区域)，这两个子像素区域p对应的两条数据线12分别位于这两个子像素区域p在行向(行向即图3所示的横向)上的不同侧。由图3可以看出，两个相邻的子像素区域p中，左侧的子像素区域p对应的数据线12位于其左侧，右侧的子像素区域p对应的数据线12位于其右侧。
公共电极和多个像素电极，位于衬底基板11上。
图1所示的这两个子像素区域p之间不存在数据线，没有了数据线的干扰，这使得这两个子像素区域p中像素电极之间的距离可以更近，缩小了这两个子像素区域之间的无电场区域，进而缩小了子像素区域之间的黑影线。
如图4所示，其为本公开实施例示出的一种阵列基板的结构示意图，其中的白色区域即为子像素区域，而白色区域之间的黑色区域即为黑影线。可以看出，由于白色区域之间没有了数据线，因而白色区域之间的黑影线明显变窄(相较于图2所示的阵列基板)。
如图5所示，其为图3所示的阵列基板的剖面图，阵列基板11的两个子像素区域p中均分别设置有像素电极13和公共电极14。两个子像素区域p的两侧分别设置有两条数据线12。可以看出，相邻的两个子像素区域p中的像素电极13和公共电极14的距离较近。
综上所述，本公开实施例提供的一种阵列基板，通过将同一行且相邻的两个子像素区域对应的两条数据线，分别设置在这两个子像素区域在行向上的不同侧，使得衬底基板上存在相邻的两个子像素区域之间未设置数据线的结构，如此结构下，这相邻的两个子像素区域的像素电极的距离就可以较近，进而无法产生电场的区域就会较小，使得该阵列基板制成的显示面板的显示效果较高。解决了相关技术中阵列基板所制成的显示面板的显示效果较差的问题。提高了阵列基板制成的显示面板的显示效果。
图6是本公开实施例示出的另一种阵列基板的结构示意图。该阵列基板在图6所示的阵列基板的基础上做了一些调整。
可选的，公共电极14包括多个梳状子电极141，多个梳状子电极141与多个子像素区域p一一对应，多个梳状子电极141中任一梳状子电极在衬底基板11上的正投影所在区域与该任一梳状子电极对应的子像素区域p存在重叠。梳状子电极在衬底基板的正投影与子像素区域存在重叠后，即可以和子像素区域中的像素电极之间构成横向电场以控制液晶层。
其中，梳状子电极141包括多个条状的空隙，便于梳状子电极141与位于其下方的像素电极产生横向电场，并对显示面板的液晶层进行控制。
可选的，如图6所示，两个相邻的子像素区域p之间并未设置数据线，公共电极并不会与数据线互相影响，因此公共电极可以设置在这两个相邻的子像素区域p之间的区域的上方，也即是任意一个子像素区域对中的两个子像素区域p对应的两个梳状子电极141在衬底基板11上的正投影(图6中未示出)与这两个子像素区域p之间的区域存在重叠。
上述结构增加了公共电极的面积，减小了子像素区域之间未设置有公共电 极的区域的面积，进而减小了子像素区域之间的无电场区域的面积。
图1所示的阵列基板中，由于相邻的两个子像素区域p之间设置有数据线D，若这相邻的两个子像素区域p对应的梳状子电极通过走线相连，则该走线必然会横跨数据线，并对数据线以及梳状子电极造成影响。但图6所示的阵列基板中，由于相邻的两个子像素区域p之间并未设置数据线，因而这两个梳状子电极141可以电连接。图6示出的是这两个梳状子电极141通过走线电连接的结构。但这两个梳状子电极141还可以通过其他方式电连接。示例性的，如图7所示，其为本公开实施例提供的另一种阵列基板的结构示意图。其中，两个梳状子电极141为一体结构，如此结构下，两个梳状子电极覆盖了其对应的两个子像素区域之间的区域，进一步减小了子像素区域之间的无电场区域的面积。
在图7中，每个梳状子电极141均包括多个互相平行的条状结构(即图7中的黑色条状部分)，梳状子电极141正是由这些条状结构所构成的。公共电极可以包括有框架，用于固定梳状子电极141中的条状结构。
在图7所示的阵列基板上，每个子像素区域对中的两个子像素区域p对应的两个梳状子电极141中的条状结构成第一指定夹角x。该第一指定夹角可以大于90度且小于180度。在该夹角范围下，梳状子电极可以给显示面板中的液晶加载上预倾角，以提高液晶的偏转速度。
图7示出的阵列基板中的公共电极是本公开实施例提供的一种双畴结构的公共电极，但公共电极还可以为其他结构。如图8所示，其为本公开实施例提供的另一种阵列基板的结构示意图。
其中，每个梳状子电极141均包括两个条状结构集合(图8中的每个梳状子电极141的上半部分为一个条状结构集合，下半部分为另一个条状结构集合)，每个条状结构集合包括多个互相平行的多个条状结构(即图8中的黑色条状部分)，且两个条状结构集合中的条状结构成第二指定夹角y。可选的，第二指定夹角y可以大于0度小于90度。
子像素区域对中的两个子像素区域p对应的两个梳状子电极141中的四个条状结构集合中的条状结构成x型排列。图8示出的阵列基板中的公共电极是本公开实施例提供的一种四畴结构的公共电极。
可选的，如图9所示，其为本公开实施例示出的另一种阵列基板的结构示意图。其中，多个像素电极13与多个子像素区域p一一对应，且每个像素电极13在衬底基板11的正投影位于每个像素电极13对应的子像素区域p中，与子 像素区域对中的两个子像素区域p对应的两个像素电极13之间的最小距离s1大于或等于第一指定距离，该第一指定距离为两个像素电极13互相不会影响的最小距离。
由于不同子像素区域中的像素电极导通后会互相严重影响，因而该第一指定距离可以为两个像素电极13互相不会导通的最小距离。该第一指定距离通常可以由这两个像素电极的制造工艺的精度来决定，即该第一指定距离可以大于或等于制造工艺所能实现的最小距离。示例性的，该距离可以为3.0微米至3.5微米。如此这两个像素电极便不会互相影响。相较于图1所示的阵列基板中，相邻的两个子像素区域中的像素电极之间的距离h，本公开实施例中相邻的两个子像素区域中的像素电极之间的距离明显更近，这能够缩小子像素区域之间的无电场区域的面积，减小子像素区域之间的黑影线，还能够提高显示面板的透过率。
可选的，衬底基板11上可以具有多列子像素区域，多条数据线与这多列子像素区域一一对应，即每条数据线与一列子像素区域对应，如此结构下，两个相邻的子像素区域对之间可能存在两条数据线，这两条数据线12之间的距离s2大于或等于第二指定距离，该第二指定距离为两条数据线12互相不会影响的最小距离。如此可以避免设置在一起的数据线互相造成影响。第二指定距离的确定方式可以参照上述第一指定距离，在此不再赘述。
如图10所示，其为图9所示的阵列基板的另一种结构示意图。其中，两条数据线12两侧的两个像素电极13之间的距离大于或等于第三指定距离，第三指定距离为第二指定距离、两条数据线12的宽度(即两条数据线12的宽度之和)以及2倍的第四指定距离s3的和，第四指定距离s3为衬底基板上的像素电极与数据线互相不会影响的最小距离。
可选的，多个梳状子电极141均由透明导电材料构成，如此能够提高阵列基板的透过率。透明导电材料可以包括氧化铟锡(英文：Indium tin oxide；简称：ITO)。
此外，本公开实施例提供的一种阵列基板还可以包括栅极金属、源极金属、以及各绝缘层等结构，本公开实施例在此不再赘述。
本公开实施例提供的阵列基板可以应用于高级超维场转换(英文：Advanced Super Dimension Switch；简称：ADS)显示面板或边缘场开关型(英文：Fringe Field Switching；简称：FFS)显示面板中。
综上所述，本公开实施例提供的一种阵列基板，通过将同一行且相邻的两个子像素区域对应的两条数据线，分别设置在这两个子像素区域在行向上的不同侧，使得衬底基板上存在相邻的两个子像素区域之间未设置数据线的结构，如此结构下，这相邻的两个子像素区域的像素电极的距离就可以较近，进而无法产生电场的区域就会较小，使得该阵列基板制成的显示面板的显示效果较高。解决了相关技术中阵列基板所制成的显示面板的显示效果较差的问题。提高了阵列基板制成的显示面板的显示效果。
图11是本公开实施例提供的一种显示面板的结构示意图，该显示面板可以包括彩膜基板20、液晶层30以及上述实施例提供的任意一个阵列基板10。
可选的，多个像素电极13与多个子像素区域p一一对应，且每个像素电极13在衬底基板11的正投影位于每个像素电极13对应的子像素区域p中，与子像素区域对中的两个子像素区域p对应的两个像素电极13之间的最小距离s1大于或等于第一指定距离，该第一指定距离为两个像素电极互相不会影响的最小距离。
彩膜基板20上具有第一黑矩阵21，两个像素电极13(这两个像素电极13之间未设置有数据线)之间的区域在衬底基板11上的正投影位于第一黑矩阵21在衬底基板11上的正投影中。即该第一黑矩阵能够正好挡住两个像素电极13之间的区域，避免相邻的子像素区域发出的光线互相影响。该第一黑矩阵的宽度和两个像素电极13之间的区域的宽度正相关，该第一黑矩阵的最小宽度可以为能够避免相邻的子像素区域串色和漏光的宽度。此外，彩膜基板上还可以设置有平坦层、间隔柱以及屏蔽电场的氧化铟锡等等结构，本公开实施例在此不再赘述。
相较于本公开实施例提供的显示面板，相关技术中由于相邻的两个像素电极之间的距离(参考图1所示的距离h)较大，因而用于遮挡两个子像素区域之间的区域的黑矩阵也会较宽，导致子像素区域之间的黑影线也会较宽，进而导致显示面板的白态亮度较低。而本公开实施例提供的显示面板，由于黑矩阵的遮光面积较小，使得显示面板的白态亮度较高，黑态亮度较低，且对比度较高，整体的显示效果较好。
示例性的，当显示面板中的阵列基板为图7示出的阵列基板时，通过软件进行光学模拟得出显示面板的白态亮度提升5％，暗态亮度下降5％，对比度提 高10％。当显示面板中的阵列基板为图8示出的阵列基板时，通过模拟发现，本公开实施例提供的显示面的黑态亮度下降3％，白态亮度提高2.8％，对比度提高6.5％。
可选的，彩膜基板20上还设置有第二黑矩阵22，任意一条数据线12两侧的两个像素电极13之间的区域在衬底基板11上的正投影位于该第二黑矩阵22在衬底基板11上的正投影中。即该第二黑矩阵22可以挡住这两个像素电极13之间的区域。虽然相较于相关技术中的显示面板，该第二黑矩阵22的宽度较高，但黑矩阵的未遮挡区域与像素电极的重叠区域的面积并未减小。
此外，本公开实施例提供的显示面板，通过减小黑影线的尺寸，提高了显示面板的垂直对比度以及侧视角对比度。
如图12所示，其为本公开实施例示出的显示面板的亮度示意图。其横坐标为电压(该电压为加载在液晶层上的电压)，单位为伏特，纵坐标为亮度的相对百分比，该相对百分比以一种显示面板(例如图1所示的阵列基板制成的显示面板)的最大亮度为100％亮度为基准。在图12中，曲线q1为图1所示的阵列基板制成的一种显示面板的亮度曲线图；曲线q2和曲线q3为本公开实施例的图8所示的阵列基板制成的显示面板的亮度曲线，曲线q2和曲线q3不同的是，曲线q2是将图8所示的阵列基板中，相邻的子像素区域中的像素电极的距离设置为与图1所示的阵列基板相同的情况，而曲线q3是将相邻的子像素区域中的像素电极的距离设置为第一指定距离的情况。
曲线q4和曲线q5为本公开实施例的图7所示阵列基板制成的显示面板的亮度曲线，曲线q4是将相邻的子像素区域中的像素电极的距离设置为与与图1所示的阵列基板相同的情况；而曲线q5是将相邻的子像素区域中的像素电极的距离设置为第一指定距离的情况。可以看出，曲线q5所示的最大亮度明显高于其他的显示面板的最大亮度，这表明其最大亮度得到了明显的提升。
如图13所示，其为图12所示的曲线图中，横坐标为0伏至0.6伏这一区间的亮度(这一区间可以认为是暗态亮度)曲线图。其中，曲线q3和曲线q5的亮度接近(图13中为了便于示出，使曲线q5高于曲线q3，但这并非是对曲线q5和曲线q3的限制)，曲线q2和曲线q4的亮度接近(图13中为了便于示出，使曲线q2高于曲线q4，但这并非是对曲线q2和曲线q4的限制)，曲线q1的亮度相较于曲线q3和曲线q5高3％左右，曲线q1的亮度相较于曲线q2和曲线q4高5％左右。由图13可以看出，本公开实施例提供的显示面板的暗态亮度明显 低于与图1所示的阵列基板制成的显示面板的暗态亮度。
如图14所示，其为图12所示的曲线图中，6伏至6.6伏这一区间(这一区间可以认为是最大亮度区间)的亮度曲线图。其中，曲线q2的亮度相较于曲线q1高3％左右，曲线q3的亮度相较于曲线q1高2.5％左右，曲线q5的亮度相较于曲线q1高8％左右，曲线q4的亮度相较于曲线q1高5％左右。由图14可以看出，本公开实施例提供的显示面板的最大亮度明显高于图1所示的阵列基板制成的显示面板的最大亮度。
如图15所示，其为图12所示的曲线图中，各个曲线对应的显示面板的开口率和对比度的趋势图。其中，横坐标标识了各个显示面板所对应的曲线，左侧的纵坐标为对比度(英文：Contrast Ratio)，该对比度以曲线q1对应的显示面板的对比度为100％为基准。右侧的纵坐标为开口率(英文：Aperture Ratio)(该开口率为实际值)。黑色圆形符号代表开口率，黑色方形符号代表对比度。示例性的，曲线q1对应的显示面板的开口率大致在65％至66％之间，对比度为100％。可以看出，本公开实施例提供的显示面板的对比度明显高于图1所示的阵列基板制成的显示面板的对比度。
如图16所示，其为图12所示的曲线图中，各个曲线对应的显示面板的开口率和液晶效率(英文：liquid crystal efficient)的趋势图。横坐标标识了各个显示面板所对应的曲线，左侧的纵坐标为液晶效率，液晶效率是一种用于表示液晶层对于光线的偏转能力的参数，液晶效率越高，表示液晶对于光线的偏转能力越强。右侧的纵坐标为开口率(该开口率为实际值)。黑色圆形符号代表开口率，矩形框的高度代表液晶效率。可以看出，图1所示的阵列基板制成的显示面板的液晶效率(即曲线q1所表示的液晶效率)在80％至82％之间，而本公开实施例提供的显示面板的液晶效率均在85％以上，明显高于图1所示的阵列基板制成的显示面板的液晶效率。
图17是图12所示的曲线图中，曲线q1、曲线q4和曲线q5对应的显示面板的各角度对比度示意图。其中圆形图内部被多个实线线条分为多个区域，越靠近内部的区域所代表的对比度越高。该圆形图外边缘所标示的为观察视线在显示面板的显示面上的正投影与显示面板一条边沿的角度，内部的虚线圆圈标识观察视线与显示面板显示面的角度，由内向外分别包括20度、40度和60度。矩形框k表示对于显示面板的对比度的要求。圆形图最中心的实线线条所包围的区域在矩形框k的所在的面积越大，表明该显示面板在各个角度上的对比度 越高，显示效果越好。可以从图17看出，曲线q5和曲线q4所对应的显示面板在各个角度的对比度均优于曲线q1所对应的图1所示的阵列基板制成的显示面板。
由上述图12至图17所示的数据可以看出，本公开实施例提供的显示面板在各个方面的性能均优于图1所示的阵列基板制成的显示面板。
综上所述，本公开实施例提供的一种显示面板，包括阵列基板，通过将同一行且相邻的两个子像素区域对应的两条数据线，分别设置在这两个子像素区域在行向上的不同侧，使得衬底基板上存在相邻的两个子像素区域之间未设置数据线的结构，如此结构下，这相邻的两个子像素区域的像素电极的距离就可以较近，进而无法产生电场的区域就会较小，使得该阵列基板制成的显示面板的显示效果较高。解决了相关技术中显示面板的显示效果较差的问题。提高了显示面板的显示效果。
在本公开的附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开中，术语“第一”、“第二”、“第三”和“第四”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种阵列基板，所述阵列基板包括：
    衬底基板(11)，所述衬底基板(11)上具有多个子像素区域(p)，所述多个子像素区域(p)在所述衬底基板(11)上以多行多列的方式排布；
    多条数据线(12)，所述多条数据线(12)位于所述衬底基板(11)上，每条所述数据线(12)均与任意一列所述子像素区域(p)中的至少一个子像素区域(p)对应，任意一行所述子像素区域(p)包括多个子像素区域对，每个所述子像素区域对包括相邻的两个子像素区域(p)，且任意两个所述子像素区域对包括的子像素区域均不相同，所述两个子像素区域(p)对应的两条数据线(12)分别位于所述两个子像素区域(p)在行向上的不同侧；
    公共电极(14)和多个像素电极(13)，位于所述衬底基板上。
  2. 根据权利要求1所述的阵列基板，所述多个像素电极(13)与所述多个子像素区域(p)一一对应，且每个所述像素电极(13)在所述衬底基板(11)的正投影位于每个所述像素电极(13)对应的子像素区域(p)中，与所述两个子像素区域(p)对应的两个像素电极(13)之间的最小距离(s1)大于或等于第一指定距离，所述第一指定距离为所述两个像素电极(13)互相不会影响的最小距离。
  3. 根据权利要求1所述的阵列基板，所述公共电极(14)包括多个梳状子电极(141)，所述多个梳状子电极(141)与所述多个子像素区域(p)一一对应，所述两个子像素区域(p)对应的两个梳状子电极(141)在所述衬底基板(11)上的正投影与所述两个子像素区域(p)之间的区域存在重叠。
  4. 根据权利要求3所述的阵列基板，每个所述梳状子电极(141)均包括多个互相平行的条状结构，所述两个子像素区域(p)对应的两个梳状子电极(141)中的条状结构成第一指定夹角(x)，所述第一指定夹角(x)大于90度且小于180度。
  5. 根据权利要求3所述的阵列基板，每个所述梳状子电极(141)均包括 两个条状结构集合，每个所述条状结构集合包括多个互相平行的条状结构，所述两个子像素区域(p)对应的两个梳状子电极(141)中的四个条状结构集合的条状结构成x型排列。
  6. 根据权利要求3所述的阵列基板，所述多个梳状子电极(141)中任一梳状子电极(141)在所述衬底基板(11)上的正投影与所述任一梳状子电极(141)对应的子像素区域(p)存在重叠。
  7. 根据权利要求3所述的阵列基板，所述两个梳状子电极(141)电连接。
  8. 根据权利要求1所述的阵列基板，任意一行所述子像素区域中，位于任意两个相邻的所述子像素区域对之间的两条数据线(12)之间的距离(s2)大于或等于第二指定距离，所述第二指定距离为所述两条数据线(12)互相不会影响的最小距离。
  9. 根据权利要求8所述的阵列基板，所述两条数据线(12)两侧的两个像素电极(13)之间的距离大于或等于第三指定距离，所述第三指定距离为所述第二指定距离、所述两条数据线(12)的宽度以及2倍的第四指定距离(s3)的和，所述第四指定距离(s3)为所述衬底基板(11)上的像素电极(13)与数据线(12)互相不会影响的最小距离。
  10. 根据权利要求1至9任一所述的阵列基板，所述多个梳状子电极(141)均由透明导电材料构成。
  11. 根据权利要求1所述的阵列基板，所述多个像素电极(13)与所述多个子像素区域(p)一一对应，且每个所述像素电极(13)在所述衬底基板(11)的正投影位于每个所述像素电极(13)对应的子像素区域(p)中，与所述两个子像素区域(p)对应的两个像素电极(13)之间的最小距离(s1)大于或等于第一指定距离，所述第一指定距离为所述两个像素电极(13)互相不会影响的最小距离；
    所述公共电极(14)包括多个梳状子电极(141)，所述多个梳状子电极(141)与所述多个子像素区域(p)一一对应，所述两个子像素区域(p)对应的两个梳状子电极(141)在所述衬底基板(11)上的正投影与所述两个子像素区域(p)之间的区域存在重叠；
    每个所述梳状子电极(141)均包括多个互相平行的条状结构，所述两个子像素区域(p)对应的两个梳状子电极(141)中的条状结构成第一指定夹角(x)，所述第一指定夹角(x)大于90度且小于180度，所述两个梳状子电极(141)电连接；
    所述多个梳状子电极(141)中任一梳状子电极(141)在所述衬底基板(11)上的正投影与所述任一梳状子电极(141)对应的子像素区域(p)存在重叠。
  12. 一种显示面板，所述显示面板包括彩膜基板(20)、液晶层(30)以及权利要求1-11任一所述的阵列基板(10)，所述阵列基板(10)包括：
    衬底基板(11)，所述衬底基板(11)上具有多个子像素区域(p)，所述多个子像素区域(p)在所述衬底基板(11)上以多行多列的方式排布；多条数据线(12)，所述多条数据线(12)位于所述衬底基板(11)上，每条所述数据线(12)均与任意一列所述子像素区域(p)中的至少一个子像素区域(p)对应，任意一行所述子像素区域(p)包括多个子像素区域对，每个所述子像素区域对包括相邻的两个子像素区域，且任意两个所述子像素区域对包括的子像素区域均不相同，所述两个子像素区域(p)对应的两条数据线(12)分别位于所述两个子像素区域(p)在行向上的不同侧；公共电极(14)和多个像素电极(13)，位于所述衬底基板(11)上。
  13. 根据权利要求12所述的显示面板，所述多个像素电极(13)与所述多个子像素区域(p)一一对应，且每个所述像素电极(13)在所述衬底基板(11)的正投影位于每个所述像素电极(13)对应的子像素区域(p)中，所述彩膜基板(20)上具有第一黑矩阵(21)，所述两个子像素区域(p)对应的两个像素电极(13)之间的区域在所述衬底基板(11)上的正投影位于所述第一黑矩阵(21)在所述衬底基板(21)上的正投影中。
  14. 根据权利要求12所述的显示面板，所述彩膜基板(20)上具有第二黑矩阵(22)，任意一条所述数据线(12)两侧的两个像素电极(13)之间的区域在所述衬底基板(11)上的正投影位于所述第二黑矩阵(22)在所述衬底基板(11)上的正投影中。
  15. 根据权利要求12所述的显示面板，所述多个像素电极(13)与所述多个子像素区域(p)一一对应，且每个所述像素电极(13)在所述衬底基板(11)的正投影位于每个所述像素电极(13)对应的子像素区域(p)中，与所述两个子像素区域(p)对应的两个像素电极(13)之间的最小距离(s1)大于或等于第一指定距离，所述第一指定距离为所述两个像素电极(13)互相不会影响的最小距离；
    所述公共电极(14)包括多个梳状子电极(141)，所述多个梳状子电极(141)与所述多个子像素区域(p)一一对应，所述两个子像素区域(p)对应的两个梳状子电极(141)在所述衬底基板(11)上的正投影与所述两个子像素区域(p)之间的区域存在重叠；
    每个所述梳状子电极(141)均包括多个互相平行的条状结构，所述两个子像素区域(p)对应的两个梳状子电极(141)中的条状结构成第一指定夹角(x)，所述第一指定夹角(x)大于90度且小于180度，所述两个梳状子电极(141)电连接；
    所述多个梳状子电极(141)中任一梳状子电极(141)在所述衬底基板(11)上的正投影与所述任一梳状子电极(141)对应的子像素区域(p)存在重叠。
  16. 一种显示装置，所述显示装置包括权利要求12-15任一所述的显示面板。
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