WO2020095140A1 - 半導体装置、及び電子機器 - Google Patents

半導体装置、及び電子機器 Download PDF

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Publication number
WO2020095140A1
WO2020095140A1 PCT/IB2019/059204 IB2019059204W WO2020095140A1 WO 2020095140 A1 WO2020095140 A1 WO 2020095140A1 IB 2019059204 W IB2019059204 W IB 2019059204W WO 2020095140 A1 WO2020095140 A1 WO 2020095140A1
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Prior art keywords
circuit
transistor
wiring
potential
terminal
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Ceased
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PCT/IB2019/059204
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English (en)
French (fr)
Japanese (ja)
Inventor
木村肇
黒川義元
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/289,357 priority Critical patent/US12453072B2/en
Priority to JP2020556355A priority patent/JP7441175B2/ja
Publication of WO2020095140A1 publication Critical patent/WO2020095140A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024021696A priority patent/JP2024055903A/ja
Priority to JP2025094375A priority patent/JP7854547B2/ja
Priority to US19/338,408 priority patent/US20260020215A1/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • One embodiment of the present invention relates to a semiconductor device and an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, as technical fields of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, and a processor.
  • Electronic devices, systems, driving methods thereof, manufacturing methods thereof, or inspection methods thereof can be given as examples.
  • the integrated circuit incorporates the brain mechanism as an electronic circuit and has circuits corresponding to “neurons” and “synapses” in the human brain. Therefore, such an integrated circuit may be called “neuromorphic", “brain morphic”, or “brain inspire”.
  • the integrated circuit has a non-Neumann architecture, and is expected to be capable of performing parallel processing with extremely low power consumption as compared with the Neumann architecture in which power consumption increases as the processing speed increases.
  • Non-Patent Document 1 and Non-Patent Document 2 disclose an arithmetic unit that constitutes an artificial neural network by using an SRAM (Static Random Access Memory).
  • a calculation is performed by multiplying the synaptic connection strength (which may be called a weighting coefficient) that connects two neurons with the signal transmitted between the two neurons.
  • the connection strength of each synapse between the plurality of first neurons of the first layer and one of the second neurons of the second layer, and the plurality of first neurons of the first layer It is necessary to multiply by each signal input to one of the second neurons of the second layer from and to add, and depending on the scale of the artificial neural network, for example, the number of the connection strength, a parameter indicating the signal, and the like. Is determined. That is, in the artificial neural network, as the number of layers and the number of neurons increase, the number of circuits corresponding to each of “neurons” and “synapses” increases and the amount of calculation may increase.
  • the power consumption increases as the number of circuits that make up the chip increases, and the amount of heat generated when driving the device also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip are affected. Therefore, it is preferable that the circuit forming the chip has circuit elements that are not easily affected by temperature.
  • One aspect of the present invention is to provide a semiconductor device in which a hierarchical artificial neural network is built and the like. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like with low power consumption. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device or the like that is less likely to be affected by the temperature of the environment. Alternatively, it is an object of one embodiment of the present invention to provide a novel semiconductor device or the like.
  • the problem of one embodiment of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are the ones not mentioned in this item, which will be described below.
  • Problems that are not mentioned in this item can be derived from descriptions in the specification, drawings, and the like by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention is to solve at least one of the problems listed above and other problems. Note that according to one embodiment of the present invention, it is not necessary to solve all the problems listed above and other problems.
  • One embodiment of the present invention includes a first circuit, the first circuit includes a first transistor, a second transistor, and a first capacitor, and the first transistor includes a first gate and a first gate. Two gates, the first gate of the first transistor is electrically connected to the first input wiring, the second gate of the first transistor is the first terminal of the second transistor, and the first capacitance element. Is electrically connected to the first terminal of the first circuit, and the first circuit turns off the second transistor to turn off the second terminal of the first capacitor and the second gate of the first transistor.
  • a semiconductor device having a function of holding one potential, a function of turning the first transistor on or off depending on the first potential and the second potential input to the first input wiring Is.
  • the first potential has an analog value and an analog current flows through the first transistor when the first transistor is on.
  • the third transistor has a third transistor, the third transistor has a first gate, and a second gate. Has a first gate electrically connected to a second input wiring, and a second gate of the third transistor has a first terminal of the second transistor, a first terminal of the first capacitive element, and a first terminal of the first transistor.
  • the second circuit includes a second circuit, a fourth to a sixth transistor, and a second capacitor, and the fourth transistor.
  • the sixth transistor each have a first gate and a second gate, the first gate of the fourth transistor is electrically connected to the first input wiring, and the first gate of the sixth transistor is Is electrically connected to the second input wiring, and the second gate of the fourth transistor has a first terminal of the fifth transistor, a first terminal of the second capacitance element, and a second gate of the sixth transistor, The first terminal of the first transistor is electrically connected to the first wiring, the first terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the fourth transistor is electrically connected to the second wiring.
  • the first terminal is electrically connected to the second wiring and The first terminal of the transistor is electrically connected to the first wiring, and the second circuit turns off the fifth transistor so that the first terminal of the second capacitor and the second gate of the fourth transistor are turned on.
  • the sixth transistor is a semiconductor device in which an analog current flows.
  • the third circuit and the fourth circuit are provided, and the first potential and the fourth potential are potentials corresponding to the first data.
  • the third circuit has a function of inputting the first potential and the third potential according to the second data to the first input wiring and the second input wiring, respectively, and the fourth circuit has the function of inputting the first potential and the third potential.
  • the semiconductor device has a function of comparing currents flowing from two wirings and outputting a potential according to the product of the first data and the second data from the output terminal of the fourth circuit.
  • one embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (6) and performing a neural network operation using the semiconductor device.
  • a semiconductor device is a device utilizing semiconductor characteristics, and means a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like.
  • a semiconductor element a transistor, a diode, a photodiode, or the like
  • it refers to all devices that can function by utilizing semiconductor characteristics.
  • an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is housed in a package are examples of semiconductor devices.
  • a memory device, a display device, a light-emitting device, a lighting device, an electronic device, or the like is a semiconductor device in its own right and may have a semiconductor device.
  • X and Y are connected, a case where X and Y are electrically connected and a case where X and Y are functionally connected are described. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also disclosed in the drawing or the text.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.
  • Element, light emitting element, load, etc. can be connected between X and Y one or more.
  • the switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state) and has a function of controlling whether or not to pass a current.
  • Examples of the case where X and Y are functionally connected include a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.)) that enables functional connection between X and Y, and signal conversion.
  • Circuits digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (step-up circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals), voltage sources, current sources , Switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. It is possible to connect more than one between and. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functional
  • X and Y, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are electrically connected to each other, and X, the source of the transistor (or 1 terminal), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal or the like) is electrically connected to X
  • the drain of the transistor (or the second terminal or the like) is electrically connected to Y
  • X, the source of the transistor ( Alternatively, the first terminal or the like), the drain of the transistor (or the second terminal, or the like), and Y are electrically connected in this order ”.
  • X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of the transistor, and X, a source (or a first terminal) of the transistor, or the like. Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order ”.
  • the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are separated from each other by defining the order of connection in the circuit structure by using the expression method similar to these examples. Apart from this, the technical scope can be determined. Note that these expression methods are examples, and the present invention is not limited to these expression methods.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • a transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals functioning as a source or a drain are input / output terminals of the transistor.
  • One of the two input / output terminals serves as a source and the other serves as a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms source and drain can be rephrased.
  • a transistor may have a back gate in addition to the above-described three terminals depending on the structure of the transistor.
  • one of the gate and the back gate of the transistor is referred to as a first gate
  • the other of the gate and the back gate of the transistor is referred to as a second gate.
  • the terms "gate” and “back gate” may be interchangeable with each other. In the case where the transistor has three or more gates, each gate is referred to as a first gate, a second gate, a third gate, or the like in this specification and the like.
  • a node can be restated as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on a circuit configuration, a device structure, or the like. Further, terminals, wirings, etc. can be paraphrased as nodes.
  • Voltage refers to a potential difference from a reference potential, and for example, when the reference potential is a ground potential (ground potential), “voltage” can be paraphrased to “potential”. The ground potential does not always mean 0V. Note that the potentials are relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description "the electrical conduction of a positively charged body is occurring” means “the electrical conduction of a negatively charged body in the opposite direction.” Is happening. " Therefore, in this specification and the like, the term “current” refers to a charge transfer phenomenon (electric conduction) associated with carrier transfer, unless otherwise specified.
  • the carrier as used herein include electrons, holes, anions, cations, complex ions, and the like, and the carriers are different depending on the system in which current flows (for example, semiconductor, metal, electrolytic solution, in vacuum, etc.). Further, the “direction of current” in the wiring or the like is the direction in which positive carriers move, and is described as the amount of positive current.
  • the direction in which the negative carriers move is opposite to the direction of the current, and is expressed by the negative current amount. Therefore, in this specification and the like, unless otherwise specified as to whether the current is positive or negative (or the direction of the current), a description such as “a current flows from the element A to the element B" is "a current flows from the element B to the element A” or the like. Can be paraphrased into. Further, the description such as “current is input to the element A” can be translated into “current is output from the element A” and the like.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion among constituent elements. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, a component referred to as “first” in one of the embodiments of the present specification and the like is a component referred to as “second” in another embodiment or in the claims. There is also a possibility. Further, for example, the component referred to as “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • the terms “upper” and “lower” do not necessarily mean that the positional relationship of the constituent elements is directly above or below and is in direct contact with each other.
  • the expression “electrode B on insulating layer A” it is not necessary that the electrode B is directly formed on the insulating layer A, and another structure is provided between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • terms such as “film” and “layer” can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.
  • electrode and “wiring” do not limit the functional elements.
  • electrode may be used as part of “wiring” and vice versa.
  • electrode and wiring also include the case where a plurality of “electrodes” and “wirings” are integrally formed.
  • terms such as “wiring”, “signal line”, and “power line” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term “wiring” to the term “signal line”. Further, for example, it may be possible to change the term “wiring” to a term such as “power line”. The reverse is also true, and in some cases, terms such as “signal line” and “power line” can be changed to "wiring”. In some cases, terms such as “power line” can be changed to terms such as “signal line”. Also, the reverse is also true, and in some cases, the term “signal line” or the like can be changed to the term “power line” or the like. In addition, the term “potential” applied to the wiring can be changed to the term “signal” or the like depending on the case or circumstances. Also, the reverse is also true, and in some cases, terms such as “signal” can be changed to the term “potential”.
  • the semiconductor impurities mean, for example, components other than the main components constituting the semiconductor layer.
  • an element whose concentration is less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, and crystallinity may be reduced.
  • the impurities that change the characteristics of the semiconductor include, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and a component other than the main component.
  • transition metals and the like in particular hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 elements other than oxygen and hydrogen, group 2 elements, group 13 elements, group 15 elements, and the like. There is.
  • a switch refers to a switch which is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to flow a current.
  • a switch has a function of selecting and switching a path through which current flows.
  • an electrical switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a particular one as long as it can control the current.
  • Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , A diode-connected transistor, or the like, or a logic circuit in which these are combined. Note that when a transistor is used as a switch, the “conductive state” of the transistor means a state where the source and drain electrodes of the transistor can be regarded as being electrically short-circuited.
  • non-conduction state of a transistor refers to a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when the transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.
  • a mechanical switch there is a switch using MEMS (micro electro mechanical system) technology.
  • the switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.
  • a semiconductor device in which a hierarchical artificial neural network is built can be provided.
  • a semiconductor device or the like with low power consumption can be provided.
  • a semiconductor device or the like which is unlikely to be affected by the temperature of the environment can be provided.
  • a novel semiconductor device or the like can be provided.
  • the effects of one aspect of the present invention are not limited to the effects listed above.
  • the effects listed above do not prevent the existence of other effects.
  • the other effects are the effects which are not mentioned in this item, which will be described below.
  • the effects not mentioned in this item can be derived from the description such as the specification or the drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.
  • FIG. 1A and 1B are diagrams for explaining a hierarchical neural network.
  • FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device.
  • 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing configuration examples of circuits included in the semiconductor device.
  • 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing configuration examples of circuits included in the semiconductor device.
  • 5A, 5B, 5C, 5D, and 5E are circuit diagrams showing configuration examples of circuits included in the semiconductor device.
  • FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device.
  • 9A and 9B are circuit diagrams each illustrating a structural example of a circuit included in a semiconductor device.
  • FIG. 10 is a circuit diagram illustrating a configuration example of a circuit included in a semiconductor device.
  • 11A and 11B are circuit diagrams each illustrating a structural example of a circuit included in the semiconductor device.
  • 12A and 12B are diagrams showing voltage-current characteristics of a transistor included in a semiconductor device.
  • 13A, 13B, and 13C are timing charts showing an operation example of a circuit included in the semiconductor device.
  • 14A, 14B, and 14C are timing charts showing operation examples of circuits included in the semiconductor device.
  • 15A, 15B, and 15C are timing charts showing an operation example of a circuit included in the semiconductor device.
  • 16A and 16B are circuit diagrams each illustrating a structural example of a circuit included in a semiconductor device.
  • FIG. 17 is a circuit diagram illustrating a configuration example of a circuit included in a semiconductor device.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a circuit included in a semiconductor device.
  • FIG. 19 is a circuit diagram illustrating a configuration example of a circuit included in a semiconductor device.
  • 20A and 20B are circuit diagrams each illustrating a structural example of a circuit included in a semiconductor device.
  • 21A and 21B are circuit diagrams each illustrating a configuration example of a circuit included in the semiconductor device.
  • FIG. 22A and 22B are circuit diagrams each illustrating a structural example of a circuit included in the semiconductor device.
  • FIG. 23 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 24 is a cross-sectional view showing a configuration example of a semiconductor device.
  • 25A, 25B, and 25C are cross-sectional views illustrating structural examples of transistors.
  • 26A, 26B, and 26C are a top view and a cross-sectional view illustrating a structural example of a transistor.
  • 27A, 27B, and 27C are a top view and a cross-sectional view illustrating a structural example of a transistor.
  • 28A, 28B, and 28C are a top view and a cross-sectional view illustrating a structural example of a transistor.
  • 29A, 29B, and 29C are a top view and a cross-sectional view illustrating a structural example of a transistor.
  • 30A, 30B, and 30C are a top view and a cross-sectional view illustrating a structural example of a transistor.
  • 31A and 31B are a top view and a perspective view illustrating a structural example of a transistor.
  • 32A and 32B are cross-sectional views illustrating a structural example of a transistor.
  • 33A, 33B, and 33C are a top view and a perspective view showing a structural example of a capacitor.
  • 34A, 34B, and 34C are a top view and a perspective view showing a structural example of a capacitor.
  • FIGS. 37B and 37C are perspective views showing an example of an electronic device.
  • synaptic connection strength can be changed by giving existing information to the neural network.
  • the process of giving existing information to the neural network and determining the coupling strength may be called “learning”.
  • a neural network having a multilayer structure may be referred to as a “deep neural network” (DNN), and machine learning by a deep neural network may be referred to as “deep learning”.
  • DNN deep neural network
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplification function, a rectification function, and a switching function, the metal oxide is referred to as a metal oxide semiconductor. You can When the term “OS FET” or “OS transistor” is used, it can be referred to as a transistor including a metal oxide or an oxide semiconductor.
  • metal oxides having nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the contents described in one embodiment are different from the contents described in the embodiment (may be a part of the contents) and one or more different embodiments. It is possible to apply, combine, replace, or the like with respect to at least one of the contents described in the form (or a part of the contents).
  • a diagram (or part of it) described in one embodiment is different from another portion of the diagram, another diagram (or part) described in the embodiment, and one or a plurality of different views. More drawings can be configured by combining at least one drawing with the drawings (which may be a part) described in the embodiments.
  • the hierarchical neural network has, for example, one input layer, one or more intermediate layers (hidden layers), and one output layer, and is configured by a total of three or more layers.
  • the hierarchical neural network 100 shown in FIG. 1A shows an example thereof, and the neural network 100 has first to R-th layers (R in this case can be an integer of 4 or more). ing.
  • R in this case can be an integer of 4 or more.
  • the first layer corresponds to the input layer
  • the R layer corresponds to the output layer
  • the other layers correspond to the intermediate layer.
  • FIG. 1A illustrates the (k-1) th layer and the kth layer (k is an integer of 3 or more and R-1 or less) as intermediate layers, and other intermediate layers. Are not shown.
  • Each layer of the neural network 100 has one or more neurons.
  • the first layer includes neurons N 1 (1) to N p (1) (where p is an integer of 1 or more), and the (k ⁇ 1) th layer includes neurons N 1 (1).
  • (K ⁇ 1) to neurons N m (k ⁇ 1) (where m is an integer of 1 or more)
  • the k-th layer includes neurons N 1 (k) to neurons N n (k) (
  • n is an integer of 1 or more.
  • the R-th layer includes neurons N 1 (R) to neurons N q (R) (q is an integer of 1 or more).
  • the k-th layer neuron N j (k) (where j is an integer of 1 or more and n or less) is illustrated, and the other neurons are not illustrated.
  • Figure 1B is a neuron N j of the k-th layer (k), shows the signal which is input to the neuron N j (k), a signal output from the neuron N j (k), the.
  • the output signals z 1 (k-1) to z m (k ⁇ ) of the neurons N 1 (k ⁇ 1) to N m (k ⁇ 1) of the (k ⁇ 1) th layer are respectively. 1) is output to the neuron N j (k) . Then, the neuron N j (k) is, z 1 (k-1) to z m (k-1) to generate a z j (k) in response to, the z j (k) is an output signal (k + 1 ) Output to each neuron of the layer (not shown).
  • the degree of signal transmission of a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the coupling strength of synapses connecting these neurons (hereinafter referred to as a weighting coefficient).
  • the signals output from the neurons in the previous layer are multiplied by the corresponding weighting factors and input to the neurons in the next layer.
  • the synaptic weighting factor between the neuron N i (k ⁇ 1) of the (k ⁇ 1) th layer and the neuron N j (k) of the kth layer is w i (k ⁇ 1) j (k)
  • the signal input to the k-th layer neuron N j (k) can be expressed by equation (1.1).
  • the neuron N j (k) produces an output signal z j (k) according to u j (k) .
  • Neuron N j output signal z j from (k) (k) defined by the following equation.
  • the function f (u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, or the like can be used.
  • the activation function may be the same or different in all neurons.
  • the activation function of the neuron may be the same or different in each layer.
  • the signals output by the neurons of each layer may be analog values or digital values.
  • the digital value may be binary or ternary, for example.
  • a linear ramp function or a sigmoid function may be used as the activation function.
  • binary digital values for example, a step function with an output of -1 or 1, or 0 or 1 may be used.
  • the signals output from the neurons of each layer may have three or more values.
  • the activation function has three values, for example, a step function with an output of -1, 0, or 1, or 0, 1, or 2 A step function or the like may be used.
  • an input signal is input to the first layer (input layer), so that the layers from the first layer (input layer) to the last layer (output layer) are sequentially input from the previous layer.
  • an operation of generating an output signal using equations (1.1) to (1.3) and outputting the output signal to the next layer is performed.
  • the signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.
  • the weighting coefficient of the synapse circuit of the neural network 100 is binary (a combination of “ ⁇ 1” and “+1”, or a combination of “0” and “+1”), or It has three values (combination of "-1", “0", "1”, etc.), and the activation function of the neuron is binary (combination of "-1", "+1", or "0", "+1”).
  • Etc. or a ternary value (a combination of “ ⁇ 1”, “0”, “1”, etc.).
  • first data the weighting factor and the value of the signal input from the neuron in the previous layer to the neuron in the next layer
  • second data one of them is referred to as first data.
  • first data the value of the signal input from the neuron in the previous layer to the neuron in the next layer
  • the arithmetic circuit 110 illustrated in FIG. 2 is, for example, a semiconductor device including an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP.
  • the arithmetic circuit 110 outputs the signals z 1 (k-1) to z m (k-1) input to the neurons N 1 (k) to N n (k) of the k-th layer in FIGS. 1A and 1B. It is a circuit that processes and generates signals z 1 (k) to z n (k) output from the neurons N 1 (k) to N n (k) , respectively.
  • the entire arithmetic circuit 110 or a part thereof may be used for purposes other than the neural network and AI.
  • the whole or a part of the arithmetic circuit 110 may be used to perform the process. That is, the whole or part of the arithmetic circuit 110 may be used for general calculation as well as calculation for AI.
  • the circuit ILD is electrically connected to the wirings IL [1] to IL [n] and the wirings ILB [1] to ILB [n], for example.
  • the circuit WLD is electrically connected to the wirings WLS [1] to WLS [m], for example.
  • the circuit XLD is electrically connected to the wirings XLS [1] to XLS [m], for example.
  • the circuit AFP is electrically connected to the wirings OL [1] to OL [n] and the wirings OLB [1] to OLB [n], for example.
  • the array unit ALP has, for example, m ⁇ n circuits MP.
  • the circuits MP are, for example, arranged in a matrix of m rows and n columns in the array unit ALP. Note that, in FIG. 2, the circuit MP located at the i-th row and the j-th column (where i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is referred to as a circuit MP [i, j]. However, in FIG. 2, only the circuit MP [1,1], the circuit MP [m, 1], the circuit MP [i, j], the circuit MP [1, n], and the circuit MP [m, n] are illustrated. The other circuits MP are not shown.
  • the circuit MP [i, j] includes the wiring IL [j], the wiring ILB [j], the wiring WLS [i], the wiring XLS [i], the wiring OL [j], and the wiring OLB [. j] and are electrically connected to.
  • the circuit MP [i, j] may be referred to as a weighting coefficient (one of the first data and the second data ) between the neuron N i (k ⁇ 1) and the neuron N j (k) .
  • it has a function of holding (referred to as first data).
  • the circuit MP [i, j] has information (for example, potential, resistance value, current) corresponding to the first data (weighting coefficient) input from the wiring IL [j] and the wiring ILB [j]. Value etc.) is retained.
  • the circuit MP [i, j] may be referred to as a signal z i (k ⁇ 1) (the other of the first data and the second data ) output from the neuron N i (k ⁇ 1) .
  • the circuit MP [i, j] receives the second data z i (k ⁇ 1) from the wiring XLS [i] to calculate the product of the first data and the second data.
  • a corresponding current for example, current, voltage, etc.
  • Information for example, current and voltage
  • information for example, current and voltage
  • the wiring IL [j] and the wiring ILB [j] are provided is described; however, one embodiment of the present invention is not limited to this.
  • Only one of the wiring IL [j] and the wiring ILB [j] may be arranged. Note that the example in which the wiring OL [j] and the wiring OLB [j] are provided is described; however, one embodiment of the present invention is not limited to this. Only one of the wiring OL [j] and the wiring OLB [j] may be arranged.
  • the circuit ILD includes the circuits MP [1,1] to MP [m, through the wirings IL [1] to IL [n] and the wirings ILB [1] to ILB [n].
  • n information corresponding to the first data w 1 (k ⁇ 1) 1 (k) to w m (k ⁇ 1) n (k) that are weighting factors (for example, potential, resistance value, It has the function of inputting the current value).
  • the circuit ILD has information (for example, potential, resistance ) corresponding to the first data w i (k ⁇ 1) j (k) , which is a weighting coefficient, for the circuit MP [i, j]. Value, current value, or the like) is supplied through the wiring IL [j] and the wiring ILB [j].
  • the circuit WLD has, for example, a function of selecting a circuit MP to which information (for example, potential, resistance value, current value, etc.) according to the first data input from the circuit ILD is written. For example, when information (for example, a potential, a resistance value, a current value, or the like) is written to the circuits MP [i, 1] to MP [i, n] located in the i-th row of the array portion ALP, the circuit WLD is , For example, a signal for turning on or off a writing switching element included in the circuits MP [i, 1] to MP [i, n] is supplied to the wiring WLS [i] and other than the i-th row The potential for turning off the writing switching element included in the circuit MP may be supplied to the wiring WLS. Note that the example in which the wiring WLS [i] is provided is described; however, one embodiment of the present invention is not limited to this. For example, the wiring WLS [i] may be arranged as a plurality of wiring
  • the circuit XLD includes a neuron N 1 (k ⁇ 1 ) for each of the circuits MP [1,1] to MP [m, n] via the wirings XLS [1] to wiring XLS [n]. ) To neuron N m (k-1) and the second data z 1 (k-1) to z m (k-1) corresponding to the calculated value. Specifically, the circuit XLD outputs the second data z i (k ⁇ 1) output from the neuron N i (k ⁇ 1) to the circuits MP [i, 1] to MP [i, n]. Information (for example, potential, current value, etc.) corresponding to is supplied by the wiring XLS [i]. Note that the example in which the wiring XLS [i] is provided is described; however, one embodiment of the present invention is not limited to this. For example, the wiring XLS [i] may be arranged as a plurality of wirings.
  • the circuit AFP includes, for example, circuits ACTF [1] to ACTF [n].
  • the circuit ACTF [j] is electrically connected to the wiring OL [j] and the wiring OLB [j], for example.
  • the circuit ACTF [j] for example, generates a signal according to each information (for example, potential, current value, etc.) input from the wiring OL [j] and the wiring OLB [j].
  • each piece of information for example, a potential or a current value
  • the signal corresponds to the signal z j (k) output from the neuron N j (k) .
  • each of the circuits ACTF [1] to ACTF [n] functions as a circuit that calculates the activation function of the neural network described above.
  • the circuits ACTF [1] to ACTF [n] may have a function of converting an analog signal into a digital signal.
  • the circuits ACTF [1] to ACTF [n] may have a function of amplifying and outputting an analog signal, that is, a function of converting output impedance. Note that the example in which the circuit ACTF is provided is described; however, one embodiment of the present invention is not limited to this.
  • the circuit ACTF may not be arranged.
  • FIG. 3A illustrates a circuit that generates a signal z j (k) in accordance with a current input from the wiring OL [j] and the wiring OLB [j].
  • FIG. 3A shows an example of an activation function arithmetic circuit that outputs an output signal z j (k) represented by two values.
  • the circuit ACTF [j] has a resistance element RE, a resistance element REB, and a comparator CMP.
  • the resistance element RE and the resistance element REB have a function of converting current into voltage. Therefore, as long as it is an element or a circuit having a function of converting a current into a voltage, it is not limited to the resistance element.
  • the wiring OL [j] is electrically connected to the first terminal of the resistance element RE and the first input terminal of the comparator CMP, and the wiring OLB [j] is connected to the first terminal of the resistance element REB and the comparator. It is electrically connected to the second input terminal of the CMP.
  • the second terminal of the resistance element RE is electrically connected to the wiring VAL
  • the second terminal of the resistance element REB is electrically connected to the wiring VAL.
  • the second terminal of the resistance element RE and the second terminal of the resistance element REB may be connected to the same wiring. Alternatively, they may be connected to different wirings having the same potential.
  • the resistance values of the resistance element RE and the resistance element REB are preferably equal to each other. For example, it is desirable that the difference between the resistance values of the resistance element RE and the resistance element REB be within 10%, and more preferably within 5%. However, one embodiment of the present invention is not limited to this. Depending on the case or the situation, the resistance values of the resistance element RE and the resistance element REB may be different from each other.
  • the wiring VAL functions as a wiring that gives a constant voltage, for example.
  • the constant voltage can be, for example, a high level potential VDD, a low level potential VSS, a ground potential (GND), or the like.
  • the constant voltage is appropriately set according to the configuration of the circuit MP.
  • the wiring VAL may be supplied with a pulse signal instead of a constant voltage.
  • the voltage between the first terminal and the second terminal of the resistance element RE is determined according to the current flowing from the wiring OL [j]. Therefore, the resistance value of the resistance element RE and the voltage corresponding to the current are input to the first input terminal of the comparator CMP.
  • the voltage between the first terminal and the second terminal of the resistance element REB is determined according to the current flowing from the wiring OLB [j]. Therefore, the resistance value of the resistance element REB and the voltage corresponding to the current are input to the second input terminal of the comparator CMP.
  • the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal and outputting a signal from the output terminal of the comparator CMP according to the comparison result.
  • the comparator CMP outputs a high level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and the second input terminal When the voltage input to the first input terminal is higher than the voltage input to, the low level potential can be output from the output terminal of the comparator CMP.
  • the output signal z j (k) output from the circuit ACTF [j] should be binary.
  • each of the high level potential and the low level potential output from the output terminal of the comparator CMP can correspond to “+1” and “ ⁇ 1” as the output signal z j (k) .
  • the high-level potential and the low-level potential output from the output terminal of the comparator CMP may correspond to “+1” and “0” as the output signal z j (k) .
  • the resistance element RE and the resistance element REB are used, but the element or circuit having a function of converting current into voltage is not limited to the resistance element. Therefore, the resistance element RE and the resistance element REB of the circuit ACTF [j] in FIG. 3A can be replaced with another circuit element.
  • the circuit ACTF [j] illustrated in FIG. 3B is a circuit in which the resistance element RE and the resistance element REB included in the circuit ACTF [j] in FIG. 3A are replaced with a capacitance element CE and a capacitance element CEB, respectively. An operation similar to that of the circuit ACTF [j] can be performed.
  • the capacitance values of the capacitance element CE and the capacitance element CEB are preferably equal to each other. For example, it is desirable that the difference between the capacitance values of the capacitive element CE and the capacitive element CEB be within 10%, and more preferably within 5%. However, one embodiment of the present invention is not limited to this.
  • a circuit for initializing the charge accumulated in the capacitor CE and the capacitor CEB may be provided.
  • a switch may be provided in parallel with the capacitive element CE. That is, the second terminal of the switch is connected to the wiring VAL, and the first terminal of the switch is connected to the first terminal of the capacitive element CE, the wiring OL [j], and the first input terminal of the comparator CMP. May be.
  • a circuit ACTF [j] illustrated in FIG. 3C is a circuit in which the resistance element RE and the resistance element REB included in the circuit ACTF [j] in FIG. 3A are replaced with a diode element DE and a diode element DEB, respectively.
  • An operation similar to that of the circuit ACTF [j] can be performed. It is desirable that the orientations of the diode element DE and the diode element DEB (connection points between the anode and the cathode) be appropriately changed depending on the magnitude of the potential of the wiring VAL.
  • comparator CMP included in the circuits ACTF [j] in FIGS. 3A to 3C can be replaced with the operational amplifier OP as an example.
  • the circuit ACTF [j] illustrated in FIG. 3D is a circuit diagram in which the comparator CMP of the circuit ACTF [j] in FIG. 3A is replaced with the operational amplifier OP.
  • the switch S01a and the switch S01b may be provided in the circuit ACTF [j] of FIG. 3B. Accordingly, the circuit ACTF [j] can hold potentials corresponding to currents input from the wiring OL [j] and the wiring OLB [j] to the capacitor CE and the capacitor CEB, respectively.
  • the wiring OL [j] is electrically connected to the first terminal of the switch S01a, and the second terminal of the switch S01a is connected to the first terminal of the capacitive element CE.
  • the first input terminal of the comparator CMP is electrically connected
  • the wiring OLB [j] is electrically connected to the first terminal of the switch S01b
  • the second terminal of the switch S01b is connected to the first terminal of the capacitive element CEB.
  • the configuration may be such that the second input terminal of the comparator CMP is electrically connected.
  • the switch S01a and the switch S01b are turned on. This can be done by turning it on.
  • the switches S01a and S01b are turned off to hold the potential input to each of the first input terminal and the second input terminal of the comparator CMP in the capacitor CE and the capacitor CEB. be able to.
  • the switch S01a and the switch S01b for example, an electrical switch such as an analog switch or a transistor can be used.
  • the switches S01a and S01b for example, mechanical switches may be applied.
  • the transistor when a transistor is used as the switch S01a or the switch S01b, the transistor can be an OS transistor or a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor).
  • the voltage values of the capacitor CE and the capacitor CEB can be controlled by controlling the period in which the switch S01a and the switch S01b are kept on. For example, when the value of the current flowing through the capacitive element CE and the capacitive element CEB is large, the voltage of the capacitive element CE and the capacitive element CEB can be reduced by shortening the period in which the switch S01a and the switch S01b are kept on. It is possible to prevent the value from becoming too large.
  • the comparator CMP included in the circuits ACTF [j] of FIGS. 3A to 3C and 3E can be, for example, a chopper type comparator.
  • the comparator CMP shown in FIG. 3F shows a chopper type comparator, and the comparator CMP includes a switch S02a, a switch S02b, a switch S03, a capacitive element CC, and an inverter circuit INV3.
  • the switch S02a, the switch S02b, and the switch S03 can be mechanical switches, transistors such as OS transistors, Si transistors, and the like, like the switches S01a and S01b described above.
  • the first terminal of the switch S02a is electrically connected to the terminal VinT
  • the first terminal of the switch S02b is electrically connected to the terminal VrefT
  • the second terminal of the switch S02a is the second terminal of the switch S02b. It is electrically connected to the first terminal of the capacitive element CC.
  • the second terminal of the capacitive element CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03.
  • the terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.
  • the terminal VinT functions as a terminal for inputting an input potential to the comparator CMP
  • the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP
  • the terminal VoutT is an output potential from the comparator CMP. Functions as a terminal for outputting.
  • the terminal VinT corresponds to one of the first terminal and the second terminal of the comparator CMP of FIGS. 3A to 3C and 3E
  • the terminal VrefT is the first terminal of the comparator CMP of FIGS. 3A to 3C and 3E. It can correspond to the other of the one terminal or the second terminal.
  • ACTF [j] is a calculation circuit of the activation function for outputting an output signal z j (k) expressed by binary
  • circuit ACTF [j] is the output signal z j ( k) may be output in three or more values or as an analog value.
  • 4A to 4F are circuits that generate a signal z j (k) in accordance with a current input from the wiring OL [j] and the wiring OLB [j], and are output signals z j represented by three values.
  • An example of an activation function arithmetic circuit that outputs (k) is shown.
  • the circuit ACTF [j] shown in FIG. 4A has a resistance element RE, a resistance element REB, a comparator CMPa, and a comparator CMPb.
  • the wiring OL [j] is electrically connected to the first terminal of the resistance element RE and the first input terminal of the comparator CMPa
  • the wiring OLB [j] is connected to the first terminal of the resistance element REB and the comparator. It is electrically connected to the first input terminal of CMPb.
  • the second input terminal of the comparator CMPa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL.
  • the second terminal of the resistance element RE is electrically connected to the wiring VAL
  • the second terminal of the resistance element REB is electrically connected to the wiring VAL.
  • VrefL functions as a voltage line that applies a constant voltage Vref, and Vref is preferably GND or more and VDD or less, for example. Further, depending on the situation, V ref may be a potential lower than GND or a potential higher than VDD. V ref is treated as a reference potential (comparison potential) in the comparator CMPa and the comparator CMPb.
  • the voltage between the first terminal and the second terminal of the resistance element RE is determined according to the current flowing from the wiring OL [j]. Therefore, the resistance value of the resistance element RE and the voltage corresponding to the current are input to the first input terminal of the comparator CMPa.
  • the voltage between the first terminal and the second terminal of the resistance element REB is determined according to the current flowing from the wiring OLB [j]. Therefore, the resistance value of the resistance element REB and the voltage corresponding to the current are input to the first input terminal of the comparator CMPb.
  • the comparator CMPa compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPa according to the comparison result. For example, the comparator CMPa outputs a high level potential from the output terminal of the comparator CMPa when the voltage (V ref ) input to the second input terminal is higher than the voltage input to the first input terminal, When the voltage input to the first input terminal is higher than the voltage (V ref ) input to the second input terminal, the low-level potential can be output from the output terminal of the comparator CMPa.
  • the comparator CMPb compares the voltages input to the first input terminal and the second input terminal and outputs a signal from the output terminal of the comparator CMPb according to the comparison result. To do. For example, the comparator CMPb outputs a high level potential from the output terminal of the comparator CMPb when the voltage (V ref ) input to the second input terminal is higher than the voltage input to the first input terminal, When the voltage input to the first input terminal is higher than the voltage (V ref ) input to the second input terminal, the low-level potential can be output from the output terminal of the comparator CMPb.
  • a ternary output signal z j (k) can be represented according to the potentials output from the output terminals of the comparator CMPa and the comparator CMPb. For example, when a high level potential is output from the output terminal of the comparator CMPa and a low level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to “+1” and the output of the comparator CMPa is output.
  • the output signal z j (k) is “ ⁇ 1”, and the low-level potential is output from the output terminal of the comparator CMPa.
  • the output signal z j (k) can be “+0”.
  • the circuit ACTF [j] is not limited to the circuit configuration illustrated in FIG. 4A and can be changed depending on the situation.
  • the conversion circuit TRF may be provided in the circuit ACTF [j].
  • the circuit ACTF [j] of FIG. 4B is a configuration example in which the conversion circuit TRF is provided in the circuit ACTF [j] of FIG. 4A, and the output terminals of the comparators CMPa and CMPb are electrically connected to the input terminals of the conversion circuit TRF. Connected to each other.
  • a digital-analog conversion circuit in this case, the signal z j (k) becomes an analog value
  • the wiring VrefL electrically connected to the second input terminals of the comparator CMPa and the comparator CMPb may be replaced with separate wirings Vref1L and Vref2L.
  • the second terminal of the comparator CMPa included in the circuit ACTF [j] of FIG. 4A is electrically connected to the wiring Vref1L instead of the wiring VrefL, and the second terminal of the comparator CMPb is included.
  • the terminal is electrically connected to the wiring Vref2L instead of the wiring VrefL.
  • the reference potentials in the comparator CMPa and the comparator CMPb can be set separately by setting the potentials input to the wirings Vref1L and Vref2L to different values.
  • an amplifier circuit or an impedance conversion circuit may be used as a configuration different from the circuit ACTF [j] of FIGS. 4A to 4C.
  • the circuit ACTF [j] illustrated in FIG. 4D can be applied to the circuit AFP of the arithmetic circuit 110 in FIG.
  • the circuit ACTF [j] in FIG. 4D has a resistance element RE, a resistance element REB, an operational amplifier OPa, and an operational amplifier OPb, and functions as an amplifier circuit.
  • the wiring OL [j] is electrically connected to the first terminal of the resistance element RE and the non-inverting input terminal of the operational amplifier OPa, and the wiring OLB [j] is connected to the first terminal of the resistance element REB and the operational amplifier OPb. It is electrically connected to the non-inverting input terminal.
  • the inverting input terminal of the operational amplifier OPa is electrically connected to the output terminal of the operational amplifier OPa, and the inverting input terminal of the operational amplifier OPb is electrically connected to the output terminal of the operational amplifier OPb.
  • the second terminal of the resistance element RE is electrically connected to the wiring VAL, and the second terminal of the resistance element REB is electrically connected to the wiring VAL.
  • the operational amplifiers OPa and OPb included in the circuit ACTF [j] of FIG. 4D have a voltage follower connection configuration.
  • the potential output from the output terminal of the operational amplifier OPa becomes substantially equal to the potential input to the non-inverting input terminal of the operational amplifier OPa
  • the potential output from the output terminal of the operational amplifier OPb is the non-inverting input terminal of the operational amplifier OPb. It is almost equal to the potential input to the terminal.
  • the output signal z j (k) is output from the circuit ACTF [j] as two analog values.
  • the output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP, respectively. Then, the output from the comparator CMP may be used as the output signal z j (k) .
  • an integration circuit, a current-voltage conversion circuit, or the like may be used as a configuration different from the circuit ACTF [j] of FIGS. 4A to 4D.
  • the operational amplifier may be used to configure an integrating circuit or a current-voltage converting circuit.
  • the circuit ACTF [j] illustrated in FIG. 4E can be applied to the circuit AFP of the arithmetic circuit 110 in FIG.
  • the circuit ACTF [j] in FIG. 4E includes an operational amplifier OPa, an operational amplifier OPb, a load element LEa, and a load element LEb.
  • the wiring OL [j] is electrically connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa and the first terminal of the load element LEa, and the wiring OLB [j] is the first input terminal of the operational amplifier OPb.
  • One input terminal (for example, an inverting input terminal) is electrically connected to the first terminal of the load element LEb.
  • the second input terminal (for example, non-inverting input terminal) of the operational amplifier OPa is electrically connected to the wiring Vref1L
  • the second input terminal (for example, non-inverting input terminal) of the operational amplifier OPb is electrically connected to the wiring Vref2L. It is connected to the.
  • the second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPa
  • the second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPb.
  • the wiring Vref1L and the wiring Vref2L here function as wirings that supply a voltage equal to or different from each other. Therefore, the wiring Vref1L and the wiring Vref2L can be combined into one wiring in some cases.
  • the load element LEa and the load element LEb can be, for example, a resistance element or a capacitance element.
  • the capacitive element as the load element LEa and the load element LEb
  • the operational amplifier OPa and the load element LEa, and the operational amplifier OPb and the load element LEb respectively function as an integrating circuit. That is, electric charge is stored in each of the capacitor elements (load elements LEa and LEb) depending on the amount of current flowing through the wiring OL [j] or the wiring OLB [j].
  • the current flowing from the wiring OL [j] and the wiring OLB [j] is converted into a voltage by the integration circuit and the integrated current amount is output as a signal z j (k) .
  • the output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP, respectively. Then, the output from the comparator CMP may be used as the output signal z j (k) .
  • a circuit for initializing the charge accumulated in the capacitive elements of the load element LEa and the load element LEb may be provided.
  • a switch may be provided in parallel with the load element LEa (capacitive element).
  • the second terminal of the switch is connected to the output terminal of the operational amplifier OPa, and the first terminal of the switch is connected to the wiring OL [j] and the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa. May be.
  • the load element LEa and the load element LEb should be other than the capacitive element. Can use a resistance element.
  • the circuit ACTF [j] shown in FIG. 4F can be applied to the circuit AFP of the arithmetic circuit 110 in FIG.
  • the circuit ACTF [j] in FIG. 4F includes a resistance element RE, a resistance element REB, an analog-digital conversion circuit ADCa, and an analog-digital conversion circuit ADCb.
  • the wiring OL [j] is electrically connected to the input terminal of the analog-digital conversion circuit ADCa and the first terminal of the resistance element RE, and the wiring OLB [j] is the input terminal of the analog-digital conversion circuit ADCb. It is electrically connected to the first terminal of the resistance element REB.
  • the second terminal of the resistance element RE is electrically connected to the wiring VAL, and the second terminal of the resistance element REB is electrically connected to the wiring VAL.
  • the potentials of the first terminals of the resistance element RE and the resistance element REB are determined according to the currents flowing from the wiring OL [j] and the wiring OLB [j]. Then, the circuit ACTF [j] converts the potential, which is an analog value, into a binary value or a digital value of three values or more (for example, 256 values) by the analog-digital conversion circuits ADCa and ADCb, and outputs the signal z j. It has a function of outputting as (k) .
  • the resistance element RE and the resistance element REB illustrated in FIGS. 4A to 4F can be replaced with the capacitance element CE, the capacitance element CEB, or the diode element DE and the diode element DEB, as in FIGS. 3B and 3C.
  • the resistance element RE and the resistance element REB illustrated in FIGS. 4A to 4F are replaced with the capacitance element CE and the capacitance element CEB, by further providing the switch S01a and the switch S01b similarly to FIG. 3E, the wiring OL [j ], And the potential input from the wiring OLB [j] can be held.
  • the arithmetic circuit 110 of FIG. 2 can change the number of wirings electrically connected to the circuit MP [i, j] according to the circuit configuration of the circuit MP [i, j].
  • the wiring WLS [i] electrically connected to the circuit MP [i, j] can be one or a plurality of wirings.
  • the wiring XLS [i] electrically connected to the circuit MP [i, j] can be one wiring or a plurality of wirings.
  • FIG. 5A shows a configuration example of the circuit MP [i, j] applicable to the arithmetic circuit 110, and the circuit MP [i, j] includes, for example, a circuit MC and a circuit MCr.
  • the circuit MC and the circuit MCr are circuits for calculating the product of the weight coefficient and the input signal (calculated value) of the neuron in the circuit MP.
  • the circuit MC can have a structure similar to that of the circuit MCr or a structure different from that of the circuit MCr. Therefore, in order to distinguish the circuit MCr from the circuit MC, “r” is added to the code.
  • reference numerals of circuit elements, which will be described later, included in the circuit MCr are also denoted by “r”.
  • the circuit MC has, for example, a holding unit HC, and the circuit MCr has a holding unit HCr.
  • the holding unit HC and the holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, or the like).
  • the first data w i (k ⁇ 1) j (k) set in the circuit MP [i, j] is information (for example, potential, resistance value) held in each of the holding unit HC and the holding unit HCr. , Or current value). Therefore, each of the holding unit HC and the holding unit HCr is a wiring that supplies each information (for example, potential, resistance value, or current value) according to the first data w i (k ⁇ 1) j (k). It is electrically connected to IL [j] and the wiring ILB [j].
  • the wiring WL [i] illustrated in FIG. 5A corresponds to the wiring WLS [i] in FIG.
  • the wiring WL [i] is electrically connected to each of the holding portion HC and the holding portion HCr.
  • Information for example, a potential, a resistance value, or a current
  • Information corresponding to the first data w i (k ⁇ 1) j (k) is stored in each of the holding unit HC and the holding unit HCr included in the circuit MP [i, j].
  • Value is written, by supplying a predetermined potential to the wiring WL [i], the wiring IL [j] and the holding portion HC are brought into conduction and the wiring ILB [j] and holding portion HCr are brought into conduction. Put in a state.
  • the holding portion HC and the holding portion HCr are discharged.
  • the potential or the like can be input to each.
  • a predetermined potential is supplied to the wiring WL [i] so that the wiring IL [j] and the holding portion HC are in a non-conduction state and the wiring ILB [j] and the holding portion HCr are in a non-conduction state.
  • each of the holding unit HC and the holding unit HCr holds a potential or the like corresponding to the first data w i (k ⁇ 1) j (k) .
  • the holding unit HC holds the high level potential and the holding unit HCr holds the low level potential.
  • the holding unit HC holds the low level potential and the holding unit HCr holds the high level potential.
  • the holding unit HC holds the low-level potential and the holding unit HCr holds the low-level potential.
  • the first data w i (k ⁇ 1) j (k) is an analog value, specifically, a “negative analog value”, “0”, or a “positive analog value”.
  • the holding unit HC holds a high level analog potential and the holding unit HCr holds a low level potential.
  • the holding unit HC holds the low-level potential and the holding unit HCr holds the high-level analog potential. Hold.
  • the analog value may be a multi-bit (multi-value) digital value. That is, as an example, when the first data w i (k ⁇ 1) j (k) is “1”, “2”, “3”, as an example, the holding unit HC has “1”, “3”. A high level potential having a potential corresponding to 2 ”and“ 3 ”is held, and a low level potential is held in the holding portion HCr.
  • the holding unit HC holds the low level potential.
  • the holding unit HCr holds high-level potentials corresponding to the absolute values “1”, “2”, and “3” of “ ⁇ 1”, “-2”, and “-3”. Then, when the first data w i (k ⁇ 1) j (k) is “0”, as an example, the holding unit HC holds the low-level potential and the holding unit HCr holds the low-level potential.
  • the circuit MC supplies a current or a voltage corresponding to the information (for example, a potential, a resistance value, a current value, or the like) held in the holding unit HC to the wiring OL [j] or the wiring OLB [j].
  • the circuit MCr has a function of outputting to one side, and the circuit MCr outputs a current or a voltage corresponding to the information (eg, potential, resistance value, current value, or the like) held in the holding unit HCr to the wiring OL [j] or the wiring OLB. It has a function of outputting to the other of [j].
  • the circuit MC when the holding unit HC holds the high level potential, the circuit MC outputs a current having the first current value, and when the holding unit HC holds the low level potential, the circuit MC outputs the second current. A current with a value shall be output.
  • the circuit MCr when the holding portion HCr holds the high level potential, the circuit MCr outputs a current having the first current value, and when the holding portion HCr holds the low level potential, the circuit MCr holds the second level. A current having a current value shall be output.
  • the magnitudes of the first current value and the second current value are determined by the configurations of the circuit MC, the circuit MCr, the holding unit HC, the holding unit HCr, and the first data w i (k ⁇ 1) j (k).
  • the first current value may be larger or smaller than the second current value. Further, one of the first current value and the second current value may be zero current, that is, the current value may be zero. Alternatively, the current flowing direction may be different between the current having the first current value and the current having the second current value.
  • the first current value or the second current value It is preferable to configure the circuit MC and the circuit MCr so that one of them becomes zero.
  • the first data w i (k ⁇ 1) j (k) has an analog value, for example, “negative analog value”, “0”, or “positive analog value”
  • the first current The value or the second current value can also be an analog value, for example.
  • a current or a voltage in accordance with information (eg, a potential, a resistance value, a current value, or the like) held in the holding portion HC and the holding portion HCr may be a positive current, a voltage, or the like. It may be a negative current or voltage, or both positive and negative may be mixed. That is, for example, a current or a voltage corresponding to the information (for example, the potential, the resistance value, the current value, and the like) held in the holding unit HC is supplied to one of the wiring OL [j] and the wiring OLB [j].
  • the circuit MCr has a function of outputting, and the circuit MCr outputs a current, a voltage, or the like in accordance with the information (eg, potential, resistance value, current value, or the like) held in the holding portion HCr by the wiring OL [j] or the wiring OLB [j.
  • the circuit MCr has a function of discharging from one of the wirings OLB [j], and the circuit MCr has a function of discharging a current corresponding to the potential held in the holding portion HCr from the other of the wiring OL [j] and the wiring OLB [j]. In other words It can be.
  • the wiring X1L [i] and the wiring X2L [i] illustrated in FIG. 5A correspond to the wiring XLS [i] in FIG.
  • the second data z i (k ⁇ 1) input to the circuit MP [i, j] is determined by, for example, the potentials and currents of the wiring X1L [i] and the wiring X2L [i], respectively. Be done. Therefore, the potentials corresponding to the second data z i (k ⁇ 1) are input to the circuit MC and the circuit MCr, for example, through the wiring X1L [i] and the wiring X2L [i].
  • the circuit MC is electrically connected to the wiring OL [j] and the wiring OLB [j]
  • the circuit MCr is electrically connected to the wiring OL [j] and the wiring OLB [j].
  • the circuit MC and the circuit MCr provide the first data in the wiring OL [j] and the wiring OLB [j] in accordance with the potential, the current, and the like input to the wiring X1L [i] and the wiring X2L [i]. It outputs a current, a potential or the like according to the product of w i (k ⁇ 1) j (k) and the second data z i (k ⁇ 1) .
  • the output destination of the current from the circuit MC and the circuit MCr is determined by the potentials of the wiring X1L [i] and the wiring X2L [i].
  • a current output from the circuit MC flows to one of the wiring OL [j] and the wiring OLB [j]
  • a current output from the circuit MCr flows to the wiring OL [j] or
  • the circuit configuration is such that it flows to the other side of the wiring OLB [j]. That is, the respective currents output from the circuit MC and the circuit MCr flow not in the same wiring but in different wirings. Note that as an example, current may not flow from the circuit MC and the circuit MCr to either the wiring OL [j] or the wiring OLB [j].
  • the second data z i (k ⁇ 1) takes one of three values “ ⁇ 1”, “0”, and “1”.
  • the circuit MP brings the circuit MC and the wiring OL [j] into a conductive state and connects the circuit MCr and the wiring OLB [j].
  • the circuit MP brings the circuit MC and the wiring OLB [j] into a conductive state and connects the circuit MCr and the wiring OL [j].
  • the two are made conductive.
  • the circuit MP makes the circuit MC and the wiring OL [j] and the circuit MC and the wiring OLB [j] into a non-conductive state, and the circuit MCr and the wiring OL [j]. And the circuit MCr and the wiring OLB [j] are brought out of conduction.
  • the first data w i (k ⁇ 1) j (k) is “1” and the second data z i (k ⁇ 1) is “1”.
  • the current I1 [i, j] having the first current value flows from the circuit MC to the wiring OL [j] and the current I2 [i, j] having the second current value from the circuit MCr to the wiring OLB [j].
  • the magnitude of the second current value is, for example, zero. That is, strictly speaking, no current flows from the circuit MCr to the wiring OLB [j].
  • the first line from the circuit MC to the wiring OL [j] is A current I1 [i, j] having two current values flows, and a current I2 [i, j] having a second current value flows from the circuit MCr to the wiring OLB [j].
  • the magnitude of the second current value is, for example, zero. That is, strictly speaking, no current flows from the circuit MC to the wiring OL [j], and no current flows from the circuit MCr to the wiring OLB [j].
  • the circuit MC When the first data w i (k ⁇ 1) j (k) is “1” and the second data z i (k ⁇ 1) is “ ⁇ 1”, the circuit MC to the wiring OLB [j ], The current I1 [i, j] having the first current value flows, and the circuit MCr flows the current I2 [i, j] having the second current value to the wiring OL [j]. At this time, the magnitude of the second current value is, for example, zero. That is, strictly speaking, no current flows from the circuit MCr to the wiring OL [j]. When the first data w i (k ⁇ 1) j (k) is “ ⁇ 1” and the second data z i (k ⁇ 1) is “ ⁇ 1”, the circuit OL to the wiring OLB [j].
  • the current I1 [i, j] having the second current value flows through the circuit MCr, and the current I2 [i, j] having the first current value flows through the wiring OL [j] from the circuit MCr.
  • the magnitude of the second current value is, for example, zero. That is, strictly speaking, no current flows from the circuit MC to the wiring OLB [j].
  • the current I1 [i, j] having the second current value flows, and the current I2 [i, j] having the second current value flows from the circuit MCr to the wiring OL [j].
  • the magnitude of the second current value is, for example, zero. That is, strictly speaking, no current flows from the circuit MC to the wiring OLB [j], and no current flows from the circuit MCr to the wiring OL [j].
  • the circuit MC or the circuit A current flows through the wiring OL [j] from any of MCr.
  • the first data w i (k ⁇ 1) j (k) has a positive value
  • a current flows from the circuit MC to the wiring OL [j] and the first data w i (k ⁇ 1) j.
  • (k) has a negative value
  • a current flows from the circuit MCr to the wiring OL [j].
  • the sum total of the currents output from the plurality of circuits MC or the circuits MCr connected to the wiring OL [j] flows to the wiring OL [j]. That is, a current having a sum of positive values flows through the wiring OL [j].
  • the sum of the currents output from the plurality of circuits MC or the circuits MCr connected to the wiring OLB [j] flows to the wiring OLB [j]. That is, in the wiring OLB [j], a current having a value obtained by adding the negative values flows.
  • the total current value flowing through the wiring OL [j] that is, the sum of positive values
  • the total current value flowing through the wiring OLB [j] that is, the sum of negative values
  • the product-sum calculation process can be performed. For example, when the total current value flowing through the wiring OL [j] is larger than the total current value flowing through the wiring OLB [j], it is determined that the product-sum operation has a positive value. You can When the total current value flowing through the wiring OL [j] is smaller than the total current value flowing through the wiring OLB [j], it can be determined that the product-sum operation has a negative value. . When the total current value flowing through the wiring OL [j] and the total current value flowing through the wiring OLB [j] are approximately the same value, it is determined that the result of the product-sum calculation is zero. You can
  • the second data z i (k ⁇ 1) is a binary value of “ ⁇ 1”, “0”, and “1”, for example, a binary value of “ ⁇ 1” and “1”.
  • the same operation can be performed in the case of binary values of "0” and "1”.
  • the first data w i (k ⁇ 1) j (k) is one of two values “ ⁇ 1”, “0”, and “1”, for example, “ ⁇ 1”, “1”. The same operation can be performed in the case of the binary value of 0 or in the case of the binary value of “0” and “1”.
  • the first data w i (k ⁇ 1) j (k) may take an analog value or a multi-bit (multi-value) digital value.
  • a “negative analog value” may be taken instead of “ ⁇ 1”
  • a “positive analog value” may be taken instead of “1”.
  • the magnitude of the current flowing from the circuit MC or the circuit MCr is, for example, an analog value corresponding to the absolute value of the value of the first data w i (k ⁇ 1) j (k) .
  • circuit MP [i, j] of FIG. 5A is modified.
  • the parts different from the circuit MP [i, j] of FIG. 5A will be mainly described, and the parts common to the circuit MP [i, j] of FIG. 5A will be described. The description may be omitted.
  • the circuit MP [i, j] shown in FIG. 5B is a modification of the circuit MP [i, j] shown in FIG. 5A.
  • the circuit MP [i, j] in FIG. 5B includes a circuit MC and a circuit MCr, similar to the circuit MP [i, j] in FIG. 5A.
  • the circuit MP [i, j] of FIG. 5B differs from the circuit MP [i, j] of FIG. 5A in that the circuit MCr does not include the holding unit HCr.
  • the circuit MCr does not include the holding portion HCr, the arithmetic circuit to which the circuit MP [i, j] in FIG. 5B is applied has the wiring ILB [j] for supplying the potential held in the holding portion HCr. You don't have to have it. In addition, the circuit MCr does not need to be electrically connected to the wiring WL [i].
  • the holding unit HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP [i, j] in FIG. 5B is configured such that the circuit MCr and the circuit MC share the holding unit HC with each other.
  • an inverted signal of the signal held in the holding unit HC can be supplied from the holding unit HC to the circuit MCr. This allows the circuit MC and the circuit MCr to perform different operations.
  • the circuit MC and the circuit MCr have different internal circuit configurations, and as a result, the magnitudes of the currents output by the circuit MC and the circuit MCr are the same with respect to the same signal held in the holding unit HC.
  • a potential corresponding to the first data w i (k ⁇ 1) j (k) is held in the holding unit HC, and a potential corresponding to the second data z i (k ⁇ 1) is applied to the wiring X1L [i] and
  • the circuit MP [i, j] supplies the first data w i (k ⁇ 1) j (k) and the second data to the wiring OL [j] and the wiring OLB [j] by supplying the wiring X2L [i]. It is possible to output a current according to the product of the data z i (k-1) .
  • the arithmetic circuit 110 to which the circuit MP of FIG. 5B is applied can be changed to the circuit configuration of the arithmetic circuit 120 shown in FIG.
  • the arithmetic circuit 120 has a structure in which the wirings ILB [1] to ILB [m] are removed from the arithmetic circuit 110 in FIG.
  • the circuit MP [i, j] shown in FIG. 5C is a modification of the circuit MP [i, j] of FIG. 5A, and specifically, the circuit MP [i, j] applicable to the arithmetic circuit 120 of FIG. It is a configuration example of.
  • the circuit MP [i, j] in FIG. 5C includes a circuit MC and a circuit MCr, similar to the circuit MP [i, j] in FIG. 5A.
  • the circuit MP [i, j] of FIG. 5C and the circuit MP [i, j] of FIG. 5A have different wiring configurations electrically connected.
  • the wiring W1L [i] and the wiring W2L [i] illustrated in FIG. 5C correspond to the wiring WLS [i] in FIG.
  • the wiring W1L [i] is electrically connected to the holding portion HC, and the wiring W2L [i] is electrically connected to the holding portion HCr.
  • the wiring IL [j] is electrically connected to the holding unit HC and the holding unit HCr.
  • the holding unit HC and the holding unit HCr perform the holding operation of the potentials sequentially, not simultaneously.
  • the first data w i (k ⁇ 1) j (k) of the circuit MP [i, j] can be expressed by holding the first potential in the holding unit HC and the second potential in the holding unit HCr.
  • a predetermined potential is applied to each of the wiring W1L [i] and the wiring W2L [i] to bring the holding portion HC and the wiring IL [j] into a conductive state, and the holding portion HCr and the wiring IL [j].
  • the first potential can be applied to the holding portion HC by supplying the first potential to the wiring IL [j].
  • a predetermined potential is applied to each of the wiring W1L [i] and the wiring W2L [i] so that the holding portion HC and the wiring IL [j] are brought into a non-conducting state and the holding portion HCr and the wiring IL [].
  • j] is brought into conduction.
  • the circuit MP [i, j] can set w i (k ⁇ 1) j (k) as the first data.
  • the holding unit HC and the holding unit HCr when holding substantially equal potentials to the holding unit HC and the holding unit HCr (the first data w i (k ⁇ 1) j (k) of the circuit MP [i, j] is the holding unit HC and the holding unit HC, respectively.
  • the holding portion HC and the wiring IL [j] When set by holding potentials that are substantially equal to each of the HCr), the holding portion HC and the wiring IL [j] are brought into conduction, and the holding portion HCr and the wiring IL [j] are brought into conduction.
  • a predetermined potential may be applied to each of the wiring W1L [i] and the wiring W2L [i] so that the wiring is in the state, and then the potential is supplied to the wiring IL [j].
  • the circuit MP [i, j] in FIG. 5C holds the potential according to the first data w i (k ⁇ 1) j (k) in the holding unit HC and the holding unit HCr, and the second data z i (k).
  • the wiring OL [j] and the wiring OLB [j] are provided as in the circuit MP [i, j] in FIG. 5A.
  • the circuit MP [i, j] shown in FIG. 5D is a modification of the circuit MP [i, j] shown in FIG. 5A.
  • the circuit MP [i, j] in FIG. 5D includes a circuit MC and a circuit MCr, similar to the circuit MP [i, j] in FIG. 5A.
  • the circuit MP [i, j] of FIG. 5D and the circuit MP [i, j] of FIG. 5A have different wiring configurations electrically connected.
  • the wiring IOL [j] in FIG. 5D functions as a wiring in which the wiring IL [j] and the wiring OL [j] in FIG. 5A are integrated, and the wiring IOLB [j] in FIG. 5D is the wiring in FIG. 5A.
  • the ILB [j] and the wiring OLB [j] function as one wiring. Therefore, the wiring IOL [j] is electrically connected to the holding portion HC, the circuit MC, and the circuit MCr, and the wiring IOL [j] is connected to the holding portion HCr, the circuit MC, and the circuit MCr. It is electrically connected.
  • the holding unit HC and the holding unit each potential can be input to each of the HCr.
  • the wiring WL [i] is predetermined so that the holding portion HC and the wiring IOL [j] are brought out of conduction and the holding portion HCr and the wiring IOLB [j] are brought out of conduction.
  • each of the holding unit HC and the holding unit HCr can hold each potential according to the first data w i (k ⁇ 1) j (k) .
  • the potential corresponding to the second data z i (k-1) is wired.
  • the first data w i (k -1) It is possible to output a current according to the product of j (k) and the second data z i (k-1) .
  • the arithmetic circuit 110 to which the circuit MP of FIG. 5D is applied can be changed to the circuit configuration of the arithmetic circuit 130 shown in FIG. 7.
  • the arithmetic circuit 130 in FIG. 2 includes the wirings IL [1] to IL [n] and the wirings OL [1] to OL [n] in the wirings IOL [1] to IOL [n. ],
  • the wirings ILB [1] to ILB [n] and the wirings OLB [1] to OLB [n] are combined as wirings IOLB [1] to IOLB [n]. .
  • the wirings IOL [1] to IOL [n] and the wirings IOLB [1] to IOLB [n] are electrically connected to the circuit ILD and the circuits ACTF [1] to ACTF [n]. It is connected. That is, the wirings IOL [1] to IOL [n] and the wirings IOLB [1] to IOLB [n] have the first data w i ( for the circuits MP [1, j] to MP [m, j]). It has a function of a signal line for transmitting k-1) j (k) and a current line for supplying a current to the circuit ACTF [j].
  • the circuit ILD when the first data wi (k ⁇ 1) j (k) is transmitted to the circuit MP [i, j], the circuit ILD includes the circuit ILD and the wiring IOL [j] and the circuits ILD and IOLB.
  • the circuit ACTF [j] does not conduct between the circuit ACTF [j] and the wiring IOL [j] and between the circuits ACTF [j] and IOLB [j]. It is preferable to put it in a state.
  • the circuit ILD sets the circuit ILD and the wiring IOL [j] and the circuits ILD and IOLB [j] to the non-conducting state, and the circuit ACTF [j].
  • [J] is preferably in a conductive state between the circuit ACTF [j] and the wiring IOL [j] and between the circuits ACTF [j] and IOLB [j].
  • the circuit MP [i, j] shown in FIG. 5E is a modification of the circuit MP [i, j] shown in FIG. 5A, and specifically, the circuit MP [i, j] applicable to the arithmetic circuit 110 shown in FIG. It is a configuration example of.
  • the circuit MP [i, j] in FIG. 5E includes a circuit MC and a circuit MCr, similar to the circuit MP [i, j] in FIG. 5A.
  • the circuit MC is not electrically connected to the wiring OLB [j] and the circuit MCr is not electrically connected to the wiring OL [j]. And are different from the circuit MP [i, j] of FIG. 5A.
  • the wiring WL [i] shown in FIG. 5E corresponds to the wiring WLS [i] in FIG.
  • the wiring WL [i] is electrically connected to the holding portion HC and the holding portion HCr.
  • the wiring XL [i] shown in FIG. 5E corresponds to the wiring XLS [i] in FIG.
  • the wiring XL [i] is electrically connected to the circuit MC and the circuit MCr.
  • the circuit MC is not electrically connected to the wiring OLB [j] and the circuit MCr is not electrically connected to the wiring OL [j], as described later. That is, in the circuit MP [i, j] of FIG. 5E, unlike the circuits MP [i, j] of FIGS. 5A to 5E, the current output from the circuit MC does not flow to the wiring OLB [j] and the circuit MCr outputs the current. The output current does not flow to the wiring OL [j].
  • the circuit MP [i, j] of FIG. 5E is preferably applied to the arithmetic circuit when the second data z i (k ⁇ 1) is a binary value of “0” or “1”.
  • the circuit MP brings the circuit MC and the wiring OL [j] into a conductive state and connects the circuit MCr and the wiring OLB [j]. Make the space conductive.
  • the second data z i (k ⁇ 1) is “0”
  • the current output from each of the circuit MC and the circuit MCr is applied to both the wirings OL [j] and OLB [j].
  • the circuit MP makes the circuit MC and the wiring OL [j] and the circuit MC and the wiring OLB [j] into a non-conducting state, and the circuit MP and the wiring OL [j]. , And the circuit MCr and the wiring OLB [j] are brought out of conduction.
  • the first data w i (k ⁇ 1) j (k) is “ ⁇ 1”, “0”, “. It is possible to perform an operation in the case where the second data z i (k ⁇ 1) takes any one of the three values of “1” and takes the two values of “0” and “1”.
  • any one of the first data w i (k ⁇ 1) j (k) of “ ⁇ 1”, “0”, and “1” is 2
  • the operation can be performed in the case of a binary value such as "-1" or "1” or in the case of a binary value of "0" or "1".
  • the first data w i (k ⁇ 1) j (k) may take an analog value or a multi-bit (multi-value) digital value.
  • a “negative analog value” may be taken instead of “ ⁇ 1”
  • a “positive analog value” may be taken instead of “1”.
  • the magnitude of the current flowing from the circuit MC or the circuit MCr is, for example, an analog value corresponding to the absolute value of the value of the first data w i (k ⁇ 1) j (k) .
  • the arithmetic circuit 110 of FIG. 8 is shown focusing on the circuit located in the j-th column of the arithmetic circuit 110 of FIG. That is, the arithmetic circuit 110 of FIG. 8 outputs signals from the neurons N 1 (k ⁇ 1) to N m (k ⁇ 1) input to the neurons N j (k) in the neural network 100 shown in FIG. 1A.
  • a product-sum operation of the signals z 1 (k-1) to z m (k-1) and the weighting factors w 1 (k-1) j (k) to w m (k-1) j (k) And a calculation of the activation function using the result of the product-sum calculation.
  • the circuit MP included in the array unit ALP of the arithmetic circuit 110 in FIG. 8 is the circuit MP in FIG. 5A.
  • the first data w 1 (k ⁇ 1) j (k) to w m (k ⁇ 1) j (k) are added to the circuits MP [1, j] to MP [m, j]. Is set.
  • a predetermined potential is sequentially input to the wirings WLS [1] to WLS [m] by the circuit WLD, and the circuit MP [1 , J] to the circuit MP [m, j] are sequentially selected, and for the holding portion HC of the circuit MC and the holding portion HCr of the circuit MCr included in the selected circuit MP, from the circuit ILD, A potential corresponding to the first data is supplied through the wiring IL [j] and the wiring ILB [j].
  • the circuits MP [1, j] to MP [m, j] are deselected by the circuit WLD, whereby the circuits MP [1, j] to MP [m, j].
  • the holding unit HC stores that positive value.
  • a value corresponding to a positive value is input, and a value corresponding to zero is input to the holding unit HCr.
  • the holding unit HC corresponds to zero.
  • the value corresponding to the absolute value of the negative value is input to the holding unit HCr.
  • the second data z 1 (k-1) to z m (k- 1) is supplied.
  • the second data z i (k ⁇ 1) is supplied to the wiring X1L [i] and the wiring X2L [i].
  • the wiring X1L [i] and the wiring X2L [i] correspond to the wiring XLS [i] of the arithmetic circuit 110 illustrated in FIG.
  • the circuit MP [1, j] According to the second data z 1 (k ⁇ 1) to z m (k ⁇ 1) input to each of the circuits MP [1, j] to MP [m, j], the circuit MP [1, j].
  • the conduction states of the circuit MC and the circuit MCr included in the circuit MP [m, j], the wiring OL [j], and the circuit OLB [j] are determined.
  • the circuit MP [i, j] according to the second data z i (k ⁇ 1) , “the circuit MC and the wiring OL [j] are electrically connected, and the circuit MCr and the wiring are connected.
  • One of the “state in which the circuit MC and the circuit MCr are not electrically connected to the wiring OL [j] and the wiring OLB [j]” is obtained.
  • the second data z 1 (k ⁇ 1) takes a positive value
  • the wiring X1L [1] is electrically connected between the circuit MC and the wiring OL [j]
  • a value that brings the circuit MCr and the wiring OLB [j] into a conductive state is input.
  • a value that makes the circuit MC and the wiring OLB [j] non-conductive and the circuit MCr and the wiring OL [j] non-conductive is input to the wiring X2L [1]. ..
  • the wiring X2L [1] is electrically connected between the circuit MC and the wiring OLB [j]
  • a value that allows conduction between MCr and the wiring OL [j] is input.
  • a value that makes the circuit MC and the wiring OL [j] non-conductive and the circuit MCr and the wiring OLB [j] non-conductive is input to the wiring X1L [1]. ..
  • the wiring X2L [1] is not electrically connected between the circuit MC and the wiring OLB [j], and A value that causes a non-conduction state between the circuit MCr and the wiring OL [j] is input. Then, a value that makes the circuit MC and the wiring OL [j] non-conductive and the circuit MCr and the wiring OLB [j] non-conductive is input to the wiring X1L [1]. ..
  • current is input / output between the circuit MC and the circuit MCr and the wiring OL [j] and the wiring OLB [j].
  • the amount of the current is determined according to the first data w i (k ⁇ 1) j (k) and / or the second data z i (k ⁇ 1) set in the circuit MP [i, j]. .
  • the current flowing from the wiring OL [j] to the circuit MC or the circuit MCr is I [i, j]
  • the current flowing from the wiring OLB [j] to the circuit MC or the circuit MCr Be IB [i, j].
  • I out [j] is a current flowing from the circuit ACTF [j] to the wiring OL [j]
  • I Bout [j] is a current flowing from the wiring OLB [j] to the circuit ACTF [j]
  • I out [j] j] and I Bout [j] can be expressed by the following equations.
  • the circuit MC when the first data w i (k ⁇ 1) j (k) is “+1”, the circuit MC outputs I (+1) and the circuit MCr outputs I (+1). ⁇ 1) is discharged, and when the first data w i (k ⁇ 1) j (k) is “ ⁇ 1”, the circuit MC discharges I ( ⁇ 1) and the circuit MCr discharges I (+1). ) Is discharged, and when the first data w i (k ⁇ 1) j (k) is “0”, the circuit MC discharges I ( ⁇ 1) and the circuit MCr discharges I ( ⁇ 1). Shall be discharged.
  • the circuit MP [i, j] has “a conduction between the circuit MC and the wiring OL [j], and the circuit MCr and the wiring.
  • the circuit MC and the wiring OLB [j] are non-conductive
  • the circuit MCr and the wiring OL [j] are non-conductive ".
  • I B [i, j] is as shown in the table below.
  • the circuit MP [i, j] may be configured so that the current amount of I ( ⁇ 1) becomes zero.
  • the current I [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL [j].
  • the current I B [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB [j].
  • each of I out [j] and I Bout [j] flowing from each of the wiring OL [j] and the wiring OLB [j] is input to the circuit ACTF [j], whereby the circuit ACTF [j]. j], for example, compares I out [j] and I Bout [j].
  • the circuit ACTF [j] outputs the signal z j (k) that the neuron N j (k) transmits to the (k + 1) -th layer neuron according to the result of the comparison.
  • the arithmetic circuit 110 of FIG. 8 inputs the signals z 1 (k-1) from the neurons N 1 (k-1) to the neurons N m (k-1) to the neurons N j (k ). To z m (k-1) and weighting factors w 1 (k-1) j (k) to w m (k-1) j (k), and the result of the product-sum operation.
  • the activation function used can be calculated.
  • a circuit equivalent to the arithmetic circuit 110 of FIG. 2 can be configured. That is, the arithmetic circuit 110 of FIG. 2 simultaneously performs the product-sum operation and the activation function operation using the result of the product-sum operation in each of the neurons N 1 (k) to N n (k). It can be carried out.
  • the transistors included in each of the array unit ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like described above are preferably OS transistors.
  • a transistor whose off-state current is desired to be low, specifically, a transistor having a function of holding charge accumulated in a capacitor is preferably an OS transistor.
  • the OS transistor when an OS transistor is used as the transistor, the OS transistor preferably has the structure of the transistor described in Embodiment 3 in particular.
  • one embodiment of the present invention is not limited to this.
  • the transistors included in the array unit ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like are transistors other than OS transistors, for example, a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor). It may be called).
  • a Si transistor a transistor including silicon in a channel formation region
  • the silicon for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used.
  • the transistors other than the OS transistor and the Si transistor include, for example, a transistor having a semiconductor such as Ge as an active layer, a transistor having a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, and SiGe as an active layer, and a carbon nanotube.
  • a transistor including an active layer, a transistor including an organic semiconductor as an active layer, or the like can be used.
  • an n-type semiconductor can be formed using a metal oxide containing indium (eg, In oxide) or a metal oxide containing zinc (eg, Zn oxide) in the metal oxide of the semiconductor layer of the OS transistor.
  • the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 apply OS transistors as n-channel transistors included in the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like, and p-channel A configuration in which a Si transistor is applied as the type transistor may be used.
  • the reference numeral of the circuit MP includes [1,1], [i, j], [m, n], etc. indicating the position in the array unit ALP, but in the present embodiment, Unless otherwise specified, the description of [1, 1], [i, j], [m, n], etc. with respect to the code of the circuit MP is omitted.
  • the circuit MP illustrated in FIG. 9A is an example of a configuration of the circuit MP in FIG. 5A
  • the circuit MC included in the circuit MP in FIG. 9A includes, for example, a transistor M3, a transistor M4, a transistor M8, and a capacitor element. And C3.
  • the holding unit HC is configured by the transistor M8 and the capacitive element C3.
  • the transistor M3, the transistor M4, and the transistor M8 illustrated in FIG. 9A are, for example, multi-gate n-channel transistors each having a gate above and below a channel, and each of the transistor M3, the transistor M4, and the transistor M8 is It has a first gate and a second gate.
  • the transistors M3 and M4 have the same size.
  • the first gate is described as a gate (may be referred to as a front gate) and the second gate is described as a back gate, but the first gate And the second gate can be interchanged. Therefore, in this specification and the like, the phrase “gate” can be replaced with the phrase “backgate”.
  • the phrase “back gate” can be interchanged with the phrase “gate”.
  • the connection configuration "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring” is "the back gate is electrically connected to the first wiring. And the gate is electrically connected to the second wiring ”.
  • connection structure of the back gate of the transistor included in the semiconductor device of one embodiment of the present invention is not particularly limited.
  • a back gate is illustrated in the transistor M8 illustrated in FIG. 9A, and a connection configuration of the back gate is not illustrated, but an electrical connection destination of the back gate can be determined at a design stage. it can.
  • the gate and the back gate may be electrically connected to each other in order to increase the on-state current of the transistor. That is, for example, the gate of the transistor M8 and the back gate may be electrically connected.
  • a wiring electrically connected to an external circuit or the like is provided in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Then, a potential may be applied to the back gate of the transistor by the external circuit or the like. Note that this is the same not only in FIG. 9A but also in transistors described in other parts of the specification or transistors illustrated in other drawings.
  • the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not particularly limited.
  • the transistor M8 illustrated in FIG. 9A may have a structure without a back gate, that is, a single-gate transistor as illustrated in FIG. 9B. Further, some of the transistors may have a back gate and some of the other transistors may not have a back gate. Note that this applies not only to the circuit diagram shown in FIG. 9A, but also to transistors described in other parts of the specification or transistors illustrated in other drawings.
  • transistors with various structures can be used as transistors. Therefore, there is no limitation on the type of transistor used.
  • a transistor including single crystal silicon, or a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystal (also referred to as microcrystal, nanocrystal, or semiamorphous) silicon, or the like is used.
  • a transistor or the like included therein can be used.
  • a thin film transistor (TFT) in which those semiconductors are thinned can be used. There are various advantages when using a TFT.
  • the manufacturing apparatus since it can be manufactured at a temperature lower than that of the case of single crystal silicon, it is possible to reduce the manufacturing cost or increase the size of the manufacturing apparatus. Since the manufacturing apparatus can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, the manufacturing cost can be reduced.
  • the manufacturing temperature is low, a substrate having low heat resistance can be used. Therefore, a transistor can be manufactured over a light-transmitting substrate. Alternatively, light transmission through a display element can be controlled using a transistor over a light-transmitting substrate. Alternatively, since the thickness of the transistor is small, part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.
  • a compound semiconductor eg, SiGe, GaAs, or the like
  • an oxide semiconductor eg, Zn—O, In—Ga—Zn—O, In—Zn—O, In—Sn—O
  • ITO ITO
  • Sn-O Sn-O
  • Ti-O Ti-O
  • Al-Zn-Sn-O AZTO
  • In-Sn-Zn-O or the like
  • the manufacturing temperature can be lowered, so that the transistor can be manufactured at room temperature, for example.
  • the transistor can be formed directly on a substrate having low heat resistance, such as a plastic substrate or a film substrate.
  • a substrate having low heat resistance such as a plastic substrate or a film substrate.
  • these compound semiconductors or oxide semiconductors can be used not only for the channel portion of a transistor but also for other purposes.
  • these compound semiconductors or oxide semiconductors can be used for wirings, resistance elements, pixel electrodes, light-transmitting electrodes, or the like. Since they can be formed or formed at the same time as the transistor, cost can be reduced.
  • the transistor a transistor or the like formed by an inkjet method or a printing method can be used. As a result, they can be manufactured at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, manufacturing can be performed without using a mask (reticle), so that the layout of the transistor can be easily changed. Alternatively, since it can be manufactured without using a resist, the material cost can be reduced and the number of steps can be reduced. Alternatively, since the film can be attached only to a necessary portion, the material is not wasted and the cost can be reduced as compared with the manufacturing method of etching after forming the film on the entire surface.
  • a transistor having an organic semiconductor or a carbon nanotube, or the like can be used as an example of the transistor. With these, a transistor can be formed over a bendable substrate. A device using a transistor having an organic semiconductor or a carbon nanotube can withstand shock.
  • transistors having various structures can be used as the transistor.
  • a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor.
  • MOS transistor the size of the transistor can be reduced. Therefore, a large number of transistors can be mounted.
  • bipolar transistor a large amount of current can flow. Therefore, the circuit can be operated at high speed.
  • the MOS type transistor and the bipolar transistor may be mixed and formed on one substrate. As a result, low power consumption, miniaturization, high speed operation, etc. can be realized.
  • a transistor having a structure in which gate electrodes are provided above and below an active layer can be applied.
  • the gate electrodes With the structure in which the gate electrodes are arranged above and below the active layer, a circuit configuration in which a plurality of transistors are connected in parallel is obtained. Therefore, since the channel formation region is increased, the current value can be increased.
  • a structure in which the gate electrodes are provided above and below the active layer facilitates formation of a depletion layer, so that the S value can be improved.
  • examples of transistors include a structure in which a gate electrode is provided over an active layer, a structure in which a gate electrode is provided under an active layer, a positive stagger structure, an inverted stagger structure, and a plurality of channel regions.
  • a transistor having a divided structure, a structure in which active layers are connected in parallel, a structure in which active layers are connected in series, or the like can be used.
  • a planar type, a FIN type (fin type), a TRI-GATE type (tri-gate type), a top gate type, a bottom gate type, a double gate type (the gates are arranged above and below a channel), and the like are used. , Can take various configurations.
  • a transistor having a structure in which a source electrode and a drain electrode overlap with an active layer (or part thereof) can be used.
  • the structure in which the source electrode and the drain electrode overlap with the active layer (or part thereof) can prevent the operation from becoming unstable due to the accumulation of charges in part of the active layer.
  • a structure having an LDD region can be applied.
  • the LDD region By providing the LDD region, off-current can be reduced or breakdown voltage of the transistor can be improved (reliability can be improved).
  • the LDD region when operating in the saturation region, even if the voltage between the drain and the source changes, the drain current does not change so much and a voltage-current characteristic with a flat slope can be obtained. it can.
  • a transistor can be formed using a variety of substrates.
  • the type of substrate is not limited to a particular one.
  • the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a stainless steel foil.
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • Examples of the flexible substrate, the laminated film, the base film and the like include the following.
  • plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • a synthetic resin such as acrylic resin.
  • polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like can be used.
  • polyamide, polyimide, aramid, epoxy resin, an inorganic vapor deposition film, paper, or the like can be given.
  • a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, shape, or the like, high current capability, and small size can be manufactured.
  • a circuit is formed using such a transistor, low power consumption of the circuit or high integration of the circuit can be achieved.
  • a flexible substrate may be used as the substrate, and the transistor may be formed directly on the flexible substrate.
  • a separation layer may be provided between the substrate and the transistor.
  • the peeling layer can be used for separating a semiconductor device over a part or the whole of the semiconductor layer, separating it from the substrate, and transferring the semiconductor device to another substrate.
  • the transistor can be transferred to a substrate having low heat resistance or a flexible substrate.
  • a structure having a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or the like can be used for the above-mentioned release layer.
  • a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and the transistor may be arranged on another substrate.
  • a substrate on which a transistor is transferred in addition to a substrate on which the above transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) (Including silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (including acetate, cupra, rayon, recycled polyester), leather substrate, or rubber substrate.
  • the cost can be reduced by reducing the number of parts, or the reliability can be improved by reducing the number of connection points with circuit parts.
  • part of a circuit necessary for realizing a predetermined function is formed over one substrate and another part of the circuit necessary for realizing a predetermined function is formed over another substrate. It is possible. For example, a part of a circuit necessary for realizing a predetermined function is formed over a glass substrate and another part of a circuit necessary for realizing the predetermined function is a single crystal substrate (or an SOI substrate). Can be formed. Then, a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary for realizing a predetermined function is formed is connected to the glass substrate by COG (Chip On Glass), and the glass substrate is connected.
  • COG Chip On Glass
  • the IC chip can be placed in the.
  • the IC chip can be connected to the glass substrate using a TAB (Tape Automated Bonding), a COF (Chip On Film), an SMT (Surface Mount Technology), a printed circuit board, or the like. Since part of the circuit is formed over the same substrate as the pixel portion in this manner, cost can be reduced by reducing the number of parts or reliability can be improved by reducing the number of connection points with circuit parts. . In particular, the power consumption of the circuit in the part where the driving voltage is high, the circuit in the part where the driving frequency is high, or the like is often large. Therefore, such a circuit is formed over a substrate (for example, a single crystal substrate) different from the pixel portion to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.
  • the first terminal of the transistor M8 is electrically connected to the wiring IL.
  • the second terminal of the transistor M8 is electrically connected to the first terminal of the capacitive element C3, the back gate of the transistor M3, and the back gate of the transistor M4.
  • the gate of the transistor M8 is electrically connected to the wiring WL.
  • the second terminal of the capacitor C3 is electrically connected to the wiring VLs.
  • the first terminal of the transistor M3 and the first terminal of the transistor M4 are electrically connected to the wiring VL.
  • the second terminal of the transistor M3 is electrically connected to the wiring OL.
  • the gate of the transistor M3 is electrically connected to the wiring X1L.
  • the second terminal of the transistor M4 is electrically connected to the wiring OLB.
  • the gate of the transistor M4 is electrically connected to the wiring X2L.
  • the first terminal of the transistor M4 may be electrically connected to another wiring VLm instead of the wiring VL.
  • the first terminal of the transistor M4r may be electrically connected to another wiring VLmr instead of the wiring VLr.
  • the first terminal of M4r may be electrically connected to another wiring VLmr instead of the wiring VLr.
  • the wiring VL and the wiring VLr may be one and the same wiring
  • the wiring VLm and the wiring VLmr may be one and the same wiring (not shown).
  • an electrical connection point between the second terminal of the transistor M8, the first terminal of the capacitor C3, the back gate of the transistor M3, and the back gate of the transistor M4 is a node nd3. I am trying.
  • the holding unit HC has a function of holding a potential according to the first data w, as an example.
  • the potential in the holding portion HC included in the circuit MC in FIG. 9A when the transistor M8 is turned on, the potential is input from the wiring IL and written to the capacitor C3, and then the transistor M8 is turned on. This is done by turning off M8. Accordingly, the potential of the node nd3 can be held as the potential according to the first data.
  • the transistor M8 holds the potential of the node nd3 for a long time, it is preferable to use a transistor with a small off-state current.
  • a transistor with low off-state current for example, an OS transistor can be used.
  • a transistor having a back gate may be used as the transistor M8, a low-level potential may be applied to the back gate, the threshold voltage may be shifted to the positive side, and the off-state current may be reduced.
  • the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, in order to distinguish the circuit element of the circuit MCr from the circuit element of the circuit MC, “r” is added to the symbol.
  • the connection configuration of the circuit MCr different from that of the circuit MC will be described.
  • the second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL
  • the second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB.
  • the first terminal of the transistor M3r and the first terminal of the transistor M4r are electrically connected to the wiring VLr.
  • both ends of the wiring OL shown in FIG. 9A will be referred to as nodes ina and outa, and both ends of the wiring OLB will be referred to as nodes inb and outb.
  • the wiring VL functions as a wiring that supplies a constant voltage, for example.
  • the constant voltage when the transistor M3, the transistor M3r, the transistor M4, or the transistor M4r is an n-channel transistor, for example, VSS which is a low level potential, the ground potential, or a low level potential other than those And so on.
  • the wiring VLs, the wiring VLr, and the wiring VLsr each function as a voltage line that supplies a constant voltage, and the constant voltage is a low-level potential other than VSS and VSS that are low-level potentials. , Ground potential, etc.
  • the constant voltage may be VDD, which is a high level potential.
  • the circuit ACTF is applied.
  • [1] to the circuit ACTF [n] are electrically connected to the constant voltage VAL, which is preferably higher than the potentials of the wiring VL and the wiring VLr, for example, VDD.
  • the constant voltages supplied by the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr may be different from each other, or some or all of them may be the same. Further, when the voltages supplied to the respective wirings are the same, the wirings may be selected and made the same wiring. For example, when the constant voltage applied to each of the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr is substantially equal, the wiring VLs, the wiring VLr, and the wiring VLsr are the same wiring as the wiring VL as in the circuit MP of FIG. 11A. be able to.
  • the wiring VL and the wiring VLr can be one and the same wiring.
  • the wiring VLs and the wiring VLsr can be one and the same wiring.
  • the wiring VL and the wiring VLr may be one and the same wiring
  • the wiring VLm and the wiring VLmr may be one and the same wiring.
  • the wiring VL and the wiring VLmr may be one and the same wiring
  • the wiring VLm and the wiring VLr may be one and the same wiring.
  • each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r of the circuit MP in FIG. 9A may be replaced with a p-channel transistor M3p, a transistor M3pr, a transistor M4p, and a transistor M4pr.
  • a transistor M3p, the transistor M3pr, the transistor M4p, and the transistor M4pr for example, a p-channel transistor having an SOI (Silicon On Insulator) structure can be applied.
  • the constant voltage applied to the wiring VL and the wiring VLr be VDD, which is a high-level potential.
  • FIGS. 3A to 3E, 4A to 4D, and 4F are applied as the circuits ACTF [1] to ACTF [n] of the arithmetic circuit 110, the arithmetic circuit 120, or the arithmetic circuit 130.
  • the constant voltage provided by VAL electrically connected to the circuits ACTF [1] to ACTF [n] is preferably ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of current flow is also changed.
  • the transistor M8 may be replaced with a p-channel type transistor.
  • the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r shown in FIGS. 9A, 9B, 10, 11A, and 11B have the same size, for example, the channel length L or the channel width.
  • the layout can be efficiently performed.
  • the currents flowing through the transistors M3, M3r, M4, and M4r can be made uniform.
  • FIG. 12A is a graph simply showing the characteristics of the gate-source voltage and the drain current of one of the transistors M3, M3r, M4, and M4r included in the circuit MP of FIG. 9A.
  • the horizontal axis represents the gate-source voltage Vgs of the transistor, and the vertical axis represents the drain current Id of the transistor.
  • the vertical axis shown in FIG. 12A has a linear scale.
  • the potential applied to the gate of the transistor is Vg
  • the potential applied to the back gate of the transistor is Vbg.
  • the constant potential applied to the source of the transistor is set to 0 V as an example.
  • FIG. 12A shows two curves, and one curve shows the gate-source voltage Vgs and the drain when the Vbg of the transistor is at a high level potential (shown as High in FIG. 12A). The characteristics with the current Id are shown, and the other curve shows the gate-source voltage Vgs and the drain current Id when Vbg of the transistor is at a low level potential (illustrated as Low in FIG. 12A). Shows the characteristics. From FIG. 12A, it is found that the threshold voltage Vth2 of the transistor when Vbg is a high-level potential is lower than the threshold voltage Vth1 of the transistor when Vbg is a low-level potential. That is, by changing Vbg of the transistor, Vgs (which can be translated into Vg because the potential of the source is 0 V) necessary to turn on the transistor can be changed.
  • Vbg of the transistor Vgs (which can be translated into Vg because the potential of the source is 0 V) necessary to turn on the transistor can be changed.
  • Vg of the transistor when Vbg of the transistor is at a high level potential, the transistor is turned on, and when Vbg of the transistor is at a low level potential, the transistor Vg is turned off so that the transistor is turned off.
  • Vg of the transistor is shown as Vg1. That is, Vg1 may be higher than the threshold voltage Vth2 of the transistor in which Vbg is a high-level potential and lower than the threshold voltage Vth1 of the transistor in which Vbg is a low-level potential.
  • Vg of the transistor is determined such that when the Vbg of the transistor is at a high level potential, the transistor is in an off state, and when the Vbg of the transistor is at a low level potential, the transistor is in an off state. ..
  • Vg of the transistor is shown as Vg2. That is, Vg2 may be set to a potential lower than the threshold voltage Vth2 of the transistor M3 (transistor M4) in which Vbg is a high-level potential.
  • Vg of the gates of the transistors M3 and M3r is given from the wiring X1L. Therefore, Vg1 and Vg2 can be potentials applied from the wiring X1L.
  • the potential Vg of the gates of the transistors M4 and M4r is supplied from the wiring X2L. Therefore, Vg1 and Vg2 can be a potential applied from the wiring X2L.
  • Vg1 and Vg2 can be referred to as a high-level potential and a low-level potential, respectively.
  • the terms “low-level potential” and “high-level potential” do not mean a specific potential, and different wirings may have different specific potentials. Therefore, the high-level potential applied to the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r may be different from the high-level potential (Vg1) applied to the wiring X1L and the wiring X2L. Similarly, the low-level potential applied to the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r may be different from the low-level potential (Vg2) applied to the wiring X1L and the wiring X2L.
  • the high-level potentials applied to the back gates of the transistors M3, M3r, M4, and M4r may be the same as the source potentials of the transistors M3, M3r, M4, and M4r.
  • the low-level potential applied to the back gates of the transistors M3, M3r, M4, and M4r may be lower than the source potentials of the transistors M3, M3r, M4, and M4r. Therefore, for example, when the source potentials of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are 0 V, the low-level potential applied to the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r is minus.
  • the potential may be, for example, ⁇ 11 V or more and ⁇ 2 V or less, and more preferably about ⁇ 3 V.
  • the potential (Vg1 or Vg2) applied to the wiring X1L and the wiring X2L and the potentials of the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are binary (digital value).
  • one embodiment of the present invention is not limited to this.
  • the gate of the transistor is Vga1
  • the drain current Id of the transistor can be increased or decreased by changing the potential of the back gate of the transistor to any one of Vbg1, Vbg2, and Vbg3. it can.
  • the gate potentials of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are made constant, and the potentials of the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are changed to change the transistor M3, the transistor M3r, and the transistor M4.
  • the drain current Id of the transistor M4r can be changed to increase or decrease the amount of current flowing through the wiring OL and the wiring OLB. That is, by changing the potentials of the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r as analog values, the circuit MP can perform calculation using the analog values.
  • the back gate potential of the transistor when the back gate potential of the transistor is set to any one of Vbg1, Vbg2, and Vbg3, the gate potential of the transistor is changed to one of Vga1, Vga2, and Vga3.
  • the drain current Id of the transistor can be increased or decreased.
  • the back gate potentials of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are kept constant, and the gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are set.
  • the amount of current flowing through the wiring OL and the wiring OLB can be increased or decreased by changing the potential of the transistor M3 and changing the drain current Id of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r. That is, by changing the potentials of the gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r as analog values, the circuit MP can perform calculation using the analog values. In addition, the potentials of the gate and the back gate of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are kept constant, and the potential of the source electrode is changed as the analog value to change the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r.
  • the drain current Id may be changed (not shown).
  • FIGS. 14A to 14C, and 15A to 15C are timing charts showing operation examples of the circuit MP, and a wiring IL, a wiring ILB, a wiring WL, a wiring X1L, a wiring X2L, and a node, respectively. Changes in the potentials of nd3 and node nd3r are shown. 13A to 13C, 14A to 14C, and 15A to 15C, high indicates a high-level potential and low indicates a low-level potential. Further, in this operation example, from the wiring OL to node outa (or the wiring OL from node outa) the amount of current output is set to I OL.
  • the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is IOLB .
  • the timing charts shown in FIGS. 13A to 13C, 14A to 14C, and 15A to 15C also show the amounts of change in the current amounts I OL and I OLB .
  • the constant voltage given by the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr is VSS (low level potential).
  • a current flows from the wiring VAL to the wiring VL via the wiring OL.
  • a current flows from the wiring VAL to the wiring VLr via the wiring OLB.
  • the weighting coefficient held by the circuit MP is defined as follows.
  • a high level potential is held at the node nd3 of the holding unit HC and a low level potential is held at the node nd3r of the holding unit HCr
  • the circuit MP holds “+1” as a weighting coefficient.
  • the circuit MP holds “ ⁇ 1” as the weighting coefficient.
  • the circuit MP When the low-level potential is held at the node nd3 of the holding unit HC and the low-level potential is held at the node nd3r of the holding unit HCr, the circuit MP is assumed to hold "0" as the weighting coefficient.
  • the high-level potential held in the nodes nd3 and nd3r can be VDD or a potential slightly lower than VDD, for example, and the low-level potential held in the nodes nd3 and nd3r can be Can be, for example, VSS.
  • the high-level potential held at the nodes nd3 and nd3r can be VSS, and the low-level potential held at the nodes nd3 and nd3r can be lower than VSS, for example, It can be a negative potential.
  • the weighting factor may be an analog value. In that case, for example, when the weighting factor is “positive analog value”, the high level analog potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr.
  • the weighting coefficient is “negative analog value”, for example, the low-level potential is held at the node nd3 of the holding unit HC and the high-level analog potential is held at the node nd3r of the holding unit HCr.
  • the weighting coefficient is “0”, for example, the low level potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr.
  • the neuron signal (calculated value) input to the circuit MP is defined as follows as an example.
  • a high-level potential (Vg1) is applied to the wiring X1L and a low-level potential (Vg2) is applied to the wiring X2L
  • “+1” is input to the circuit MP as a neuron signal.
  • the low-level potential (Vg2) is applied to the wiring X1L and the high-level potential (Vg1) is applied to the wiring X2L
  • "-1" is input to the circuit MP as a neuron signal.
  • the low-level potential (Vg2) is applied to the wiring X1L and the low-level potential (Vg2) is applied to the wiring X2L
  • “0” is input as a neuron signal to the circuit MP.
  • the high-level potential (Vg1) is VDD or a potential higher than VDD by 10% or more, or 20% or more.
  • each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r included in the circuit MP is supplied with a high-level potential at the back gate as described in FIG. 12A, It is assumed that when the threshold voltage is shifted to the negative side, a high level potential (Vg1) is applied to the gate to turn it on. As described with reference to FIG. 12A, each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r has a back gate to which a low-level potential is applied and the threshold voltage is shifted to the positive side. It is assumed that the gate is turned off by applying a high-level potential (Vg1) to the gate.
  • each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r is applied with a high level potential as described in FIG. 12A, the threshold voltage is shifted to the negative side. , Is turned off by applying a low-level potential (Vg2) to the gate. In that case, each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r is given a low level potential to the back gate and the threshold voltage is shifted to the positive side, as described with reference to FIG. 12A. Even in this case, the gate is turned off by applying the low-level potential (Vg2) to the gate.
  • Vg2 low-level potential
  • each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r has a high level potential applied to the back gate and a high level potential applied to the gate. It is turned on by being applied, and turned off by applying a low-level potential to at least one of the gate and the back gate.
  • the above-described operation of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r is an example, and one embodiment of the present invention is not limited to this.
  • each of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r supplies a current having an analog value according to a voltage (analog voltage or multi-valued digital voltage) applied to the gate and the back gate. May serve as a source.
  • the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r include the case where the transistor M3, the transistor M3r, the transistor M4r, and the transistor finally operate in a saturation region. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-described transistors include the case where they are appropriately biased to the voltage in the range operating in the saturation region.
  • the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r may operate in the linear region.
  • the weighting factor is an analog value
  • the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r operate in the linear region and in the saturation region depending on the magnitude of the weighting factor. It may be mixed with the case.
  • the transistor M8 and the transistor M8r include the case where the transistor M8 and the transistor M8r finally operate in a linear region when they are in an on state. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-described transistors include the case where they are appropriately biased to the voltage in the range of operating in the linear region.
  • circuit MP In the following, an operation example of the circuit MP will be described for each combination of the weight coefficient and the value that can be taken by each of the neuron signals.
  • FIG. 13A is a timing chart of the circuit MP in that case.
  • the wiring IL and the wiring ILB each have an initialization potential V ini for initializing the potential of the node nd3 of the holding portion HC and the potential of the node nd3r of the holding portion HCr. It has been entered. Note that in FIG. 13A, V ini is higher than the low-level potential and lower than the high-level potential, but V ini is lower than the low-level potential or higher than the high-level potential. You may set it. Alternatively, V ini may be set as the same potential as the low-level potential or the same potential as the high-level potential. Further, the initialization potentials V ini applied to the wiring IL and the wiring ILB may be different from each other. Note that the initialization potential V ini does not need to be input to each of the wiring IL and the wiring ILB. That is, it is not necessary to provide a period from time T1 to time T2.
  • the potentials of the node nd3 and the node nd3r are not particularly determined from the time T1 to the time T2.
  • the potentials of the node nd3 and the node nd3r are higher than the low-level potential and lower than V ini .
  • a low level potential (Vg2) is input to each of the wiring X1L and the wiring X2L.
  • the threshold voltages of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r are determined depending on the potentials of the back gates of the transistors M3, M4, M3r, and M4r. In some cases, it is turned on instead of off.
  • a high-level potential is input to the wiring WL from time T2 to time T3. Accordingly, the transistor M8 and the transistor M8r are each turned on, the wiring IL and the node nd3 are brought into conduction, and the wiring ILB and the node nd3r are brought into conduction. Therefore, the potentials of the node nd3 and the node nd3r are V ini , respectively.
  • V ini is input to the back gates of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r.
  • Each of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r is assumed to be in a normally off state by inputting V ini to the back gate. Therefore, each of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r is turned off. Note that the potentials of the node nd3 and the node nd3r do not have to be the initialization potential V ini . That is, the period from time T2 to time T3 may not be provided.
  • a low-level potential is input to the wiring WL from time T4 to time T5. Accordingly, the transistor M8 and the transistor M8r are turned off, and the potentials of the node nd3 and the node nd3r are held by the capacitor C3 and the capacitor C3r.
  • the potentials of the back gates of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r become low-level potentials.
  • the value voltage shifts to the plus side with respect to the threshold voltage from time T2 to time T3.
  • the potentials of the first terminals of the transistors M3, M4, M3r, and M4r are 0 V, and the potentials of the gates of the transistors M3, M4, and M4 are low level potentials (Vg2).
  • Vg2 low level potentials
  • the initialization potential V ini is input to the wiring IL and the wiring ILB. Note that this operation is not a particularly necessary operation, and thus the initialization potential V ini does not need to be input to the wiring IL and the wiring ILB. That is, the period from time T5 to time T6 may not be provided. Further, different potentials may be input to each of the wiring IL and the wiring ILB.
  • a high-level potential (Vg1) is input to the wiring X1L and a low-level potential (Vg2) is input to the wiring X2L as inputs of the neuron signal (calculated value) “+1” to the circuit MP.
  • the high-level potential (Vg1) is input to the gates of the transistor M3 and the transistor M3r
  • the low-level potential (Vg2) is input to the gates of the transistor M4 and the transistor M4r. Since low-level potentials are input to the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are turned off.
  • the circuit MC and the wiring OL and the circuit MC and the wiring OLB are brought out of electrical conduction, and the circuit MCr and the wiring OL and the circuit MCr and the wiring OLB are disconnected. It becomes a non-conduction state.
  • the weighting coefficient is “0” and the neuron signal “+1” input to the circuit MP is used. Therefore, using the equation (1.1), the product of the weighting coefficient and the neuron signal is It becomes "0". The result that the product of the weighting coefficient and the signal of the neuron is “0” corresponds to the case where the current I OL and the current I OLB do not change after the time T6 in the operation of the circuit MP.
  • weighting coefficient w is input, a plurality of sum-of-products calculation processing may be performed by changing only the calculation value without updating the value. In this case, it is not necessary to update the weighting coefficient w, so that power consumption can be reduced. In order to reduce the updating of the weighting coefficient w, it is necessary to hold the weighting coefficient w for a long period of time. At this time, for example, when an OS transistor is used, the weighting factor w can be held for a long period of time by utilizing the fact that the off current is low.
  • FIG. 13B is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T3 is the same as the operation from time T1 to time T3 of condition 1, so the description of the operation from time T1 to time T3 of condition 1 will be referred to.
  • a high level potential is applied to the wiring IL and a low level potential is applied to the wiring ILB, and “1” is input as the weighting coefficient w. Since the high-level potential is continuously input to the wiring WL before time T3, the transistors M8 and M8r are on. Therefore, “1” is input as the weighting factor w, the potential of the node nd3 becomes a high level potential, and the potential of the node nd3r becomes a low level potential.
  • a low-level potential is input to the wiring WL from time T4 to time T5. Accordingly, the transistor M8 and the transistor M8r are turned off, and the potentials of the node nd3 and the node nd3r are held by the capacitor C3 and the capacitor C3r, respectively.
  • the threshold voltage of each of the transistors M3 and M4 shifts to the negative side from the threshold voltage from time T2 to time T3, and the threshold voltage of each of the transistors M3r and M4r becomes , Shifts to the plus side from the threshold voltage from time T2 to time T3.
  • the potentials of the first terminals of the transistors M3, M4, M3r, and M4r are 0V, and the potentials of the gates of the transistors M3, M4, and M4r are low-level potentials (Vg2).
  • Each of the transistor M3r and the transistor M4r is turned off.
  • the operation from time T5 to time T6 is the same as the operation from time T5 to time T6 of condition 1, so the description of the operation from time T5 to time T6 of condition 1 will be referred to.
  • a high-level potential (Vg1) is input to the wiring X1L and a low-level potential (Vg2) is input to the wiring X2L as inputs of the neuron signal (calculated value) “+1” to the circuit MP.
  • the high-level potential (Vg1) is input to the gates of the transistors M3 and M3r
  • the low-level potential (Vg2) is input to the gates of the transistor M4 and the transistor M4r.
  • a high-level potential is input to the back gates of the transistor M3 and the transistor M4, and a low-level potential is input to the back gates of the transistor M3r and the transistor M4r.
  • the M3r, the transistor M4, and the transistor M4r are turned off.
  • the circuit MC and the wiring OL are in a conductive state
  • the circuit MC and the wiring OLB are in a non-conductive state
  • the circuit MCr and the wiring OL are in a non-conductive state
  • the weighting coefficient w is “+1” and the neuron signal (calculated value) input to the circuit MP is “+1”.
  • the product of the signals is "+1".
  • the result that the product of the weighting coefficient and the signal of the neuron is “1” corresponds to the case where the current I OL changes and the current I OLB does not change after time T6 in the operation of the circuit MP.
  • FIG. 13C is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T3 is the same as the operation from time T1 to time T3 of condition 1, so the description of the operation from time T1 to time T3 of condition 1 will be referred to.
  • a low level potential is applied to the wiring IL and a high level potential is applied to the wiring ILB, and “ ⁇ 1” is input as the weighting coefficient w. Since the high-level potential is continuously input to the wiring WL before time T3, the transistors M8 and M8r are on. Therefore, “ ⁇ 1” is input as the weighting coefficient w, the potential of the node nd3 becomes a low level potential, and the potential of the node nd3r becomes a high level potential.
  • a low-level potential is input to the wiring WL from time T4 to time T5. Accordingly, the transistor M8 and the transistor M8r are turned off, and the potentials of the node nd3 and the node nd3r are held by the capacitor C3 and the capacitor C3r, respectively.
  • the threshold voltages of the transistor M3 and the transistor M4 shift to the plus side with respect to the threshold voltage from the time T2 to the time T3, and the threshold voltages of the transistor M3r and the transistor M4r respectively. The voltage shifts to the plus side with respect to the threshold voltage from time T2 to time T3.
  • the potentials of the first terminals of the transistors M3, M4, M3r, and M4r are 0V, and the potentials of the gates of the transistors M3, M4, and M4r are low-level potentials (Vg2). Each of the transistor M3r and the transistor M4r is in an off state.
  • the operation from time T5 to time T6 is the same as the operation from time T5 to time T6 of condition 1, so the description of the operation from time T5 to time T6 of condition 1 will be referred to.
  • the circuit MC and the wiring OL are brought out of conduction, the circuit MC and the wiring OLB are brought out of conduction, and the circuit MCr and the wiring OL are brought out of conduction.
  • the circuit MCr and the wiring OLB are electrically connected.
  • the weight coefficient w is “ ⁇ 1” and the signal (calculated value) of the neuron input to the circuit MP is “+1”.
  • the product of these signals is "-1".
  • the result that the product of the weighting factor and the signal of the neuron is “ ⁇ 1” corresponds to the case where the current I OL does not change after time T6 and the current I OLB changes in the operation of the circuit MP.
  • FIG. 14A is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 1, so the description of the operation from time T1 to time T6 of condition 1 will be referred to.
  • a low-level potential (Vg2) is input to the wiring X1L and a high-level potential (Vg1) is input to the wiring X2L as a neuron signal (calculated value) “ ⁇ 1” to the circuit MP.
  • the low-level potential (Vg2) is input to the gates of the transistor M3 and the transistor M3r
  • the high-level potential (Vg1) is input to the gates of the transistor M4 and the transistor M4r. Since low-level potentials are input to the back gates of the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r, the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are turned off.
  • the circuit MC and the wiring OL and the circuit MC and the wiring OLB are brought out of electrical conduction, so that the circuit MCr and the wiring OL and between the circuit MCr and the wiring OLB. Becomes non-conductive.
  • the weight coefficient w is “0” and the signal (calculated value) of the neuron input to the circuit MP is “ ⁇ 1”.
  • the product of these signals is “0”.
  • the result that the product of the weighting coefficient and the signal of the neuron is “0” corresponds to the case where the current I OL and the current I OLB do not change after time T6 in the operation of the circuit MP, which corresponds to the circuit of condition 1. Matches the result of the action.
  • FIG. 14B is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 2, so the description of the operation from time T1 to time T6 of condition 2 will be taken into consideration.
  • a low-level potential (Vg2) is input to the wiring X1L and a high-level potential (Vg1) is input to the wiring X2L as a neuron signal (calculated value) “ ⁇ 1” to the circuit MP.
  • the low-level potential (Vg2) is input to the gates of the transistor M3 and the transistor M3r
  • the high-level potential (Vg1) is input to the gates of the transistor M4 and the transistor M4r.
  • a high-level potential is input to the back gates of the transistor M3 and the transistor M4, and a low-level potential is input to the back gates of the transistor M3r and the transistor M4r.
  • M3, the transistor M3r, and the transistor M4r are turned off.
  • the circuit MC and the wiring OL are brought out of conduction, the circuit MC and the wiring OLB are brought into conduction, and the circuit MCr and the wiring OL are brought out of conduction. There is a non-conduction state between the circuit MCr and the wiring OLB.
  • the weight coefficient w is “+1” and the signal (calculated value) of the neuron input to the circuit MP is “ ⁇ 1”. Therefore, using the equation (1.1), the weight coefficient and the neuron are calculated. The product of these signals is "-1". The result that the product of the weighting coefficient and the signal of the neuron is “ ⁇ 1” corresponds to the case where the current I OL does not change after time T6 and the current I OLB changes in the operation of the circuit MP, which is a condition. This coincides with the result of the circuit operation of No. 3.
  • FIG. 14C is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 3, so the description of the operation from time T1 to time T6 of condition 3 will be taken into consideration.
  • a low-level potential (Vg2) is input to the wiring X1L and a high-level potential (Vg1) is input to the wiring X2L as a neuron signal (calculated value) “ ⁇ 1” to the circuit MP.
  • the low-level potential (Vg2) is input to the gates of the transistor M3 and the transistor M3r
  • the high-level potential (Vg1) is input to the gates of the transistor M4 and the transistor M4r.
  • a low-level potential is input to the back gates of the transistor M3 and the transistor M4, and a high-level potential is input to the back gates of the transistor M3r and the transistor M4r.
  • M3, the transistor M3r, and the transistor M4 are turned off.
  • the circuit MC and the wiring OL are brought out of conduction, the circuit MC and the wiring OLB are brought out of conduction, and the circuit MCr and the wiring OL are brought into conduction. There is a non-conduction state between the circuit MCr and the wiring OLB.
  • the weight coefficient w is “ ⁇ 1” and the neuron signal (calculated value) input to the circuit MP is “ ⁇ 1”.
  • the product of the signals of the neurons is "+1".
  • the result that the product of the weighting factor and the signal of the neuron is “+1” corresponds to the case where the current I OL changes and the current I OLB does not change after the time T6 in the operation of the circuit MP, which corresponds to the condition 2 It matches the result of circuit operation.
  • FIG. 15A is a timing chart of the circuit MP in that case.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 1, so the description of the operation from time T1 to time T6 of condition 1 will be referred to.
  • the low-level potential (Vg2) is input to the wiring X1L and the low-level potential (Vg2) is input to the wiring X2L as the input of the neuron signal (calculated value) “0” to the circuit MP.
  • the low-level potential (Vg2) is input to the gates of the transistor M3 and the transistor M3r
  • the low-level potential (Vg2) is input to the gates of the transistor M4 and the transistor M4r. That is, the transistors M3, M3r, M4, and M4r are turned off regardless of the potentials of the back gates of the transistors M3, M3r, M4, and M4r. That is, by this operation, the circuit MC and the wiring OL, the circuit MC and the wiring OLB, the circuit MCr and the wiring OL, and the circuit MCr and the wiring OLB are brought out of electrical conduction.
  • the weight coefficient w is “0” and the signal (calculated value) of the neuron input to the circuit MP is “0”.
  • the product of the signals is "0".
  • the result that the product of the weighting factor and the signal of the neuron is “0” corresponds to the case where the current I OL and the current I OLB do not change after the time T6 in the operation of the circuit MP, which corresponds to the condition 1 and This matches the result of the circuit operation under condition 4.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 2, so the description of the operation from time T1 to time T6 of condition 2 will be taken into consideration.
  • a low-level potential (Vg2) is input to the wiring X1L and a low-level potential (Vg2) is input to the wiring X2L as a neuron signal (calculated value) “0” to the circuit MP. That is, the transistors M3, M3r, M4, and M4r are turned off regardless of the back gate potentials of the transistors M3, M3r, M4, and M4r.
  • the circuit MC and the wiring OL and the circuit MC and the wiring OLB are brought out of conduction, and the circuit MCr and the wiring OL and between the circuit MCr and the wiring OLB are brought out of conduction.
  • the weight coefficient w is “+1” and the signal (calculated value) of the neuron input to the circuit MP is “0”.
  • the product of the signals is "0".
  • the result that the product of the weighting factor and the signal of the neuron is “0” corresponds to the case where the current I OL and the current I OLB do not change after the time T6 in the operation of the circuit MP. 4 and the result of the circuit operation of Condition 7.
  • the operation from time T1 to time T6 is the same as the operation from time T1 to time T6 of condition 3, so the description of the operation from time T1 to time T6 of condition 3 will be taken into consideration.
  • a low-level potential (Vg2) is input to the wiring X1L and a low-level potential (Vg2) is input to the wiring X2L as a neuron signal (calculated value) “0” to the circuit MP. That is, the transistors M3, M3r, M4, and M4r are turned off regardless of the back gate potentials of the transistors M3, M3r, M4, and M4r. With this operation, the circuit MC is brought out of conduction regardless of whether the wiring OL or the wiring OLB is provided, and the circuit MCr is brought out of conduction between the wiring OL or the wiring OLB.
  • the current I OL output from the node outa of the wiring OL and the node outb of the wiring OLB are output.
  • Each of the currents I OLB to be changed does not change before and after the time T6.
  • the weight coefficient w is “ ⁇ 1” and the neuron signal (calculated value) input to the circuit MP is “0”.
  • the product of these signals is “0”.
  • the result that the product of the weighting factor and the signal of the neuron is “0” corresponds to the case where the current I OL and the current I OLB do not change after the time T6 in the operation of the circuit MP. 4.
  • the results of the circuit operations of Condition 4, Condition 7 and Condition 8 match.
  • FIG. 2 an example is shown in which one circuit MC and one circuit MCr are connected to the wiring OL and the wiring OLB.
  • FIG. 2 FIG. 6, FIG. 7, FIG. 8, etc.
  • a plurality of circuits MC and circuits MCr are connected to the wiring OL and the wiring OLB
  • each circuit MC The current output from the circuit MCr is added up based on Kirchhoff's current law.
  • the sum operation is performed. That is, a product operation is performed in the circuit MC and the circuit MCr, and a sum operation is performed by adding the currents from the plurality of circuits MC and circuit MCr.
  • the product-sum calculation process is performed.
  • the weighting coefficient is set to only binary values of “+1” and “ ⁇ 1”, and the signal of the neuron is set to only binary values of “+1” and “ ⁇ 1”.
  • the MP can perform the same operation as the exclusive OR negation circuit (match circuit).
  • the circuit MP can be calculated by performing the calculation with the weighting coefficient only having two values of “+1” and “0” and the neuron signal having only two values of “+1” and “0”. The same operation as that of the logical product circuit can be performed.
  • the potential held in the circuit MC of the circuit MP, the holding unit HC included in the circuit MCr, and the holding unit HCr is set to the high-level potential or the low-level potential.
  • the portion HCr may hold a potential showing an analog value.
  • the weighting factor is “positive analog value”
  • the high level analog potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr.
  • the weighting factor is “negative analog value”
  • the low level potential is held at the node nd3 of the holding unit HC and the high level analog potential is held at the node nd3r of the holding unit HCr.
  • the magnitudes of the currents I OL and I OLB are according to the analog potential. Further, holding the potential indicating an analog value in the holding units HC and HCr is not limited to the operation example of the circuit MP in FIG. 9A, and may be performed for other circuits MP described in this specification and the like. Good.
  • the circuit MP shown in FIG. 16A shows a configuration example of the circuit MP of FIG. 5C.
  • the difference from the circuit MP of FIG. 9A is that the wiring IL and the wiring ILB are combined into one, and the wiring of FIG. 9A.
  • the point is to have a wiring W1L and a wiring W2L as WL.
  • the first terminal of the transistor M8 and the transistor M8r are electrically connected to the wiring IL.
  • the gate of the transistor M8 is electrically connected to the wiring W1L
  • the gate of the transistor M8r is electrically connected to the wiring W2L. Note that the description of the portions having the same connection configuration as the circuit MP of FIG. 16A and the circuit MP of FIG. 9A will be omitted.
  • the potentials supplied to the wiring W1L and the wiring W2L are changed to turn on the transistor M8 and turn off the transistor M8r, and then to the wiring IL.
  • the transistor M8 is turned off, the transistor M8r is turned on, and then the potential for holding the wiring IL in the holding portion HCr is supplied.
  • the transistor M8r is turned off.
  • the potentials corresponding to the weighting factors can be held in the holding units HC and HCr by sequentially supplying the potentials from the wiring IL to the holding units HC and HCr. it can.
  • the circuit MP shown in FIG. 16B shows a configuration example of the circuit MP of FIG. 5D.
  • the difference from the circuit MP of FIG. 9A is that the wiring IL and the wiring OL are combined into a wiring IOL and the wiring ILB and the wiring OLB are combined. This is the point that they are put together in the wiring IOLB.
  • the first terminal of the transistor M8 is electrically connected to the wiring IOL
  • the transistor M8r is electrically connected to the wiring IOLB
  • the second terminal of the transistor M3 is electrically connected to the wiring IOL
  • the second terminal of the transistor M4 is electrically connected to the wiring IOLB
  • the second terminal of the transistor M3r is electrically connected to the wiring IOLB.
  • the second terminal of the transistor M4r is electrically connected to the wiring IOL.
  • the wiring IOL is electrically connected to the holding portion HC
  • the wiring IOLB is electrically connected to the holding portion HCr
  • the gates of the transistor M8 and the transistor M8r are electrically connected to the wiring WL. Therefore, similarly to the circuit MP of FIG. 9A, the potentials corresponding to the weighting factors can be simultaneously written in the holding unit HC and the holding unit HCr.
  • the circuit MP illustrated in FIG. 17 is a circuit including not only the holding unit HC and the holding unit HCr but also the holding unit HCs and the holding unit HCsr.
  • the circuit MC included in the circuit MP in FIG. 17 includes a transistor M8s, a transistor M5a, a transistor M5b, a transistor M5sa, a transistor M5sb, and a capacitor C3s in addition to the circuit elements included in the circuit MP in FIG. 9A.
  • the circuit MCr included in the circuit MP of FIG. 17 has the same circuit elements as the circuit MC, and thus the transistor M8s, the transistor M5a, the transistor M5b, the transistor M5sa, the transistor M5sb, and the capacitor C3s of the circuit MC, respectively.
  • the transistor M8sr the transistor M5ar, the transistor M5br, the transistor M5sar, the transistor M5sbr, and the capacitor C3sr.
  • the transistor M5a, the transistor M5b, the transistor M5sa, the transistor M5sb, the transistor M5ar, the transistor M5br, the transistor M5sar, and the transistor M5sbr are finally linear regions in the ON state unless otherwise specified. It includes the case of operating in. That is, the gate voltage, the source voltage, and the drain voltage of each of the above-described transistors include the case where they are appropriately biased to the voltage in the range of operating in the linear region.
  • a first terminal of the transistor M5a is electrically connected to a second terminal of the transistor M3, a second terminal of the transistor M5a is electrically connected to the wiring OL, and a gate of the transistor M5a is electrically connected to the wiring S1L.
  • a first terminal of the transistor M5b is electrically connected to a second terminal of the transistor M4, a second terminal of the transistor M5b is electrically connected to the wiring OLB, and a gate of the transistor M5b is electrically connected to the wiring S1L. Has been done.
  • a first terminal of the transistor M5sa is electrically connected to a second terminal of the transistor M3s, a second terminal of the transistor M5sa is electrically connected to the wiring OL, and a gate of the transistor M5sa is electrically connected to the wiring S2L.
  • a first terminal of the transistor M5sb is electrically connected to a second terminal of the transistor M4s, a second terminal of the transistor M5sb is electrically connected to the wiring OLB, and a gate of the transistor M5sb is electrically connected to the wiring S2L. Has been done.
  • the first terminal of the transistor M3s and the first terminal of the transistor M4s are electrically connected to the wiring VLc, the gate of the transistor M3s is electrically connected to the wiring X1L, and the gate of the transistor M4s is electrically connected to the wiring X2L. Connected to each other.
  • the first terminal of the transistor M8 is electrically connected to the wiring I1L.
  • a gate of the transistor M8s is electrically connected to the wiring WL, a first terminal of the transistor M8s is electrically connected to the wiring I2L, and a second terminal of the transistor M8s is connected to the first terminal of the capacitor C3s and a transistor. It is electrically connected to the back gate of M3s and the back gate of the transistor M4s.
  • the second terminal of the capacitor C3s is electrically connected to the wiring VLcs.
  • the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, in order to distinguish the circuit element of the circuit MCr from the circuit element of the circuit MC, “r” is added to the symbol.
  • the wiring VLs, the wiring VLr, and the wiring VLsr function as a voltage line for supplying a constant voltage, and the constant voltage has a low-level potential.
  • VSS a low level potential other than VSS, a ground potential, or the like.
  • the constant voltage may be VDD, which is a high level potential.
  • the constant voltages supplied to the wiring VL, the wiring VLs, the wiring VLr, the wiring VLsr, the wiring VLc, the wiring VLcs, the wiring VLcr, and the wiring VLcsr may be different from each other, or some or all of them may be the same. May be.
  • the wiring S1L functions as a voltage line which supplies a potential for turning on or off the transistor M5a, the transistor M5b, the transistor M5ar, and the transistor M5br
  • the wiring S2L is a transistor M5sa, the transistor M5sb, the transistor M5sar, and It functions as a voltage line which supplies a potential for turning on or off the transistor M5sbr.
  • the circuit MP illustrated in FIGS. 5C and 5D can hold two weighting factors by applying the configuration illustrated in the circuit MP of FIG. 17. Specifically, the circuit MP of FIG. 17 holds the potential according to the first weighting coefficient in the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr, and holds the potential of the second weighting coefficient. It is possible to hold the potential according to the above in the holding portion HCs of the circuit MC and the holding portion HCsr of the circuit MC. In addition, the circuit MP in FIG. 17 can switch the weighting factor used for the calculation depending on the potentials applied from the wiring S1L and the wiring S2L.
  • the weighting factors w 1 (k ⁇ 1) j (k) to w m are assigned to the respective holding units HC and HCr included in the circuits MP [1, j] to MP [m, j] of the arithmetic circuit 110.
  • (K-1) j A potential corresponding to (k) is held, and the weighting factor w is held in each of the holding units HCs and HCsr included in the circuits MP [1, j] to MP [m, j] of the arithmetic circuit 110.
  • the wiring XLS is held while holding a potential corresponding to 1 (k-1) h (k) to w m (k-1) h (k) (here, h is 1 or more and is not an integer of j). [1] to the wiring XLS [m] (the wiring X1L and the wiring X2L in the circuit MP in FIG. 17) are supplied with potentials corresponding to the signals z 1 (k ⁇ 1) to z m (k ⁇ 1) .
  • the circuits MP [1, j] to MP [m, j] of the arithmetic circuit 110 have weighting factors w 1 (k ⁇ 1) j (k) to w m ( w ).
  • the sum of products of k-1) j (k) and the signals z 1 (k-1) to z m (k-1) and the activation function can be calculated. Further, a low-level potential is applied to the wiring S1L to turn off the transistor M5a, the transistor M5b, the transistor M5ar, and the transistor M5br, and a high-level potential is applied to the wiring S2L so that the transistor M5sa, the transistor M5sb, the transistor M5sar, By turning on the transistor M5sbr and the transistor M5sbr, the circuits MP [1, j] to MP [m, j] of the arithmetic circuit 110 have weighting factors w 1 (k ⁇ 1) h (k) to w m (k ). -1) h (k) and the signal z 1 (k-1) to be able to perform the calculation of the sum-of-products and activation function of z m (k-1).
  • the circuit MP of FIG. 17 As described above, by applying the circuit MP of FIG. 17 to the arithmetic circuit 110, two weighting factors can be held, and the weighting factors can be switched to perform the calculation of the sum of products and the activation function. it can.
  • the arithmetic circuit 110 that configures the circuit MP of FIG. 17 is effective, for example, when the number of neurons in the kth layer is larger than n, when performing an arithmetic operation in an intermediate layer different from the kth layer, and the like. Further, in the circuit MP of FIG. 17, the circuit MC and the circuit MCr each have two holding units, but each of the circuit MC and the circuit MCr has three or more holding units depending on the situation. You may.
  • the circuit MP included in the semiconductor device of one embodiment of the present invention is not limited to the circuit MP in FIG.
  • the circuit configuration of the circuit MP of the semiconductor device of one embodiment of the present invention can be changed from the circuit MP in FIG. 17 depending on the situation.
  • the circuit MP shown in FIG. 18 has a circuit configuration in which the number of transistors included in the circuit MP of FIG. 17 is changed.
  • the circuit MP in FIG. 18 includes a transistor M5a, a transistor M5b, a transistor M5ar, a transistor M5br, a transistor M5sa, a transistor M5sb, a transistor M5sar, and a transistor M5sbr in the circuit MP in FIG. It has an M5r, a transistor M5s, and a transistor M5sr.
  • a first terminal of the transistor M5 is electrically connected to a first terminal of the transistor M3 and a first terminal of the transistor M4, and a second terminal of the transistor M5 is electrically connected to the wiring VL,
  • the gate of M5 is electrically connected to the wiring S1L.
  • a first terminal of the transistor M5s is electrically connected to a first terminal of the transistor M3 and a first terminal of the transistor M4, and a second terminal of the transistor M5s is electrically connected to the wiring VLc.
  • the gate of M5s is electrically connected to the wiring S2L.
  • the second terminal of the transistor M3 and the second terminal of the transistor M3s are electrically connected to the wiring OL, and the second terminal of the transistor M4 and the second terminal of the transistor M4s are electrically connected to the wiring OLB. There is.
  • the circuit MCr of the circuit MP of FIG. 18 has a circuit configuration similar to that of the circuit MC. Therefore, in order to distinguish the circuit element of the circuit MCr from the circuit element of the circuit MC, “r” is added to the symbol.
  • the second terminal of the transistor M3r and the second terminal of the transistor M3sr are electrically connected to the wiring OL, and the second terminal of the transistor M4r and the second terminal of the transistor M4sr are connected to the wiring OLB. It is electrically connected.
  • the circuit MP of FIG. 18 can reduce the number of circuit elements more than the circuit MP of FIG. 17, the circuit area of the arithmetic circuit 110 can be reduced by using the circuit MP of FIG. 18 for the arithmetic circuit 110. it can.
  • the circuit MP shown in FIG. 19 has a circuit configuration in which the wiring configuration around the circuit MP in FIG. 18 is changed.
  • the wiring I1L and the wiring I2L of the circuit MP of FIG. 18 are combined into a wiring IL
  • the wiring I1LB and the wiring I2LB of the circuit MP of FIG. 18 are combined into a wiring ILB
  • the wiring WL for MP the wiring W1L and the wiring W2L are provided.
  • the wiring W1L is electrically connected to the gate of the transistor M8 and the gate of the transistor M8r
  • the wiring W2L is electrically connected to the gate of the transistor M8s and the gate of the transistor M8sr.
  • the potentials supplied to the wiring W1L and the wiring W2L are changed to turn on the transistors M8 and M8r, and the transistors M8s and M8sr. Is turned off, potentials for holding the holding portion HC and the holding portion HCr are supplied from the wiring IL and the wiring ILB, respectively, so that the transistors M8 and M8r are turned off. After that, the potentials supplied to the wirings W1L and W2L are changed, the transistors M8 and M8r are turned off, the transistors M8s and M8sr are turned on, and the wiring IL and the wiring ILB are then supplied.
  • the circuit MP shown in FIG. 20A is a circuit that can be applied to the circuit MP of FIG. 5A. It is different from the circuit MP of 9A.
  • the holding unit HC has an inverter circuit INV5 and an inverter circuit INV6.
  • the input terminal of the inverter circuit INV5 is electrically connected to the output terminal of the inverter circuit INV6, the second terminal of the transistor M8, the back gate of the transistor M3, and the back gate of the transistor M4.
  • electrical connection between the second terminal of the transistor M8, the back gate of the transistor M3, the back gate of the transistor M4, the input terminal of the inverter circuit INV5, and the output terminal of the inverter circuit INV6 is performed.
  • the physical connection point is called a node nd3.
  • the node nd3 may be connected to the output terminal of the inverter circuit INV5 instead of the input terminal of the inverter circuit INV5.
  • the circuit MCr of the circuit MP of FIG. 20A has a circuit configuration similar to that of the circuit MC. Therefore, in order to distinguish the circuit element of the circuit MCr from the circuit element of the circuit MC, “r” is added to the symbol.
  • the holding unit HC included in the circuit MC forms an inverter loop by the inverter circuit INV5 and the inverter circuit INV6, and the holding unit HCr included in the circuit MCr includes the inverter circuit INV5r and the inverter circuit INV6r. , Form an inverter loop. That is, the circuit MP of FIG. 20A can hold the potential corresponding to the weighting coefficient by the respective inverter loops of the holding unit HC and the holding unit HCr.
  • the circuit MP of FIG. 20A shows the inverter circuit INV5, the inverter circuit INV5r, the inverter circuit INV6, and the inverter circuit INV6r, at least one of the inverter circuit INV5, the inverter circuit INV5r, the inverter circuit INV6, and the inverter circuit INV6r is shown.
  • the logic circuit can be, for example, a NAND circuit, a NOR circuit, an XOR circuit, a circuit combining these, or the like.
  • the NAND circuit when the inverter circuit is replaced with a NAND circuit, the NAND circuit can function as an inverter circuit by inputting a high-level potential as a fixed potential to one of the two input terminals of the NAND circuit. Further, when the inverter circuit is replaced with a NOR circuit, the NOR circuit can function as an inverter circuit by inputting a low-level potential as a fixed potential to one of the two input terminals of the NOR circuit. When the inverter circuit is replaced with an XOR circuit, the XOR circuit can function as an inverter circuit by inputting a high level potential as a fixed potential to one of the two input terminals of the XOR circuit.
  • inverter circuit As described above, the inverter circuit described in this specification and the like can be replaced with a logic circuit such as a NAND circuit, a NOR circuit, an XOR circuit, or a circuit in which these are combined. Therefore, in this specification and the like, the term “inverter circuit” can be referred to as a “logic circuit”.
  • FIG. 20B shows an example in which the circuit MP of FIG. 20A is modified.
  • the circuit MP of FIG. 20B has a configuration in which the holding unit HCr is removed from the circuit MCr of the circuit MP of FIG. 20A, and the holding unit HC of the circuit MC electrically connects to the back gates of the transistor M3r and the transistor M4r of the circuit MCr. It is a connected configuration.
  • a node nd3r is an electrical connection point between the output terminal of the inverter circuit INV5 and the input terminal of the inverter circuit INV6. That is, the potential of the node nd3r is input to the back gate of the transistor M3r and the back gate of the transistor M4r.
  • the holding portion HCr is not included in the circuit MCr, and the potentials given to the back gate of the transistor M3r and the back gate of the transistor M4r are held by the holding portion HC of the circuit MC.
  • the holding portion HC has an inverter loop configuration including the inverter circuit INV5 and the inverter circuit INV6, one of the high level potential and the low level potential is held at the node nd3 and the high level potential or the low level potential at the node nd3r. The other of the potentials is held.
  • the holding unit HC cannot hold the same potential at each of the node nd3 and the node nd3r. Therefore, in the circuit MP of FIG. 20B, it is not possible to set the weighting coefficient expressed by holding the same potential in each of the node nd3 and the node nd3r. Specifically, in the above operation example, since the back gates of the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r cannot hold the low-level potential, the weighting coefficient “0” is set in the circuit MP of FIG. 20B. Can not do it.
  • the weighting coefficient held by the circuit MP is three values of “+1”, “ ⁇ 1”, and “0” and the signal of the neuron according to the potential input from the wirings X1L and X2L is
  • the circuit MP that can calculate the product of the three values of “+1”, “ ⁇ 1”, and “0” has been described, but in the present configuration example, as an example, the weighting factors are “+1”, “ ⁇ ”.
  • the circuit MP shown in FIG. 21A is a circuit obtained by removing the transistors M4 and M4r from the circuit MP of FIG. 9A. Since the transistor M4 and the transistor M4r are omitted, the wiring X2L for inputting a potential to the gates of the transistor M4 and the transistor M4r is also omitted in FIG. 21A. A wiring corresponding to the wiring X1L is described as a wiring XL in FIG. 21A.
  • the weighting factor set in the circuit MP of FIG. 21A is set to “+1” when the high level potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr, and the weighting factor of the holding unit HC is set. If the node nd3 has a low level potential, and the node nd3r of the holding unit HCr holds a high level potential, it is set to "-1", the node nd3 of the holding unit HC has a low level potential, and the node nd3r of the holding unit HCr has a low level potential. When the potential is held, it is set to "0".
  • the signal of the neuron input to the circuit MP in FIG. 21A is “+1” when a high-level potential is applied to the wiring XL and “0” when a low-level potential is applied to the wiring XL.
  • the signal of the neuron to be input with the weight coefficient when the signal of the neuron to be input with the weight coefficient is defined as described above, the signal of the neuron is input to the circuit MP in each case of the weight coefficient.
  • the current I OL output from outa changes and whether or not the current I OLB output from the node outb of the wiring OLB changes are as shown in the following table. In the table below, the high level potential is described as high and the low level potential is described as low.
  • the weighting coefficient may be not only three values but also two values or three or more values. For example, binary values of "+1” and “0” or binary values of "+1” and “-1” may be used. Alternatively, the weight coefficient may be an analog value or a multi-bit (multi-value) digital value.
  • the circuit MC of the circuit MP, the holding unit HC included in the circuit MCr, and the potential held in the holding unit HCr are the high-level potential or the low-level potential, but the holding unit HC and the holding unit A potential indicating an analog value may be held in HCr.
  • the weighting factor is “positive analog value”
  • the high level analog potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr.
  • the weighting factor is “negative analog value”
  • the low level potential is held at the node nd3 of the holding unit HC and the high level analog potential is held at the node nd3r of the holding unit HCr.
  • the magnitudes of the currents I OL and I OLB are according to the analog potential.
  • FIG. 21B shows a modified example of the circuit MP of FIG. 21A.
  • the circuit MP of FIG. 21B has a configuration in which the gates of the transistor M3 and the transistor M3r and the back gate of the transistor M3 of FIG. 21A are replaced with each other, and the potentials of the gates of the transistor M3 and the transistor M3r are held in the holding unit HC.
  • the holding section HCr is used for holding.
  • the circuit MP has a structure in which a potential is applied from the wiring XL to the back gates of the transistor M3 and the transistor M3r, and the threshold voltage of the transistor M3 and the transistor M3r is changed by the potential given from the wiring XL to turn on. It is configured to switch between the state and the off state.
  • the change in current flowing through the wiring OL and the wiring OLB can be considered as in the circuit MP in FIG. 21A. Therefore, in the circuit MP in FIG. 21B, the node nd3, and combinations of potential held in the node Nd3r, defined by a potential wiring XL gives, presence or absence of a change in the current I OL outputted from the node outa wiring OL , And the presence or absence of a change in the current I OLB output from the node outb of the wiring OLB is as shown in the table above in the circuit MP of FIG. 21A.
  • the wiring IL and the wiring ILB may be integrated and the wiring WL may be divided into the wiring W1L and the wiring W2L.
  • FIG. 22A Such a circuit configuration is shown in FIG. 22A.
  • the circuit MP of FIG. 22A can be applied to the arithmetic circuit 120 of FIG. 6 as an example. Note that the description of the operation method of the circuit MP in FIG. 16A is referred to for the operation method of the circuit MP in FIG. 22A.
  • the wiring XL may be divided into the wiring X1L and the wiring X2L.
  • FIG. 22B Such a circuit configuration is shown in FIG. 22B. If a high-level potential (Vg1) or a low-level potential (Vg2) is applied to each of the wiring X1L and the wiring X2L, there are four combinations of potentials given by the wiring X1L and the wiring X2L. Further, assuming that a high-level potential or a low-level potential is held at the respective nodes nd3 and nd3r of the holding section HC and the holding section HCr, there are four combinations of potentials held at the node nd3 and the node nd3r. Becomes
  • the current I output from the node outa of the wiring OL is determined by the combination of potentials held in the nodes nd3 and nd3r and the combination of potentials given by the wirings X1L and X2L. Whether or not the OL has changed and whether or not the current I OLB output from the node outb of the wiring OLB has changed is shown in the following table. In the table below, the high level potential is described as high and the low level potential is described as low.
  • the holding portions HC and the holding portions HCr of the circuits MP and MCr of the circuit MP are set to the high-level potential or the low-level potential, respectively.
  • the holding portion HCr may hold a potential indicating an analog value. For example, when the weighting factor is “positive analog value”, the high level analog potential is held at the node nd3 of the holding unit HC and the low level potential is held at the node nd3r of the holding unit HCr.
  • the weighting factor is “negative analog value”, for example, the low level potential is held at the node nd3 of the holding unit HC and the high level analog potential is held at the node nd3r of the holding unit HCr. Then, the magnitudes of the currents I OL and I OLB are according to the analog potential.
  • the semiconductor device illustrated in FIG. 23 includes a transistor 300, a transistor 500, and a capacitor 600.
  • 25A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 25B is a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 25C is a cross-sectional view of the transistor 300 in the channel width direction.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. Since the transistor 500 has a small off-state current, it can be used for a long period of time by using the semiconductor device, in particular, the transistor M3, the transistor M4, the transistor M8, and the like of the circuit MP included in the arithmetic circuit 110. Is possible. That is, the frequency of refresh operation is low or the refresh operation is not necessary, so that power consumption of the semiconductor device can be reduced.
  • the transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistors 300 and 500.
  • the capacitor 600 can be the capacitor C3, the capacitor C3r, or the like in the circuit MP.
  • the transistor 300 is provided over the substrate 311, and includes a conductor 316, an insulator 315, a semiconductor region 313 which is part of the substrate 311, a low-resistance region 314a which functions as a source region or a drain region, and a low-resistance region 314b. .. Note that the transistor 300 can be applied to, for example, the transistor in the above embodiment.
  • the transistor 300 As shown in FIG. 25C, in the transistor 300, the upper surface and the side surface in the channel width direction of the semiconductor region 313 are covered with the conductor 316 with the insulator 315 interposed therebetween. As described above, when the transistor 300 is a Fin type, the effective channel width is increased, so that the on-state characteristics of the transistor 300 can be improved. Further, since the electric field contribution of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a region of the semiconductor region 313 in which a channel is formed, a region in the vicinity thereof, a low-resistance region 314a serving as a source region or a drain region, a low-resistance region 314b, or the like preferably contains a semiconductor such as a silicon-based semiconductor. It preferably includes crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration may be used in which silicon is used, in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b impart an n-type conductivity imparting element such as arsenic or phosphorus or a p-type conductivity imparting boron, in addition to the semiconductor material applied to the semiconductor region 313. Including the element to do.
  • the conductor 316 functioning as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the transistor 300 illustrated in FIG. 23 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the transistor 300 may have a structure similar to that of the transistor 500 including an oxide semiconductor as illustrated in FIG. Note that details of the transistor 500 will be described later.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. Good.
  • silicon oxynitride refers to a material whose content of oxygen is higher than that of nitrogen
  • silicon oxynitride is a material whose content of nitrogen is higher than that of oxygen.
  • aluminum oxynitride refers to a material having a higher oxygen content than nitrogen as its composition
  • aluminum oxynitride as a material having a higher nitrogen content than oxygen as its composition. Indicates.
  • the insulator 322 may have a function as a flattening film for flattening a step caused by the transistor 300 and the like provided below the insulator 322.
  • the upper surface of the insulator 322 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to enhance planarity.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311, the transistor 300, or the like to a region where the transistor 500 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen is diffused into a semiconductor element including an oxide semiconductor, such as the transistor 500, characteristics of the semiconductor element may be deteriorated in some cases. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the film that suppresses hydrogen diffusion is a film in which the amount of released hydrogen is small.
  • the desorption amount of hydrogen can be analyzed using, for example, a thermal desorption gas analysis method (TDS).
  • TDS thermal desorption gas analysis method
  • the desorption amount of hydrogen in the insulator 324 is calculated by converting the desorption amount converted into hydrogen atoms into the area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C to 500 ° C. Therefore, it may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less that of the insulator 324.
  • a conductor 328, a conductor 330, and the like which are connected to the capacitor 600 or the transistor 500 are embedded.
  • the conductor 328 and the conductor 330 have a function as a plug or a wiring.
  • the conductor having a function as a plug or a wiring may have a plurality of structures collectively given the same reference numeral. In this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, part of the conductor may function as a wiring, and part of the conductor may function as a plug.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a laminated layer. be able to. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided.
  • a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 350 is preferably an insulator having a barrier property against hydrogen, like the insulator 324.
  • the conductor 356 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a hydrogen barrier property is formed in an opening portion of the insulator 350 having a hydrogen barrier property.
  • tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen.
  • tantalum nitride and tungsten having high conductivity diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring.
  • the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 354 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked and provided.
  • a conductor 366 is formed over the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 360 is preferably an insulator having a barrier property against hydrogen, like the insulator 324.
  • the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a hydrogen barrier property is formed in the opening of the insulator 360 having a hydrogen barrier property.
  • a wiring layer may be provided on the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked and provided. Further, a conductor 376 is formed over the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 has a function as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 370 is preferably an insulator having a barrier property against hydrogen, like the insulator 324.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a hydrogen barrier property is formed in the opening of the insulator 370 having a hydrogen barrier property.
  • a wiring layer may be provided on the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked and provided. Further, a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 380 it is preferable to use an insulator having a barrier property against hydrogen, like the insulator 324.
  • the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening portion of the insulator 380 having a barrier property against hydrogen.
  • the semiconductor device has been described above, the semiconductor device according to this embodiment It is not limited to this.
  • the wiring layer similar to the wiring layer including the conductor 356 may be three layers or less, or the wiring layer similar to the wiring layer including the conductor 356 may be five layers or more.
  • An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance having a barrier property against oxygen and hydrogen.
  • insulator 510 and the insulator 514 for example, a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided is used. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen is diffused into a semiconductor element including an oxide semiconductor, such as the transistor 500, characteristics of the semiconductor element might be deteriorated in some cases. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the film that suppresses hydrogen diffusion is a film in which the amount of released hydrogen is small.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 500.
  • the same material as that of the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516.
  • a conductor 518, a conductor (eg, a conductor 503) included in the transistor 500, and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516.
  • the conductor 518 has a function as a plug or a wiring which is connected to the capacitor 600 or the transistor 300.
  • the conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the conductor 510 in a region which is in contact with the insulator 510 and the insulator 514 be a conductor having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • the transistor 500 is provided above the insulator 516.
  • the transistor 500 includes a conductor 503 arranged so as to be embedded in an insulator 514 and an insulator 516, and an insulator arranged above the insulator 516 and the conductor 503.
  • An insulator 580 having an opening formed so as to overlap with the oxide 530, an oxide 530c arranged on the bottom and side surfaces of the opening, and an insulator 55 arranged on the formation surface of the oxide 530c.
  • an insulator 544 is preferably provided between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 550, a conductor 560b provided so as to be embedded inside the conductor 560a, and It is preferable to have
  • an insulator 574 is preferably provided over the insulator 580, the conductor 560, and the insulator 550.
  • the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.
  • the transistor 500 has a structure in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are stacked in the region where the channel is formed and in the vicinity thereof, the present invention is not limited to this. Not a thing. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. Further, in the transistor 500, the conductor 560 is shown as a stacked structure of two layers, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure including three or more layers. In addition, the transistor 500 illustrated in FIGS. 23 and 25A is an example, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region between the conductors 542a and 542b.
  • the arrangement of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a positioning margin, so that the area occupied by the transistor 500 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Accordingly, parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 and without changing the potential. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be higher than 0 V and the off-state current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, as compared to the case where no potential is applied.
  • the conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover a channel formation region formed in the oxide 530.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside.
  • the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this.
  • the conductor 503 may have a single-layer structure or a stacked structure including three or more layers.
  • the conductor 503a is preferably made of a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are less likely to permeate).
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms
  • the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the impurities or oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and being reduced in conductivity.
  • the conductor 503 also has a function of wiring
  • the conductor 503b be formed using a conductive material having high conductivity, which contains tungsten, copper, or aluminum as its main component.
  • the conductor 505 is not necessarily provided.
  • the conductor 503b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material.
  • the insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 which is in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than that satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 be formed with an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
  • an oxide material in which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 or more by TDS (Thermal Desorption Spectroscopy) analysis. It is an oxide film having a concentration of 0.0 ⁇ 10 19 atoms / cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms / cm 3 or more, or 3.0 ⁇ 10 20 atoms / cm 3 or more.
  • the surface temperature of the film during the TDS analysis is preferably 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • any one or more of heat treatment, microwave treatment, and RF treatment may be performed in a state where the insulator having the excess oxygen region is in contact with the oxide 530.
  • water or hydrogen in the oxide 530 can be removed.
  • a reaction bond VoH is cut and reaction occurs that when other words "V O H ⁇ V O + H", can be dehydrogenated.
  • Part of the hydrogen generated at this time may be combined with oxygen and converted into H 2 O, which is removed from the oxide 530 or the insulator in the vicinity of the oxide 530.
  • part of hydrogen may be diffused or captured (also referred to as gettering) in the conductors 542a and 542b.
  • a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side for the microwave treatment.
  • a gas containing oxygen and using high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be generated.
  • the pressure may be 133 Pa or higher, preferably 200 Pa or higher, more preferably 400 Pa or higher.
  • oxygen and argon are used, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more 30 % Or less is recommended.
  • heat treatment is preferably performed with the surface of the oxide 530 exposed.
  • the heat treatment may be performed at 100 ° C to 450 ° C inclusive, preferably 350 ° C to 400 ° C inclusive.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V 2 O 3 ).
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher in order to supplement desorbed oxygen after the heat treatment is performed in a nitrogen gas or inert gas atmosphere.
  • heat treatment may be performed in an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more, and then continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the insulator 522 when the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (eg, oxygen atoms, oxygen molecules) (the oxygen is less likely to permeate).
  • oxygen eg, oxygen atoms, oxygen molecules
  • the insulator 522 has a function of suppressing diffusion of oxygen and impurities, oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, the conductor 503 can be prevented from reacting with the insulator 524 and the oxygen contained in the oxide 530.
  • the insulator 522 is, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or a laminated layer. As miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulating film. By using a high-k material for the insulator functioning as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing an oxide of one or both of aluminum and hafnium which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 522 is formed using such a material, the insulator 522 suppresses release of oxygen from the oxide 530 and mixture of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulator and used.
  • the insulator 520 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • an insulator 520 having a stacked structure which is thermally stable and has a high relative dielectric constant can be obtained.
  • the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a stacked-layer structure of three layers.
  • the gate insulating film may have a single-layer structure, a double-layer structure, or a stacked structure of four or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the oxide 530 including the channel formation region is preferably a metal oxide functioning as an oxide semiconductor.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium).
  • the In-M-Zn oxide that can be used as the oxide 530 is preferably the CAAC-OS or the CAC-OS described in Embodiment 4.
  • an In—Ga oxide or an In—Zn oxide may be used.
  • a metal oxide having a low carrier concentration for the transistor 500 it is preferable to use a metal oxide having a low carrier concentration for the transistor 500.
  • the concentration of impurities in the metal oxide may be lowered and the density of defect states may be lowered.
  • low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • the impurities in the metal oxide include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to be water, which may cause oxygen vacancies in the metal oxide.
  • oxygen vacancies and hydrogen combine to form a V O H.
  • V O H acts as a donor, sometimes electrons serving as carriers are generated.
  • part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics.
  • the metal oxide easily moves due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the metal oxide, reliability of the transistor might be deteriorated.
  • the highly purified intrinsic or substantially highly purified intrinsic it is preferable that the highly purified intrinsic or substantially highly purified intrinsic.
  • the impurities such as hydrogen (dehydration, may be described as dehydrogenation.)
  • oxygenation treatment it is important to supply oxygen to the metal oxide to fill oxygen vacancies (sometimes referred to as oxygenation treatment).
  • the metal oxide impurities is sufficiently reduced such V O H By using the channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • the metal oxide may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, the carrier concentration which is assumed to be a state where no electric field is applied may be used as the parameter of the metal oxide, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.
  • the hydrogen concentration obtained by secondary ion mass spectroscopy is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm 3. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the carrier concentration of the metal oxide in the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less and less than 1 ⁇ 10 17 cm ⁇ 3. Is more preferable, less than 1 ⁇ 10 16 cm ⁇ 3 is more preferable, less than 1 ⁇ 10 13 cm ⁇ 3 is still more preferable, and less than 1 ⁇ 10 12 cm ⁇ 3 is further preferable.
  • the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but can be set to, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • oxygen in the oxide 530 is diffused to the conductor 542a and the conductor 542b,
  • the 542a and the conductor 542b may be oxidized. Oxidation of the conductors 542a and 542b is likely to reduce the conductivity of the conductors 542a and 542b. Note that diffusion of oxygen in the oxide 530 to the conductor 542a and the conductor 542b can be restated as absorption of oxygen in the oxide 530 by the conductor 542a and the conductor 542b.
  • the oxide 530 diffuses into the conductors 542a and 542b, so that different layers are formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. May be done. Since the different layer contains more oxygen than the conductor 542a and the conductor 542b, it is estimated that the different layer has an insulating property.
  • the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure including metal-insulator-semiconductor, and MIS (Metal-Insulator-). It may be called a "Semiconductor structure" or a diode junction structure mainly composed of a MIS structure.
  • the different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b; for example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c. In some cases, or in some cases, between the conductor 542a and the conductor 542b and the oxide 530b, and between the conductor 542a and the conductor 542b and the oxide 530c.
  • the metal oxide functioning as a channel formation region in the oxide 530 preferably has a bandgap of 2 eV or more, preferably 2.5 eV or more.
  • the oxide 530 has the oxide 530a below the oxide 530b, diffusion of impurities into the oxide 530b from a structure formed below the oxide 530a can be suppressed. Further, by including the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c into the oxide 530b can be suppressed.
  • the oxide 530 preferably has a stacked structure due to oxides in which the atomic ratio of each metal atom is different.
  • the atomic ratio of the element M in the constituent elements is higher than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.
  • a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
  • the energy at the bottom of the conduction band of the oxide 530a and the oxide 530c be higher than the energy at the bottom of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a and the oxide 530c be smaller than the electron affinity of the oxide 530b.
  • the energy level at the bottom of the conduction band changes gently at the junction of the oxide 530a, the oxide 530b, and the oxide 530c.
  • the energy levels at the bottoms of the conduction bands at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c are continuously changed or continuously joined.
  • the density of defect states in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c may be low.
  • the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element other than oxygen (as a main component), so that a mixed layer with low density of defect states is formed.
  • the oxide 530b is an In—Ga—Zn oxide, In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like may be used as the oxide 530a and the oxide 530c.
  • the main carrier path is the oxide 530b.
  • the oxide 530a and the oxide 530c have the above structure, the density of defect states in the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced and the transistor 500 can obtain high on-state current.
  • the conductor 542a and the conductor 542b which function as a source electrode and a drain electrode are provided over the oxide 530b.
  • Examples of the conductor 542a and the conductor 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. It is preferable to use a metal element selected from iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even when absorbing oxygen. Further, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single layer structure, but may be a laminated structure of two or more layers.
  • a tantalum nitride film and a tungsten film may be stacked.
  • a titanium film and an aluminum film may be stacked.
  • a two-layer structure in which an aluminum film is stacked over a tungsten film a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, and a tungsten film is formed over the tungsten film.
  • a two-layer structure in which copper films are laminated may be used.
  • a titanium film or a titanium nitride film a three-layer structure in which an aluminum film or a copper film is stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereover, a molybdenum film, or
  • a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereover.
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
  • regions 543a and 543b may be formed as low resistance regions at and near the interface between the conductor 542a (conductor 542b) and the oxide 530.
  • the region 543a functions as one of the source region and the drain region
  • the region 543b functions as the other of the source region and the drain region.
  • a channel formation region is formed in a region between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced.
  • a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. At this time, the insulator 544 may be provided so as to cover a side surface of the oxide 530 and be in contact with the insulator 524.
  • the insulator 544 one or two or more kinds of metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, and the like are included. Can be used. Alternatively, as the insulator 544, silicon nitride oxide, silicon nitride, or the like can be used.
  • hafnium oxide aluminum, or oxide containing hafnium (hafnium aluminate), which is an insulator containing oxide of one or both of aluminum and hafnium, as the insulator 544. ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, crystallization is less likely to occur in heat treatment in a later step, which is preferable.
  • the insulator 544 is not an essential component when the conductors 542a and 542b are materials having oxidation resistance or when the conductivity does not significantly decrease even when oxygen is absorbed. It may be appropriately designed depending on the desired transistor characteristics.
  • impurities such as water and hydrogen contained in the insulator 580 can be suppressed from diffusing into the oxide 530b through the oxide 530c and the insulator 550.
  • oxidation of the conductor 560 due to excess oxygen in the insulator 580 can be suppressed.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably arranged in contact with the inside (top surface and side surface) of the oxide 530c.
  • the insulator 550 is preferably formed using an insulator which contains excess oxygen and releases oxygen by heating.
  • silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon oxide added with carbon, and nitrogen are added.
  • the silicon oxide which it has can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • oxygen is effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Can be supplied. Further, like the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced.
  • the thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 550 and the conductor 560 in order to efficiently supply the excess oxygen included in the insulator 550 to the oxide 530.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
  • diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 550 may have a stacked structure like the second gate insulating film.
  • an insulator functioning as a gate insulating film is formed using a high-k material and a thermal insulator.
  • a layered structure of a stable material it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Further, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 25A and 25B, it may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 560a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), and copper atoms. It is preferable to use materials. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used. Since the conductor 560a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 550 can prevent oxidation of the conductor 560b and decrease in conductivity.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), and copper atoms. It is preferable to use materials. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used. Since the
  • the conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • an oxide semiconductor which can be used for the oxide 530 can be used as the conductor 560a. In that case, by forming a film of the conductor 560b by a sputtering method, the electric resistance value of the conductor 560a can be reduced to be a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used.
  • the conductor 560b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b through the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and nitrogen-added silicon oxide a voided oxide
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.
  • the opening of the insulator 580 is formed so as to overlap with a region between the conductor 542a and the conductor 542b. Accordingly, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region between the conductor 542a and the conductor 542b.
  • the conductor 560 When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the thickness of the conductor 560 is increased, the conductor 560 can have a shape with a high aspect ratio. In this embodiment mode, the conductor 560 is provided so as to be embedded in the opening of the insulator 580; therefore, even if the conductor 560 has a high aspect ratio, the conductor 560 can be formed without being destroyed during the process. You can
  • the insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550.
  • an excess oxygen region can be provided in the insulator 550 and the insulator 580. Accordingly, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • insulator 574 a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. You can
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even if it is a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide film formed by a sputtering method can have a function as a barrier film against impurities such as hydrogen as well as an oxygen supply source.
  • the insulator 581 functioning as an interlayer film over the insulator 574.
  • the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductor 540a and the conductor 540b are provided to face each other with the conductor 560 interposed therebetween.
  • the conductors 540a and 540b have the same structures as conductors 546 and 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, a material similar to that of the insulator 514 can be used for the insulator 582.
  • the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
  • aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • a material similar to that of the insulator 320 can be used.
  • a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.
  • the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546, the conductor 548, and the like. Is embedded.
  • the conductor 546 and the conductor 548 have a function as a plug connected to the capacitor 600, the transistor 500, or the transistor 300, or a wiring.
  • the conductor 546 and the conductor 548 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • an insulator having a high barrier property against hydrogen or water By wrapping the transistor 500 with the above-described insulator having a high barrier property, moisture and hydrogen can be prevented from entering from the outside.
  • the plurality of transistors 500 may be collectively wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening reaching the insulator 514 or the insulator 522 is formed and the above-described insulator having a high barrier property is provided so as to be in contact with the insulator 514 or the insulator 522.
  • the formation is preferable because it can serve as part of a manufacturing process of the transistor 500.
  • the insulator having a high barrier property against hydrogen or water a material similar to that of the insulator 522 may be used, for example.
  • the capacitor element 600 is provided above the transistor 500.
  • the capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided over the conductor 546 and the conductor 548.
  • the conductor 612 has a function of a plug connected to the transistor 500 or a wiring.
  • the conductor 610 has a function as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.
  • a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above element as a component (Tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or silicon oxide is added.
  • a conductive material such as indium tin oxide described above can also be applied.
  • the conductor 612 and the conductor 610 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having high adhesion to the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having high conductivity.
  • a conductor 620 is provided so as to overlap with the conductor 610 through the insulator 630.
  • the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
  • a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.
  • An insulator 650 is provided on the conductor 620 and the insulator 630.
  • the insulator 650 can be provided using a material similar to that of the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650.
  • a semiconductor device including a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated.
  • transistor 500 in the semiconductor device described in this embodiment is not limited to the above structure.
  • structural examples that can be used for the transistor 500 will be described.
  • the transistor described below is a modification of the above-described transistor, and therefore, in the following description, different points are mainly described and the same points may be omitted.
  • FIG. 26A is a top view of the transistor 500A.
  • 26B is a cross-sectional view of a portion indicated by alternate long and short dash line L1-L2 in FIG. 26A.
  • FIG. 26C is a sectional view of a portion indicated by alternate long and short dash line W1-W2 in FIG. 26A.
  • some elements are omitted for clarity of the drawing.
  • the transistor 500A illustrated in FIGS. 26A to 26C has a structure in which an insulator 511 which functions as an interlayer film and a conductor 505 which functions as a wiring are added to the transistor 500 illustrated in FIG. 25A.
  • the oxide 530c, the insulator 550, and the conductor 560 are provided in the opening provided in the insulator 580 with the insulator 544 interposed therebetween.
  • the oxide 530c, the insulator 550, and the conductor 560 are provided between the conductor 542a and the conductor 542b.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) is used.
  • An insulator such as TiO 3 (BST) can be used in a single layer or a laminated layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulator and used.
  • the insulator 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 500A from the substrate side. Therefore, the insulator 511 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities do not easily pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Further, for example, aluminum oxide, silicon nitride, or the like may be used as the insulator 511. With such a structure, diffusion of impurities such as hydrogen and water from the substrate side of the insulator 511 to the transistor 500A side can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the
  • the insulator 512 preferably has a lower dielectric constant than the insulator 511.
  • a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the conductor 505 is formed so as to be embedded in the insulator 512.
  • the height of the upper surface of the conductor 505 and the height of the upper surface of the insulator 512 can be approximately the same.
  • the conductor 505 is shown as a single layer structure, but the present invention is not limited to this.
  • the conductor 505 may have a multilayer film structure including two or more layers.
  • the conductor 505 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component and having high conductivity.
  • the insulator 514 and the insulator 516 function as an interlayer film similarly to the insulator 511 or the insulator 512.
  • the insulator 514 preferably functions as a barrier film which suppresses impurities such as water or hydrogen from entering the transistor 500A from the substrate side. With such a structure, diffusion of impurities such as hydrogen and water from the substrate side of the insulator 514 to the transistor 500A side can be suppressed.
  • the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 522 preferably has a barrier property.
  • the insulator 522 having a barrier function functions as a layer for suppressing entry of impurities such as hydrogen from the peripheral portion of the transistor 500A into the transistor 500A.
  • the oxide 530c is preferably provided in the opening provided in the insulator 580 with the insulator 544 interposed therebetween.
  • the insulator 544 has a barrier property, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.
  • a barrier layer may be provided on the conductors 542a and 542b.
  • a substance having a barrier property against oxygen or hydrogen is preferably used. With this structure, oxidation of the conductors 542a and 542b can be suppressed when the insulator 544 is formed.
  • a metal oxide can be used for the barrier layer.
  • an insulating film having a barrier property against oxygen or hydrogen such as aluminum oxide, hafnium oxide, or gallium oxide.
  • silicon nitride formed by a CVD method may be used.
  • the conductors 542a and 542b By having a barrier layer, it is possible to widen the selection range of materials for the conductors 542a and 542b.
  • a material such as tungsten or aluminum which has low oxidation resistance and high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably provided in the opening provided in the insulator 580 with the oxide 530c and the insulator 544 provided therebetween.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is formed into a single layer or a stacked layer.
  • a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity.
  • a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
  • the conductor 540a and the conductor 540b for example, a stacked structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten, which has high conductivity, is used for wiring. It is possible to suppress the diffusion of impurities from the outside while maintaining the conductivity as described above.
  • a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided.
  • Transistor structure example 2 A structural example of the transistor 500B is described with reference to FIGS. 27A to 27C.
  • 27A is a top view of the transistor 500B.
  • 27B is a cross-sectional view of a portion indicated by alternate long and short dash line L1-L2 in FIG. 27A.
  • 27C is a cross-sectional view of a portion indicated by alternate long and short dash line W1-W2 in FIG. 27A.
  • some elements are omitted for the sake of clarity.
  • the transistor 500B is a modification of the transistor 500A. Therefore, in order to prevent repetition of description, points different from the transistor 500A are mainly described.
  • the transistor 500B has a region where a conductor 542a (a conductor 542b), an oxide 530c, an insulator 550, and a conductor 560 overlap with each other. With such a structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.
  • the conductor 560 functioning as the first gate electrode has a conductor 560a and a conductor 560b over the conductor 560a.
  • the conductor 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms.
  • a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 560a has a function of suppressing diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed and the conductivity can be prevented from being lowered.
  • the insulator 544 is preferably provided so as to cover the top surface and the side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c.
  • oxidation of the conductor 560 can be suppressed.
  • impurities such as water and hydrogen in the insulator 580 can be suppressed from diffusing into the transistor 500B.
  • the contact plug of the transistor 500B is different from the contact plug of the transistor 500A.
  • an insulator 576a (insulator 576b) having a barrier property is provided between the conductor 546a (conductor 546b) functioning as a contact plug and the insulator 580.
  • oxygen in the insulator 580 can be prevented from reacting with the conductor 546 and oxidizing the conductor 546.
  • insulator 576a (insulator 576b) having the barrier property
  • a semiconductor device with low power consumption can be provided by using a metal material having high conductivity while having a property of absorbing oxygen for the conductor 546a (conductor 546b).
  • a material such as tungsten or aluminum which has low oxidation resistance but high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • FIGS. 28A to 28C A structural example of the transistor 500C is described with reference to FIGS. 28A to 28C.
  • 28A is a top view of the transistor 500C.
  • 28B is a cross-sectional view of a portion indicated by alternate long and short dash line L1-L2 in FIG. 28A.
  • 28C is a cross-sectional view of a portion indicated by alternate long and short dash line W1-W2 in FIG. 28A. Note that in the top view of FIG. 28A, some elements are omitted for clarity of the drawing.
  • the transistor 500C is a modification of the transistor 500A. Therefore, in order to prevent repetition of description, points different from the transistor 500A are mainly described.
  • the conductor 547a is provided between the conductor 542a and the oxide 530b
  • the conductor 547b is provided between the conductor 542b and the oxide 530b.
  • the conductor 542a extends over the top surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side and has a region in contact with the top surface of the oxide 530b.
  • a conductor that can be used for the conductor 542a and the conductor 542b may be used as the conductor 547a and the conductor 542b.
  • the thicknesses of the conductors 547a and 547b be at least larger than those of the conductors 542a and 542b.
  • the transistor 500C illustrated in FIGS. 28A to 28C can have the conductors 542a and 542b closer to the conductor 560 than the transistor 500A by having the above structure.
  • the conductor 560 can overlap with the end of the conductor 542a and the end of the conductor 542b. Accordingly, the substantial channel length of the transistor 500C can be shortened, an on-current can be improved, and frequency characteristics can be improved.
  • the conductor 547a (conductor 547b) is preferably provided so as to overlap with the conductor 542a (conductor 542b).
  • the conductor 547a (conductor 547b) functions as a stopper and the oxide 530b is over-etched in etching for forming an opening in which the conductor 540a (conductor 540b) is embedded. Can be prevented.
  • the transistor 500C illustrated in FIG. 28 has a structure in which the insulator 545 is provided in contact with the insulator 544.
  • the insulator 544 preferably functions as a barrier insulating film which suppresses impurities such as water or hydrogen and excess oxygen from entering the transistor 500C from the insulator 580 side.
  • an insulator that can be used for the insulator 544 can be used.
  • a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used.
  • the transistor 500C shown in FIG. 28 has a single-layer structure of the conductor 503.
  • an insulating film to be the insulator 516 is formed over the patterned conductor 503, and the upper portion of the insulating film is removed by a CMP method or the like until the upper surface of the conductor 503 is exposed.
  • the top surface of the conductor 503 it is preferable that the top surface of the conductor 503 have good flatness.
  • the average surface roughness (Ra) of the top surface of the conductor 503 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the flatness of the insulating layer formed over the conductor 503 can be favorable and the crystallinity of the oxide 530b and the oxide 530c can be improved.
  • FIG. 29A is a top view of the transistor 500D.
  • FIG. 29B is a sectional view of a portion indicated by alternate long and short dash line L1-L2 in FIG. 29A.
  • FIG. 29C is a sectional view of a portion indicated by alternate long and short dash line W1-W2 in FIG. 29A. Note that in the top view of FIG. 29A, some elements are omitted for clarity.
  • the transistor 500D is a modification of the above transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.
  • the transistor 500D illustrated in FIGS. 29A to 29C is different from the transistor 500 and the transistors 500A to 500C in that the conductor 542a and the conductor 542b are not provided and the region 531a and the region 531b are provided in a part of the exposed surface of the oxide 530b. Have. One of the region 531a and the region 531b functions as a source region and the other functions as a drain region.
  • the transistor 500D does not include the conductor 505 and also allows the conductor 503 having a function as a second gate to function as a wiring.
  • the insulator 550 is provided over the oxide 530c, and the metal oxide 552 is provided over the insulator 550.
  • the conductor 560 is provided over the metal oxide 552, and the insulator 570 is provided over the conductor 560.
  • the insulator 571 is provided over the insulator 570.
  • the metal oxide 552 preferably has a function of suppressing oxygen diffusion.
  • the metal oxide 552 which suppresses diffusion of oxygen between the insulator 550 and the conductor 560, diffusion of oxygen into the conductor 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to oxygen can be suppressed.
  • the metal oxide 552 may have a function as a part of the first gate.
  • an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552.
  • the conductor 560 by forming the conductor 560 by a sputtering method, the electric resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.
  • the metal oxide 552 may have a function as a part of the gate insulating film. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 550, the metal oxide 552 is preferably a high-k material which has a high relative dielectric constant. With this laminated structure, a laminated structure that is stable to heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Further, the equivalent oxide film thickness (EOT) of the insulating layer functioning as the gate insulating film can be reduced.
  • EOT equivalent oxide film thickness
  • the metal oxide 552 is shown as a single layer, but it may have a laminated structure of two or more layers.
  • a metal oxide functioning as part of the gate electrode and a metal oxide functioning as part of the gate insulating film may be stacked.
  • the on-state current of the transistor 500D can be improved without weakening the influence of the electric field from the conductor 560.
  • the distance between the conductor 560 and the oxide 530 is kept by the physical thickness of the insulator 550 and the metal oxide 552, so that Leakage current with the oxide 530 can be suppressed. Therefore, by providing a laminated structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be obtained. It can be easily adjusted appropriately.
  • the metal oxide 552 can be used as the metal oxide 552 by reducing the resistance of an oxide semiconductor that can be used for the oxide 530.
  • a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like can be used.
  • hafnium oxide aluminum, and oxide containing hafnium (hafnium aluminate), which is an insulating layer containing oxide of one or both of aluminum and hafnium.
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, crystallization is less likely to occur in heat treatment in a later step, which is preferable.
  • the metal oxide 552 is not an essential component. It may be appropriately designed depending on the desired transistor characteristics.
  • the insulator 570 it is preferable to use an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen For example, it is preferable to use aluminum oxide or hafnium oxide. Accordingly, oxidation of the conductor 560 with oxygen from above the insulator 570 can be suppressed. Further, impurities such as water or hydrogen from above the insulator 570 can be suppressed from entering the oxide 530 through the conductor 560 and the insulator 550.
  • the insulator 571 functions as a hard mask.
  • the side surface of the conductor 560 is substantially vertical, specifically, the angle formed by the side surface of the conductor 560 and the substrate surface is 75 degrees or more and 100 degrees or less, It is preferably 80 degrees or more and 95 degrees or less.
  • the insulator 571 may also serve as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 570 may not be provided.
  • the insulator 571 As a hard mask and selectively removing a part of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c, these side surfaces are approximately aligned. In addition, part of the surface of the oxide 530b can be exposed.
  • the transistor 500D has a region 531a and a region 531b in a part of the exposed surface of the oxide 530b.
  • One of the region 531a and the region 531b functions as a source region and the other functions as a drain region.
  • the regions 531a and 531b are formed by, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like to introduce an impurity element such as phosphorus or boron into the exposed surface of the oxide 530b. It can be realized. Note that in this embodiment and the like, an “impurity element” refers to an element other than a main component element.
  • a metal film is formed and then heat treatment is performed, so that an element contained in the metal film is diffused into the oxide 530b to form a region 531a and a region 531b. You can also do it.
  • the regions 531a and 531b may be referred to as “impurity regions” or "low resistance regions”.
  • the regions 531a and 531b can be formed in a self-aligned manner. Therefore, the region 531a and / or the region 531b does not overlap with the conductor 560, so that parasitic capacitance can be reduced. Further, no offset region is formed between the channel formation region and the source / drain region (region 531a or region 531b).
  • a self-aligned manner self-alignment
  • an increase in on-current, a reduction in threshold voltage, an improvement in operating frequency, and the like can be realized.
  • an offset region may be provided between the channel formation region and the source / drain region in order to further reduce the off-state current.
  • the offset region is a region having a high electric resistivity and is a region in which the above-mentioned impurity element is not introduced.
  • the offset region can be formed by introducing the above-described impurity element after forming the insulator 575.
  • the insulator 575 also functions as a mask similarly to the insulator 571 and the like. Therefore, an impurity element is not introduced into a region of the oxide 530b which overlaps with the insulator 575, so that the electric resistivity of the region can be kept high.
  • the transistor 500D includes an insulator 570, a conductor 560, a metal oxide 552, an insulator 550, and an insulator 575 on a side surface of the oxide 530c.
  • the insulator 575 is preferably an insulator having a low relative dielectric constant.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes for the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later step.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulator 575 preferably has a function of diffusing oxygen.
  • the transistor 500D includes the insulator 575 and the insulator 544 over the oxide 530.
  • the insulator 544 is preferably formed by a sputtering method. By using the sputtering method, an insulator containing few impurities such as water or hydrogen can be formed. For example, aluminum oxide is preferably used as the insulator 544.
  • an oxide film formed by a sputtering method may extract hydrogen from a structure to be formed. Therefore, the insulator 544 absorbs hydrogen and water from the oxide 530 and the insulator 575, whereby the hydrogen concentration of the oxide 530 and the insulator 575 can be reduced.
  • FIG. 30A is a top view of the transistor 500E.
  • 30B is a cross-sectional view of a portion indicated by alternate long and short dash line L1-L2 in FIG. 30A.
  • FIG. 30C is a sectional view of a portion indicated by alternate long and short dash line W1-W2 in FIG. 30A. Note that in the top view of FIG. 30A, some elements are omitted for clarity.
  • the transistor 500E is a modification of the above transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.
  • the conductor 542a and the conductor 542b are not provided, and the region 531a and the region 531b are provided in part of the exposed surface of the oxide 530b.
  • One of the region 531a and the region 531b functions as a source region and the other functions as a drain region.
  • the insulator 573 is provided between the oxide 530b and the insulator 544.
  • the regions 531a and 531b illustrated in FIGS. 30A to 30C are regions in which the following elements are added to the oxide 530b.
  • the region 531a and the region 531b can be formed by using a dummy gate, for example.
  • a dummy gate may be provided over the oxide 530b, the dummy gate may be used as a mask, and an element which reduces the resistance of a part of the oxide 530b may be added. That is, the element is added to a region where the oxide 530 does not overlap with the dummy gate, so that the region 531a and the region 531b are formed.
  • an ion implantation method in which an ionized raw material gas is added by mass separation an ion doping method in which an ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, etc. Can be used.
  • boron or phosphorus is typically given.
  • hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas element, or the like may be used.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • the concentration of the element may be measured using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.
  • boron and phosphorus can be added to an Si transistor manufacturing line device in which amorphous silicon, low-temperature polysilicon, or the like is included in a semiconductor layer, it is possible to add one of the oxides 530b by using the manufacturing line device. The resistance of the part can be reduced. That is, part of the Si transistor manufacturing line can be used for the manufacturing process of the transistor 500E.
  • an insulating film to be the insulator 573 and an insulating film to be the insulator 544 may be formed over the oxide 530b and the dummy gate.
  • the insulating film to be the insulator 580 is provided on the insulating film to be the insulator 544, the insulating film to be the insulator 580 is subjected to a CMP (Chemical Mechanical Polishing) treatment to form the insulator 580.
  • CMP Chemical Mechanical Polishing
  • a part of the insulating film is removed to expose the dummy gate.
  • part of the insulator 573 which is in contact with the dummy gate may be removed. Therefore, the insulator 544 and the insulator 573 are exposed on the side surface of the opening provided in the insulator 580, and the regions 531a and 531b provided in the oxide 530b are exposed on the bottom surface of the opening. Part of each is exposed.
  • an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening, and then CMP treatment or the like is performed until the insulator 580 is exposed.
  • CMP treatment or the like is performed until the insulator 580 is exposed.
  • the insulator 573 and the insulator 544 are not essential components. It may be appropriately designed depending on the desired transistor characteristics.
  • the transistor shown in FIG. 30 is not provided with the conductor 542a and the conductor 542b, so that cost reduction can be achieved.
  • Transistor Structure Example 6 >> 25A and 25B, the structure example in which the conductor 560 functioning as a gate is formed inside the opening of the insulator 580 is described, but, for example, above the conductor, A structure provided with the insulator can also be used. A structural example of such a transistor is shown in FIGS. 31A, 31B, 32A, and 32B.
  • FIG. 31A is a top view of the transistor
  • FIG. 31B is a perspective view of the transistor.
  • 32A shows a cross-sectional view of L1-L2 in FIG. 31A
  • FIG. 32B shows a cross-sectional view of W1-W2.
  • the transistors shown in FIGS. 31A, 31B, 32A, and 32B each include a conductor BGE having a function as a back gate, an insulator BGI having a function as a gate insulating film, an oxide semiconductor S, and a gate insulating film.
  • the conductor PE has a function as a plug for connecting the conductor WE to the oxide S, the conductor BGE, or the conductor FGE. Note that here, an example in which the oxide semiconductor S is formed of three layers of oxides S1, S2, and S3 is shown.
  • FIG. 33A is a top view of the capacitor 600A
  • FIG. 33B is a perspective view illustrating a cross section taken along alternate long and short dash line L3-L4 of the capacitive element 600A
  • FIG. 33C is a cross section taken along alternate long and short dash line W3-L4 of the capacitive element 600A.
  • the conductor 610 functions as one of the pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A.
  • the insulator 630 functions as a dielectric sandwiched between the pair of electrodes.
  • the capacitive element 600 is electrically connected to a conductor 546 and a conductor 548 below the conductor 610.
  • the conductor 546 and the conductor 548 function as a plug or a wiring for connecting to another circuit element.
  • 33A to 33C, the conductor 546 and the conductor 548 are collectively referred to as a conductor 540.
  • an insulator 586 in which conductors 546 and 548 are embedded an insulator 650 covering the conductors 620 and 630, and Is omitted.
  • the capacitor 600 shown in FIGS. 23, 24, and 33A to 33C is a planar type, the shape of the capacitor is not limited to this.
  • the capacitor 600 may be the cylinder-type capacitor 600B shown in FIGS. 34A to 34C.
  • FIG. 34A is a top view of the capacitor 600B
  • FIG. 34B is a cross-sectional view taken along dashed-dotted line L3-L4 of the capacitor 600B
  • FIG. 34C is a perspective view showing a cross-section taken along dashed-dotted line W3-L4 of the capacitor 600B. is there.
  • a capacitor 600B includes an insulator 631 over an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, and a conductor 610 functioning as one of a pair of electrodes. And a conductor 620 that functions as the other of the pair of electrodes.
  • the insulator 586, the insulator 650, and the insulator 651 are omitted for the sake of clearly showing the figure.
  • the same material as the insulator 586 can be used.
  • a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540.
  • a material similar to that of the conductor 330 and the conductor 518 can be used, for example.
  • the same material as the insulator 586 can be used.
  • the insulator 651 has an opening as described above, and the opening overlaps the conductor 611.
  • the conductor 610 is formed on the bottom and side surfaces of the opening. That is, the conductor 610 overlaps with the conductor 611 and is electrically connected to the conductor 611.
  • an opening is formed in the insulator 651 by an etching method or the like, and then the conductor 610 is formed by a sputtering method, an ALD method, or the like. After that, the conductor 610 formed over the insulator 651 may be removed by a CMP (Chemical Mechanical Polishing) method or the like, leaving the conductor 610 formed over the opening.
  • CMP Chemical Mechanical Polishing
  • the insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. Note that the insulator 630 functions as a dielectric which is sandwiched between a pair of electrodes in the capacitor.
  • the conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled.
  • the insulator 650 is formed so as to cover the insulator 630 and the conductor 620.
  • the cylinder type capacitance element 600B shown in FIG. 34 can have a higher capacitance value than the planar type capacitance element 600A. Therefore, for example, by applying the capacitor 600B as the capacitor C3, the capacitor C3r, or the like described in the above embodiment, the voltage between the terminals of the capacitor can be maintained for a long time.
  • a metal oxide that can be used for the OS transistor described in any of the above embodiments is a CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), and a CAAC-OS (c-axis aligned Crystal Oxide Semiconductor). ) Will be described.
  • CAC represents an example of a function or a material structure
  • CAAC represents an example of a crystal structure.
  • CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) which are carriers and the insulating function is a function of electrons that are carriers. It is a function that does not flow.
  • the CAC-OS or the CAC-metal oxide has a conductive area and an insulating area.
  • the conductive region has the above-mentioned conductive function
  • the insulating region has the above-mentioned insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material.
  • the conductive region may be observed as a cloudy connection at the periphery and connected in a cloud shape.
  • the conductive region and the insulating region are each dispersed in the material in a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • the CAC-OS or the CAC-metal oxide is composed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region.
  • a carrier when flowing a carrier, a carrier mainly flows in the component which has a narrow gap.
  • the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force, that is, a large on-current and a high field-effect mobility can be obtained in the on-state of the transistor.
  • the CAC-OS or the CAC-metal oxide can also be referred to as a matrix composite material or a metal matrix composite material.
  • Oxide semiconductors are classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, a nc-OS (nanocrystal oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide).
  • OS amorphous-like oxide semiconductor (OS) and amorphous oxide semiconductors.
  • CAAC-OS has a crystal structure having a c-axis orientation, and a plurality of nanocrystals are connected in the ab plane direction to have a strain.
  • the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where a plurality of nanocrystals are connected.
  • Nanocrystals are basically hexagonal, but they are not limited to regular hexagons and may be non-regular hexagons.
  • the strain may have a lattice arrangement such as a pentagon and a heptagon.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the distortion of the lattice arrangement suppresses the formation of crystal grain boundaries. This is because the CAAC-OS can tolerate strain due to a non-dense arrangement of oxygen atoms in the ab plane direction, a change in bond distance between atoms due to substitution with a metal element, or the like. It is thought to be because.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure).
  • indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as an (In, M, Zn) layer.
  • the indium of the In layer is replaced with the element M, it can be expressed as an (In, M) layer.
  • CAAC-OS is an oxide semiconductor with high crystallinity.
  • the CAAC-OS a clear crystal grain boundary cannot be confirmed, so that it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • the crystallinity of an oxide semiconductor might be lowered due to the inclusion of impurities, the generation of defects, or the like; therefore, it can be said that the CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor including the CAAC-OS has stable physical properties. Therefore, the oxide semiconductor including the CAAC-OS is highly heat resistant and highly reliable. Further, the CAAC-OS is stable even at a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when the CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be increased.
  • Nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • an oxide semiconductor having a low carrier density is preferably used for the transistor.
  • the concentration of impurities in the oxide semiconductor film may be lowered and the density of defect states may be lowered.
  • low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • the oxide semiconductor has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 and less than 1 ⁇ 10 ⁇ 9 / cm 3. It may be cm 3 or more.
  • the density of trap states may be low.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level might be formed and a carrier might be generated. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
  • the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor obtained by SIMS is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the concentration of nitrogen in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ 10 18. Atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and further preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency.
  • oxygen When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm 3. It is less than 3 , and more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • This embodiment mode shows an example of a semiconductor wafer in which the semiconductor device or the like shown in the above embodiment mode is formed and an electronic component in which the semiconductor device is incorporated.
  • a semiconductor wafer 4800 illustrated in FIG. 35A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the top surface of the wafer 4801. A portion without the circuit portion 4802 on the upper surface of the wafer 4801 is a spacing 4803, which is a dicing area.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to reduce the thickness of the wafer 4801. Through this step, warpage of the wafer 4801 can be reduced and the size of the component can be reduced.
  • the next step is the dicing process.
  • the dicing is performed along the scribe line SCL1 and the scribe line SCL2 (which may be referred to as a dicing line or a cutting line) indicated by the one-dot chain line.
  • the spacing 4803 is provided so that the plurality of scribe lines SCL1 are parallel to each other and the plurality of scribe lines SCL2 are parallel to each other in order to easily perform the dicing process, and the scribe lines SCL1 and SCL2 are It is preferable that they are provided vertically.
  • a chip 4800a as shown in FIG. 35B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a includes a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that it is preferable that the spacing 4803a be as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit portions 4802 may be substantially equal to the cut margin of the scribe line SCL1 or the cut margin of the scribe line SCL2.
  • the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 35A.
  • it may be a semiconductor wafer having a rectangular shape.
  • the shape of the element substrate can be changed as appropriate depending on a manufacturing process of the element and an apparatus for manufacturing the element.
  • FIG. 35C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted.
  • the electronic component 4700 illustrated in FIG. 35C includes the lead 4701 and the chip 4800a described above, and functions as an IC chip or the like.
  • an electronic component 4700 including a semiconductor device such as the arithmetic circuit 110 described in the above embodiment is referred to as a brain morphic processor (BMP).
  • BMP brain morphic processor
  • the electronic component 4700 includes, for example, a wire bonding step of electrically connecting the lead 4701 of the lead frame and the electrode on the chip 4800a with a thin metal wire, a molding step of sealing with an epoxy resin, and a lead frame. It can be manufactured by performing a plating process on the lead 4701 and a printing process on the surface of the package. Further, in the wire bonding process, for example, ball bonding, wedge bonding or the like can be used. Further, in FIG. 35C, QFP (Quad Flat Package) is applied to the package of the electronic component 4700, but the form of the package is not limited to this.
  • QFP Quad Flat Package
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702.
  • a plurality of such IC chips are combined and electrically connected to each other on the printed board 4702, whereby the mounting board 4704 is completed.
  • FIG. 35D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 4731 is provided on a package substrate 4732 (printed substrate), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 for example, the semiconductor device described in the above embodiment, a wide band memory (HBM: High Bandwidth Memory), or the like can be used.
  • the semiconductor device 4735 an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or a multilayer.
  • the interposer 4731 has a function of electrically connecting an integrated circuit provided over the interposer 4731 to an electrode provided over the package substrate 4732.
  • an interposer may be called a "redistribution board" or an "intermediate board.”
  • a through electrode may be provided in the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • TSV Three Silicon Via
  • a silicon interposer As the interposer 4731. Since a silicon interposer does not need to have an active element, it can be manufactured at lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use the silicon interposer as the interposer for mounting the HBM.
  • a heat sink may be provided so as to overlap with the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 be uniform.
  • the semiconductor device 4710 and the semiconductor device 4735 have the same height.
  • An electrode 4733 may be provided on the bottom of the package substrate 4732 in order to mount the electronic component 4730 on another substrate.
  • FIG. 35D shows an example in which the electrode 4733 is formed of a solder ball.
  • BGA Ball Grid Array
  • the electrode 4733 may be formed using a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 4730 can be mounted on another board by using various mounting methods other than BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN Quad-on-Flag
  • FIG. 36 illustrates a state where an electronic component 4700 (BMP) including the semiconductor device is included in each electronic device.
  • BMP electronic component 4700
  • the information terminal 5500 illustrated in FIG. 36 is a mobile phone (smartphone) that is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 and a button is provided in the housing 5510 as an input interface.
  • the information terminal 5500 can execute an application utilizing artificial intelligence.
  • an application using artificial intelligence for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5511, a character input by a user on a touch panel included in the display unit 5511, a figure, etc. are recognized, An application displayed on the display portion 5511, an application for biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • FIG. 36 illustrates an information terminal 5900 as an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, operators 5904, a band 5905, and the like.
  • the wearable terminal can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiments.
  • applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, and a navigation system that selects and guides an optimal route by inputting a destination.
  • FIG. 36 shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the desktop information terminal 5300, new artificial intelligence can be developed.
  • a smartphone and a desktop information terminal are illustrated as electronic devices in FIG. 36, respectively, but information terminals other than the smartphone and the desktop information terminal can be applied.
  • information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
  • FIG. 36 illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the food items stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuff, and the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature according to the food.
  • an electric refrigerator / freezer is described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, a microwave oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner including an air conditioner. Examples include appliances, washing machines, dryers and audiovisual equipment.
  • FIG. 36 shows a portable game machine 5200 which is an example of a game machine.
  • the portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 36 shows a stationary game machine 7500 which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit for displaying a game image, a touch panel or a stick that serves as an input interface other than the buttons, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 36, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a trigger can be used as a button and a controller simulating a gun can be used.
  • a controller having a shape imitating a musical instrument, a musical instrument, or the like can be used.
  • the stationary game machine may be provided with a camera, a depth sensor, a microphone, etc. instead of using the controller, and may be operated by the game player's gesture and / or voice.
  • the video image of the game machine described above can be output by a display device such as a television device, a display for personal computer, a display for game, or a head mounted display.
  • a display device such as a television device, a display for personal computer, a display for game, or a head mounted display.
  • the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced by the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behaviors of the creatures appearing in the game, and the phenomena occurring in the game are determined by the program included in the game.
  • artificial intelligence to the portable game machine 5200, It enables expressions that are not limited to game programs. For example, it is possible to express that the contents of the question asked by the player, the progress of the game, the time, and the behavior of the person appearing in the game change.
  • the artificial intelligence can configure the game player as an anthropomorphic person. You can play games.
  • a portable game machine is illustrated as an example of a game machine, but the electronic device of one embodiment of the present invention is not limited to this.
  • Examples of the electronic device of one embodiment of the present invention include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a batting practice pitch installed in a sports facility. Machines and the like.
  • the semiconductor device described in any of the above embodiments can be applied to an automobile which is a moving object and the periphery of a driver's seat of the automobile.
  • FIG. 36 shows an automobile 5700, which is an example of a moving body.
  • a display device showing the information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment can be applied as a component of artificial intelligence
  • the semiconductor device can be used for an automatic driving system of a car 5700, for example.
  • the semiconductor device can be used for a system that performs road guidance, risk prediction, or the like.
  • the display device may be configured to display information such as road guidance and risk prediction.
  • a car is described as an example of the moving body, but the moving body is not limited to a car.
  • a moving object a train, a monorail, a ship, an flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), or the like can be given.
  • the semiconductor device of one embodiment of the present invention is applied to these moving objects. Then, a system using artificial intelligence can be added.
  • FIG. 36 shows a digital camera 6240 which is an example of an image pickup apparatus.
  • the digital camera 6240 includes a housing 6241, a display portion 6242, operation buttons 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately mounted.
  • the digital camera 6240 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced by the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the digital camera 6240 having artificial intelligence can be realized.
  • the digital camera 6240 has a function of automatically recognizing a subject such as a face or an object, a function of adjusting focus according to the subject, a function of automatically lighting a flash according to an environment, It can have a function of adjusting the color of a captured image.
  • Video camera The semiconductor device described in any of the above embodiments can be applied to a video camera.
  • FIG. 36 shows a video camera 6300 which is an example of an image pickup apparatus.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, operation keys 6304, a lens 6305, a connecting portion 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display portion 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by the connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. is there.
  • the image on the display portion 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 in the connection portion 6306.
  • the video camera 6300 can perform pattern recognition by artificial intelligence at the time of encoding. By this pattern recognition, it is possible to calculate difference data of a person, an animal, an object, etc. included in continuous captured image data, and compress the data.
  • the semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) or an expansion device for an information terminal.
  • FIG. 37A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable, arithmetic-processing chip.
  • the expansion device 6100 can perform arithmetic processing by the chip by connecting to the PC with, for example, a USB (Universal Serial Bus) or the like.
  • FIG. 37A illustrates the portable expansion device 6100
  • the expansion device of one embodiment of the present invention is not limited to this, and for example, has a relatively small cooling fan or the like. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • the substrate 6104 is housed in the housing 6101.
  • a circuit for driving the semiconductor device and the like described in the above embodiment is provided on the substrate 6104.
  • a chip 6105 for example, the semiconductor device described in the above embodiment, an electronic component 4700, a memory chip, or the like
  • a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • the expansion device 6100 for a PC or the like, it is possible to increase the arithmetic processing capacity of the PC. As a result, even a PC with insufficient processing capacity can perform calculations such as artificial intelligence and moving image processing.
  • FIG. 37B schematically shows data transmission in the broadcasting system. Specifically, FIG. 37B shows a path through which a radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches a television receiver (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna, but a BS 110 ° CS antenna, a CS antenna, or the like can be applied as the antenna 5650.
  • UHF Ultra High Frequency
  • Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and a radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. In each home, the reception of the radio wave 5675B by the antenna 5650 allows the terrestrial broadcast to be viewed on the TV 5600.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 37B, and satellite broadcasting using artificial satellites, data broadcasting using optical lines, etc. may be used.
  • the broadcasting system described above may be a broadcasting system using artificial intelligence by applying the semiconductor device described in the above embodiments.
  • the encoder compresses the broadcasting data
  • the decoder of the receiving device included in the TV 5600 decodes the broadcasting data. Restore is performed.
  • the artificial intelligence it is possible to recognize the display pattern included in the display image in the motion compensation prediction which is one of the encoder compression methods. It is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, an image interpolation process such as up-conversion can be performed when the decoder restores the broadcast data.
  • the above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.
  • UHDTV ultra-high definition television
  • the TV 5600 may be provided with a recording device having artificial intelligence.
  • a recording device having artificial intelligence it is possible to automatically record a program suitable for the user by making the artificial intelligence of the recording apparatus learn the user's preference.
  • FIG. 37C shows a palm print authentication device, which includes a housing 6431, a display portion 6432, a palm print reading portion 6433, and a wiring 6434.
  • FIG. 37C shows how the palm print authentication device acquires the palm print of the hand 6435.
  • the acquired palm print is subjected to pattern recognition processing using artificial intelligence, and it is possible to determine whether or not the palm print belongs to the person. As a result, it is possible to construct a system that performs highly secure authentication.
  • the authentication system according to one embodiment of the present invention is not limited to a palm print authentication device, and is a device for performing biometric authentication by acquiring biometric information such as a fingerprint, vein, face, iris, voiceprint, gene, and physique. Good.
  • ALP Array part, ILD: Circuit, WLD: Circuit, XLD: Circuit, AFP: Circuit, MP: Circuit, MP [1,1]: Circuit, MP [m, 1]: Circuit, MP [i, j]: Circuit, MP [1, n]: circuit, MP [m, n]: circuit, MC: circuit, MCr: circuit, HC: holding unit, HCr: holding unit, HCs: holding unit, HCsr: holding unit, ACTF [ 1]: circuit, ACTF [j]: circuit, ACTF [n]: circuit, TRF: conversion circuit, CMP: comparator, CMPa: comparator, CMPb: comparator, OP: operational amplifier, OPa: operational amplifier, OPb: operational amplifier.
  • INV3 inverter circuit
  • INV5 inverter circuit
  • INV5r inverter circuit
  • INV6 inverter circuit
  • INV6r inverter circuit
  • ADCa analog-digital conversion circuit
  • ADCb analog Digital conversion circuit
  • IL wiring, IL [1]: wiring, IL [j]: wiring, IL [n]: wiring, I1L: wiring, I2L: wiring, ILB: wiring, ILB [1]: wiring, ILB [ j]: wiring, ILB [n]: wiring, I1LB: wiring, I2LB: wiring, OL: wiring, OL [1]: wiring, OL [j]: wiring, OL [n]: wiring, OLB: wiring, OLB [1]: wiring, OLB [j]: wiring, OLB [n]: wiring, IOL: wiring, IOL [1]: wiring, IOL [j]: wiring, IOL [n]: wiring, IOL [1]: wiring, IOL [j]: wiring, IOL

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JP2020556355A JP7441175B2 (ja) 2018-11-08 2019-10-28 半導体装置、及び電子機器
JP2024021696A JP2024055903A (ja) 2018-11-08 2024-02-16 半導体装置
JP2025094375A JP7854547B2 (ja) 2018-11-08 2025-06-05 半導体装置
US19/338,408 US20260020215A1 (en) 2018-11-08 2025-09-24 Semiconductor device and electronic device

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