WO2020093387A1 - 对相变存储单元的操作方法及相关装置 - Google Patents

对相变存储单元的操作方法及相关装置 Download PDF

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Publication number
WO2020093387A1
WO2020093387A1 PCT/CN2018/114885 CN2018114885W WO2020093387A1 WO 2020093387 A1 WO2020093387 A1 WO 2020093387A1 CN 2018114885 W CN2018114885 W CN 2018114885W WO 2020093387 A1 WO2020093387 A1 WO 2020093387A1
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Prior art keywords
pulse
phase change
resistance state
state
change memory
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PCT/CN2018/114885
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English (en)
French (fr)
Inventor
何强
王涛
董广超
李欢
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华为技术有限公司
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Priority to CN201880092772.9A priority Critical patent/CN112041930A/zh
Priority to PCT/CN2018/114885 priority patent/WO2020093387A1/zh
Publication of WO2020093387A1 publication Critical patent/WO2020093387A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable

Definitions

  • the present application relates to the technical field of memory operation, and in particular to an operation method and related device for a phase change memory cell.
  • the phase change memory is a non-volatile memory, including a plurality of phase change memory cells
  • the resistance value of the phase change memory cell can be changed by changing the state of the phase change material, and by resolving the resistance value of the phase change memory cell, data can be realized Write, erase and read operations.
  • the data reading operation is realized by measuring the resistance of the phase change memory cell. At this time, the intensity of the pulse applied to the phase change memory cell is very weak and the time is short, which does not cause the phase change of the phase change material.
  • Both the data writing operation and the erasing operation need to change the phase of the phase change material to change the resistance value of the phase change memory cell. As the number of erasures increases, the resistance value of the phase change memory cell will gradually increase, that is, the problem of resistance drift occurs, and the resistance drift will cause data reading errors.
  • Embodiments of the present application provide an operation method and related device for a phase change memory cell, so as to reduce the occurrence of resistance drift of the phase change memory cell, and thereby improve the data retention capability of the phase change memory cell.
  • an embodiment of the present application provides an operation method for a phase change memory cell.
  • the phase change memory cell includes a first electrode, a phase change layer, and a second electrode.
  • the second electrode is grounded.
  • the method includes:
  • the first pulse and the second pulse are sequentially applied to the first electrode, and the first pulse and the second pulse can respectively adjust the resistance state of the phase change memory cell; wherein, the polarity of the first pulse is opposite to the polarity of the second pulse .
  • the polarities of the first pulse and the second pulse are opposite, so that the elements in the phase change layer will not accumulate excessively in a fixed direction, and even if the number of erasures continues to increase, the elements will be reduced.
  • the accumulation degree of the electrode or the lower electrode, and at the same time, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, thereby reducing the degree of resistance drift of the phase change memory cell and improving the data retention capability.
  • the first pulse may be a positive pulse
  • the second pulse may be a negative pulse.
  • the polarities of the first pulse and the second pulse are opposite, which can further reduce the resistance drift of the phase change memory cell and improve the data retention capability.
  • the first pulse may be a negative pulse
  • the second pulse may be a positive pulse.
  • the polarities of the first pulse and the second pulse are opposite, which can further reduce the resistance drift of the phase change memory cell and improve the data retention capability.
  • the amplitudes of the multiple pulses are unequal and the pulse widths are unequal
  • multiple pulses have the same amplitude and unequal pulse widths, or multiple pulses have unequal amplitudes and the same pulse widths, or multiple pulses have the same amplitude and the same pulse widths.
  • the amplitude and pulse width of the multiple pulses of the first pulse are not limited.
  • the amplitudes of the multiple pulses are unequal and the pulse widths are unequal, or the amplitudes of the multiple pulses are the same and the pulse widths are unequal, or the amplitudes of the multiple pulses are not Equal and the pulse width is the same, or multiple pulses have the same amplitude and the same pulse width.
  • the amplitude and pulse width of the multiple pulses of the second pulse are not limited.
  • the resistance state of the phase change memory cell includes a high resistance state and a low resistance state; a phase change unit corresponding to the high resistance state The resistance value of is greater than the resistance value of the phase change unit corresponding to the low resistance state.
  • the resistance state of the phase change memory cell includes the high resistance state and the low resistance state.
  • the resistance state also includes at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is less than the resistance value of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is greater than the low resistance
  • the resistance of the phase change unit corresponding to the state can realize the multi-value storage of the phase change memory cell.
  • the first pulse is used to adjust the resistance state of the phase change memory unit to the first state; the second pulse is used The resistance state of the phase change memory cell is adjusted from the first state to the second state.
  • the current resistance value of the phase change memory cell can be detected, if the current resistance value falls within the resistance value corresponding to the desired resistance state Within the range, there is no need to apply a pulse to the phase change memory cell, which can improve the efficiency of changing the resistance state.
  • the premise is that the first pulse is one pulse and the second pulse is one pulse; when the first state is a low resistance state When the second state is the first target resistance state, the amplitude of the first pulse is smaller than the amplitude of the second pulse, and the pulse width of the first pulse is greater than the pulse width of the second pulse, where the first target resistance state is Any one of the high resistance state and at least one intermediate resistance state.
  • the amplitude of the first pulse is greater than the amplitude of the second pulse, and the pulse width of the first pulse is smaller than the pulse width of the second pulse,
  • the second target resistance state is any one of the low resistance state and at least one intermediate resistance state.
  • the first pulse is M pulses and the second pulse is N pulses; the method further Including: if the resistance value corresponding to the phase change memory cell read after applying M pulses is within the resistance value range corresponding to the first state, determine to adjust the resistance state of the phase change memory cell to the first state, and M is positive Integer; if the resistance value of the phase change memory unit read after applying N pulses is within the resistance value range corresponding to the second state, then determine to adjust the resistance state of the phase change memory unit to the second state, and N is positive Integer. In this way, the resistance state of the phase change memory cell can be adjusted and determined.
  • the first electrode may be an upper electrode and the second electrode may be a lower electrode; in this case, the upper electrodes are sequentially The first pulse and the second pulse are applied.
  • the first electrode may be a lower electrode
  • the second electrode may be an upper electrode.
  • the first pulse and the second pulse are sequentially applied to the lower electrode.
  • an embodiment of the present application provides an operating device for operating a phase change memory unit.
  • the phase change memory unit includes a first electrode, a phase change layer, and a second electrode.
  • the second electrode is grounded and includes : Pulse application module, which is used to apply the first pulse and the second pulse to the first electrode in sequence, the first pulse and the second pulse are used to adjust the resistance state of the phase change memory cell; wherein, the polarity of the first pulse The polarity of the second pulse is reversed.
  • the polarities of the first pulse and the second pulse are opposite, so that the elements in the phase change layer will not accumulate excessively in a fixed direction, and even if the number of erasures continues to increase, the elements will be reduced.
  • the accumulation degree of the electrode or the lower electrode, and at the same time, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, thereby reducing the degree of resistance drift of the phase change memory cell and improving the data retention capability.
  • the operation device may also implement part or all of the possible implementation manners of the first aspect.
  • an embodiment of the present application provides a chip.
  • the chip includes a controller and a memory.
  • the memory is used to store a computer program.
  • the controller is used to call and run the computer program from the memory.
  • the computer program is used to execute the first aspect. Or all possible implementations.
  • an embodiment of the present application provides a terminal device.
  • the terminal device includes a processor, a memory, and at least one phase change memory unit.
  • the phase change memory unit includes a first electrode, a phase change layer, and a second electrode.
  • the second electrode Grounded, the memory is used to store the computer program, the processor is used to call and run the computer program from the memory, and the processor is used to execute part or all of the possible implementation manners of the first aspect.
  • an embodiment of the present application provides a computer program product.
  • the computer program product includes: computer program code, which, when the computer program code runs on a computer, causes the computer to perform part or all of the possible implementation manners of the first aspect .
  • an embodiment of the present application provides a computer-readable medium that stores program code, and when the computer program code runs on a computer, causes the computer to perform part or all of the possible implementation of the first aspect the way.
  • FIG. 1 is a schematic structural diagram of a possible phase change memory unit provided by an embodiment of the present application
  • FIG. 2a is an example diagram of a pulse application manner provided by an embodiment of the present application.
  • FIG. 2b provides an example diagram of yet another pulse application method according to an embodiment of the present application
  • FIG. 3 provides an example diagram of a pulse form provided by an embodiment of the present application
  • FIG. 4 provides an example diagram of another pulse form provided by an embodiment of the present application.
  • FIG. 5 provides another example diagram of a pulse form provided by an embodiment of the present application.
  • FIG. 6 provides another example diagram of a pulse form provided by an embodiment of the present application.
  • FIG. 7a is an example diagram of yet another pulse form provided by an embodiment of the present application.
  • FIG. 7b is an exemplary diagram of yet another pulse form provided by an embodiment of the present application.
  • 7c is an example diagram of yet another pulse form provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an operation device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another operation device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a possible phase change memory cell according to an embodiment of the present application.
  • the phase change memory cell includes an upper electrode 101, a lower electrode 102, and a phase change layer 103.
  • the phase change layer 103 includes a phase change material.
  • the phase change material can reversibly change between a crystalline state and an amorphous state. The difference in resistance between the two forms makes it possible to store information.
  • the same substance can exist in states such as solids, liquids, gases, condensates, and plasma. These states are called phases.
  • Phase change memory works by using the resistance difference of phase change materials between different phases.
  • a chalcogenide compound can be used as a phase change material, such as Ge 2 Sb 2 Te 5 .
  • the phase change material In the amorphous state, the phase change material has a short distance atomic energy level and a low free electron density, making it have a high resistivity. In the crystalline state, the phase change material has a long-range atomic energy level and a higher free electron density, and thus has a lower resistivity.
  • the pulse voltage source or the pulse current source is connected to the phase change memory unit, and under the excitation of the electric pulse generated by the pulse voltage source or the pulse current source, the phase change material is in a crystalline state and an amorphous state Shift between. Normally, the resistance value of the phase change material in the crystalline state is smaller than that in the amorphous state. By resolving the resistance value of the phase change material, data writing, erasing, and reading operations can be realized.
  • the connection mode of the pulse voltage source and the phase change memory unit is that the pulse voltage source is connected to the upper electrode 101 and the lower electrode 102 is grounded. If it is detected that the resistance value of the phase change memory cell falls within the resistance range corresponding to the crystalline state, a write operation can be performed on the phase change memory cell.
  • the write operation is to apply a short and strong voltage to the upper electrode through the pulse voltage source Pulse, the local temperature of the phase change layer 103 rises and will exceed the melting temperature of the phase change material. After the end of the voltage pulse, the local melting point of the phase change material is quenched at a faster rate, making the phase change layer 103 partially amorphous. Furthermore, it adjusted to an amorphous state.
  • the phase change memory cell can be erased.
  • the erase operation is to apply a long and moderate intensity to the upper electrode through the pulse voltage source.
  • the voltage pulse of ⁇ causes the local temperature of the phase change layer 103 to rise above the crystallization temperature and below the melting point temperature, crystallize the amorphous region of the phase change layer 103, and then adjust to the crystalline state.
  • the data reading operation is realized by measuring the resistance value of the phase change material. At this time, the intensity of the pulse applied to the phase change memory cell is very weak and the time is short, which does not cause the change of the phase change material.
  • phase change material takes Ge 2 Sb 2 Te 5 as an example
  • the Ge element, Sb element, and Te element inside the phase change memory cell will migrate to different extents along the direction of the electric field, where the Ge element and Sb element will move toward the cathode Migrating and accumulating, the Te element migrates and accumulates towards the anode, and the accumulated element will form a defect state.
  • a first pulse and a second pulse with opposite polarities can be sequentially applied to the upper electrode, and the resistance state of the phase change memory cell can be adjusted through the first pulse or the second pulse.
  • the polarities of the first pulse and the second pulse are opposite, so that the elements in the phase change layer will not accumulate excessively in one direction. Even if the number of erasures continues to increase, the accumulation of each element on the upper or lower electrode will be reduced. At the same time, the degree of accumulation of defect states on the upper electrode or the lower electrode of the phase change layer is low, thereby reducing the degree of resistance drift of the phase change memory cell and improving the data retention capability.
  • the amplitude and width of the pulse are determined by factors such as phase change material, medium, and device structure. According to these factors, the amplitude and width of the pulse are different.
  • FIG. 1 is a possible phase change memory cell to which this application is applicable, and this application does not limit the structure of other phase change memory cells including an upper electrode, a lower electrode, and a phase change layer .
  • FIGS. 2 a and 2 b respectively provide example diagrams of pulse application modes for the embodiments of the present application.
  • the example diagram includes a pulse signal source 200 and a phase change memory cell.
  • the phase change memory cell in the embodiment of the present application includes a first electrode, a second electrode, and a phase change layer.
  • the first electrode is the upper electrode 101
  • the second electrode is the lower electrode 102.
  • the lower electrode 102 of the phase change memory cell is grounded, and the pulse signal source 200 applies a pulse to the upper electrode 101 of the phase change memory cell.
  • the first electrode is the lower electrode 103
  • the second electrode is the upper electrode 104.
  • the upper electrode 103 of the phase change memory cell is grounded, and the pulse signal source 200 applies a pulse to the lower electrode 104 of the phase change memory cell.
  • the pulse signal source 200 may be a pulse voltage source or a pulse current source.
  • the pulses are applied to the phase change memory cell according to the connection mode of FIG. 2a or FIG. 2b.
  • the first pulse and the second pulse may be sequentially applied to the first electrode in FIG. 2a or FIG. 2b.
  • the first pulse and the second pulse are used to adjust the resistance state of the phase change memory cell. Among them, the polarities of the first pulse and the second pulse are opposite.
  • the first pulse includes one or more pulses
  • the second pulse includes one or more pulses.
  • the possible combination of the first pulse and the second pulse applied in the embodiment of the present application is: the first pulse is one pulse and the second pulse is one pulse, or the first pulse is multiple pulses and the second pulse is one pulse
  • the first pulse is one pulse and the second pulse is multiple pulses
  • the first pulse is multiple pulses and the second pulse is multiple pulses.
  • a first pulse and a second pulse with opposite polarities can be sequentially applied to the upper electrode, and the resistance state of the phase change memory cell can be adjusted through the first pulse or the second pulse.
  • the polarity of the first pulse and the second pulse are opposite, so that the elements in the phase change layer will not move in one direction.
  • the phase change material uses Ge 2 Sb 2 Te 5 as an example, and the first pulse is a positive pulse
  • the upper electrode is the anode and the lower electrode is the cathode.
  • the Ge and Sb elements will migrate to the lower electrode, and the Te element will migrate to the upper electrode.
  • the second pulse is a negative pulse.
  • the upper electrode is the cathode and the lower electrode is the anode.
  • Ge element and Sb element will migrate to the upper electrode
  • Te element will migrate to the lower electrode.
  • Te element will migrate toward the upper electrode and the lower electrode respectively, instead of the Ge element and the Sb element only toward the lower electrode
  • Te element only migrates towards the upper electrode. It is understandable that since each element will accumulate to form a defect state after multiple migrations, the accumulation degree of the Te element in the upper electrode after migrating in different directions must be smaller than that of the Te element only after migrating in the direction of the upper electrode.
  • the degree of accumulation of the electrode, the defect state will decrease as the degree of accumulation decreases, the same is true for the Ge element and the Sb element. Therefore, even if the number of erasures continues to increase, the degree of accumulation of each element on the upper electrode or the lower electrode will be reduced.
  • the degree of accumulation of defect states on the upper or lower electrode of the phase change layer is lower, thereby reducing the resistance drift of the phase change memory cell. Degree, improve data retention.
  • the resistance of the phase change memory cell can be adjusted by the first pulse or the second pulse.
  • the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer will not be excessively accumulated in one direction, and even if the number of erasures continues to increase, it will reduce the elements on the upper or lower electrode.
  • the degree of accumulation of defect states on the upper or lower electrode of the phase change layer is low, which further reduces the degree of resistance drift of the phase change memory cell and improves the data retention capability.
  • the first pulse is a pulse and the second pulse is a pulse.
  • the polarities of the two pulses are opposite.
  • the first pulse is a positive pulse and the second pulse is The negative pulse, or the first pulse may be a negative pulse and the second pulse may be a positive pulse.
  • the first pulse is used to adjust the resistance state of the phase change memory cell to the first state
  • the second pulse is used to adjust the resistance state of the phase change memory cell from the first state to the second state. Since the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer will not migrate in one direction, and even if the number of erasures continues to increase, it will reduce the accumulation of each element on the upper electrode or the lower electrode.
  • the degree of accumulation of the defect state on the upper electrode or the lower electrode of the phase change layer is low, which further reduces the degree of resistance drift of the phase change memory cell and improves the data retention capability.
  • the resistance state of the phase change memory unit includes a high resistance state and a low resistance state, and the resistance value of the phase change unit corresponding to the high resistance state is greater than the phase change corresponding to the low resistance state The resistance of the unit.
  • the first pulse and the second pulse may be used to adjust the resistance state of the phase-change memory unit to achieve binary storage.
  • the first pulse can be used to adjust the resistance state of the phase change memory cell from the high resistance state to the low resistance state
  • the second pulse can be used to change the resistance state of the phase change memory cell from The low resistance state is adjusted to the high resistance state.
  • the first state is a low resistance state
  • the second state is a high resistance state.
  • the amplitude of the first pulse is smaller than the amplitude of the second pulse
  • the pulse width of the first pulse is larger than the pulse width of the second pulse.
  • the amplitude range of the first pulse is (0.8 volts to 1.5 volts); the pulse width range of the first pulse is (200 nanoseconds to 400 nanoseconds); the amplitude range of the second pulse is ( 1.6 volts to 4 volts); the pulse width of the second pulse is (20 nanoseconds to 100 nanoseconds).
  • the amplitude of the first pulse is 1.3 volts and the pulse width is 300 nanoseconds; the amplitude of the second pulse is 3 volts and the pulse width is 30 nanoseconds.
  • the resistance range of the phase change memory cell corresponding to the low resistance state is (0 ohms to 10 kiloohms), and the resistance range of the phase change memory cell corresponding to the high resistance state is (1 megohms to 10 megohms).
  • the embodiments of the application do not limit the resistance value range corresponding to each resistance value state.
  • FIG. 3 provides an example diagram of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • the first pulse can adjust the phase change material of the phase change memory cell from the amorphous state to the crystalline state, and the resistance state of the phase change memory cell is adjusted to a low resistance state after the adjustment;
  • the second pulse can change the phase change memory cell The phase change material is adjusted from the crystalline state to the amorphous state. After the adjustment, the resistance state of the phase change memory cell is the high resistance state.
  • the first pulse may be a forward set pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 5 kiloohms, determined The phase change memory cell is currently in a low-impedance state; the second pulse is a negative reset pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds.
  • the phase change memory cell After the first pulse is applied, the phase change memory cell ’s The resistance value is 8 megohms, which determines that the phase change memory cell is currently in a high resistance state.
  • the first pulse can be used to adjust the resistance state of the phase change memory cell to a high resistance state
  • the second pulse can be used to adjust the resistance state of the phase change memory cell from the high resistance state to Low resistance state.
  • the first state is a high resistance state
  • the second state is a low resistance state.
  • the "first pulse” in the a2 possible design is equivalent to The "second pulse” in the a1 possible design and the “second pulse” in the a2 possible design are equivalent to the "first pulse” in the a1 possible design; they are not repeated here.
  • performing an erasing operation on a phase change memory cell may specifically implement an erasing operation by applying a first pulse, at which time the phase change memory cell remains at a low resistance State; write operation to the phase change memory cell, if the specified binary number "0" corresponds to the low resistance state, the binary number "1" corresponds to the high resistance state, if you need to write "1", you can achieve by applying a second pulse To keep the phase change memory cell in a high resistance state; if "0" needs to be written, it can be achieved by applying a first pulse to keep the phase change memory cell in a low resistance state.
  • the embodiments of the present application do not limit the resistance value range of the phase change memory cell corresponding to the high resistance state, the low resistance state, and the at least one intermediate resistance state, respectively.
  • the current resistance value of the phase change memory cell can be detected, if the current resistance value falls within the resistance value corresponding to the desired resistance state Within the range, there is no need to apply a pulse to the phase change memory cell.
  • the resistance state of the phase change memory unit includes a high resistance state, a low resistance state, and at least one intermediate resistance state, and the resistance state of the phase change memory unit further includes at least one intermediate state Resistance state; the resistance value of the phase change unit corresponding to the middle resistance state is less than the resistance value of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the middle resistance state is greater than the resistance value of the phase change unit corresponding to the low resistance state value.
  • the first pulse and the second pulse may be used to adjust the resistance state of the phase-change memory unit to achieve multi-value storage.
  • the first pulse can be used to adjust the resistance state of the phase change memory cell to a low resistance state
  • the second pulse can be used to adjust the resistance state of the phase change memory cell to a low resistance state It is the first target resistance state.
  • the first state is a low resistance state
  • the second state is a first target resistance state
  • the first target resistance state is any one of the low resistance state and at least one intermediate resistance state.
  • the amplitude of the first pulse is smaller than the amplitude of the second pulse
  • the pulse width of the first pulse is larger than the pulse width of the second pulse.
  • the amplitude range of the first pulse is (0.8 volts to 1.5 volts); the pulse width range of the first pulse is (200 nanoseconds to 400 nanoseconds); the amplitude range of the second pulse is ( 1.6 volts to 4 volts); the pulse width of the second pulse is (20 nanoseconds to 100 nanoseconds).
  • the amplitude of the first pulse is 1.3 volts and the pulse width is 300 nanoseconds; the amplitude of the second pulse can be increased in the range of 1.5 volts to 3.5 volts and the pulse width is 30 nanoseconds, the different amplitude of the second pulse Corresponding to different resistance states in the first target resistance state, for example, the first target resistance state includes a first intermediate resistance state, a second intermediate resistance state and a high resistance state, and the amplitude of the second pulse is 1.5 volts corresponding to the first intermediate resistance state The amplitude of the second pulse is 2.5V corresponding to the second intermediate resistance state, and the amplitude of the second pulse is 3.5V corresponding to the high resistance state.
  • the resistance value range of the phase change memory cell corresponding to the low resistance state is: (0 ohms to 10 kiloohms), and the resistance value range of the phase change memory cell corresponding to the first intermediate resistance state is (50 kiloohms to 200 kiloohms),
  • the resistance value range of the phase change memory cell corresponding to the second intermediate resistance state is (500 kohm to 700 kohm), and the resistance value range of the phase change memory cell corresponding to the high resistance state is (1 megohm to 10 megohm)
  • the resistance value range corresponding to each resistance value state is not limited.
  • FIG. 4 provides another example of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • This FIG. 4 includes a first pulse 400, a second pulse 401, a second pulse 402, and a second pulse 403.
  • the phase change memory cell applicable to the pulse form of FIG. 4 includes a low resistance state, a first intermediate resistance state, a second intermediate resistance state, and a high resistance state.
  • the resistance value corresponding to the phase change memory cell in the high resistance state is from low to high.
  • the first pulse 400 may be used to adjust the resistance state of the phase change memory cell to a low resistance state
  • the second pulse 401 may be used to adjust the resistance state of the phase change memory cell to a first intermediate resistance state
  • the second pulse 402 It can be used to adjust the resistance state of the phase change memory cell to the second intermediate resistance state
  • the second pulse 403 can be used to adjust the resistance state of the phase change memory cell to the high resistance state.
  • the pulse amplitudes of the second pulse 401, the second pulse 402, and the second pulse 403 are sequentially increased, and the pulse widths of the second pulse 401, the second pulse 402, and the second pulse 403 may be the same.
  • the first pulse 400 is a set pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds; the second pulse 401, the second pulse 402, and the second pulse 403 have a pulse width of 30 nanoseconds and the second pulse 401 ,
  • the pulse amplitude of the second pulse 402 and the second pulse 403 increases from 1.5V to 3.5V.
  • the resistance value range of the phase change memory cell corresponding to the low resistance state is (0 ohms to 10 kiloohms)
  • the resistance value range of the phase change memory cell corresponding to the first intermediate resistance state is (50 kiloohms to 200 kiloohms Europe)
  • the resistance range of the phase change memory cell corresponding to the second intermediate resistance state is (500 kohm to 700 kohm)
  • the resistance value range of the phase change memory cell corresponding to the high resistance state is (1 megohm to 10 Megaohm)
  • the first pulse 400 may be a forward set pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds.
  • the resistance value of the phase change memory cell is detected 5 kiloohms, confirming that the phase change memory cell is currently in a low-impedance state;
  • the second pulse 401 is a negative-going pulse with an amplitude of 1.5 volts and a pulse width of 30 nanoseconds.
  • the phase change is detected The resistance value of the memory cell is 150 kiloohms, and it is determined that the phase-change memory cell is currently in the first intermediate resistance state;
  • the second pulse 402 is a negative-going pulse with an amplitude of 2.5 volts and a pulse width of 30 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 600 kiloohms, and it is determined that the phase change memory cell is currently in the second middle
  • the second pulse 403 is a negative-going pulse with an amplitude of 3.5 volts and a pulse width of 30 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 8 megohms, and the phase change is determined.
  • the memory cell is currently in a high-impedance state.
  • the phase change memory unit shown in FIG. 4 can realize four-value storage, such as 00, 01, 10, and 11; a value corresponds to a resistance state uniquely.
  • the medium-high resistance state shown in FIG. 4 corresponds to 00
  • the first middle resistance state corresponds to 01
  • the second middle resistance state corresponds to 10
  • the low resistance state corresponds to 11.
  • a pulse signal can be applied according to the pulse amplitude and pulse width corresponding to each resistance state shown in FIG.
  • phase change memory cell 4 to change the resistance value of the phase change memory cell, and thereby change the resistance state of the phase change memory cell, For example, if data 11 needs to be written, a pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds is used to change the resistance of the phase change memory cell.
  • the current resistance value of the phase change memory cell can be detected. If the resistance value of the phase change memory cell is in a range corresponding to the low resistance state, it is determined that the data written by the phase change memory cell is 11.
  • the first pulse can be used to adjust the resistance state of the phase change memory cell to a high resistance state
  • the second pulse can be used to adjust the resistance state of the phase change memory cell from the high resistance state to The second target resistance state.
  • the second target resistance state is any one of a low resistance state and at least one intermediate resistance state.
  • the first state is a high resistance state
  • the second state is any one of a low resistance state and at least one intermediate resistance state.
  • the amplitude of the first pulse is greater than the amplitude of the second pulse, and the pulse width of the first pulse is smaller than the pulse width of the second pulse.
  • the amplitude range of the first pulse is (1.6 volts to 4 volts); the pulse width range of the first pulse is (20 nanoseconds to 100 nanoseconds); the amplitude range of the second pulse is ( 0.8 volts to 1.5 volts); the pulse width of the second pulse ranges from (200 nanoseconds to 400 nanoseconds).
  • the amplitude of the first pulse is 3 volts and the pulse width is 30 nanoseconds; the amplitude of the second pulse is 1.3 volts and the pulse width increases from 200 nanoseconds to 400 nanoseconds.
  • the first target resistance state includes a first intermediate resistance state, a second intermediate resistance state and a high resistance state
  • the pulse width of the second pulse is 200 nanoseconds corresponding to the first intermediate resistance State
  • the pulse width of the second pulse is 300 nanoseconds corresponding to the second intermediate resistance state
  • the pulse width of the second pulse is 400 nanoseconds corresponding to the high resistance state.
  • FIG. 5 provides another example diagram of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • This FIG. 5 includes a first pulse 500, a second pulse 501, a second pulse 502, and a second pulse 503.
  • the phase change memory cell applicable to the pulse form of FIG. 5 includes a low resistance state, a first intermediate resistance state, a second intermediate resistance state, and a high resistance state.
  • the resistance value corresponding to the phase change memory cell in the high resistance state is from low to high.
  • the first pulse 500 may be used to adjust the resistance state of the phase change memory cell to a high resistance state
  • the second pulse 501 may be used to adjust the resistance state of the phase change memory cell to a second intermediate resistance state
  • the second pulse 502 may It is used to adjust the resistance state of the phase change memory cell to the first intermediate resistance state
  • the second pulse 503 can be used to adjust the resistance state of the phase change memory cell to the low resistance state.
  • the pulse widths of the second pulse 501, the second pulse 502, and the second pulse 503 increase in sequence, and the pulse amplitudes of the second pulse 501, the second pulse 502, and the second pulse 503 may be the same.
  • the first pulse 500 is a set pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds; the amplitude of the second pulse 501, second pulse 502, and second pulse 503 is 1.3 volts, and the second pulse 501, The pulse widths of the second pulse 502 and the second pulse 503 increase in the range of 200 nanoseconds to 400 nanoseconds.
  • the resistance value range of the phase change memory cell corresponding to the low resistance state is (0 ohms to 10 kiloohms)
  • the resistance value range of the phase change memory cell corresponding to the first intermediate resistance state is (50 kiloohms to 200 kiloohms Europe)
  • the resistance range of the phase change memory cell corresponding to the second intermediate resistance state is (500 kohm to 700 kohm)
  • the resistance value range of the phase change memory cell corresponding to the high resistance state is (1 megohm to 10 Megohms)
  • the first pulse 500 may be a forward pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 8 megohms, Determine that the phase-change memory cell is currently in a high-impedance state; the second pulse 501 is a negative-going pulse with an amplitude of 1.3 volts and a pulse width of 100 nanoseconds. After the second pulse 501 is applied, the resistance of the phase-change memory cell is detected The value is 550 kilohms, and it is determined that the phase change memory cell is currently in the second intermediate resistance state; the second pulse 502 is a negative pulse with an amplitude of 1.3 volts and a pulse width of 200 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 130 kiloohms, and it is determined that the phase change memory cell is currently in the first intermediate resistance state;
  • the second pulse 503 is a negative-going pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds.
  • the resistance value of the phase change memory cell is detected to be 5 kilohms, and the current phase change memory cell is determined It is in a low resistance state.
  • the phase change memory unit shown in FIG. 5 can realize four-value storage, such as 00, 01, 10, and 11; a value corresponds to a resistance state uniquely.
  • the resistance value of the phase change memory cell is changed, thereby changing the resistance state of the phase change memory cell.
  • the middle-high resistance state shown in FIG. 5 corresponds to 11
  • the first middle resistance state corresponds to 01
  • the second middle resistance state corresponds to 10
  • the low resistance state corresponds to 00.
  • a pulse signal can be applied according to the pulse amplitude and pulse width corresponding to each resistance state shown in FIG.
  • phase change memory cell changes the resistance value of the phase change memory cell, and thereby change the resistance state of the phase change memory cell, For example, if data 11 needs to be written, a pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds is used to change the resistance of the phase change memory cell.
  • the current resistance value of the phase change memory cell can be detected. If the resistance value of the phase change memory cell is in a range corresponding to the high resistance state, it is determined that the data written by the phase change memory cell is 11.
  • the erasing operation on the phase-change memory cell can be performed by applying a pulse so that the resistance state of the phase-change memory cell is in a preset initial state, where the initial state is preset It may be a high-resistance state or a low-resistance state in a binary storage scenario, or any one of multiple resistance states in a multi-value storage.
  • the embodiment of the present application does not limit the setting of the preset initial state.
  • the embodiments of the present application do not limit the resistance value range of the phase change memory cell corresponding to the high resistance state, the low resistance state, and at least one intermediate resistance state, respectively.
  • the current resistance value of the phase change memory cell can be detected, if the current resistance value corresponds to the desired resistance state Within the resistance range, there is no need to apply a pulse to the phase change memory cell.
  • an initialization operation may be performed on the phase change memory cell, as shown in FIG. 4
  • the first pulse 400 shown and the first pulse 500 shown in FIG. 5, for example, the initialization operation may be to adjust the resistance state of the phase change memory cell to a low resistance state or a high resistance state, and then to adjust the phase change memory by applying a pulse The resistance state of the unit.
  • the first pulse is multiple pulses and the second pulse is multiple pulses.
  • the polarities of the two pulses are opposite.
  • the first pulse may be a positive pulse.
  • the second pulse is a negative pulse, or the first pulse may be a negative pulse, and the second pulse may be a positive pulse.
  • the first pulse is used to adjust the resistance state of the phase change memory cell to the first state
  • the second pulse is used to adjust the resistance state of the phase change memory cell from the first state to the second state. Since the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer will not migrate in one direction, and even if the number of erasures continues to increase, it will reduce the accumulation of each element on the upper electrode or the lower electrode.
  • the degree of accumulation of the defect state on the upper electrode or the lower electrode of the phase change layer is low, which further reduces the degree of resistance drift of the phase change memory cell and improves the data retention capability.
  • the resistance state of the phase change memory unit includes a high resistance state and a low resistance state, and the resistance value of the phase change unit corresponding to the high resistance state is greater than the phase change corresponding to the low resistance state The resistance of the unit.
  • the first pulse and the second pulse may be used to adjust the resistance state of the phase-change memory unit to achieve binary storage.
  • multiple pulses included in the first pulse can be used to adjust the resistance state of the phase change memory cell from a high resistance state to a low resistance state
  • multiple pulses included in the second pulse can be used to change the resistance value of the phase change memory cell The resistance state is adjusted from a low resistance state to a high resistance state
  • multiple pulses included in the first pulse can be used to adjust the resistance state of the phase change memory cell from the low resistance state to the high resistance state
  • the second pulse includes Multiple pulses can be used to adjust the resistance state of the phase change memory cell from a high resistance state to a low resistance state.
  • the amplitudes of the multiple pulses may be the same or different
  • the pulse widths of the multiple pulses may be the same or different, which is not limited in the embodiment of the present application.
  • the resistance state of the phase change memory unit includes a high resistance state, a high resistance state, a low resistance state, and at least one intermediate resistance state
  • the resistance state of the phase change memory unit also includes At least one intermediate resistance state
  • the resistance value of the phase change unit corresponding to the intermediate resistance state is less than the resistance value of the phase change unit corresponding to the high resistance state
  • the resistance value of the phase change unit corresponding to the intermediate resistance state is greater than the phase change corresponding to the low resistance state
  • the resistance of the unit may be used to adjust the resistance state of the phase-change memory unit to achieve multi-value storage.
  • multiple pulses included in the first pulse can be used to adjust the resistance state of the phase change memory cell to a low resistance state
  • multiple pulses included in the second pulse can be used to change the resistance state of the phase change memory cell by The low resistance state is adjusted to the first target resistance state; the first target resistance state is any one of the low resistance state and at least one intermediate resistance state; or, the multiple pulses contained in the first pulse can be used to The resistance state is adjusted to a high resistance state.
  • the multiple pulses included in the second pulse can be used to adjust the resistance state of the phase change memory cell from the high resistance state to the second target resistance state.
  • the second target resistance state is the low resistance state and Any one of at least one intermediate resistance state.
  • the amplitudes of the multiple pulses may be the same or different, and the pulse widths of the multiple pulses may be the same or different, which is not limited in the embodiment of the present application.
  • FIG. 6 provides another example diagram of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • the first pulse includes pulse 601, pulse 602, and pulse 603; the second pulse includes pulse 604, pulse 605, and pulse 606.
  • the resistance state of the phase change memory cell can be adjusted to the first state, and after applying pulse 604, pulse 605, and pulse 606, the resistance of the phase change memory cell can be adjusted.
  • the value state is adjusted to the second state.
  • the resistance state of the phase change memory cell is also adjusted to the first state.
  • a pulse with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds is used to achieve Figure 6 can be implemented with three pulses with an amplitude of 1.3 volts and a pulse width of 100 nanoseconds.
  • the resistance state of the phase-change memory cell is adjusted to the second state.
  • a pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds is used for implementation.
  • FIG. 6 can use a pulse width of 30 In nanoseconds, three pulses with amplitudes of 2 volts are implemented.
  • the A mode is to realize the one-time adjustment of the resistance state of the phase change storage unit with only one pulse
  • the B mode is to use multiple pulses Realize the one-time adjustment of the resistance state of the phase change memory cell, so that the state of the resistance state of the phase change memory cell introduced by A mode can be changed by multiple pulses to change the resistance state of the phase change memory cell .
  • the first pulse 400 with an amplitude of 1.3 volts and a pulse width of 300 nanoseconds in mode A can be replaced by three nanosecond pulses with an amplitude of 1.3 volts and a pulse width of 100 in mode B, and multiple The pulses are applied to the first electrode in turn; for another example, the first pulse 500 in mode A with a amplitude of 3 volts and a pulse width of 30 nanoseconds can pass mode B with a medium amplitude of 2 volts and a pulse width of 30 nanoseconds. Instead of multiple pulses, and multiple pulses are applied to the first electrode in sequence.
  • the amplitude and pulse width settings of the multiple pulses are not limited.
  • the specific process of performing the erase operation in mode B can refer to the introduction in mode A. The difference between the two lies in the number of pulses applied, the pulse amplitude, and the pulse width, which will not be repeated here.
  • the first pulse is a plurality of pulses and the second pulse is a plurality of pulses.
  • the polarities of the two pulses are opposite.
  • the first pulse may be a positive pulse.
  • the second pulse is a negative pulse, or the first pulse may be a negative pulse, and the second pulse may be a positive pulse.
  • This application does not limit the number of multiple pulses included in the first pulse and the number of multiple pulses included in the second pulse.
  • the amplitudes of the multiple pulses may be the same or different, and the pulse widths of the multiple pulses may be the same or different, which is not limited in the embodiments of the present application.
  • each element in the phase change layer will not migrate in one direction, and even if the number of erasures continues to increase, it will reduce the accumulation of each element on the upper electrode or the lower electrode.
  • the degree of accumulation of the defect state on the upper electrode or the lower electrode of the phase change layer is low, which further reduces the degree of resistance drift of the phase change memory cell and improves the data retention capability.
  • one pulse or a part of the pulses included in the first pulse can adjust the resistance state of the phase change memory unit; one of the pulses included in the second pulse
  • the pulse or part of the pulse can adjust the resistance state of the phase change memory cell.
  • the second pulse can refer to the introduction of the first pulse.
  • the specific process of performing the erasing and writing operation in mode C can refer to the introduction in mode A, and will not be repeated here.
  • FIG. 7a provides another example of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • the first pulse includes pulse 7a01 and pulse 7a02; the second pulse includes pulse 7a03 and pulse 7a04.
  • Each pulse in FIG. 7a can realize the adjustment of the resistance state of the phase change memory cell.
  • pulse 7a01 adjusts the resistance state of the phase change memory cell to the first state
  • pulse 7a02 changes the resistance state of the phase change memory cell by The first state is adjusted to the second state.
  • Pulse 7a03 adjusts the resistance state of the phase change memory cell to the first state
  • pulse 7a04 adjusts the resistance state of the phase change memory cell from the first state to the second state.
  • FIG. 7b provides another example of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • the first pulse includes pulse 7b01, pulse 7b02, pulse 7b03, pulse 7b04, pulse 7b05 and pulse 7b06;
  • the second pulse includes pulse 7b07, pulse 7b08, pulse 7b09, pulse 7b10, pulse 7b11 and pulse 7b12. Two or more pulses in FIG.
  • pulse 7b realize the adjustment of the resistance state of the phase change memory unit, for example, pulse 7b01, pulse 7b02, and pulse 7b03 adjust the resistance state of the phase change memory unit to the first state, pulse 7b04 , Pulse 7b05 and Pulse 7b06 adjust the resistance state of the phase change memory cell from the first state to the second state.
  • 7b07, pulse 7b08, and pulse 7b09 adjust the resistance state of the phase change memory cell to the first state
  • pulse 7b10, pulse 7b11, and pulse 7b12 adjust the resistance state of the phase change memory cell from the first state to the second state. status.
  • FIG. 7c provides another example of a pulse form for the embodiment of the present application.
  • this example diagram takes the first pulse as a positive pulse and the second pulse as a negative pulse as an example.
  • the first pulse includes pulse 7c01, pulse 7c02, pulse 7c03, and pulse 7c04;
  • the second pulse includes pulse 7c05, pulse 7c06, pulse 7c07, and pulse 7c08.
  • One of Fig. 7c can realize the adjustment of the resistance state of the phase change memory cell, and multiple pulses can also realize the adjustment of the resistance state of the phase change memory cell.
  • pulse 7c01, pulse 7c02, and pulse 7c03 change the resistance of the phase change memory cell.
  • pulse 7c04 adjusts the resistance state of the phase change memory cell from the first state to the second state.
  • pulse 7c05, pulse 7c06, and pulse 7c07 adjust the resistance state of the phase change memory cell to the first state
  • pulse 7c08 adjusts the resistance state of the phase change memory cell from the first state to the second state.
  • FIGS. 7a to 7b are only examples of the pulse forms included in the C mode.
  • the embodiment of the present application includes many of the first pulse or the second pulse.
  • the form of each pulse is not limited.
  • the resistance state of the phase change memory unit can be adjusted once by one pulse, or by multiple pulses. Realize one-time adjustment of the resistance state of the phase change memory cell.
  • the above A mode is to realize the one-time adjustment of the resistance state of the phase change memory cell with only one pulse
  • the above B mode is to realize the one time adjustment of the resistance state of the phase change memory cell with multiple pulses, so that in the C mode, one pulse
  • the introduction in mode A for the implementation of the primary resistance state adjustment
  • the resistance value corresponding to the phase-change memory cell read after the i-th pulse is applied, if the read resistance value is not within the resistance value range corresponding to the first state , Then continue to apply the (i + 1) th pulse, if the read resistance is within the resistance range corresponding to the first state, then stop applying to adjust the resistance state of the phase change memory cell to the first state Pulse.
  • N pulses are applied to the phase change memory cell to adjust the resistance state of the phase change memory cell to the second state
  • the resistance value of the phase change memory cell read after applying N pulses is within the resistance range corresponding to the second state, it is determined to adjust the resistance state of the phase change memory cell to the second state, and N is a positive integer.
  • the resistance value corresponding to the phase change memory cell read after the jth pulse is applied, if the read resistance value is not within the resistance value range corresponding to the second state , Continue to apply the (j + 1) th pulse, and if the read resistance is within the resistance range corresponding to the second state, stop the application to adjust the resistance state of the phase change memory cell to the second state Pulse.
  • the resistance range of the phase change memory cell corresponding to the low resistance state For: (0 Euro ⁇ 10 thousand Euro).
  • the resistance value of the phase change memory cell is read to 550 kiloohms, because the resistance value is greater than the corresponding resistance range of the low resistance state. Then continue to apply the second pulse with amplitude of 1.3 volts and pulse width of 100 nanoseconds, and read the resistance value of the phase change memory cell to 80 kiloohms, because the resistance value is greater than the corresponding resistance range of the low resistance state, then continue Apply a third pulse with amplitude of 1.3 volts and a pulse width of 100 nanoseconds, and read the resistance of the phase change memory cell at 7 kiloohms, because the resistance of the current phase change memory cell corresponds to the resistance in the low resistance state Within the range, the application of pulses for adjusting the resistance state of the phase change memory cell to a low resistance state is stopped.
  • the embodiments of the present application do not limit the resistance value range of the phase change memory cell corresponding to the high resistance state, the low resistance state, and at least one intermediate resistance state, respectively, and adjust the resistance of the phase change memory cell
  • the amplitude and pulse width of the pulse used in the value state reference may be made to the specific description in mode A, which will not be repeated here.
  • the number of pulses included in the first pulse and the second pulse exemplified in the above methods A, B, and C are the same, but the number of pulses included in the first pulse and the second pulse in the embodiment of the present application may be different .
  • FIG. 8 is a schematic structural diagram of an operation device provided by an embodiment of the present application.
  • the operating device is used to implement the embodiments of FIGS. 2a to 7c.
  • the operation device 800 is used to operate a phase change memory unit.
  • the phase change memory unit includes a first electrode, a phase change layer, and a second electrode.
  • the second electrode is grounded, and the operation device 800
  • the pulse application module 801 is included, and optionally, the determination module 802 is also included.
  • the pulse applying module 801 is configured to sequentially apply the first pulse and the second pulse to the first electrode, and the first pulse and the second pulse are respectively used to adjust the resistance state of the phase change memory unit; Wherein, the polarity of the first pulse is opposite to the polarity of the second pulse.
  • the first pulse is a positive pulse and the second pulse is a negative pulse;
  • the first pulse is a negative pulse
  • the second pulse is a positive pulse
  • the amplitudes of the plurality of pulses are unequal and the pulse widths are unequal, or the amplitudes of the plurality of pulses are the same and The pulse widths are not equal, or the amplitudes of the multiple pulses are unequal and the pulse widths are the same, or the amplitudes of the multiple pulses are the same and the pulse widths are the same;
  • the amplitudes of the plurality of pulses are unequal and the pulse widths are unequal, or the amplitudes of the plurality of pulses are the same and the pulse widths are unequal, or,
  • the amplitudes of the multiple pulses are unequal and the pulse width is the same, or the amplitudes of the multiple pulses are the same and the pulse width is the same.
  • the resistance state of the phase change memory unit includes a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is greater than that corresponding to the low resistance state The resistance of the phase change unit.
  • the resistance state of the phase change memory unit further includes at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is less than the corresponding resistance value of the high resistance state The resistance value of the phase change unit, and the resistance value of the phase change unit corresponding to the intermediate resistance state is greater than the resistance value of the phase change unit corresponding to the low resistance state.
  • the first pulse is used to adjust the resistance state of the phase change memory unit to the first state;
  • the second pulse is used to change the resistance state of the phase change memory unit Adjust from the first state to the second state.
  • the first pulse is a pulse
  • the second pulse is a pulse
  • the amplitude of the first pulse is greater than the amplitude of the second pulse, the first The pulse width of the pulse is smaller than the pulse width of the second pulse;
  • the amplitude of the first pulse is smaller than the amplitude of the second pulse, the first The pulse width of the pulse is greater than the pulse width of the second pulse;
  • the first target resistance state is any one of the low resistance state and the at least one intermediate resistance state; the second target resistance state is the high resistance state and the at least one intermediate resistance state Any one of them.
  • the first pulse is M pulses and the second pulse is N pulses; the device further includes:
  • the determining module 802 is configured to determine if the resistance value of the phase change memory unit read after applying the M pulses is within the resistance value range corresponding to the first state The resistance state is adjusted to the first state, M is a positive integer;
  • the determining module 802 is further configured to determine the phase change if the resistance value corresponding to the phase change memory unit read after applying the N pulses is within the resistance value range corresponding to the second state The resistance state of the memory cell is adjusted to the second state, and N is a positive integer.
  • the first electrode is an upper electrode and the second electrode is a lower electrode; or, the first electrode is a lower electrode and the second electrode is an upper electrode.
  • the operation device 800 can implement the operation method for the phase change memory unit described in FIGS. 2a to 7c.
  • the detailed process performed by each module refer to the detailed introduction of the embodiments shown in FIGS. 2a to 7c. Repeat.
  • the operation device 800 shown in FIG. 8 described above may be implemented by the operation device 900 shown in FIG. 9.
  • FIG. 9 it is a schematic structural diagram of another operation device provided by the embodiment of the present application.
  • the operation device 900 shown in FIG. 9 includes: a controller 901 and a transceiver 902, and the transceiver 902 is used to support the operation device
  • the signal is transmitted between 900 and the pulse signal source and / or the phase change storage unit, for example, to implement the function of the pulse application module 801 in the embodiment shown in FIG. 8, the controller 901 may be used to implement the determination in the embodiment shown in FIG.
  • the controller 901 and the transceiver 902 are communicatively connected, for example, via a bus.
  • the operation device 900 may further include a memory 903.
  • the memory 903 is used to store program codes and data for execution by the operating device 900, and the controller 901 is used to execute application program codes stored in the memory 903 to implement various modules of the operating device provided in the embodiment shown in FIG.
  • the operation device may include one or more controllers, and the structure of the operation device 900 does not constitute a limitation on the embodiments of the present application.
  • the controller 901 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof.
  • the above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL), or any combination thereof.
  • the memory 903 may include volatile memory (volatile memory), such as random access memory (random access memory, RAM); the memory 903 may also include non-volatile memory (non-volatile memory), such as read-only memory (read-memory) only memory (ROM), flash memory (flash memory), hard disk (hard disk drive) or solid state drive (SSD); the memory 903 may also include a combination of the above types of memory.
  • volatile memory volatile memory
  • RAM random access memory
  • non-volatile memory non-volatile memory
  • ROM read-only memory
  • flash memory flash memory
  • hard disk hard disk drive
  • SSD solid state drive
  • the controller 901 executes the program code and data in the memory 903 specifically: the first pulse and the second pulse are sequentially applied to the first electrode, and the first pulse and the second pulse are respectively It is used to adjust the resistance state of the phase change memory cell; wherein, the polarity of the first pulse is opposite to the polarity of the second pulse.
  • the first pulse and the second pulse are received through the transceiver 902.
  • the first pulse is a positive pulse
  • the second pulse is a negative pulse
  • the first pulse is a negative pulse
  • the second pulse is a positive pulse
  • the amplitudes of the plurality of pulses are unequal and the pulse widths are unequal, or the amplitudes of the plurality of pulses are the same
  • the pulse widths are unequal, or the amplitudes of the multiple pulses are unequal and the pulse width is the same, or the amplitudes of the multiple pulses are the same and the pulse width is the same;
  • the amplitudes of the plurality of pulses are unequal and the pulse widths are unequal, or the amplitudes of the plurality of pulses are the same and the pulse widths are unequal, or,
  • the amplitudes of the multiple pulses are unequal and the pulse width is the same, or the amplitudes of the multiple pulses are the same and the pulse width is the same.
  • the resistance state of the phase change memory unit includes a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is greater than that corresponding to the low resistance state The resistance of the phase change unit.
  • the resistance state of the phase change memory unit further includes at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is less than that corresponding to the high resistance state The resistance value of the phase change unit, and the resistance value of the phase change unit corresponding to the intermediate resistance state is greater than the resistance value of the phase change unit corresponding to the low resistance state.
  • the first pulse is used to adjust the resistance state of the phase change memory unit to the first state; the second pulse is used to change the resistance value of the phase change memory unit The state is adjusted from the first state to the second state.
  • the first pulse is a pulse
  • the second pulse is a pulse
  • the amplitude of the first pulse is smaller than the amplitude of the second pulse, the first The pulse width of the pulse is greater than the pulse width of the second pulse;
  • the amplitude of the first pulse is greater than the amplitude of the second pulse, the first The pulse width of the pulse is smaller than the pulse width of the second pulse;
  • first target resistance state is any one of the high resistance state and the at least one intermediate resistance state
  • second target resistance state is the low resistance state and the at least one intermediate resistance state Any one of them.
  • the first pulse is M pulses
  • the second pulse is N pulses
  • the method further includes:
  • the controller 901 determines the resistance value of the phase change memory unit The value state is adjusted to the first state, M is a positive integer;
  • the controller 901 determines the resistance value of the phase change memory cell The value state is adjusted to the second state, and N is a positive integer.
  • the first electrode is an upper electrode
  • the second electrode is a lower electrode
  • the first electrode is a lower electrode
  • the second electrode is an upper electrode
  • An embodiment of the present application further provides a chip including a processor and a memory.
  • the memory is used to store a computer program.
  • the processor is used to call and run the computer program from the memory. Change the operation method of the storage unit.
  • a computer storage medium which can be used to store computer software instructions used by the operating device, which includes a program designed to execute the operating device in the foregoing embodiment.
  • the storage medium includes but is not limited to flash memory, hard disk, and solid-state hard disk.
  • a computer program product is also provided.
  • the above-mentioned operation method for the phase change storage unit can be performed.
  • FIG. 10 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
  • the terminal device 1000 shown in FIG. 10 includes a processor 1001, a transceiver 1004, a memory 1003, a controller 1005, a phase change memory cell array 1006, and a pulse signal source 1007.
  • the controller 1005 may be used to implement the function of the determining module 802 in the embodiment shown in FIG. 8.
  • the controller 1005 pulses the phase change memory cell array 1006 through the pulse signal source 1007 to implement the embodiment shown in FIG. 8
  • the processor 1001, the controller 1005, the phase change memory cell array 1006, the pulse signal source 1007, and the transceiver 1002 are communicatively connected, for example, via a bus.
  • the terminal device 1000 may further include a memory 1003.
  • the memory 1003 is used to store program codes and data for execution by the terminal device 1000, and the controller 1005 is used to execute application program codes stored in the memory 1003 to implement various modules of the operating device provided in the embodiment shown in FIG.
  • the processor 1001 may be a CPU, NP, hardware chip, or any combination thereof.
  • the above hardware chip may be ASIC, PLD or a combination thereof.
  • the above PLD may be CPLD, FPGA, GAL or any combination thereof.
  • the memory 1003 may include a volatile memory, such as RAM; the memory 1003 may also include a non-volatile memory, such as ROM, flash memory, a hard disk, or a solid-state hard disk; the memory 1003 may also include a combination of the foregoing types of memories.
  • a volatile memory such as RAM
  • the memory 1003 may also include a non-volatile memory, such as ROM, flash memory, a hard disk, or a solid-state hard disk
  • the memory 1003 may also include a combination of the foregoing types of memories.
  • the controller 1005 is used to control a read operation, an erase operation, a write operation, etc. of the phase change memory cell array.
  • the controller may also be a processor, which is combined with the processor 1001 in the terminal device 1000 to implement the functions of the processor 1001 and the controller 1005 later.
  • the phase-change memory cell array 1006 includes a plurality of phase-change memory cells, and each phase-change memory cell can implement binary storage or multi-value storage, that is, the phase-change memory cell includes two or more resistance states.
  • the terminal device may include one or more processors, and the structure of the terminal device 1000 does not constitute a limitation on the embodiments of the present application.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server or data center Transmit to another website, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device including a server, a data center, and the like integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, Solid State Disk (SSD)) or the like.
  • a magnetic medium for example, a floppy disk, a hard disk, a magnetic tape
  • an optical medium for example, a DVD
  • a semiconductor medium for example, Solid State Disk (SSD)
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

Abstract

一种对相变存储单元的操作方法及相关装置，相变存储单元包括第一电极（101）、相变层（103）和第二电极（102），所述第二电极（102）接地，其特征在于，所述方法包括：将第一脉冲和第二脉冲依次施加至所述第一电极（101），所述第一脉冲和所述第二脉冲分别用于调整所述相变存储单元的阻值状态；其中，所述第一脉冲的极性与所述第二脉冲的极性相反。该方法可以减小相变存储单元的阻值漂移的情况发生，进而提高相变存储单元的数据保持能力。

Description

对相变存储单元的操作方法及相关装置 技术领域
本申请涉及存储器的操作技术领域，尤其涉及一种对相变存储单元的操作方法及相关装置。
背景技术
相变存储器为非易失性存储器，包括多个相变存储单元，相变存储单元的电阻值可以通过改变相变材料的状态而变化，通过分辨相变存储单元的电阻值，可以实现数据的写入、擦除和读出操作。其中，数据的读取操作是通过测量相变存储单元的电阻大小来实现的，此时对相变存储单元所施加的脉冲强度很弱且时间较短，不引起相变材料的相位变化。数据写入操作和擦除操作均需要改变相变材料的相位，以改变相变存储单元的电阻值。而随着擦写次数的增多，相变存储单元的阻值会逐渐增大，即引发产生阻值漂移的问题，而阻值漂移会导致数据读取错误。
发明内容
本申请实施例提供一种对相变存储单元的操作方法及相关装置，以期减小相变存储单元的阻值漂移的情况发生，进而提高相变存储单元的数据保持能力。
第一方面，本申请实施例提供了一种对相变存储单元的操作方法，相变存储单元包括第一电极、相变层和第二电极，第二电极接地，该方法包括：
将第一脉冲和第二脉冲依次施加至第一电极，第一脉冲和第二脉冲分别可以调整相变存储单元的阻值状态；其中，第一脉冲的极性与第二脉冲的极性相反。
在第一方面中，由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着固定一个方向过度积累，即使擦写次数不断增加也会降低各元素在上电极或下电极的累积程度，同时，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
结合第一方面，在第一方面的第一种可能实现方式中，第一脉冲可以为正向脉冲，第二脉冲可以为负向脉冲。这样第一脉冲和第二脉冲的极性是相反的，进而可以降低相变存储单元的阻值漂移程度，提高了数据保持能力。
结合第一方面，在第一方面的第二种可能实现方式中，第一脉冲可以为负向脉冲，第二脉冲可以为正向脉冲。这样第一脉冲和第二脉冲的极性是相反的，进而可以降低相变存储单元的阻值漂移程度，提高了数据保持能力。
结合第一方面以及上述各种可能实现方式，在第一方面的第三种可能实现方式中，在第一脉冲为多个脉冲的情况下，多个脉冲的幅值不等且脉宽不等，或者，多个脉冲的幅值相同且脉宽不等，或者，多个脉冲的幅值不等且脉宽相同，或者，多个脉冲的幅值相同且脉宽相同。本申请实施例中对第一脉冲的多个脉冲的幅值和脉宽不做限定。
在第二脉冲为多个脉冲的情况下，多个脉冲的幅值不等且脉宽不等，或者，多个脉冲的幅值相同且脉宽不等，或者，多个脉冲的幅值不等且脉宽相同，或者，多个脉冲的幅值相同且脉宽相同。本申请实施例中对第二脉冲的多个脉冲的幅值和脉宽不做限定。
结合第一方面以及上述各种可能实现方式，在第一方面的第四种可能实现方式中，相变存储单元的阻值状态包括高阻态和低阻态；高阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。通过这两个阻值状态可以实现相变存储单元的二值存储。
结合第一方面的第四种可能实现方式，在第一方面的第五种可能实现方式中，相变存储单元的阻值状态除了包括高阻态和低阻态之外，相变存储单元的阻值状态还包括至少一个中间阻态；中间阻态对应的相变单元的阻值小于高阻态对应的相变单元的阻值，且中间阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。通过这三个或者三个以上的阻值状态可以实现相变存储单元的多值存储。
结合第一方面的第五种可能实现方式，在第一方面的第六种可能实现方式中，第一脉冲用于将相变存储单元的阻值状态调整为第一状态；第二脉冲用于将相变存储单元的阻值状态由第一状态调整为第二状态。可选的，在对相变存储单元执行施加脉冲的操作以改变阻值状态之前，可以检测相变存储单元当前的阻值，若当前的阻值落在所需的阻值状态对应的阻值范围内，则无需对相变存储单元施加脉冲，这样可以提高改变阻值状态的效率。
结合第一方面的第六种可能实现方式，在第一方面的第七种可能实现方式中，以第一脉冲为一个脉冲且第二脉冲为一个脉冲为前提；在第一状态为低阻态且第二状态为第一目标阻态的情况下，第一脉冲的幅值小于第二脉冲的幅值，第一脉冲的脉宽大于第二脉冲的脉宽，其中，第一目标阻态为高阻态和至少一个中间阻态中的任意一个。在第一状态为高阻态且第二状态为第二目标阻态的情况下，第一脉冲的幅值大于第二脉冲的幅值，第一脉冲的脉宽小于第二脉冲的脉宽，其中，第二目标阻态为低阻态和至少一个中间阻态中的任意一个。
结合第一方面的第五种可能实现方式或第六种可能实现方式，在第一方面的第八种可能实现方式中，第一脉冲为M个脉冲，第二脉冲为N个脉冲；方法还包括：若施加M个脉冲后读取的相变存储单元对应的阻值在第一状态对应的阻值范围内，则确定将相变存储单元的阻值状态调整为第一状态，M为正整数；若施加N个脉冲后读取的相变存储单元对应的阻值在第二状态对应的阻值范围内，则确定将相变存储单元的阻值状态调整为第二状态，N为正整数。通过这一方式可以调整和确定相变存储单元的阻值状态。
结合第一方面以及上述各种可能实现方式，在第一方面的第九种可能实现方式中，第一电极可以为上电极，第二电极可以为下电极；这一情况下是对上电极依次施加第一脉冲和第二脉冲。
结合第一方面以及上述各种可能实现方式，在第一方面的第九种可能实现方式中，第一电极可以为下电极，第二电极可以为上电极。这一情况下是对下电极依次施加第一脉冲和第二脉冲。
第二方面，本申请实施例提供了一种操作装置，操作装置用于对相变存储单元进行操作，相变存储单元包括第一电极、相变层和第二电极，第二电极接地，包括：脉冲施加模块，用于将第一脉冲和第二脉冲依次施加至第一电极，第一脉冲和第二脉冲分别用于调整相变存储单元的阻值状态；其中，第一脉冲的极性与第二脉冲的极性相反。
在第二方面中，由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着固定一个方向过度积累，即使擦写次数不断增加也会降低各元素在上电极或下电极的累 积程度，同时，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
可选的，该操作装置还可以实现第一方面的部分或全部的可能的实现方式。
第三方面，本申请实施例提供了一种芯片，芯片包括控制器和存储器，存储器用于存储计算机程序，控制器用于从存储器中调用并运行计算机程序，计算机程序用于执行第一方面的部分或全部的可能的实现方式。
第四方面，本申请实施例提供了一种终端设备，终端设备包括处理器、存储器、至少一个相变存储单元，相变存储单元包括第一电极、相变层和第二电极，第二电极接地，存储器用于存储计算机程序，处理器用于从存储器中调用并运行计算机程序，处理器用于执行第一方面的部分或全部的可能的实现方式。
第五方面，本申请实施例提供了一种计算机程序产品，计算机程序产品包括：计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行第一方面的部分或全部的可能的实现方式。
第六方面，本申请实施例提供了一种计算机可读介质，计算机可读介质存储有程序代码，当计算机程序代码在计算机上运行时，使得计算机执行第一方面的部分或全部的可能的实现方式。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图进行说明。
图1为本申请实施例提供了一种可能的相变存储单元的结构示意图；
图2a为本申请实施例提供了一种脉冲施加方式的示例图；
图2b为本申请实施例提供了又一种脉冲施加方式的示例图；
图3为本申请实施例提供了一种脉冲形式的示例图；
图4为本申请实施例提供了又一种脉冲形式的示例图；
图5为本申请实施例提供了又一种脉冲形式的示例图；
图6为本申请实施例提供了又一种脉冲形式的示例图；
图7a是本申请实施例提供的又一种脉冲形式的示例图；
图7b是本申请实施例提供的又一种脉冲形式的示例图图；
图7c是本申请实施例提供的又一种脉冲形式的示例图；
图8是本申请实施例提供的一种操作装置的结构示意图；
图9是本申请实施例提供了另一种操作装置的结构示意图；
图10是本申请实施例提供的一种终端设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行说明。
请参见图1，图1是本申请实施例涉及的一种可能的相变存储单元的结构示意图。如 图1所示，该相变存储单元包括上电极101、下电极102、相变层103。
其中，相变层103包括相变材料，相变材料能在晶态和非晶态之间可逆转变，两种形态的电阻差异使其可以用于存储信息。同一物质可以在诸如固体、液体、气体、冷凝物和等离子体等状态下存在，这些状态都称为相。相变存储器便是利用相变材料在不同相间的电阻差异进行工作的。例如，可以使用硫系化合物作为相变材料，如Ge 2Sb 2Te 5。
在非晶态下，相变材料具有短距离的原子能级和较低的自由电子密度，使得其具有较高的电阻率。在晶态下，相变材料具有长距离的原子能级和较高的自由电子密度，从而具有较低的电阻率。
在可能的实现方案中，将脉冲电压源或脉冲电流源与相变存储单元连接，在由脉冲电压源或脉冲电流源产生的电脉冲的激励下，使相变材料在晶态和非晶态之间转变。通常情况下，相变材料在晶态对应的电阻值小于在非晶态对应的电阻值，通过分辨相变材料的电阻值，可以实现数据的写入、擦除和读出操作。
举例来说，脉冲电压源与相变存储单元连接的连接方式为脉冲电压源与上电极101相连接，下电极102接地。若检测出相变存储单元的电阻值落在晶态对应的阻值范围内，可以对相变存储单元执行写入操作，写入操作是通过脉冲电压源对上电极施加一个短而强的电压脉冲，相变层103局部温度上升且会超过相变材料的熔点温度，当该电压脉冲结束后相变材料局部的熔融点以较快的速度急冷，使相变层103局部非晶态化，进而调整为非晶态。若检测出相变存储单元的电阻值落在非晶态对应的阻值范围内，可以对相变存储单元执行擦除操作，擦除操作是通过脉冲电压源对上电极施加一个长而强度中等的电压脉冲，使相变层103局部温度上升到结晶温度以上且熔点温度以下，使相变层103的非晶化区发生晶化，进而调整为晶态。数据的读取操作是通过测量相变材料的电阻值来实现的，此时对相变存储单元所施加的脉冲强度很弱且时间较短，不引起相变材料的变化。
实际中，往往是对上电极施加单极性的脉冲来实现数据的写入、擦除和读出操作，随着擦写次数的增多，相变存储单元的阻值会逐渐增大，即出现阻值漂移的现象。是因为：相变材料以Ge 2Sb 2Te 5为例，相变存储单元内部的Ge元素、Sb元素、Te元素会沿着电场方向发生不同程度迁移，其中，Ge元素和Sb元素会向阴极迁移并积累，Te元素向阳极迁移并积累，所积累的元素会形成缺陷态。结合图1所示的相变存储单元的结构示意图来说，如果下电极102接地，且通过脉冲电压源对上电极施加正向的电压脉冲，这样上电极是阳极、下电极是阴极，随着擦写次数增加，Ge元素和Sb元素会累积在下电极与相变层界面处，Te元素会累积在上电极与相变层界面处。随擦写次数的增加，相变层中的各元素会朝着一个方向过度积累，缺陷态在相变层上电极或下电极的累积程度较高，进而相变存储单元的阻值会出现大幅度的增加，即出现了阻值漂移，而写入、擦除和读出操作是通过分辨阻值来实现的，阻值漂移后会影响数据读取的准确性，降低了数据的保持能力。
而本申请的实施例可以在下电极接地的情况下向上电极依次施加极性相反的第一脉冲和第二脉冲，能够通过第一脉冲或第二脉冲调整相变存储单元的阻值状态，另外由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向过度积累，即使擦写次数不断增加也会降低各元素在上电极或下电极的累积程度，同时，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持 能力。
在本申请实施例中，脉冲的幅度和宽度是由相变材料、介质、器件结构等因素决定的，根据这些因素的不同，脉冲的幅度和宽度是不同的。
可以理解的是，图1所示结构示意图是本申请所适用的一种可能的相变存储单元，本申请对其他包含上电极、下电极、相变层的相变存储单元的结构不做限定。
基于图1所示的可能的相变存储单元的结构示意图，请参见图2a和图2b，分别为本申请实施例提供了脉冲施加方式的示例图。该示例图包括脉冲信号源200和相变存储单元。本申请实施例的相变存储单元包括第一电极、第二电极和相变层。
在一种可能的实现方案中，第一电极为上电极101，第二电极为下电极102。如图2a所示，相变存储单元的下电极102接地，通过脉冲信号源200对相变存储单元的上电极101施加脉冲。
在又一种可能的是实现方案中，第一电极为下电极103，第二电极为上电极104。如图2b所示，相变存储单元的上电极103接地，通过脉冲信号源200对相变存储单元的下电极104施加脉冲。
在本申请实施例中，脉冲信号源200可以为脉冲电压源或脉冲电流源。
按照图2a或图2b的连接方式实现对相变存储单元施加脉冲。具体可以将第一脉冲和第二脉冲依次施加至图2a或图2b中的第一电极。第一脉冲和第二脉冲用于调整相变存储单元的阻值状态。其中，第一脉冲和第二脉冲的极性相反。
其中，第一脉冲包括一个或者多个脉冲，第二脉冲包括一个或者多个脉冲。这样本申请实施例中施加的第一脉冲和第二脉冲可能的组合为：第一脉冲为一个脉冲且第二脉冲为一个脉冲，或者，第一脉冲为多个脉冲且第二脉冲为一个脉冲，或者，第一脉冲为一个脉冲且第二脉冲为多个脉冲，或者，第一脉冲为多个脉冲且第二脉冲为多个脉冲。
而本申请的实施例可以在下电极接地的情况下向上电极依次施加极性相反的第一脉冲和第二脉冲，能够通过第一脉冲或第二脉冲调整相变存储单元的阻值状态，另外由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向迁移，比如，相变材料以Ge 2Sb 2Te 5为例，第一脉冲为正向脉冲，此时上电极为阳极、下电极为阴极，Ge元素和Sb元素会向下电极迁移，Te元素向上电极迁移；第二脉冲为负向脉冲，此时上电极为阴极、下电极为阳极，Ge元素和Sb元素会向上电极迁移，Te元素向下电极迁移。这样在多次改变相变存储单元的阻值状态的情况下，Te元素、Ge元素和Sb元素分别会朝着上电极和下电极的方向迁移，而不是Ge元素和Sb元素仅朝着下电极方向迁移、Te元素仅朝着上电极方向迁移。可以理解的是，由于各元素在迁移多次之后会产生累积形成缺陷态，而Te元素朝着不同方向迁移之后在上电极的累积程度，必然小于Te元素仅朝着上电极方向迁移之后在上电极的累积程度，缺陷态也会随着累积程度的降低而减低，对于Ge元素和Sb元素同样如此。因此，即使擦写次数不断增加也会降低各元素在上电极或者下电极的累积程度，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
同理，对于本申请实施例中在上电极接地的情况下向下电极依次施加极性相反的第一 脉冲和第二脉冲，能够通过第一脉冲或第二脉冲调整相变存储单元的阻值状态，另外由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向过度积累，即使擦写次数不断增加也会降低各元素在上电极或下电极的累积程度，同时，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
接下来对所施加的第一脉冲和第二脉冲包括的多种形式进行介绍。
A、在一种可选的脉冲形式中，第一脉冲为一个脉冲，第二脉冲为一个脉冲，这两个脉冲的极性相反，例如可以为第一脉冲为正向脉冲，第二脉冲为负向脉冲，或者可以为第一脉冲为负向脉冲，第二脉冲为正向脉冲。第一脉冲用于将相变存储单元的阻值状态调整至第一状态，第二脉冲用于将相变存储单元的阻值状态由第一状态调整为第二状态。由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向迁移，即使擦写次数不断增加也会降低各元素在上电极或者下电极的累积程度，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
在相变存储单元可以实现二值存储的场景中，相变存储单元的阻值状态包括高阻态和低阻态，高阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。本申请实施例可以通过第一脉冲和第二脉冲调整相变存储单元的阻值状态，来实现二值存储。
在第a1种可能的设计中，第一脉冲可以用于将相变存储单元的阻值状态由高阻态调整至低阻态，第二脉冲可以用于将相变存储单元的阻值状态由低阻态调整为高阻态。在这一情况下，第一状态为低阻态，第二状态为高阻态。第一脉冲的幅值小于第二脉冲的幅值，第一脉冲的脉宽大于第二脉冲的脉宽。在该可能的设计中，第一脉冲的幅值范围为(0.8伏～1.5伏)；第一脉冲的脉宽范围为(200纳秒～400纳秒)；第二脉冲的幅值范围为(1.6伏～4伏)；第二脉冲的脉宽范围为(20纳秒～100纳秒)。例如，第一脉冲的幅值为1.3伏、脉宽为300纳秒；第二脉冲的幅值为3伏、脉宽为30纳秒。低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)、高阻态对应的相变存储单元的的阻值范围为(1兆欧～10兆欧)，本申请实施例对各阻值状态对应的阻值范围不做限定。
请参见图3，为本申请实施例提供了一种脉冲形式的示例图。如图3所示，该示例图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。具体是：第一脉冲可以将相变存储单元的相变材料由非晶态调整至晶态，调整之后相变存储单元的阻值状态为低阻态；第二脉冲可以将相变存储单元的相变材料由晶态调整至非晶态，调整之后相变存储单元的阻值状态为高阻态。假设低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)、高阻态对应的相变存储单元的的阻值范围为(1兆欧～10兆欧)；第一脉冲可以为正向置位(set)脉冲，其幅值为1.3伏，脉宽为300纳秒，在施加第一脉冲之后，检测到相变存储单元的电阻值为5千欧，确定相变存储单元当前处于低阻态；第二脉冲为负向复位(reset)脉冲，其幅值为3伏，脉宽为30纳秒，在施加第一脉冲之后，检测到相变存储单元的电阻值为8兆欧，确定相变存储单元当前处于高阻态。
在第a2种可能的设计中，第一脉冲可以用于将相变存储单元的阻值状态调整至高阻态， 第二脉冲可以用于将相变存储单元的阻值状态由高阻态调整为低阻态。在这一情况下，第一状态为高阻态，第二状态为低阻态。该可能的设计可以参考第a1种可能的设计“第一状态为低阻态，第二状态为高阻态”的具体描述，具体是第a2种可能的设计中的“第一脉冲”相当于第a1种可能的设计中的“第二脉冲”，第a2种可能的设计中的“第二脉冲”相当于第a1种可能的设计中的“第一脉冲”；在此不再赘述。
针对第a1种可能的设计和第a2种可能的设计，举例来说，对相变存储单元执行擦除操作具体可以通过施加第一脉冲实现擦除操作，此时相变存储单元保持在低阻态；对相变存储单元执行写入操作，若规定二进制数“0”对应低阻态，二进制数“1”对应高阻态，若需要写入“1”，则可以通过施加第二脉冲实现，使相变存储单元保持在高阻态；若需要写入“0”，则可以通过施加第一脉冲实现，使相变存储单元保持在低阻态。
针对第a1种可能的设计和第a2种可能的设计，本申请实施例对高阻态、低阻态、至少一个中间阻态分别对应的相变存储单元的阻值范围不做限定。可选的，在对相变存储单元执行施加脉冲的操作以改变阻值状态之前，可以检测相变存储单元当前的阻值，若当前的阻值落在所需的阻值状态对应的阻值范围内，则无需对相变存储单元施加脉冲。
在相变存储单元可以实现多值存储的场景中，相变存储单元的阻值状态包括高阻态、低阻态和至少一个中间阻态，相变存储单元的阻值状态还包括至少一个中间阻态；中间阻态对应的相变单元的阻值小于高阻态对应的相变单元的阻值，且中间阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。本申请实施例可以通过第一脉冲和第二脉冲调整相变存储单元的阻值状态，来实现多值存储。
在第b1种可能的设计中，第一脉冲可以用于将相变存储单元的阻值状态调整至低阻态，第二脉冲可以用于将相变存储单元的阻值状态由低阻态调整为第一目标阻态。在这一情况下，第一状态为低阻态，第二状态为第一目标阻态，第一目标阻态为低阻态和至少一个中间阻态中的任意一个。第一脉冲的幅值小于第二脉冲的幅值，第一脉冲的脉宽大于第二脉冲的脉宽。在该可能的设计中，第一脉冲的幅值范围为(0.8伏～1.5伏)；第一脉冲的脉宽范围为(200纳秒～400纳秒)；第二脉冲的幅值范围为(1.6伏～4伏)；第二脉冲的脉宽范围为(20纳秒～100纳秒)。例如，第一脉冲的幅值为1.3伏、脉宽为300纳秒；第二脉冲的幅值可以在1.5伏至3.5伏范围内递增、脉宽为30纳秒，第二脉冲的不同幅值对应第一目标阻态中的不同阻态，比如第一目标阻态包括第一中间阻态、第二中间阻态和高阻态，第二脉冲的幅值为1.5伏对应第一中间阻态，第二脉冲的幅值为2.5V对应第二中间阻态，第二脉冲的幅值为3.5伏对应高阻态。低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)、第一中间阻态对应的相变存储单元的阻值范围为(50千欧～200千欧)、第二中间阻态对应的相变存储单元的阻值范围为(500千欧～700千欧)、高阻态对应的相变存储单元的的阻值范围为(1兆欧～10兆欧)，本申请实施例对各阻值状态对应的阻值范围不做限定。
请参见图4，为本申请实施例提供了又一种脉冲形式的示例图。如图4所示，该示例图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。该图4中包括第一脉冲400、第二脉冲401、第二脉冲402、第二脉冲403。
其中，图4的脉冲形式适用的相变存储单元包括低阻态、第一中间阻态、第二中间阻 态和高阻态，在低阻态、第一中间阻态、第二中间阻态和高阻态下相变存储单元对应的阻值是由低到高的。第一脉冲400可以用于将相变存储单元的阻值状态调整至低阻态，第二脉冲401可以用于将相变存储单元的阻值状态调整至第一中间阻态，第二脉冲402可以用于将相变存储单元的阻值状态调整至第二中间阻态，第二脉冲403可以用于将相变存储单元的阻值状态调整至高阻态。
可选的，第二脉冲401、第二脉冲402、第二脉冲403的脉冲幅值依次递增，第二脉冲401、第二脉冲402、第二脉冲403的脉宽可以相同。例如，第一脉冲400为set脉冲，其幅值为1.3伏，脉宽为300纳秒；第二脉冲401、第二脉冲402、第二脉冲403的脉宽为30纳秒，第二脉冲401、第二脉冲402、第二脉冲403的脉冲幅值在1.5V至3.5V递增。例如，假设低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)、第一中间阻态对应的相变存储单元的阻值范围为(50千欧～200千欧)、第二中间阻态对应的相变存储单元的阻值范围为(500千欧～700千欧)、高阻态对应的相变存储单元的的阻值范围为(1兆欧～10兆欧)；第一脉冲400可以为正向置位(set)脉冲，其幅值为1.3伏、脉宽为300纳秒，在施加第一脉冲之后，检测到相变存储单元的电阻值为5千欧，确定相变存储单元当前处于低阻态；第二脉冲401为负向脉冲，其幅值为1.5伏、脉宽为30纳秒，在施加第二脉冲401之后，检测到相变存储单元的电阻值为150千欧，确定相变存储单元当前处于第一中间阻态；第二脉冲402为负向脉冲，其幅值为2.5伏、脉宽为30纳秒，在施加第二脉冲402之后，检测到相变存储单元的电阻值为600千欧，确定相变存储单元当前处于第二中间阻态；第二脉冲403为负向脉冲，其幅值为3.5伏、脉宽为30纳秒，在施加第二脉冲403之后，检测到相变存储单元的电阻值为8兆欧，确定相变存储单元当前处于高阻态。
图4所示的这一相变存储单元可以实现四值存储，如00、01、10、11；一个值与一个阻值状态唯一对应。例如将图4所示中高阻态与00对应、第一中间阻态与01对应、第二中间阻态与10对应、低阻态与11对应。在执行写入操作时，可以按照图4所示的各阻态对应的脉冲幅值和脉宽来施加脉冲信号可以改变相变存储单元的阻值，进而改变相变存储单元的阻值状态，比如若需要写入数据11，则施加幅值为1.3伏、脉宽为300纳秒的脉冲改变相变存储单元的阻值。在执行读操作时，可以检测相变存储单元当前的电阻值，如果相变存储单元的电阻值在低阻态对应的取值范围，则确定该相变存储单元写入的数据为11。
在第b2种可能的设计中，第一脉冲可以用于将相变存储单元的阻值状态调整至高阻态，第二脉冲可以用于将相变存储单元的阻值状态由高阻态调整为第二目标阻态，第二目标阻态为低阻态和至少一个中间阻态中的任意一个。在这一情况下，第一状态为高阻态，第二状态为低阻态和至少一个中间阻态中的任意一个。第一脉冲的幅值大于第二脉冲的幅值，第一脉冲的脉宽小于第二脉冲的脉宽。
在该可能的设计中，第一脉冲的幅值范围为(1.6伏～4伏)；第一脉冲的脉宽范围为(20纳秒～100纳秒)；第二脉冲的幅值范围为(0.8伏～1.5伏)；第二脉冲的脉宽范围为(200纳秒～400纳秒)。例如，第一脉冲的幅值为3伏、脉宽为30纳秒；第二脉冲的幅值为1.3伏、脉宽在200纳秒至400纳秒范围内递增，第二脉冲的不同脉宽对应第二目标阻态中的不同阻态，比如第一目标阻态包括第一中间阻态、第二中间阻态和高阻态，第二脉冲的脉宽为200纳秒对应第一中间阻态，第二脉冲的脉宽为300纳秒对应第二中间阻态，第二脉冲的 脉宽为400纳秒对应高阻态。
请参见图5，为本申请实施例提供了又一种脉冲形式的示例图。如图5所示，该示例图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。该图5中包括第一脉冲500、第二脉冲501、第二脉冲502、第二脉冲503。
其中，图5的脉冲形式适用的相变存储单元包括低阻态、第一中间阻态、第二中间阻态和高阻态，在低阻态、第一中间阻态、第二中间阻态和高阻态下相变存储单元对应的阻值是由低到高的。第一脉冲500可以用于将相变存储单元的阻值状态调整至高阻态，第二脉冲501可以用于将相变存储单元的阻值状态调整至第二中间阻态，第二脉冲502可以用于将相变存储单元的阻值状态调整至第一中间阻态，第二脉冲503可以用于将相变存储单元的阻值状态调整至低阻态。
可选的，第二脉冲501、第二脉冲502、第二脉冲503的脉宽依次递增，第二脉冲501、第二脉冲502、第二脉冲503的脉冲幅值可以相同。例如，第一脉冲500为set脉冲，其幅值为3伏，脉宽为30纳秒；第二脉冲501、第二脉冲502、第二脉冲503的幅值为1.3伏，第二脉冲501、第二脉冲502、第二脉冲503的脉宽在200纳秒至400纳秒范围内递增。例如，假设低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)、第一中间阻态对应的相变存储单元的阻值范围为(50千欧～200千欧)、第二中间阻态对应的相变存储单元的阻值范围为(500千欧～700千欧)、高阻态对应的相变存储单元的的阻值范围为(1兆欧～10兆欧)；第一脉冲500可以为正向脉冲，其幅值为3伏、脉宽为30纳秒，在施加第一脉冲500之后，检测到相变存储单元的电阻值为8兆欧，确定相变存储单元当前处于高阻态；第二脉冲501为负向脉冲，其幅值为1.3伏、脉宽为100纳秒，在施加第二脉冲501之后，检测到相变存储单元的电阻值为550千欧，确定相变存储单元当前处于第二中间阻态；第二脉冲502为负向脉冲，其幅值为1.3伏、脉宽为200纳秒，在施加第二脉冲502之后，检测到相变存储单元的电阻值为130千欧，确定相变存储单元当前处于第一中间阻态；第二脉冲503为负向脉冲，其幅值为1.3伏、脉宽为300纳秒，在施加第二脉冲503之后，检测到相变存储单元的电阻值为5千欧，确定相变存储单元当前处于低阻态。
图5所示的相变存储单元可以实现四值存储，如00、01、10、11；一个值与一个阻值状态唯一对应。通过设定所施加的脉冲的幅值和脉宽，来改变相变存储单元的阻值，进而改变相变存储单元的阻值状态。例如将图5所示中高阻态与11对应、第一中间阻态与01对应、第二中间阻态与10对应、低阻态与00对应。在执行写入操作时，可以按照图5所示的各阻态对应的脉冲幅值和脉宽来施加脉冲信号可以改变相变存储单元的阻值，进而改变相变存储单元的阻值状态，比如若需要写入数据11，则施加幅值为3伏、脉宽为30纳秒的脉冲改变相变存储单元的阻值。在执行读操作时，可以检测相变存储单元当前的电阻值，如果相变存储单元的电阻值在高阻态对应的取值范围，则确定该相变存储单元写入的数据为11。
针对第b1种可能的设计和第b2种可能的设计，对相变存储单元执行擦除操作具体可以通过施加脉冲使得相变存储单元的阻值状态处于预设的初始状态，这里预设初始状态可以为二值存储场景下的高阻态或者低阻态，也可以为多值存储下的多个阻态中的任意一个，本申请实施例对预设初始状态的设定不做限定。
针对第b1种可能的设计和第b2种可能的设计，本申请实施例对高阻态、低阻态、至少一个中间阻态分别对应的相变存储单元的阻值范围不做限定。可选的，在对相变存储单元执行擦除操作或写入操作以改变阻值状态之前，可以检测相变存储单元当前的阻值，若当前的阻值落在所需的阻值状态对应的阻值范围内，则无需对相变存储单元施加脉冲。
针对第b1种可能的设计和第b2种可能的设计，可选的，在对相变存储单元执行写入操作以改变阻值状态之前，可以对相变存储单元执行初始化操作，如图4所示的第一脉冲400和图5所示的第一脉冲500，例如初始化操作可以为调整相变存储单元的阻值状态为低阻态或者高阻态，接着再通过施加脉冲来调整相变存储单元的阻值状态。
B、在又一种可选的脉冲形式中，第一脉冲为多个脉冲，第二脉冲为多个脉冲，这两个脉冲的极性相反，例如可以为第一脉冲为正向脉冲，第二脉冲为负向脉冲，或者可以为第一脉冲为负向脉冲，第二脉冲为正向脉冲。第一脉冲用于将相变存储单元的阻值状态调整至第一状态，第二脉冲用于将相变存储单元的阻值状态由第一状态调整为第二状态。由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向迁移，即使擦写次数不断增加也会降低各元素在上电极或者下电极的累积程度，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
在相变存储单元可以实现二值存储的场景中，相变存储单元的阻值状态包括高阻态和低阻态，高阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。本申请实施例可以通过第一脉冲和第二脉冲调整相变存储单元的阻值状态，来实现二值存储。具体是：第一脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由高阻态调整至低阻态，第二脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由低阻态调整为高阻态；或者，第一脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由低阻态调整为高阻态，第二脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由高阻态调整至低阻态。这里多个脉冲的幅值可以相同也可以不同，多个脉冲的脉宽可以相同也可以不同，本申请实施例对此不做限定。
在相变存储单元可以实现多值存储的场景中，相变存储单元的阻值状态包括高阻态高阻态、低阻态和至少一个中间阻态，相变存储单元的阻值状态还包括至少一个中间阻态；中间阻态对应的相变单元的阻值小于高阻态对应的相变单元的阻值，且中间阻态对应的相变单元的阻值大于低阻态对应的相变单元的阻值。本申请实施例可以通过第一脉冲和第二脉冲调整相变存储单元的阻值状态，来实现多值存储。具体是：第一脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态调整至低阻态，第二脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由低阻态调整为第一目标阻态；第一目标阻态为低阻态和至少一个中间阻态中的任意一个；或者，第一脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态调整至高阻态，第二脉冲包含的多个脉冲可以用于将相变存储单元的阻值状态由高阻态调整至第二目标阻态，第二目标阻态为低阻态和至少一个中间阻态中的任意一个。这里多个脉冲的幅值可以相同也可以不同，多个脉冲的脉宽可以相同也可以不同，本申请实施例对此不做限定。
请参见图6，为本申请实施例提供了又一种脉冲形式的示例图。如图6所示，该示例 图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。其中，第一脉冲包括脉冲601、脉冲602和脉冲603；第二脉冲包括脉冲604、脉冲605和脉冲606。
其中，在施加脉冲601、脉冲602和脉冲603之后，可以将相变存储单元的阻值状态调整为第一状态，在施加脉冲604、脉冲605和脉冲606之后，可以将相变存储单元的阻值状态调整为第二状态。
举例来说，与图3相比，同样是将相变存储单元的阻值状态调整至第一状态，图3的举例中采用幅值为1.3伏，脉宽为300纳秒的一个脉冲来实现，图6可以采用幅值均为1.3伏，脉宽均为100纳秒的三个脉冲来实现。同样是将相变存储单元的阻值状态调整至第二状态，图3的举例中采用幅值为3伏，脉宽为30纳秒的一个脉冲来实现，图6可以采用脉宽均为30纳秒，幅值分别为2伏的三个脉冲来实现。
需要说明的是，在相变存储单元可实现二值存储或者多值存储的场景中，A方式是仅通过一个脉冲实现相变存储单元的阻值状态的一次调整，B方式是通过多个脉冲实现相变存储单元的阻值状态的一次调整，这样A方式中介绍的通过一个脉冲改变相变存储单元的阻值状态情况，均可以以通过多个脉冲来改变相变存储单元的阻值状态。例如，A方式中幅值为1.3伏、脉宽为300纳秒的第一脉冲400可以通过B方式中3个幅值为1.3伏、脉宽为100的纳秒的脉冲来替代，且多个脉冲依次施加至第一电极；又如，A方式中幅值为3伏，脉宽为30纳秒的第一脉冲500可以通过B方式中幅值为2伏且脉宽为30纳秒的3个脉冲来代替，且多个脉冲依次施加至第一电极。在本申请实施例中在通过多个脉冲实现一次阻值状态的调整的场景中，对多个脉冲的幅值和脉宽的设定不做限定。在两种场景下，B方式执行擦写操作的具体过程可以参考A方式中的介绍，两者的区别在于所施加的脉冲的数量、脉冲的幅值、脉宽不同，在此不再赘述。
C、在又一种可选的脉冲形式中，第一脉冲为多个脉冲，第二脉冲为多个脉冲，这两个脉冲的极性相反，例如可以为第一脉冲为正向脉冲，第二脉冲为负向脉冲，或者可以为第一脉冲为负向脉冲，第二脉冲为正向脉冲。本申请为第一脉冲包含的多个脉冲的数量、第二脉冲包含的多个脉冲的数量不做限定。其中，多个脉冲的幅值可以相同也可以不同，多个脉冲的脉宽可以相同也可以不同，本申请实施例对此不做限定。由于第一脉冲和第二脉冲的极性相反，使得相变层中的各元素不会朝着一个方向迁移，即使擦写次数不断增加也会降低各元素在上电极或者下电极的累积程度，缺陷态在相变层上电极或下电极累积程度较低，进而降低了相变存储单元的阻值漂移程度，提高了数据保持能力。
在C方式中，以第一脉冲为例，第一脉冲包含的多个脉冲中的一个脉冲或者部分脉冲可以实现调整相变存储单元的阻值状态；第二脉冲包含的多个脉冲中的一个脉冲或者部分脉冲可以实现调整相变存储单元的阻值状态。同理，第二脉冲可以参考第一脉冲的介绍。在相变存储单元可实现二值存储或者多值存储的场景中，C方式执行擦写操作的具体过程可以参考A方式中的介绍，在此不再赘述。
接下来对C方式中第一脉冲和第二脉冲的脉冲形式进行举例说明，具体参见图7a至图7c的介绍。
请参见图7a，为本申请实施例提供了又一种脉冲形式的示例图。如图7a所示，该示例 图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。其中，第一脉冲包括脉冲7a01和脉冲7a02；第二脉冲包括脉冲7a03和脉冲7a04。图7a中的每一个脉冲可以实现调整相变存储单元的阻值状态，例如，脉冲7a01将相变存储单元的阻值状态调整为第一状态，脉冲7a02将相变存储单元的阻值状态由第一状态调整为第二状态。脉冲7a03将相变存储单元的阻值状态调整为第一状态，脉冲7a04将相变存储单元的阻值状态由第一状态调整为第二状态。
请参见图7b，为本申请实施例提供了又一种脉冲形式的示例图。如图7b所示，该示例图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。其中，第一脉冲包括脉冲7b01、脉冲7b02、脉冲7b03、脉冲7b04、脉冲7b05和脉冲7b06；第二脉冲包括脉冲7b07、脉冲7b08、脉冲7b09、脉冲7b10、脉冲7b11和脉冲7b12。图7b中的两个或两个以上的脉冲实现调整相变存储单元的阻值状态，例如，脉冲7b01、脉冲7b02、脉冲7b03将相变存储单元的阻值状态调整为第一状态，脉冲7b04、脉冲7b05和脉冲7b06将相变存储单元的阻值状态由第一状态调整为第二状态。同理，7b07、脉冲7b08、脉冲7b09将相变存储单元的阻值状态调整为第一状态，脉冲7b10、脉冲7b11和脉冲7b12将相变存储单元的阻值状态由第一状态调整为第二状态。
请参见图7c，为本申请实施例提供了又一种脉冲形式的示例图。如图7c所示，该示例图是以第一脉冲为正向脉冲、第二脉冲为负向脉冲为例的。其中，第一脉冲包括脉冲7c01、脉冲7c02、脉冲7c03和脉冲7c04；第二脉冲包括脉冲7c05和、脉冲7c06、脉冲7c07和脉冲7c08。图7c中的一个可以实现调整相变存储单元的阻值状态，多个脉冲也可以实现调整相变存储单元的阻值状态，例如，脉冲7c01、脉冲7c02、脉冲7c03将相变存储单元的阻值状态调整为第一状态，脉冲7c04将相变存储单元的阻值状态由第一状态调整为第二状态。同理，7c05、脉冲7c06、脉冲7c07将相变存储单元的阻值状态调整为第一状态，脉冲7c08将相变存储单元的阻值状态由第一状态调整为第二状态。
以上图7a至图7b仅为C方式中包含的脉冲形式的举例说明，在第一脉冲和第二脉冲的极性相反的前提下，本申请实施例对第一脉冲或第二脉冲包括的多个脉冲的形式不做限定。
需要说明的是，在相变存储单元可实现二值存储或者多值存储的场景中，C方式中既可以通过一个脉冲实现相变存储单元的阻值状态的一次调整，又可以通过多个脉冲实现相变存储单元的阻值状态的一次调整。而上述A方式是仅通过一个脉冲实现相变存储单元的阻值状态的一次调整，上述B方式是通过多个脉冲实现相变存储单元的阻值状态的一次调整，这样C方式中通过一个脉冲实现一次阻值状态的调整的情况可以参考A方式中的介绍，C方式中通过多个脉冲实现一次阻值状态的调整的情况可以参考B方式中的介绍。
需要说明的是，在上述B方式或C方式中，在对相变存储单元施加M个脉冲以将相变存储单元的阻值状态调整为第一状态的情况下，若施加M个脉冲后读取的相变存储单元对应的阻值在第一状态对应的阻值范围内，则确定将相变存储单元的阻值状态调整为第一状态，M为正整数。可选的，在施加多个脉冲的过程中，可以在施加第i个脉冲后读取的相变存储单元对应的阻值，若所读取的阻值不在第一状态对应的阻值范围内，则继续施加第(i+1)个脉冲，若所读取的阻值在第一状态对应的阻值范围内，则停止施加用于将相变 存储单元的阻值状态调整为第一状态的脉冲。
同理，在对相变存储单元施加N个脉冲以将相变存储单元的阻值状态调整为第二状态的情况下，若施加N个脉冲后读取的相变存储单元对应的阻值在第二状态对应的阻值范围内，则确定将相变存储单元的阻值状态调整为第二状态，N为正整数。可选的，在施加多个脉冲的过程中，可以在施加第j个脉冲后读取的相变存储单元对应的阻值，若所读取的阻值不在第二状态对应的阻值范围内，则继续施加第(j+1)个脉冲，若所读取的阻值在第二状态对应的阻值范围内，则停止施加用于将相变存储单元的阻值状态调整为第二状态的脉冲。
例如，在通过多个幅值为1.3伏、脉宽为100的纳秒的脉冲来调整相变存储单元的阻值状态至低阻态，假设低阻态对应的相变存储单元的阻值范围为：(0欧～10千欧)。具体可以在施加第1个幅值为1.3伏、脉宽为100纳秒的脉冲后，读取相变存储单元的阻值为550千欧，由于阻值大于低阻态对应的阻值范围，则继续施加第2个幅值为1.3伏、脉宽为100的纳秒的脉冲，读取相变存储单元的阻值80千欧，由于阻值大于低阻态对应的阻值范围，则继续施加第3个幅值为1.3伏、脉宽为100的纳秒的脉冲，读取相变存储单元的阻值7千欧，由于当前相变存储单元的阻值在低阻态对应的阻值范围内，则停止施加用于将相变存储单元的阻值状态调整为低阻态的脉冲。
在上述B方式或C方式中，本申请实施例对高阻态、低阻态、至少一个中间阻态分别对应的相变存储单元的阻值范围不做限定，另外对相变存储单元调整阻值状态所采用的脉冲的幅值和脉宽可以参考A方式的具体描述，这里不再赘述。
上述A方式、B方式、C方式中举例介绍的第一脉冲和第二脉冲所包含的脉冲数量是相同的，但本申请实施例第一脉冲和第二脉冲所包含的脉冲数量可以是不同的。
请参见图8，图8是本申请实施例提供的一种操作装置的结构示意图。该操作装置用于实现图2a至图7c的实施例。如图8所示，所述操作装置800用于对相变存储单元进行操作，该相变存储单元包括第一电极、相变层和第二电极，所述第二电极接地，该操作装置800包括脉冲施加模块801，可选的，还包括确定模块802。
脉冲施加模块801，用于将第一脉冲和第二脉冲依次施加至所述第一电极，所述第一脉冲和所述第二脉冲分别用于调整所述相变存储单元的阻值状态；其中，所述第一脉冲的极性与所述第二脉冲的极性相反。
一种可能的实现方式中，所述第一脉冲为正向脉冲，所述第二脉冲为负向脉冲；
或者，所述第一脉冲为负向脉冲，所述第二脉冲为正向脉冲。
一种可能的实现方式中，在所述第一脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同；
在所述第二脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同。
一种可能的实现方式中，所述相变存储单元的阻值状态包括高阻态和低阻态；所述高 阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
一种可能的实现方式中，所述相变存储单元的阻值状态还包括至少一个中间阻态；所述中间阻态对应的所述相变单元的阻值小于所述高阻态对应的所述相变单元的阻值，且所述中间阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
一种可能的实现方式中，所述第一脉冲用于将所述相变存储单元的阻值状态调整为第一状态；所述第二脉冲用于将所述相变存储单元的阻值状态由所述第一状态调整为第二状态。
一种可能的实现方式中，所述第一脉冲为一个脉冲，所述第二脉冲为一个脉冲；
在所述第一状态为所述高阻态且所述第二状态为第一目标阻态的情况下，所述第一脉冲的幅值大于所述第二脉冲的幅值，所述第一脉冲的脉宽小于所述第二脉冲的脉宽；
在所述第一状态为所述低阻态且所述第二状态为第二目标阻态的情况下，所述第一脉冲的幅值小于所述第二脉冲的幅值，所述第一脉冲的脉宽大于所述第二脉冲的脉宽；
其中，所述第一目标阻态为所述低阻态和所述至少一个中间阻态中的任意一个；所述第二目标阻态为所述高阻态和所述至少一个中间阻态中的任意一个。
一种可能的实现方式中，所述第一脉冲为M个脉冲，所述第二脉冲为N个脉冲；所述装置还包括：
确定模块802，用于若施加所述M个脉冲后读取的所述相变存储单元对应的阻值在所述第一状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第一状态，M为正整数；
所述确定模块802，还用于若施加所述N个脉冲后读取的所述相变存储单元对应的阻值在所述第二状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第二状态，N为正整数。
一种可能的实现方式中，所述第一电极为上电极，所述第二电极为下电极；或者，所述第一电极为下电极，所述第二电极为上电极。
此时，该操作装置800可以实现图2a-图7c所介绍的对相变存储单元的操作方法，各个模块执行详细过程可参见图2a-图7c所示实施例的详细介绍，此处不再赘述。
上述图8所示的操作装置800可以以图9所示的操作装置900实现。如图9所示，为本申请实施例提供了另一种操作装置的结构示意图，图9所示的操作装置900包括：控制器901和收发器902，所述收发器902用于支持操作装置900与脉冲信号源和/或相变存储单元之间传输信号，例如实现图8所示实施例中脉冲施加模块801的功能，所述控制器901可以用于实现图8所示实施例中确定模块802的功能。控制器901和收发器902通信连接，例如通过总线相连。所述操作装置900还可以包括存储器903。存储器903用于存储供操作装置900执行的程序代码和数据，控制器901用于执行存储器903中存储的应用程序代码，以实现图8所示实施例提供的操作装置的各个模块。
需要说明的是，实际应用中操作装置可以包括一个或者多个控制器，该操作装置900的结构并不构成对本申请实施例的限定。
控制器901可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)，硬件芯片或者其任意组合。上述硬件芯片可以是专用集成电路 (application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器903可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)；存储器903也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器903还可以包括上述种类的存储器的组合。
可选的，所述控制器901执行存储器903中的程序代码和数据具体执行：将第一脉冲和第二脉冲依次施加至所述第一电极，所述第一脉冲和所述第二脉冲分别用于调整所述相变存储单元的阻值状态；其中，所述第一脉冲的极性与所述第二脉冲的极性相反。第一脉冲和第二脉冲为通过收发器902接收到的。
在一种可能的实现方案中，所述第一脉冲为正向脉冲，所述第二脉冲为负向脉冲；
或者，所述第一脉冲为负向脉冲，所述第二脉冲为正向脉冲。
在一种可能的实现方案中，在所述第一脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同；
在所述第二脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同。
在一种可能的实现方案中，所述相变存储单元的阻值状态包括高阻态和低阻态；所述高阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
在一种可能的实现方案中，所述相变存储单元的阻值状态还包括至少一个中间阻态；所述中间阻态对应的所述相变单元的阻值小于所述高阻态对应的所述相变单元的阻值，且所述中间阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
在一种可能的实现方案中，所述第一脉冲用于将所述相变存储单元的阻值状态调整为第一状态；所述第二脉冲用于将所述相变存储单元的阻值状态由所述第一状态调整为第二状态。
在一种可能的实现方案中，所述第一脉冲为一个脉冲，所述第二脉冲为一个脉冲；
在所述第一状态为所述低阻态且所述第二状态为第一目标阻态的情况下，所述第一脉冲的幅值小于所述第二脉冲的幅值，所述第一脉冲的脉宽大于所述第二脉冲的脉宽；
在所述第一状态为所述高阻态且所述第二状态为第二目标阻态的情况下，所述第一脉冲的幅值大于所述第二脉冲的幅值，所述第一脉冲的脉宽小于所述第二脉冲的脉宽；
其中，所述第一目标阻态为所述高阻态和所述至少一个中间阻态中的任意一个；所述第二目标阻态为所述低阻态和所述至少一个中间阻态中的任意一个。
在一种可能的实现方案中，所述第一脉冲为M个脉冲，所述第二脉冲为N个脉冲；所述方法还包括：
若施加所述M个脉冲后读取的所述相变存储单元对应的阻值在所述第一状态对应的阻值范围内，则所述控制器901确定将所述相变存储单元的阻值状态调整为第一状态，M为正整数；
若施加所述N个脉冲后读取的所述相变存储单元对应的阻值在所述第二状态对应的阻值范围内，则所述控制器901确定将所述相变存储单元的阻值状态调整为第二状态，N为正整数。
在一种可能的实现方案中，所述第一电极为上电极，所述第二电极为下电极；
或者，所述第一电极为下电极，所述第二电极为上电极。
上述控制器901执行的详细过程可参见图2a-图7c所示实施例的详细介绍，此处不再赘述。
在本申请实施例中还提供了一种芯片，包括处理器和存储器，该存储器用于存储计算机程序，该处理器用于从存储器中调用并运行该计算机程序，该计算机程序用于实现上述对相变存储单元的操作方法。
在本申请实施例中还提供了一种计算机存储介质，可以用于存储所述操作装置所用的计算机软件指令，其包含用于执行上述实施例中为操作装置所设计的程序。该存储介质包括但不限于快闪存储器、硬盘、固态硬盘。
在本申请实施例中还提供了一种计算机程序产品，该计算机产品被计算设备运行时，可以执行上述对相变存储单元的操作方法。
请参见图10，为本申请实施例提供了一种终端设备的结构示意图。图10所示的终端设备1000包括处理器1001、收发器1004、存储器1003、控制器1005、相变存储单元阵列1006和脉冲信号源1007。
所述控制器1005可以用于实现图8所示实施例中确定模块802的功能，所述控制器1005通过脉冲信号源1007对相变存储单元阵列1006施加脉冲，以实现图8所示实施例中脉冲施加模块801的功能。
处理器1001、控制器1005、相变存储单元阵列1006、脉冲信号源1007和收发器1002通信连接，例如通过总线相连。所述终端设备1000还可以包括存储器1003。存储器1003用于存储供终端设备1000执行的程序代码和数据，控制器1005用于执行存储器1003中存储的应用程序代码，以实现图8所示实施例提供的操作装置的各个模块。
处理器1001可以是CPU，NP，硬件芯片或者其任意组合。上述硬件芯片可以是ASIC，PLD或其组合。上述PLD可以是CPLD，FPGA，GAL或其任意组合。
存储器1003可以包括易失性存储器，例如RAM；存储器1003也可以包括非易失性存储器，例如ROM，快闪存储器，硬盘或固态硬盘；存储器1003还可以包括上述种类的存储器的组合。
控制器1005，用于控制相变存储单元阵列的读取操作、擦除操作、写入操作等。该控制器也可以为处理器，与该终端设备1000中的处理器1001组合来之后实现处理器1001和控制器1005的功能。
相变存储单元阵列1006包括多个相变存储单元，每个相变存储单元可以实现二值存储 或者多值存储，也就是说相变存储单元包括两个或者两个以上的阻值状态。
需要说明的是，实际应用中终端设备可以包括一个或者多个处理器，该终端设备1000的结构并不构成对本申请实施例的限定。
本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选的还包括没有列出的步骤或单元，或可选的还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
本领域普通技术人员可以理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。

Claims (20)

  1. 一种对相变存储单元的操作方法，相变存储单元包括第一电极、相变层和第二电极，所述第二电极接地，其特征在于，所述方法包括：
    将第一脉冲和第二脉冲依次施加至所述第一电极，所述第一脉冲和所述第二脉冲分别用于调整所述相变存储单元的阻值状态；
    其中，所述第一脉冲的极性与所述第二脉冲的极性相反。
  2. 根据权利要求1所述的方法，其特征在于，
    所述第一脉冲为正向脉冲，所述第二脉冲为负向脉冲；
    或者，所述第一脉冲为负向脉冲，所述第二脉冲为正向脉冲。
  3. 根据权利要求1或2所述的方法，其特征在于，
    在所述第一脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同；
    在所述第二脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，
    所述相变存储单元的阻值状态包括高阻态和低阻态；所述高阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
  5. 根据权利要求4所述的方法，其特征在于，
    所述相变存储单元的阻值状态还包括至少一个中间阻态；所述中间阻态对应的所述相变单元的阻值小于所述高阻态对应的所述相变单元的阻值，且所述中间阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
  6. 根据权利要求5所述的方法，其特征在于，所述第一脉冲用于将所述相变存储单元的阻值状态调整为第一状态；所述第二脉冲用于将所述相变存储单元的阻值状态由所述第一状态调整为第二状态。
  7. 根据权利要求6所述的方法，其特征在于，所述第一脉冲为一个脉冲，所述第二脉冲为一个脉冲；
    在所述第一状态为所述低阻态且所述第二状态为第一目标阻态的情况下，所述第一脉冲的幅值小于所述第二脉冲的幅值，所述第一脉冲的脉宽大于所述第二脉冲的脉宽；
    在所述第一状态为所述高阻态且所述第二状态为第二目标阻态的情况下，所述第一脉 冲的幅值大于所述第二脉冲的幅值，所述第一脉冲的脉宽小于所述第二脉冲的脉宽；
    其中，所述第一目标阻态为所述高阻态和所述至少一个中间阻态中的任意一个；所述第二目标阻态为所述低阻态和所述至少一个中间阻态中的任意一个。
  8. 根据权利要求5或6所述的方法，其特征在于，所述第一脉冲为M个脉冲，所述第二脉冲为N个脉冲；所述方法还包括：
    若施加所述M个脉冲后读取的所述相变存储单元对应的阻值在所述第一状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第一状态，M为正整数；
    若施加所述N个脉冲后读取的所述相变存储单元对应的阻值在所述第二状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第二状态，N为正整数。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，
    所述第一电极为上电极，所述第二电极为下电极；
    或者，所述第一电极为下电极，所述第二电极为上电极。
  10. 一种操作装置，所述操作装置用于对相变存储单元进行操作，所述相变存储单元包括第一电极、相变层和第二电极，所述第二电极接地，其特征在于，包括：
    脉冲施加模块，用于将第一脉冲和第二脉冲依次施加至所述第一电极，所述第一脉冲和所述第二脉冲分别用于调整所述相变存储单元的阻值状态；
    其中，所述第一脉冲的极性与所述第二脉冲的极性相反。
  11. 根据权利要求10所述的装置，其特征在于，
    所述第一脉冲为正向脉冲，所述第二脉冲为负向脉冲；
    或者，所述第一脉冲为负向脉冲，所述第二脉冲为正向脉冲。
  12. 根据权利要求10或11所述的装置，其特征在于，
    在所述第一脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同；
    在所述第二脉冲为多个脉冲的情况下，所述多个脉冲的幅值不等且脉宽不等，或者，所述多个脉冲的幅值相同且脉宽不等，或者，所述多个脉冲的幅值不等且脉宽相同，或者，所述多个脉冲的幅值相同且脉宽相同。
  13. 根据权利要求10-12任一项所述的装置，其特征在于，
    所述相变存储单元的阻值状态包括高阻态和低阻态；所述高阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
  14. 根据权利要求13所述的装置，其特征在于，
    所述相变存储单元的阻值状态还包括至少一个中间阻态；所述中间阻态对应的所述相变单元的阻值小于所述高阻态对应的所述相变单元的阻值，且所述中间阻态对应的所述相变单元的阻值大于所述低阻态对应的所述相变单元的阻值。
  15. 根据权利要求14所述的装置，其特征在于，所述第一脉冲用于将所述相变存储单元的阻值状态调整为第一状态；所述第二脉冲用于将所述相变存储单元的阻值状态由所述第一状态调整为第二状态。
  16. 根据权利要求15所述的装置，其特征在于，所述第一脉冲为一个脉冲，所述第二脉冲为一个脉冲；
    在所述第一状态为所述高阻态且所述第二状态为第一目标阻态的情况下，所述第一脉冲的幅值大于所述第二脉冲的幅值，所述第一脉冲的脉宽小于所述第二脉冲的脉宽；
    在所述第一状态为所述低阻态且所述第二状态为第二目标阻态的情况下，所述第一脉冲的幅值小于所述第二脉冲的幅值，所述第一脉冲的脉宽大于所述第二脉冲的脉宽；
    其中，所述第一目标阻态为所述低阻态和所述至少一个中间阻态中的任意一个；所述第二目标阻态为所述高阻态和所述至少一个中间阻态中的任意一个。
  17. 根据权利要求15所述的装置，其特征在于，所述第一脉冲为M个脉冲，所述第二脉冲为N个脉冲；所述装置还包括：
    确定模块，用于若施加所述M个脉冲后读取的所述相变存储单元对应的阻值在所述第一状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第一状态，M为正整数；
    所述确定模块，还用于若施加所述N个脉冲后读取的所述相变存储单元对应的阻值在所述第二状态对应的阻值范围内，则确定将所述相变存储单元的阻值状态调整为第二状态，N为正整数。
  18. 根据权利要求10-17任一项所述的装置，其特征在于，
    所述第一电极为上电极，所述第二电极为下电极；
    或者，所述第一电极为下电极，所述第二电极为上电极。
  19. 一种芯片，其特征在于，所述芯片包括控制器和存储器，所述存储器用于存储计算机程序，所述控制器用于从所述存储器中调用并运行所述计算机程序，所述计算机程序用于执行如权利要求1-9任一项所述的方法。
  20. 一种终端设备，其特征在于，所述终端设备包括处理器、存储器、至少一个相变存储单元，所述相变存储单元包括第一电极、相变层和第二电极，所述第二电极接地，所述存储器用于存储计算机程序，所述处理器用于从所述存储器中调用并运行所述计算机程序，所述处理器用于执行如权利要求1-9任一项所述的方法。
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CN102057438A (zh) * 2008-06-11 2011-05-11 Nxp股份有限公司 相变存储器装置和控制方法
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