WO2023019497A1

WO2023019497A1 - Memory device and controlling method thereof

Info

Publication number: WO2023019497A1
Application number: PCT/CN2021/113418
Authority: WO
Inventors: Zuqi DONG; Hanxiao DU; Jianping Li; Xiang FU; Jun Liu; Shao-Fu Sanford Chu; Chun Yuan Hou
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2023-02-23
Also published as: CN113853654A

Abstract

A memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells, a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal, and a data register configured to store readout data and the comparison output signal.

Description

MEMORY DEVICE AND CONTROLLING METHOD THEREOF

BACKGROUND

The present disclosure relates to memory devices and operation methods thereof.

The conventional read operation of a memory cell may be much more frequent and continuous than write operation or other operations, thereby becoming a critical factor of the lifespan of the memory cell. In particular, when a read signal is much higher than it may be required to read out the data, for instance, a higher read voltage is used to read a memory cell having a lower threshold voltage, it may wear out the memory cell much faster than in normal operations. On the other hand, if the read voltage is too low, it may not distinguish a “set” state from a “reset” state since the threshold voltages of the “set” state and the “reset” state are both higher than the read voltage. Finding a suitable read voltage may thus become challenging. Furthermore, since memory cells may have a wide distribution of threshold voltages in a memory array, it becomes more challenging to determine a suitable read voltage for all memory cells to distinguish “set” state and the “reset” state of the memory cell while keeping the read voltage as low as possible to increase the lifespan of the memory cell.

SUMMARY

In one aspect, a memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and configured to drive one or a plurality of incremental read voltages into one of the plurality of memory cells, a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal, and a data register configured to store readout data and the comparison output signal.

In another aspect, a system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells, a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal, and a data register configured to store readout data and the comparison output signal.

In still another aspect, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells being connected between word lines and bit lines. The method includes applying an incremental read voltage to one of the plurality of memory cell, determining whether the incremental read voltage is higher than a threshold voltage of the one of the plurality of memory cell, in response to the incremental read voltage is higher than the threshold voltage, a state of the memory cell is determined as a “set” state, and in response to the incremental read voltage is lower than the threshold voltage, repeating applying next incremental read voltage to the one of the plurality of memory cell until the incremental read voltage reaches to a maximum voltage, and then the state of the memory cell is determined as “reset” .

In yet another aspect, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells being connected between word lines and bit lines. The method includes in response to determining that a command corresponds to a read operation, setting a read voltage V _read as an initial read voltage V _{read_1}, applying the read voltage V _read to one of the plurality of memory cells, determining whether the read voltage V _read is higher than a threshold voltage V _th of the one of the plurality of memory cells, in response to the read voltage V _read is higher than the threshold voltage V _th, determining a state of the one of the plurality of memory cells is a “set” state, in response to the read voltage V _read is lower than the threshold voltage V _th, setting the read voltage V _read equals the initial read voltage V _{read_1} plus a step size voltage V _dac, determining whether the read voltage V _read is equal or higher than a maximum read voltage V _{read_max}, in response to the read voltage V _read is equal or higher than the maximum read voltage V _{read_max}, determining the state of the one of the plurality of memory cells is a “reset” state, and in response to the read voltage V _read is lower than the maximum read voltage V _{read_max}, repeating applying the read voltage V _read to the one of the plurality of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a block diagram of an exemplary system having a memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, according to some aspects of the present disclosure.

FIG. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 5 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 6 illustrates a voltage chart of a distribution of threshold voltages of a “set” and a “reset” state, and a selection of a series of read voltages based on the distribution, according to some aspects of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method for operating a memory device, according to some aspects of the present disclosure.

FIG. 8 illustrates a flowchart of an exemplary method for operating a memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material. PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. A “set” state is a low resistance state of the PCM cell that can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration. A “reset” state, on the contrary, is a high resistance state of the PCM cell that can be obtained by creating amorphous regions in the chalcogenide material. Amorphous can be created when the chalcogenide material is heated above its melting temperature and then quickly quenched to create a formation of amorphous. The “set” state can be referred to as an “on” state, while the “reset” state can be referred to as an “off” state.

As mentioned above, the conventional read operation of a memory cell may reduce the lifespan of the memory cell. In particular, when a higher read voltage is used to read a memory cell having a lower threshold voltage, it may wear out the memory cell much faster than in normal operations. This may be more significant when the threshold voltages of the memory cells are distributed in a lower voltage region. On the other hand, if a lower read voltage may not distinguish a “set” state from a “reset” state since the threshold voltages of the “set” state and the “reset” state are both higher than the read voltage. That is, it cannot be sure whether the measurement result is a set data or a reset data. Finding a suitable read voltage may thus become challenging. Furthermore, resistance distribution may vary widely subject to inherent cell variation or other factors. It is not easy to find a suitable read voltage for all the memory cells. Lastly, if the read voltage is too high, the read current may also be too high and increase the possibility of reading disturb, which may undesirably program the unselected memory cells. Therefore, it becomes more challenging to determine an ideal read voltage for all memory cells to distinguish the “set” state and the “reset” state of the memory cell while keeping the read voltage as low as possible to increase the lifespan of the memory cell.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which a stepwise read operation is introduced to identify whether the memory cell is in the “set” state or the “reset” state and read out the result after the read operation. Specifically, an initial read voltage is configured to be pre-determined according to threshold voltage distribution in the “set” state of the memory cells in the memory array. Next, apply the read voltage, e.g., the initial read voltage, to one of the memory cells, and determine whether the read voltage is higher than a threshold voltage of the one of the memory cells. If the read voltage is higher than the threshold voltage, the memory cell is in the “set” state, and therefore, the read data, e.g., a read current, can be readout. On the contrary, if the read voltage is lower than the threshold voltage, the memory cell can be either in the “set” state or in the “reset” state, a higher read voltage is required to be introduced to identify which state the memory cell is in. In response to that, a new and incremental read voltage, which is the initial read voltage plus a step size voltage, is determined. And if the read voltage is not higher than a maximum threshold read voltage, which can be determined according to threshold voltage distribution in “reset” state of the memory cells in the memory array, repeat and iterate applying the read voltage to the memory cell and the following processes thereof until the state of the memory cell is determined as either the “set” state or the “reset” state. Accordingly, a much lower initial read voltage can be used to read out the data if the initial read voltage is higher than the threshold voltage in the “set” state. And if the initial read voltage is lower than the threshold voltage in the “set” state, a few times of iteration may be able to identify the state of the memory cell and the corresponding readout data. As a result, the wear out of the memory cells can be minimized, and their lifetime is improved.

FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . In some implementations, host 108 can be configured to send or receive data to or from memory devices 104. In some implementations, the host can be a user logic, or a user interface such that the user may give instructions to the host and transmit the instructions to the memory devices or the memory array.

Memory device 104 can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device 104, such as phase change random access memory (PCRAM) , dynamic random access memory (DRAM) , or NAND Flash memory device, can include a clock input, a command bus, a control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, an input/output circuit (I/O circuit) /read data latch, and a data register/data I/O, according to some implementations.

Memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104, according to some implementations. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and write operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol. For example, memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. Furthermore, memory controller 106 can also be configured to control operations of memory device 104 to perform methods in accordance with some implementations of the present disclosure. For instance, in some implementations, memory controller 106 can determine an initial read voltage V _{read_1} based on a set threshold voltage distribution of memory cells in a memory array. In some implementations, memory controller 106 can determine whether the read voltage V _read is higher than a threshold voltage V _th of one of the plurality of memory cells. In some implementations, memory controller 106 can determine a state of the memory cell is a “set” state in response to the read voltage V _read is higher than the threshold voltage V _th. In some implementations, memory controller 106 can set the read voltage V _read as the initial read voltage V _{read_1} plus a step size voltage V _dac. In some implementations, memory controller 106 can determine a state of the memory cell is a “reset” state in response to the read voltage V _read is equal or higher than the maximum read voltage V _{read_max}. In some implementations, memory controller 106 can repeat or iterate applying the read voltage V _read to one of the plurality of memory cells in response to that the read voltage V _read is lower than the maximum read voltage V _{read_max}. It is noted that one or more of these operations of memory device 104 may also be performed partially or fully by a control logic in accordance with some implementations of the present disclosure.

FIG. 2 illustrates a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits, according to some aspects of the present disclosure. Memory device 200 can be an example of memory device 104 in FIG. 1. Memory device 200 can include a memory cell array 201 and peripheral circuits 202 coupled to memory cell array 201. Memory cell array 201 can include word lines 214, bit lines 216, and memory cells 208 formed between word lines 214 and bit lines 216. In some implementations, each memory cell 208 can include a PCM element (not shown) in series with a selector (not shown) . In some implementations, the memory cell 208 can also be a DRAM cell which includes a paired transistor and capacitor. To operate memory cell array 201, a word line voltage (V _w) can be applied to each word line 214, and a bit line voltage (V _b) can be applied to each bit line 216.

FIG. 3 illustrates a side view of a cross-section of a memory device 300 having a PCM element in series with a selector. Memory device 300 includes a plurality of parallel bit lines 304 (i.e., corresponding to bit line 216 in FIG. 2) above a substrate 302 and a plurality of parallel word lines 316 (i.e., corresponding to word line 214 in FIG. 2) above bit lines 304. Memory device 300 also includes a plurality of PCM cells 301 (i.e., corresponding to memory cell 208 in FIG. 2) each disposed at an intersection of a respective pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above selector 308. Each PCM cell 301 further includes three

electrodes

306, 310, and 314 vertically between a respective bit line 304, selector 308, PCM element 312, and a respective word line 316, respectively. As mentioned above, a read operation of a memory cell may reduce the lifespan of the memory cell. This phenomenon is observed particularly in a PCM cell (e.g., 301) having a PCM element (e.g., 312) in series with a selector (e.g., 308) because the PCM cell is more sensitive to read voltage and may have a higher chance to get stuck in a “reset” state when the read voltage is too high.

It is noted that PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change element can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.

Selector 308 may include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) is higher than the threshold voltage is applied (Vth) . At lower voltage (|Va| < Vth) , the high resistance of the OTS selector in its off-state keeps the off-state current (Ioff) low. At higher voltage (|Va| > Vth) , the OTS selector undergoes the OTS phenomenon and switches to the on-state with low resistance; thus, the current through the OTS selector in the on-state (Ion) increases. The volatile on-state is maintained as long as high voltage is supplied.

FIG. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in FIG. 1) including a memory cell array 401 (e.g., corresponding to 201 in FIG. 2) and peripheral circuits, according to some aspects of the present disclosure. In some implementations, a memory cell of memory cell array 401 includes PCM cell 301 as in FIG. 3.

As shown in FIG. 4, page buffer/sense amplifier 404 can be configured to read and program (write) data from and to memory cell array 401 according to the control signals from control logic 412. In one example, page buffer/sense amplifier 404 may store one page of program data (write data) to be programmed into one page of memory cell array 201 (e.g., in FIG. 2) . In another example, page buffer/sense amplifier 404 may perform program verify operations to ensure that the data has been properly programmed into memory cells 208 coupled to selected word lines 214. In still another example, page buffer/sense amplifier 404 may also sense the low power signals from bit line 216 that represents a data bit stored in memory cells 208 and amplify the small voltage swing to recognizable logic levels in a read operation. In some implementations, page buffer/sense amplifier 404 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a pre-determined threshold voltage of a memory cell under “set” state) .

Column decoder/bit line driver/data latch 406 can be configured to be controlled by control logic 412 and select one or more memory cells 208 and bit lines 216. Column decoder/bit line driver/data latch 406 can be further configured to drive the selected bit line 216. Column decoder/bit line driver/data latch 406 can be further configured to drive bit lines 216 using bit line voltages generated from voltage generator 410. Column decoder/bit line driver/data latch 406 can be a temporary binary data storage facility to store bits. In some implementations, column decoder/bit line driver/data latch 406 may include a read data latch to store read data temporarily.

Data register/data I/O 416 can be coupled to page buffer/sense amplifier 404 and/or column decoder/bit line driver/data latch 406 and configured to direct (route) the data input from data bus 423 to the desired memory cells 208 of memory cell array 201, as well as the data output from the desired memory cells to data bus 423.

Row decoder/word line driver 408 can be configured to be controlled by control logic 412 and select one or more memory cells 208 of memory cell array 201 and a word line 214. Row decoder/word line driver 408 can be further configured to drive the selected word line 214. Row decoder/word line driver 408 can be further configured to drive word lines 214 using word line voltages generated from voltage generator 410.

Voltage generator 410 can be configured to be controlled by control logic 412 according to the control signals from control logic 412 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc. ) , bit line voltages, and source line voltages to be supplied to memory cell array 401. In some implementations, voltage generator 410 is configured to generate the read voltage V _read to one of the memory cells in the memory cell array 401, and in response to the new, incremental read voltage V _read is lower than a maximum read voltage V _{read_max}, repeatedly generating another read voltage V _read to the memory cell in the memory cell array 401.

Control logic 412 can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit. Control logic 412 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host (e.g., 108 in FIG, 1) . The command signal is received via a command bus 421. The data signal is received via a data bus 423. In some implementations, control logic 412 can be implemented by microprocessors, microcontrollers (a. k. a. microcontroller units (MCUs) ) , digital signal processors (DSPs) , application-specific integrated circuits (ASICs) , field-programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, control logic 412 is configured to direct one or more incremental read voltages into one of the memory cells in memory cell array 401. That is, control logic 412 may instruct voltage generator 410 to generate one or more incremental read voltages and direct word line driver 408 to apply the one or more incremental read voltages to the one of the memory cells in memory cell array 401. In some implementations, control logic 412 is also configured to receive a feedback signal from data register 416 to determine whether to direct another incremental read voltage into the one of the memory cells in memory cell array 401. The feedback signal based on whether a state of the one of the memory cells in memory cell array 401 has been determined can be processed by control logic 412.

Address registers 414 can be coupled to control logic 412 or included in the control logic 412. Address registers 414 can include state registers, command registers, and address registers for storing state information, command operation codes (OP codes) , and command addresses for controlling the operations of each peripheral circuit.

FIG. 5 illustrates a block diagram of a memory device 500 (e.g., corresponding to 400 in FIG. 4) , according to some aspects of the present disclosure. As shown in FIG. 5, once control logic 412 determines that a command signal is a read command, it triggers a read operation. The read data is then transmitted to word line driver 408 to introduce read voltage to memory cell array 401. To select a suitable read voltage, a set threshold voltage distribution and a reset threshold voltage distribution of a plurality of memory cells in memory cell array 401 may be determined at first.

The set threshold voltage distribution and the reset threshold voltage distribution are illustrated in FIG. 6. As shown in FIG. 6, each of the memory cells in memory cell array 401 may have different threshold voltages in both “set” state and “reset” state. The distribution of the threshold voltages may vary from one memory array to another. In some implementations, the distribution can be obtained by preliminary endurance test cycles. When selecting an initial read voltage V _{read_1}, it can be determined to be at a peak of the distribution of the set threshold voltage, according to some implementations. The initial read voltage V _{read_1} is at least to be higher than a minimum set threshold voltage and lower than a maximum set threshold voltage, according to some implementations. The second read voltage V _{read_2} is the initial read voltage V _{read_1} plus a step size voltage V _dac. In some implementations, the second read voltage V _{read_2} should be higher than a maximum set threshold voltage, which means that the step size voltage V _dac should be high enough to let the second read voltage V _{read_2} be out of the range of distribution of the set threshold voltage. However, in some circumstances where the maximum set threshold voltage and the minimum reset threshold voltage are too close or too far, the determination of the initial read voltage V _{read_1} or the step size voltage V _dac may be adjusted accordingly. The incremental read voltage V _read is configured to be incrementally added to reach the latest incremental read voltage V _{read_n}, where V _{read_n} is equal to the previous read voltage plus one step size voltage V _dac and n is an integer representing the number of read voltages applied during a read operation in accordance with some implementations of the present disclosure. The latest incremental read voltage V _{read_n} may not be equal or higher than a maximum read voltage V _{read_max}, where the maximum read voltage V _{read_max} may be determined at a peak of the distribution of the reset threshold voltage, or a minimum reset threshold voltage, according to some implementations. Since the higher the read voltage, the higher the probability to undesirably program the memory cells. The maximum read voltage V _{read_max} may be determined to prevent programming the memory cells. In some implementations, one of the memory cells is PCM cell 301 as shown in FIG. 3.

In some implementations, the number of read voltages applied during the read operations may not be more than three since each iteration of the reading operation may require an additional 40 to 50 nanoseconds (ns) to process, which will reduce the operation speed. For instance, in a typical DRAM application that requires approximately 80 to 200 ns per read cycle, the number of read voltages may be limited to 2 or 3.

In some implementations, the initial read voltage V _{read_1} may be determined as 0.8 to 1.2 V, for instance, 1.0 V, the step size voltage V _dac may be determined as 0.3 to 0.7 V, for instance, 0.5 V, when the window of distribution of set threshold voltage and the reset threshold voltage (i.e., the range between a maximum reset threshold voltage, for instance, 2.5 V, and a minimum set threshold voltage, for instance, 0.5 V) is 1.5 to 2.5 V, for instance, 2.0 V. It is also noted that step size voltage V _dac may be adjusted such that it can be different for each read operation.

Back to FIG. 5, after selecting a suitable read voltage, the read voltage is applied to the memory cells of memory cell array 401 via word lines. Sense amplifier 404 is configured to and will receive read data, e.g., a readout current or a readout voltage. Sense amplifier 404 may also include a comparator, e.g., a voltage comparator, to compare the readout voltage with a reference voltage. The reference voltage can be pre-determined as a set threshold voltage or a reset threshold voltage, in accordance with some implementations. The comparing output signal and/or the readout signal is configured to be temporarily stored in data latch 406 as in FIG. 4. In some implementations, the data latch can be included in data register 416. For instance, a read address and read data accompanying a read command are temporarily stored in a data register, and the read address and the read data are held until a next read command. The read data stored in data register/data I/O 416 may be output via an output of data register 416 to the next stage for signal processing accordingly.

FIG. 7 illustrates a flowchart of an exemplary method 700 for operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. Method 700 may be implemented partially or fully by control logic 412 as in FIG. 4 or memory controller 106 as in FIG. 1. It is understood that the operations shown in method 700 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.

Referring to FIG. 7, method 700 starts at operation 702 in which an incremental read voltage is applied to a memory cell of a plurality of memory cells in memory cell array 401 as in FIG. 4. In particular, the incremental read voltage is applied to one of the memory cells via one of the word lines of memory cell array 401. It is noted that the incremental read voltage hereinafter means that the read voltage is configured to be incrementally added (either to increase when the read voltage is positive or to decrease when the read voltage is negative) for each iteration until it reaches a certain level of voltage, e.g., a maximum voltage, which can be pre-determined by user or according to a distribution of reset voltages of the plurality of memory cells as mentioned above. In some implementations, the memory cell is PCM cell 301 as in FIG. 3.

Method 700 proceeds to operation 704, as illustrated in FIG. 7 in which, whether the incremental read voltage is higher than a threshold voltage of the memory cell is determined. The comparison between two voltages can be performed by a comparator, e.g., a voltage comparator, included in sense amplifier 404 as in FIG. 4.

Method 700 proceeds to operation 706, as illustrated in FIG. 7, in which, in response to the incremental read voltage is higher than the threshold voltage, a state of the memory cell is determined as a “set” state. In some implementations, after operation 706, a read output data under a “set” state is obtained. The read output data under the “set” state can be, for instance, a set current or a set voltage of the memory cell. The read output data under the “set” state is then stored in a data latch of data register 416 as shown in FIGs. 4 or 5. However, if the read voltage V _read is lower than the threshold voltage V _th of the memory cell in the read operation, the state of the memory cell cannot be determined because it can be either a “set” state or a “reset” state when the read voltage V _read is too low, i.e., lower than either the threshold voltage V _th under “set” state or the threshold voltage V _th under the “reset” state. Therefore, a higher read voltage V _read is required to distinguish the “set” state from the “reset” state.

Method 700 proceeds to operation 708, as illustrated in FIG. 7 in which, in response to the incremental read voltage is lower than the threshold voltage, repeat applying next incremental read voltage to the memory cell until the incremental read voltage reaches a maximum voltage, and then the state of the memory cell is determined as “reset” . It is noted that the next incremental read voltage is higher than the initial incremental read voltage. The step-by-step increase in the read voltage can guarantee that the read voltage can stay low as much as possible such that it reduces the change of unwanted program the memory cell to reset or damage the memory cell during frequent read operations. However, as mentioned above, if the next incremental read voltage is too high (i.e., higher than a voltage that may program the memory cell to reset) , it can undesirably write the memory cell. As such, the next incremental read voltage is configured to be first determined whether it reaches a certain voltage level, i.e., a maximum read voltage, which may be pre-determined by user or according to a distribution of the reset voltages of the plurality of memory cells in memory cell array 401 as in FIG. 4. The selection or the determination of the maximum read voltage to avoid accidentally programming the memory cell has been mentioned above. To examine the next incremental read voltage, if the next incremental read voltage reaches (i.e., is equal to or higher than) the maximum read voltage, the next incremental read voltage may already reach the reset voltage level, and therefore the state of the memory cell is determined as a “reset” state. On the contrary, if the next incremental read voltage has not reached (i.e., is less than) the maximum read voltage, the next iteration can be started out. The loop of the iteration is configured to be repeated until the state of the memory cell is determined as a “set” state or a “reset” state.

FIG. 8 illustrates a flowchart of an exemplary method 800 for operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. Method 800 may be implemented partially or fully by control logic 412 as in FIG. 4 or memory controller 106 as in FIG. 1. It is understood that the operations shown in method 800 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 8.

Referring to FIG. 8, method 800 starts at operation 802 in which, in response to determining that a command signal corresponds to a read operation, set the read voltage V _read as the initial read voltage V _{read_1}, where the initial read voltage V _{read_1} is determined according to a set threshold voltage distribution of a plurality of memory cells in memory cell array 401 as in FIG. 4.In some implementations, one of the plurality of the memory cell is PCM cell 301 as in FIG. 3.

Method 800 proceeds to operation 804, as illustrated in FIG. 8 in which the read voltage V _read is applied to one of the plurality of memory cells in memory cell array 401. In particular, the read voltage V _read is applied to one of the memory cells via one of the word lines of memory cell array 401.

Method 800 proceeds to operation 806, as illustrated in FIG. 8 in which after the read voltage V _read is applied to the memory cell, determine whether the read voltage V _read is higher than a threshold voltage V _th of the memory cell under the read operation. The comparison between two voltages can be executed by a comparator, e.g., a voltage comparator, included in sense amplifier 404 as mentioned above.

Method 800 proceeds to operation 808, as illustrated in FIG. 8 in which, in response to determining that the read voltage V _read is higher than the threshold voltage V _th of the memory cell in the read operation, determine that a state of the memory cell is a “set” state. In some implementations, after operation 808, a read output data under a “set” state is obtained. The read output data under the “set” state can be, for instance, a set current or a set voltage of the memory cell. The read output data under the “set” state is then stored in a data latch of data register 416 as shown in FIGs. 4 or 5. However, if the read voltage V _read is lower than the threshold voltage V _th of the memory cell in the read operation, it cannot determine the state of the memory cell because it can be either a “set” state or a “reset” state when the read voltage V _read is too low, i.e., lower than either the threshold voltages V _th under a “set” state or the threshold voltages V _th under a “reset” state. Therefore, a higher read voltage V _read is required to distinguish the “set” state from the “reset” state.

Method 800 proceeds to operation 810, as illustrated in FIG. 8 in which, in response to determining that the read voltage V _read is lower than the threshold voltage V _th of the memory cell in the read operation, set the read voltage V _read equal to the initial read voltage V _{read_1} plus the step size voltage V _dac. However, as mentioned above, if the new read voltage V _read is too high, i.e., higher than a voltage that may program the memory cell to reset, it can undesirably write the memory cell. Therefore, the new read voltage V _read should be within the maximum read voltage V _{read_max}. The determination of the maximum read voltage V _{read_max} to avoid accidentally programming the memory cell is mentioned above. On the contrary, if the new read voltage V _read is equal to or higher than the maximum read voltage V _{read_max}, the incremented read voltage V _read has reached a reset voltage level, and therefore the state of the memory cell is determined as a “reset” state.

Based on the above illustration, method 800 then proceeds to operation 812, as illustrated in FIG. 8 in which, whether the read voltage V _read is equal or higher than the maximum read voltage V _{read_max} is determined. If the read voltage V _read is equal or higher than the maximum read voltage V _{read_max,} the memory cell is in a reset state.

Therefore, method 800 then proceeds to operation 814, as illustrated in FIG. 8 in which, in response to determining the read voltage V _read is equal or higher than the maximum read voltage V _{read_max}, determine that a state of the memory cell is a “reset” state. In some implementations, after operation 814, a read output data under a “reset” state is obtained. The read output data under the “reset” state can be, for instance, a reset current or a reset voltage of the memory cell. The read output data under the “reset” state is then stored in a data latch of data register 416 as shown in FIGs. 4 or 5.

On the contrary, method 800 proceeds to operation 816, as illustrated in FIG. 8 in which, in response to determining the read voltage V _read is lower than the maximum read voltage V _{read_max}, repeat operation 804, which is to apply the read voltage V _read to the memory cell, and the following operations after operation 804 until the state of the memory cell is determined as either “set” or “reset” . To repeat operation 804, data register 416 is configured to send a feedback signal notifying and requiring control logic 412 to send the new incremental read voltage V _read to the memory cell.

According to one aspect of the present disclosure, a memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells, a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal, and a data register configured to store readout data and the comparison output signal.

In some implementations, the memory device further includes a control logic configured to direct the one of the one or more incremental read voltages into the one of the plurality of memory cells via the word line driver.

In some implementations, the control logic is configured to receive a feedback signal from the data register to determine whether to direct another incremental read voltage into the one of the plurality of memory cells.

In some implementations, the feedback signal from the data register is whether the one of the one or more incremental read voltages is higher than a threshold voltage of the one of the plurality of memory cells.

In some implementations, the memory device further includes a voltage generator configured to generate the one or more incremental read voltages.

In some implementations, each memory cell includes a phase-change memory (PCM) cell.

In some implementations, the phase-change memory (PCM) cell includes a PCM element and a selector in series with the PCM element.

In some implementations, the one or more incremental read voltages includes an initial read voltage V _{read_1} and incrementally adding a step size voltage V _dac to a latest read voltage V _{read_n}, where n is an integer representing a number of incremental read voltages applied to the one of the plurality of memory cells during a read operation.

In some implementations, the initial read voltage V _{read_1} is determined according to a set threshold voltage distribution of the plurality of memory cells in each one of the plurality of memory cell arrays.

In some implementations, the reference voltage includes a threshold voltage of the one of the plurality of memory cells.

In some implementations, the reference voltage includes a maximum read voltage V _{read_max} of the one of the plurality of memory cells.

In some implementations, the maximum read voltage V _{read_max} is determined according to a reset threshold voltage distribution of the plurality of memory cells in each one of the plurality of memory cell arrays.

According to another aspect of the present disclosure, a system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells, a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal, and a data register configured to store readout data and the comparison output signal.

In some implementations, the memory device of the system further includes a control logic configured to direct the one or more incremental read voltages into one of the plurality of memory cells via the word line driver.

In some implementations, the feedback signal from the data register is whether the one or more incremental read voltages is higher than a threshold voltage of the one of the plurality of memory cells.

In some implementations, the memory device of the system further includes a voltage generator configured to generate the one or more incremental read voltages.

In some implementations, the PCM cell includes a PCM element and a selector in series with the PCM element.

In some implementations, the one or more incremental read voltages comprises an initial read voltage V _{read_1} and incrementally adding a step size voltage V _dac to a latest read voltage V _{read_n}, where n is an integer representing a number of incremental read voltages applied to the one of the plurality of memory cells during a read operation.

In some implementations, the initial read voltage V _{read_1} is determined according to a threshold voltage distribution in a “set” state of the plurality of memory cells in each one of the plurality of memory cell arrays.

According to still another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells being connected between word lines and bit lines. The method includes applying an incremental read voltage to one of the plurality of memory cell, determining whether the incremental read voltage is higher than a threshold voltage of the one of the plurality of memory cell, in response to the incremental read voltage is higher than the threshold voltage, a state of the memory cell is determined as a “set” state, and in response to the incremental read voltage is lower than the threshold voltage, repeating applying next incremental read voltage to the one of the plurality of memory cell until the incremental read voltage reaches to a maximum voltage, and then the state of the memory cell is determined as “reset” .

According to yet another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells being connected between word lines and bit lines. The method includes in response to determining that a command corresponds to a read operation, setting a read voltage V _read as an initial read voltage V _{read_1}, applying the read voltage V _read to one of the plurality of memory cells, determining whether the read voltage V _read is higher than a threshold voltage V _th of the one of the plurality of memory cells, in response to the read voltage V _read is higher than the threshold voltage V _th, determining a state of the one of the plurality of memory cells is a “set” state, in response to the read voltage V _read is lower than the threshold voltage V _th, setting the read voltage V _read equals the initial read voltage V _{read_1} plus a step size voltage V _dac, determining whether the read voltage V _read is equal or higher than a maximum read voltage V _{read_max}, in response to the read voltage V _read is equal or higher than the maximum read voltage V _{read_max}, determining the state of the one of the plurality of memory cells is a “reset” state, and in response to the read voltage V _read is lower than the maximum read voltage V _{read_max}, repeating applying the read voltage V _read to the one of the plurality of memory cells.

In some implementations, the initial read voltage V _{read_1} is determined according to a set threshold voltage distribution of the plurality of memory cells.

In some implementations, the maximum read voltage V _{read_max} is determined according to a reset threshold voltage distribution of the plurality of memory cells.

In some implementations, the method further includes storing a read output data under the “set” state or the “reset” state in a data latch of the memory device.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells connected between word lines and bit lines;

a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells;

a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal; and

a data register configured to store readout data and the comparison output signal.
The memory device of claim 1, further comprising:

a control logic configured to direct the one of the one or more incremental read voltages into the one of the plurality of memory cells via the word line driver.
The memory device of claim 2, wherein the control logic is configured to receive a feedback signal from the data register to determine whether to direct another incremental read voltage into the one of the plurality of memory cells.
The memory device of claim 3, wherein the feedback signal from the data register is whether the one of the one or more incremental read voltages is higher than a threshold voltage of the one of the plurality of memory cells.
The memory device of any one of claims 1-4, further comprising:

a voltage generator configured to generate the one or more incremental read voltages.
The memory device of any one of claims 1-5, wherein each memory cell comprises a phase-change memory (PCM) cell.
The memory device of claim 6, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
The memory device of any one of claims 1-7, wherein the one or more incremental read voltages comprises an initial read voltage V _{read_1} and incrementally adding a step size voltage V _dac to a latest read voltage V _{read_n}, where n is an integer representing a number of incremental read voltages applied to the one of the plurality of memory cells during a read operation.
The memory device of claim 8, wherein the initial read voltage V _{read_1} is determined according to a set threshold voltage distribution of the plurality of memory cells in each one of the plurality of memory cell arrays.
The memory device of any one of claims 1-9, wherein the reference voltage comprises a threshold voltage of the one of the plurality of memory cells.
The memory device of any one of claims 1-10, wherein the reference voltage comprises a maximum read voltage V _{read_max} of the one of the plurality of memory cells.
The memory device of claim 11, wherein the maximum read voltage V _{read_max} is determined according to a reset threshold voltage distribution of the plurality of memory cells in each one of the plurality of memory cell arrays.
A system, comprising:

a memory device configured to store data, the memory device comprising:

a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells connected between word lines and bit lines;

a word line driver coupled to the plurality of memory cell arrays and configured to drive one or more incremental read voltages into one of the plurality of memory cells;

a sense amplifier configured to compare each one of the one or more incremental read voltages with a reference voltage and generate a comparison output signal; and

a data register configured to store readout data and the comparison output signal; and

a memory controller coupled to the memory device and configured to control the memory device.
The system of claim 13, further comprising:

a control logic configured to direct the one or more incremental read voltages into one of the plurality of memory cells via the word line driver.
The system of claim 14, wherein the control logic is configured to receive a feedback signal from the data register to determine whether to direct another incremental read voltage into the one of the plurality of memory cells.
The system of claim 15, wherein the feedback signal from the data register is whether the one or more incremental read voltages is higher than a threshold voltage of the one of the plurality of memory cells.
The system of any one of claims 13-16, further comprising:

a voltage generator configured to generate the one or more incremental read voltages.
The system of any one of claims 13-17, wherein each memory cell comprises a phase-change memory (PCM) cell.
The system of claim 18, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
The system of any one of claims 13-19, wherein the one or more incremental read voltages comprises an initial read voltage V _{read_1} and incrementally adding a step size voltage V _dac to a latest read voltage V _{read_n}, where n is an integer representing a number of incremental read voltages applied to the one of the plurality of memory cells during a read operation.
The system of claim 20, wherein the initial read voltage V _{read_1} is determined according to a threshold voltage distribution in a “set” state of the plurality of memory cells in each one of the plurality of memory cell arrays.
The system of any one of claims 13-21, wherein the reference voltage comprises a threshold voltage of the one of the plurality of memory cells.
The system of any one of claims 13-22, wherein the reference voltage comprises a maximum read voltage V _{read_max} of the one of the plurality of memory cells.
The system of claim 23, wherein the maximum read voltage V _{read_max} is determined according to a reset threshold voltage distribution of the plurality of memory cells in each one of the plurality of memory cell arrays.
A method for operating a memory device, the memory device comprising:

a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells being connected between word lines and bit lines, the method comprising:

applying an incremental read voltage to one of the plurality of memory cell;

determining whether the incremental read voltage is higher than a threshold voltage of the one of the plurality of memory cell;

in response to the incremental read voltage is higher than the threshold voltage, a state of the memory cell is determined as a “set” state; and

in response to the incremental read voltage is lower than the threshold voltage, repeating applying next incremental read voltage to the one of the plurality of memory cell until the incremental read voltage reaches a maximum voltage, and then the state of the memory cell is determined as a “reset” state.
The method of claim 25, wherein each memory cell comprises a phase-change memory (PCM) cell.
The method of claim 26, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
A method for operating a memory device, the memory device comprising:

a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells being connected between word lines and bit lines, the method comprising:

in response to determining that a command corresponds to a read operation, setting a read voltage V _read as an initial read voltage V _{read_1};

applying the read voltage V _read to one of the plurality of memory cells;

determining whether the read voltage V _read is higher than a threshold voltage V _th of the one of the plurality of memory cells;

in response to the read voltage V _read is higher than the threshold voltage V _th, determining a state of the one of the plurality of memory cells is a “set” state;

in response to the read voltage V _read is lower than the threshold voltage V _th, setting the read voltage V _read equals the initial read voltage V _{read_1} plus a step size voltage V _dac;

determining whether the read voltage V _read is equal or higher than a maximum read voltage V _{read_max};

in response to the read voltage V _read is equal or higher than the maximum read voltage V _{read_max}, determining the state of the one of the plurality of memory cells is a “reset” state; and

in response to the read voltage V _read is lower than the maximum read voltage V _{read_max}, repeating applying the read voltage V _read to the one of the plurality of memory cells.
The method of claim 28, wherein the initial read voltage V _{read_1} is determined according to a set threshold voltage distribution of the plurality of memory cells.
The method of claim 28 or 29, wherein the maximum read voltage V _{read_max} is determined according to a reset threshold voltage distribution of the plurality of memory cells.
The method of any one of claims 28-30, further comprising:

storing a read output data under the “set” state or the “reset” state in a data latch of the memory device.