WO2023019495A1

WO2023019495A1 - Memory device and controlling method thereof

Info

Publication number: WO2023019495A1
Application number: PCT/CN2021/113403
Authority: WO
Inventors: Zuqi DONG; Jianping Li
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2023-02-23
Also published as: CN115004300A

Abstract

A memory device includes a memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respective word line, and an unselected memory cell connected between an unselected bit line and the respective word line. The memory device further includes a charge control circuit configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

Description

MEMORY DEVICE AND CONTROLLING METHOD THEREOF

BACKGROUND

The present disclosure relates to memory devices and operation methods thereof.

During a read operation of a memory cell, several steps may be required before applying a read voltage into the memory cell. The switches between these steps may be burdensome and redundant and generate unwanted glitches during the operation.

SUMMARY

In one aspect, a memory device includes a memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respective word line, and an unselected memory cell connected between an unselected bit line and the respective word line. The memory device further includes a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

In another aspect, a system includes a memory device including a memory cell array. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respective word line, and an unselected memory cell connected between an unselected bit line and the respective word line. The memory device further includes a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

In still another aspect, a method for operating a memory device, the memory device includes a selected memory cell connected between a selected bit line and a respective word line, an unselected memory cell connected between an unselected bit line and the respective word line, a first local control gate coupled to either the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method includes setting the selected bit line and the unselected bit line to an initial state, setting a first local control gate to “on” state to precharge either the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to “off” state and setting a second local control gate to “on” state at the same time such that the selected bit line and the unselected bit line reach a same voltage level, setting the second local control gate to “off” state and setting a third local control gate to “on” state at the same time to discharge the selected bit line to a second voltage, applying a read voltage via a respective word line and getting a read result, and resetting the selected bit line and the unselected bit line to the initial state.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a block diagram of an exemplary system having a memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, according to some aspects of the present disclosure.

FIG. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 5 illustrates a block diagram of an exemplary memory device including a charge control circuit, according to some aspects of the present disclosure.

FIG. 6 illustrates a block diagram of an exemplary memory device including a charge control circuit, according to some aspects of the present disclosure.

FIGs. 7A-7B illustrate time sequences of a read operation of an exemplary memory device, according to some aspects of the present disclosure.

FIG. 8 illustrates a simulation result of a time sequence of control signals under a read operation.

FIG. 9A illustrates a simulation result of a time sequence of control signals under a read operation.

FIG. 9B illustrates a simulation result of a time sequence of control signals under a read operation using an exemplary method of operating a memory device, according to some aspects of the present disclosure.

FIG. 10 illustrates a flowchart of an exemplary method of operating a memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. In addition, the term “couple” , “coupled to” , or “coupled between” may be understood as not necessarily intended to be “physically joined or attached, ” i.e., direct attachment, but can also be interpreted by indirect connection through an intermediate component.

Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material. PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. A “set” state is a low resistance state of the PCM cell that can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration. A “reset” state, on the contrary, is a high resistance state of the PCM cell that can be obtained by creating amorphous regions in the chalcogenide material. Amorphous can be created when the chalcogenide material is heated above its melting temperature and then quickly quenched to create a formation of amorphous. The “set” state can be referred to as an “on” state, while the “reset” state can be referred to as an “off” state.

The conventional read operation of a memory cell may require multiple steps or operations to precharge sharing, charge sharing, or discharge respective bit lines before applying a read voltage via a word line to read out the result. Due to the resistive-capacitive delay (RC delay) , a time interval should be given between each two of the multiple steps to avoid glitches caused by the control signal overlay, thereby increasing the read latency.

Specifically, to obtain a result of determining whether the memory cell is in a “set” state or “reset” state, a charge sharing process is required to bring the selected bit line and the unselected bit line to the same voltage level as a reference voltage before a read voltage is applied to the memory cells via a word line. The charge sharing process may include several precharge sharing, charge sharing, and discharge steps, which are controlled by applying several controlling signals to turn on and off several control gates and to apply the specific charging or discharging voltage bias into the bit lines. However, due to the resistive-capacitive delay (RC delay) , a time interval should be given between each of the multiple steps to avoid glitches caused by the control signal overlay, thereby increasing the read latency. Moreover, in a memory device having phase-change memory (PCM) cells (e.g., each PCM cell may include a PCM element in series with a selector) , read latency is an essential factor to the entire system performance. A solution to avoid the glitch between controlling signal overlay during the precharge sharing, charge sharing, or discharge processes while reducing the overall read time is highly desirable. In addition, because there are multiple precharge sharing, charge sharing, or discharge processes, several control signals may be required to be applied to turn on and off the control gate to precharge sharing, charge sharing, or discharge the respective bit lines; these processes are redundant and burdensome. A simplified method and corresponding circuit design to control multiple steps of on and off may also be needed.

To address one or more of the aforementioned issues, the present disclosure provides a solution in which an integrated charge control circuit is introduced to prepare phase by applying controlling signals in advance before switching to the next step of the charging or discharging process, thereby reducing the glitch between the switches and the time interval given to avoid the glitch. Moreover, the processes are also simplified to reduce the read latency. Specifically, before a read voltage is applied to the word line to read out the result of the memory cells, a selected bit line and an unselected bit line are set to an initial state. In some implementations, the initial state may be a ground state or at 0 V.

Next, during a precharge sharing process, a first local control gate is set to “on” state to precharge an unselected bit line to a first voltage, e.g., a first negative voltage. In some implementations, it can also be precharging a selected bit line instead of the unselected bit line. The precharge sharing process is used to pull one of the bit lines to a voltage (e.g., a negative voltage) such that after the following charge sharing process, two bit lines will be brought to the same voltage level (e.g., half of the previous negative voltage) . It is noted that “precharge” or “precharge sharing” hereinafter refers to charging a bit line before a charge sharing process.

Next, during a charge sharing process, the first local control gate is set to “off” state to discontinue precharging the unselected bit line (or the selected bit line) , and a second local control gate is set to “on” state at the same time such that the selected bit line and the unselected bit line reach the same voltage level, which is a reference voltage. It is noted that “charge sharing” hereinafter refers to electrically connect two bit lines to reach the same voltage level.

Next, the second local control gate is set to “off” state to discontinue charge sharing the selected bit line and the unselected bit line, and a third local control gate is set to “on” state at the same time to discharge the selected bit line to a second voltage, e.g., a second negative voltage, and then the third local control gate is set to “off” state to discontinue discharging the selected bit line. It is noted that “discharge” hereinafter refers to charge a bit line to a negative voltage level, especially to a voltage level lower than the reference voltage.

Next, after the selected bit line is discharged to the second negative voltage and the unselected bit line remains at the reference voltage, apply a read voltage via a respective word line and get the read result. If a selected memory cell on the selected bit line is in “set” state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is higher than the set threshold voltage of the selected memory cell, while the unselected bit line will remain at the reference voltage. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “set” state can be later obtained. If a selected memory cell on the selected bit line is in a “reset” state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is lower than the reset threshold voltage of the selected memory cell. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “reset” state can be later obtained.

After the read result is read out, the selected bit line and the unselected bit line are reset to the initial state during a recovery process, and the read operation is completed.

As mentioned above, by turning “on” the first local control gate and turning “off” the second local control gate, and by turning “off” the second local control gate and turning “on” the third local control gate at the same time, the time interval can be reduced to a minimum. To turn one local control gate on and another local control gate off at the same time while preventing the glitch, an integrated charge control circuit can be provided. Specifically, one of the exemplary integrated charge control circuits is to have a first control signal provided to the first local control gate, a second control signal, and an inverted first control signal (e.g., inverting the first control signal by a first inverter) provided to a first AND logic gate, and a third control signal and an inverted second control signal (e.g., inverting the second control signal by a second inverter) provided to a second AND logic gate. By doing so, before the first control signal is turned to 0 V, the inverted first control signal stays 0 V such that the second local control gate cannot be turned “on” no matter whether the second control signal is turned “on” or not. Therefore, a second control signal can be applied to the first AND logic gate in advance and waiting until the first control signal is turned to 0 V. And when the first control signal is turned to 0 V (i.e., the first local control gate is turned “off” ) , the second local control gate is turned “on” immediately. No or little glitch will be generated since the second control signal has been turned on already when the first control signal is turned off. Similarly, before the second control signal is turned to 0 V, the inverted second control signal stays 0 V such that the third local control gate cannot be turned “on” no matter whether the third control signal is turned “on” or not. Therefore, a third control signal can be applied to the second AND logic gate in advance and waiting until the second control signal is turned to 0 V. And when the second control signal is turned to 0 V (i.e., the second local control gate is turned “off” ) , the third local control gate is turned “on” immediately. No or little glitch will be generated since the third control signal has been turned on already when the second control signal is turned off. It is noted that the integrated charge control circuit in accordance with some implementations of the present disclosure is only an example to achieve the desired function or mechanism, any other control gate combinations to achieve the same or similar function are possible in light of the above teaching.

FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . In some implementations, host 108 can be configured to send or receive data to or from memory devices 104. In some implementations, the host can be a user logic, or a user interface such that the user may give instructions to the host and transmit the instructions to the memory devices or the memory array.

Memory device 104 can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device 104, such as phase-change random access memory (PCRAM) , dynamic random access memory (DRAM) , or NAND Flash memory device, can include a clock input, a command bus, a data bus, a control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, a data input/output (I/O) , according to some implementations.

Memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104, according to some implementations. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and write operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol. For example, memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. Furthermore, memory controller 106 can also be configured to control operations of memory device 104 to perform methods in accordance with some implementations of the present disclosure. For instance, in some implementations, memory controller 106 can determine whether the read voltage is higher or lower than a threshold voltage of the selected memory cell. In some implementations, memory controller 106 can determine a state of the selected memory cell is a “set” state in response to the read voltage is higher than the threshold voltage of the selected memory cell, or a state of the selected memory cell is a “reset” state in response to the read voltage is lower than the threshold voltage of the selected memory cell. It is noted that one or more of these operations of memory device 104 may also be performed partially or fully by control logic in accordance with some implementations of the present disclosure.

FIG. 2 illustrates a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits, according to some aspects of the present disclosure. Memory device 200 can be an example of memory device 104 in FIG. 1. Memory device 200 can include a memory cell array 201 and peripheral circuits 202 coupled to memory cell array 201. Memory cell array 201 can include word lines (e.g., a selected word line 214) , bit lines (e.g., a selected bit line 216 and an unselected bit line 218) , and memory cells (e.g., a selected memory cell 208 and an unselected memory cell 210) formed between word lines and bit lines. In some implementations, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) can include a PCM element (not shown) in series with a selector (not shown) . In some implementations, the memory cell (e.g., 208 or 210) can also be a DRAM cell which includes a paired transistor and capacitor. To read a selected memory cell (e.g., selected memory cell 208) , a selected word line voltage (e.g., a selected word line voltage Vwl ₁) can be applied to a selected word line (e.g., selected word line 214) , and a selected bit line voltage (e.g., a selected bit line voltage Vbl1) can be applied to a selected bit line (e.g., selected bit line 216) . The other unselected word lines will stay at an unselected word line voltage (e.g., Vwl ₀) , and the other unselected bit lines will stay at an unselected bit line voltage (e.g., Vbl0) . In some implementations, the unselected bit line voltage (e.g., Vbl0) of the unselected bit line (e.g., unselected bit line 218) is configured to be set to a reference voltage by a series of voltages during precharge sharing, charge sharing, and discharge processes before the selected word line voltage (e.g., selected word line voltage Vwl ₁) being applied to the selected word line (e.g., selected word line 214) . In some implementations, the selected bit line voltage (e.g., Vbl1) of the selected bit line (e.g., selected bit line 216) is configured to be set to a series of voltages during precharge sharing, charge sharing, and discharge processes before the selected word line voltage (e.g., selected word line voltage Vwl ₁) being applied to the selected word line (e.g., selected word line 214) . These precharge sharing, charge sharing, and discharge processes will be discussed later.

FIG. 3 illustrates a side view of a cross-section of a memory device 300 having a PCM element in series with a selector. Memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to bit line 216 in FIG. 2) above a substrate 302 and one or more parallel word lines 316 (i.e., corresponding to word line 214 in FIG. 2) above bit lines 304. Memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to memory cell 208 in FIG. 2) each disposed at an intersection of a respective pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above selector 308. Each PCM cell 301 further includes three

electrodes

306, 310, and 314 vertically between a respective bit line 304, selector 308, PCM element 312, and a respective word line 316, respectively. As mentioned above, a read operation of a memory cell may reduce the lifespan of the memory cell. This phenomenon is observed particularly in a PCM cell (e.g., 301) having a PCM element (e.g., 312) in series with a selector (e.g., 308) because the PCM cell is more sensitive to read voltage and may have a higher chance to get stuck in a “reset” state when the read voltage is too high.

It is noted that PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change element can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.

Selector 308 may include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) is higher than the threshold voltage is applied (Vth) . At lower voltage (|Va| < Vth) , the high resistance of the OTS selector in its off-state keeps the off-state current (Ioff) low. At higher voltage (|Va| > Vth) , the OTS selector undergoes the OTS phenomenon and switches to the on-state with low resistance; thus, the current through the OTS selector in the on-state (Ion) increases. The volatile on-state is maintained as long as high voltage is supplied.

FIG. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in FIG. 1) including a memory cell array 401 (e.g., corresponding to 201 in FIG. 2) , and peripheral circuits, according to some aspects of the present disclosure. In some implementations, a memory cell of memory cell array 401 includes PCM cell 301 as in FIG. 3.

As shown in FIG. 4, page buffer/sense amplifier 404 can be coupled to memory cell array 401 and configured to read and program (write) data from and to memory cell array 401 according to the control signals from control logic 412. In one example, page buffer/sense amplifier 404 may store one page of program data (write data) to be programmed into one page of memory cell array 201 (e.g., in FIG. 2) . In another example, page buffer/sense amplifier 404 may perform program verify operations to ensure that the data has been properly programmed into memory cells 208 coupled to selected word line 214. In still another example, page buffer/sense amplifier 404 may also sense the low power signals from selected bit line 216 that represents a data bit stored in memory cells 208 and amplify the small voltage swing to recognizable logic levels in a read operation.

Column decoder/bit line driver can be coupled to memory cell array 401 and control logic 412 and configured to be controlled by control logic 412 and select one or more memory cells (e.g., selected memory cell 208) and bit lines (e.g., selected bit line 216) . Column decoder/bit line driver 406 can be further configured to drive selected bit line 216. Column decoder/bit line driver 406 can be further configured to drive selected bit lines 216 using bit line voltages generated from voltage generator 410.

Data I/O 416 can be coupled to page buffer/sense amplifier 404 and/or column decoder/bit line driver 406 and configured to direct (route) the data input from data bus 423 to the selected memory cells 208 of memory cell array 201, as well as the data output from the selected memory cells to data bus 423.

Row decoder/word line driver 408 can be coupled to control logic 412 and memory cell array 401 and configured to be controlled by control logic 412 and select one or more memory cells (e.g., selected memory cell 208) of memory cell array 201 and a selected word line (e.g., selected word line 214) . Row decoder/word line driver 408 can be further configured to drive selected word line 214. Row decoder/word line driver 408 can be further configured to drive selected word line 214 using word line voltages generated from voltage generator 410.

Voltage generator 410 can be coupled to control logic 412 and configured to be controlled by control logic 412 according to the control signals from control logic 412 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc. ) , bit line voltages, and source line voltages to be supplied to memory cell array 401.

Control logic 412 can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit. Control logic 412 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host (e.g., 108 in FIG, 1) . The command signal is received via a command bus 421. The data signal is received via a data bus 423. In some implementations, control logic 412 can be implemented by microprocessors, microcontrollers (a. k. a. microcontroller units (MCUs) ) , digital signal processors (DSPs) , application-specific integrated circuits (ASICs) , field-programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, control logic 412 is coupled to word line driver 408 and configured to direct the read voltage into the selected memory cell via word line driver 408.

Address registers 414 can be coupled to control logic 412 or included in the control logic 412. Address registers 414 can include state registers, command registers, and address registers for storing state information, command operation codes (OP codes) , and command addresses for controlling the operations of each peripheral circuit.

FIG. 5 illustrates a block diagram of a memory device (e.g., corresponding to 400 in FIG. 4) including a charge control circuit 500, according to some aspects of the present disclosure. As shown in FIG. 4, once control logic 412 determines that a command signal is a read command, it triggers a read operation. The read operation includes a series of precharge sharing, charge sharing, and discharge processes before the read voltage is applied to the selected word line. These precharge sharing, charge sharing, and discharge processes are performed by charge control circuit 500 in accordance with some implementations of the present disclosure. Charge control circuit 500 may include a voltage comparator 501 (e.g., corresponding to or included in page buffer/sense amplifier 404) coupled to the memory cell array (e.g., corresponding memory cell array 201 or 401) , an unselected bit line 511 (e.g., corresponding to unselected bit line 218) connected to a first input terminal 503 of voltage comparator 501, and a selected bit line 513 (e.g., corresponding to selected bit line 216) connected to s second input terminal 505 of voltage comparator 501. In some implementations, voltage comparator 501 is configured to determine if the selected bit line voltage Vbl1 of selected bit line 513 (e.g., selected bit line 216) is higher than the reference voltage held by unselected bit line 511 (e.g., corresponding to unselected bit line 218) , the selected memory cell (e.g., selected memory cell 208) is in a “set” state, and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a “reset” state.

A first local control gate 521 is coupled to either selected bit line 513 (e.g., corresponding to selected bit line 216 in FIG. 2) or unselected bit line 511 (e.g., corresponding to unselected bit line 218) and configured to control whether either selected bit line 513 or unselected bit line 511 is precharged to a first voltage (e.g., a first negative voltage Vn1) during the precharge sharing process. In one example, as illustrated in FIG. 5, first local control gate 521 is configured to control whether unselected bit line 511 is precharged to first negative voltage Vn1. In some implementations, first negative voltage Vn1 can be -2 V to -4 V, e.g., -3.7 V.

A second local control gate 523 is coupled between selected bit line 513 and unselected bit line 511 and configured to control whether selected bit line 513 and unselected bit line 511 are brought to the same voltage level (e.g., 1/2 of first negative voltage Vn1) during the charge sharing process. The voltage level (e.g., 1/2 of first negative voltage Vn1) after the charge sharing process can be a reference voltage which can be used to determine whether the selected memory cell is in a “set” state or a “reset” state by comparing the selected bit line voltage Vbl1 with the reference voltage held by unselected bit line 511. For example, if the selected memory cell is in a “set” state, after applying a read voltage across the selected word line, the selected bit line voltage will be pulled up over the reference voltage. On the contrary, if the selected memory cell is in a “reset” state, after applying a read voltage across the selected word line, the selected bit line voltage will remain below the reference voltage.

A third local control gate 525 is coupled to selected bit line 513 and configured to control whether selected bit line 513 is discharged to a second voltage (e.g., a second negative voltage Vn2) during the discharge process. In some implementations, the second negative voltage Vn2 can be -2 V to -4 V, e.g., -3.7 V. It is noted that the charge control circuit 500 in accordance with some implementations of the present disclosure is only an example to achieve the desired function or mechanism; any other control logic gate combinations to achieve the same or similar function are possible in light of the above teaching.

FIG. 6 illustrates a block diagram of a memory device (e.g., corresponding to 400 in FIG. 4) including a charge control circuit 600, according to some aspects of the present disclosure. As mentioned above, to switch between first local control gate 521 and second local control gate 523, and second local control gate 523 and third local control gate 525 without causing the glitch and reduce time interval, an exemplary charge control circuit 600 is introduced.

First, a first control signal 621 can be transmitted to switch “on” and “off” first local control gate 521. That is, first local control gate 521 is configured to be controlled by first control signal 621.

Second, a second control signal 623 and an inverted first control signal, which is an inverted control signal of first control signal 621 by a first inverter 601, are provided to a first AND logic gate 611. The output result of first AND logic gate 611 can be transmitted to switch “on” and “off” second local control gate 523. That is, second local control gate 523 is configured to be controlled by the output result of first AND logic gate 611. First inverter 601 is coupled to first AND logic gate 611 and configured to invert first control signal 621 into the inverted first control signal. First AND logic gate 611 is configured to receive second control signal 623 and the inverted first control signal.

Third, a third control signal 625 and an inverted second control signal, which is an inverted control signal of second control signal 623 by a second inverter 603, are provided to a second AND logic gate 613. The output result of second AND logic gate 613 can be transmitted to switch “on” and “off” third local control gate 525. That is, third local control gate 525 is configured to be controlled by the output result of second AND logic gate 613. Second inverter 603 is coupled to second AND logic gate 613 and configured to invert second control signal 623 into the inverted second control signal. Second AND logic gate 613 is configured to receive third control signal 625 and the inverted second control signal.

As mentioned above, by turning “on” first local control gate 521 and turning “off” second local control gate 523, and by turning “off” second local control gate 523 and turning “on” third local control gate 525 at the same time, the time interval can be reduced to a minimum. Specifically, the first control signal 621 is provided to first local control gate 521, second control signal 623 and an inverted first control signal (e.g., inverting first control signal 621 by first inverter 601) provided to first AND logic gate 611, and third control signal 625 and an inverted second control signal (e.g., inverting second control signal 623 by second inverter 603) provided to second AND logic gate 613. By doing so, before first control signal 621 is turned to 0 V, the inverted first control signal stays 0 V such that second local control gate 523 cannot be turned “on” no matter whether second control signal 623 is turned “on” or not. Therefore, second control signal 623 can be turned on and applied to first AND logic gate 611 in advance and waiting until first control signal 621 is turned to 0 V. And when first control signal 621 is turned to 0 V (i.e., first local control gate 521 is turned “off” ) , second local control gate 523 is turned “on” immediately. No or little glitch will be generated since second control signal 623 has been turned on and already waiting when first control signal 621 is turned off. Similarly, before second control signal 623 is turned to 0 V, the inverted second control signal stays 0 V such that third local control gate 525 cannot be turned “on” no matter whether third control signal 625 is turned “on” or not. Therefore, third control signal 625 can be turned and applied to second AND logic gate 613 in advance and waiting until second control signal 623 is turned to 0 V. And when second control signal 623 is turned to 0 V (i.e., second local control gate 523 is turned “off” ) , third local control gate 525 is turned “on” immediately. No or little glitch will be generated since third control signal 625 has been turned on already when second control signal 623 is turned off. It is noted that the charge control circuit 600 in accordance with some implementations of the present disclosure is only an example to achieve the desired function or mechanism; any other control logic gate combinations to achieve the same or similar function are possible in light of the above teaching.

FIGs. 7A-7B illustrate time sequences of a read operation of an exemplary memory device, according to some aspects of the present disclosure. Specifically, FIG. 7A illustrates a “set” state read out sequence and FIG. 7B illustrates a “reset” state read out sequence. As illustrated in FIG. 7A, step 1 is an initial state in which the current (Icell) over the memory cell (e.g., selected memory cell 208) is 0 mA when the word line voltage (Vwl) has not been provided to the memory cell, and selected bit line voltage (Vbl0) and unselected bit line voltage (Vbl0) are both set at a ground voltage or 0 V.

Step 2 is a precharge sharing process in which either the selected bit line (e.g., selected bit line 216) or the unselected bit line (e.g., unselected bit line 218) is precharged to the first negative voltage Vn1.

Step 3 is a charge sharing process in which the selected bit line and the unselected bit line are electrically connected such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage.

Step 4 is a discharge process in which the selected bit line is discharged to the second negative voltage Vn2.

Step 5 is a reading process in which a read voltage, e.g., the word line voltage (Vwl) , is provided to the memory cell. Since the memory cell is in the “set” state, the current across the memory cell increases, and the selected bit line voltage is pulled up over the reference voltage held by the unselected bit line. Voltage comparator 501 (corresponding to or included in sense amplifier 404) can thus determine the memory cell is in the “set” state by sensing the flag is changed from 0 (Vbl0 > Vbl1) to 1 (Vbl0 < Vbl1) .

To the contrary, if the memory cell is in the “reset” state as in FIG. 7B, the current across the memory cell remains the same, and the selected bit line voltage is not pull up over the reference voltage. Voltage comparator 501 (corresponding to or included in sense amplifier 404) can thus determine the memory cell is in the “reset” state by sensing the flag is not changed from 0 to 1.

Step 6 is a recovery process in which both the selected bit line and the unselected bit line are reset to the initial state, which is the ground voltage or 0 V.

FIG. 8 illustrates a simulation result of a time sequence of control signals under a read operation. As shown in FIG. 8, step 2 can be divided into step 2a and step 2b because the first local control gate (corresponding to 521 in FIG. 5) is turned “on” during step 2a and turned “off” during the step 2b. Meanwhile, step 3 can be divided into step 3a and step 3b because the second local control gate (corresponding to 523 in FIG. 5) is turned “on” during step 3a and turned “off” during the step 3b. Also, step 4 can be divided into step 4a and step 4b because the third local control gate (corresponding to 525 in FIG. 5) is turned “on” during step 4a and turned “off” during the step 4b. By turning “on” and “off” of several local control gates, there are more than 9 steps for one read operation, which is burdensome and redundant to the entire system. Furthermore, since these local control gates, in some implementations, may be controlled by a basic control unit (BCU) , which is a component of the memory controller (corresponding to 106 in FIG. 1) , it may require several clock cycles to perform these steps.

For instance, FIG. 9A, a simulation result without the charge control circuit (e.g., 500 or 600) in accordance with some implementations of the present disclosure, shows that at least 2 cloak cycles (4 ns) are needed for each switch phase, and therefore, a total 10 ns are needed for each read operation, which increases overall read latency (it is noted that the entire read operation may take 120 ns) .

Therefore, after implemented the charge control circuit (e.g., 500 or 600) in accordance with some implementations of the present disclosure, FIG. 9B shows that the overall time interval is less than 0.5 nanosecond (ns) , e.g., 247 picoseconds (ps) + 104 ps = 351 ps, and without any glitch.

FIG. 10 illustrates a flowchart of an exemplary method of operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. Method 1000 may be implemented partially or fully by control logic 412 as in FIG. 4 or memory controller 106 as in FIG. 1. It is understood that the operations shown in method 1000 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 10.

Referring to FIG. 10, method 1000 starts at operation 1002 in which a selected bit line (e.g., 216 in FIG. 2) and an unselected bit line (e.g., 218 in FIG. 2) are chosen and set to an initial state. In some implementations, the initial state may be a ground state or at 0 V.

Method 1000 proceeds to operation 1004, as illustrated in FIG. 10, in which, during the precharge sharing process, a first local control gate (e.g., 521 in FIG. 5) is set to “on” state to precharge either the selected bit line or the unselected bit line (e.g., precharge the unselected bit line as in FIG. 7A) to a first voltage (e.g., the first negative voltage Vn1) . The precharge sharing process is used to pull one of the bit lines to a voltage (e.g., a negative voltage) such that after the following charge sharing process, two bit lines will be brought to the same voltage level (e.g., half of the previous negative voltage) .

Method 1000 proceeds to operation 1006, as illustrated in FIG. 10, in which, during the charge sharing process, the first local control gate is set to “off” state to discontinue precharging the unselected bit line, and a second local control gate (e.g., 523 in FIG. 5) is set to “on” state at the same time such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage.

Method 1000 proceeds to operation 1008, as illustrated in FIG. 10, in which the second local control gate is set to “off” state to discontinue charge sharing the selected bit line and the unselected bit line, and a third local control gate (e.g., 525 in FIG. 5) is set to “on” state at the same time to discharge the selected bit line to a second voltage (e.g., a second negative voltage Vn2) , and then the third local control gate is set to “off” state to discontinue discharging the selected bit line.

Method 1000 proceeds to operation 1010, as illustrated in FIG. 10, in which, after the selected bit line is discharged to the second negative voltage and the unselected bit line remains at the reference voltage, a read voltage is applied via a respective word line and get the read result. If a selected memory cell (e.g., selected memory cell 208 in FIG. 2) on the selected bit line (e.g., selected bit line 216 in FIG. 2) is in “set” state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is higher than the set threshold voltage of the selected memory cell, while the unselected bit line will remain at the reference voltage. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “set” state can be obtained. If the selected memory cell on the selected bit line is in a “reset” state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is lower than the reset threshold voltage of the selected memory cell. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “reset” state can be obtained. In some implementations, the memory cell can be PCM cell 301 as in FIG. 3.

Method 1000 proceeds to operation 1012, as illustrated in FIG. 10, in which, after the read result is read out, the selected bit line and the unselected bit line are reset to the initial state during a recovery process, and the read operation is completed.

According to one aspect of the present disclosure, a memory device includes a memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respective word line, and an unselected memory cell connected between an unselected bit line and the respective word line. The memory device further includes a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

In some implementations, an overall time interval between each process of precharging either the selected bit line or the unselected bit line to the first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage, is less than 0.5 nanosecond (ns) .

In some implementations, the charge control circuit further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

In some implementations, the charge control circuit further includes a first local control gate coupled to either the selected bit line or the unselected bit line and configured to control precharging either the selected bit line or the unselected bit line to the first voltage, a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.

In some implementations, the charge control circuit further includes: a first inverter configured to receive a first control signal and generate an inverted first control signal, a second inverter configured to receive a second control signal and generate an inverted second control signal, a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal, and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal. The first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

In some implementations, each memory cell includes a phase-change memory (PCM) cell.

In some implementations, the PCM cell includes a PCM element and a selector in series with the PCM element.

In some implementations, the first voltage is a first negative voltage of -2 V to -4 V.

In some implementations, the second voltage is a second negative voltage of -2 V to -4 V.

In some implementations, the same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit line with the selected bit line voltage of the selected bit line.

In some implementations, the voltage comparator is configured to determine if the selected bit line voltage of the selected bit line is higher than the reference voltage, the selected memory cell is in a “set” state, and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a “reset” state.

In some implementations, the memory device further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

In some implementations, the memory device further includes a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the respective word line.

In some implementations, the memory device further includes a control logic coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

In some implementations, the memory device further includes a data register coupled to the charge control circuit and configured to store readout data and the comparison output signal.

According to another aspect of the present disclosure, a system includes a memory device including a memory cell array. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respective word line, and an unselected memory cell connected between an unselected bit line and the respective word line. The memory device further includes a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

In some implementations, the charge control circuit of the system further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

In some implementations, the charge control circuit of the system further includes a first local control gate coupled to either the selected bit line or the unselected bit line and configured to control precharging either the selected bit line or the unselected bit line to the first voltage, a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.

In some implementations, the charge control circuit of the system further includes: a first inverter configured to receive a first control signal and generate an inverted first control signal, a second inverter configured to receive a second control signal and generate an inverted second control signal, a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal, and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal. The first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

In some implementations, the memory device of the system further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

In some implementations, the memory device of the system further includes a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the respective word line.

In some implementations, the memory device of the system further includes a control logic coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

In some implementations, the memory device of the system further includes a data register coupled to the charge control circuit and configured to store readout data and the comparison output signal.

According to still another aspect of the present disclosure, a method for operating a memory device, the memory device includes a selected memory cell connected between a selected bit line and a respective word line, an unselected memory cell connected between an unselected bit line and the respective word line, a first local control gate coupled to either the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method includes setting the selected bit line and the unselected bit line to an initial state, setting a first local control gate to “on” state to precharge either the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to “off” state and setting a second local control gate to “on” state at the same time such that the selected bit line and the unselected bit line reach a same voltage level, setting the second local control gate to “off” state and setting a third local control gate to “on” state at the same time to discharge the selected bit line to a second voltage, applying a read voltage via a respective word line and getting a read result, and resetting the selected bit line and the unselected bit line to the initial state.

In some implementations, the initial state is a ground state or 0 V.

In some implementations, the same voltage level is a reference voltage, and getting the read result includes determining if a selected bit line voltage is higher than the reference voltage, the selected memory cell is in a “set” state, and if the selected bit line voltage is lower than the reference voltage, the selected memory cell is in “reset” state.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a memory cell array comprising one or more memory cells connected between word lines and bit lines, wherein the one or more memory cells comprises:

a selected memory cell connected between a selected bit line and a respective word line; and

an unselected memory cell connected between an unselected bit line and the respective word line; and

a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.
The memory device of claim 1, wherein an overall time interval between each process of precharging either the selected bit line or the unselected bit line to the first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage, is less than 0.5 nanosecond (ns) .
The memory device of claim 1 or 2, wherein the charge control circuit further comprises:

a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.
The memory device of any one of claims 1-3, wherein the charge control circuit further comprises:

a first local control gate coupled to either the selected bit line or the unselected bit line and configured to control precharging either the selected bit line or the unselected bit line to the first voltage;

a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level; and

a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.
The memory device of claim 4, wherein the charge control circuit further comprising:

a first inverter configured to receive a first control signal and generate an inverted first control signal;

a second inverter configured to receive a second control signal and generate an inverted second control signal;

a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and

a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal, wherein the first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.
The memory device of any one of claims 1-5, wherein each memory cell comprises a phase-change memory (PCM) cell.
The memory device of any one of claims 1-6, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
The memory device of any one of claims 1-7, wherein the first voltage is a first negative voltage of -2 V to -4 V.
The memory device of any one of claims 1-8, wherein the second voltage is a second negative voltage of -2 V to -4 V.
The memory device of claim 3, wherein the same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit line with the selected bit line voltage of the selected bit line.
The memory device of claim 10, wherein the voltage comparator is configured to determine if the selected bit line voltage of the selected bit line is higher than the reference voltage, the selected memory cell is in a “set” state, and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a “reset” state.
The memory device of any one of claims 1-11, further comprising:

a sense amplifier coupled to the memory cell array, wherein the charge control circuit is included in the sense amplifier.
The memory device of any one of claims 1-12, further comprising:

a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the respective word line.
The memory device of claim 13, further comprising:

a control logic coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.
The memory device of claim 3, further comprising:

a data register coupled to the charge control circuit and configured to store readout data and the comparison output signal.
A system, comprising:

a memory device, comprising:

a memory cell array comprising one or more memory cells connected between word lines and bit lines, wherein the one or more memory cells comprises:

a selected memory cell connected between a selected bit line and a respective word line; and

an unselected memory cell connected between an unselected bit line and the respective word line; and

a charge control circuit coupled to the memory cell array and configured to control precharging either the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage; and

a memory controller coupled to the memory device and configured to control the memory device.
The system of claim 16, wherein an overall time interval between each process of precharging either the selected bit line or the unselected bit line to the first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage, is less than 0.5 nanosecond (ns) .
The system of claim 16 or 17, wherein the charge control circuit further comprises:

a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.
The system of any one of claims 16-18, wherein the charge control circuit further comprises:

a first local control gate coupled to either the selected bit line or the unselected bit line and configured to control precharging either the selected bit line or the unselected bit line to the first voltage;

a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level; and

a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.
The system of claim 19, wherein the charge control circuit further comprising:

a first inverter configured to receive a first control signal and generate an inverted first control signal;

a second inverter configured to receive a second control signal and generate an inverted second control signal;

a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and

a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal, wherein the first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.
The system of any one of claims 16-20, wherein each memory cell comprises a phase-change memory (PCM) cell.
The system of any one of claims 16-21, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
The system of any one of claims 16-22, wherein the first voltage is a first negative voltage of -2 V to -4 V.
The system of any one of claims 16-23, wherein the second voltage is a second negative voltage of -2 V to -4 V.
The system of claim 18, wherein the same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit line with the selected bit line voltage of the selected bit line.
The system of claim 25, wherein the voltage comparator is configured to determine if the selected bit line voltage of the selected bit line is higher than the reference voltage, the selected memory cell is in a “set” state, and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a “reset” state.
The system of any one of claims 16-26, further comprising:

a sense amplifier coupled to the memory cell array, wherein the charge control circuit is included in the sense amplifier.
The system of any one of claims 16-27, further comprising:

a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the respective word line.
The system of claim 28, further comprising:

a control logic coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.
The system of claim 18, further comprising:

a data register coupled to the charge control circuit and configured to store readout data and the comparison output signal.
A method for operating a memory device, the memory device comprising a selected memory cell connected between a selected bit line and a respective word line, an unselected memory cell connected between an unselected bit line and the respective word line, a first local control gate coupled to either the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line; and the method comprising:

setting the selected bit line and the unselected bit line to an initial state;

setting a first local control gate to “on” state to precharge either the selected bit line or the unselected bit line to a first voltage;

setting the first local control gate to “off” state and setting a second local control gate to “on” state at a same time such that the selected bit line and the unselected bit line reach a same voltage level;

setting the second local control gate to “off” state and setting a third local control gate to “on” state at a same time to discharge the selected bit line to a second voltage;

applying a read voltage via a respective word line and getting a read result; and

resetting the selected bit line and the unselected bit line to the initial state.
The method of claim 31, wherein the initial state is ground state or 0 V.
The method of claim 31 or 32, wherein the same voltage level is a reference voltage, and getting the read result comprising determining if a selected bit line voltage is higher than the reference voltage, the selected memory cell is in “set” state, and if the selected bit line voltage is lower than the reference voltage, the selected memory cell is in “reset” state.