CN215730880U

CN215730880U - Nonvolatile memory and electronic device

Info

Publication number: CN215730880U
Application number: CN202121240459.0U
Authority: CN
Inventors: 李枝勇; 耿莉荣
Original assignee: GigaDevice Semiconductor Beijing Inc; Hefei Geyi Integrated Circuit Co Ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Hefei Geyi Integrated Circuit Co Ltd
Priority date: 2021-06-03
Filing date: 2021-06-03
Publication date: 2022-02-01
Anticipated expiration: 2031-06-03

Abstract

A non-volatile memory, comprising: an array of memory cells; a plurality of word lines; a charge pump; a word line decoder electrically coupled to the charge pump and configured to control the charge pump to be electrically connected to or disconnected from the plurality of word lines; and a charge sharing module for controlling the two word lines to be electrically connected or electrically disconnected. An electronic device is also provided.

Description

Nonvolatile memory and electronic device

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a nonvolatile memory and an electronic device.

Background

NOR flash memory (NOR flash) chips and NAND flash memory (NAND flash) chips constantly charge and discharge word lines when performing operations such as reading and erasing. Both read and erase verify processes require a positive voltage to be applied to the word line. When the next word line is read or the erase verification of the current word line passes the verification of the next word line, the current word line needs to be discharged and then the next word line needs to be charged.

For example, after the read command is decoded, the NOR flash will continuously read the memory cells of multiple word lines until the chip select signal CSB is pulled high.

For another example, after one word line erase verify passes, the next word line is switched to perform erase verify. Generally, in NOR flash, the number of bit lines is thousands, that is, one word line is connected to the control gates of thousands of transistors, the load capacitance on the word line is large, and a large amount of power consumption is consumed by continuously charging and discharging the word line.

There is therefore a need to provide a solution to the problems of the prior art.

Disclosure of Invention

The invention aims to provide a nonvolatile memory and an electronic device, which can solve the problem that a large amount of power consumption is consumed by continuously charging and discharging a word line in the prior art.

To solve the above problems, the present invention provides a nonvolatile memory including: an array of memory cells; a plurality of word lines; a charge pump; a word line decoder electrically coupled to the charge pump and configured to control the charge pump to be electrically connected to or disconnected from the plurality of word lines; and a charge sharing module for controlling the two word lines to be electrically connected or electrically disconnected.

In one embodiment, the charge sharing module includes a plurality of switches, and each switch is connected between two corresponding word lines.

In an embodiment, the two word lines are adjacent word lines, and the charge sharing module includes a plurality of switches, each of the switches being connected between the corresponding adjacent two word lines.

In an embodiment, the two word lines are an ith word line and an I +1 th word line, the word line decoder disconnects the electrical connection between the charge pump and the ith word line in response to the end of the operation on the ith word line, the charge sharing module controls the ith word line and the I +1 th word line to be electrically connected, the charge sharing module disconnects the electrical connection between the ith word line and the I +1 th word line after the electrical connection between the ith word line and the I +1 th word line lasts for a predetermined time, and the word line decoder controls the electrical connection between the charge pump and the I +1 th word line to perform the operation on the I +1 th word line.

In one embodiment, the operation is a read operation.

In one embodiment, the operation is a verify operation in an erase operation.

In one embodiment, the non-volatile memory is NOR flash memory.

In an embodiment, after the verification operation in the read operation or the erase operation of one of the two word lines is finished, the word line decoder disconnects the electrical connection between the charge pump and the word line, the charge sharing module controls the two word lines to be electrically connected, the charge sharing module controls the two word lines to be electrically disconnected after the electrical connection between the two word lines is performed for a predetermined time, and the word line decoder controls the charge pump to be electrically connected to the other of the two word lines.

In order to solve the above problem, the present invention provides an electronic device including the above nonvolatile memory.

Compared with the prior art, the nonvolatile memory and the electronic device of the invention comprise the charge sharing module to realize charge sharing among the word lines, thereby reducing the time and power consumption of the charge pump for charging the word lines.

In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:

drawings

FIG. 1 shows a functional block diagram of a non-volatile memory and a host according to an embodiment of the invention.

FIG. 2 is a detailed circuit diagram of the memory cell array, word lines, bit lines, charge pump, word line decoder, and charge sharing module of FIG. 1.

FIG. 3 shows a functional block diagram of an electronic device according to an embodiment of the invention.

Detailed Description

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced.

Referring to fig. 1, fig. 1 is a functional block diagram of a nonvolatile memory 10 and a host 20 according to an embodiment of the invention.

The non-volatile memory 10 is electrically coupled to the host 20. The nonvolatile memory 10 is a built-in or external storage device of the host 20. The non-volatile memory 10 is, for example, a usb disk, a removable hard disk, a memory card, or the like. The host 20 is a user's device such as a cell phone, tablet, notebook, camera, etc. The non-volatile memory 10 may be in bi-directional data communication with the host 20. The communication standard between the nonvolatile memory 10 and the host 20 is, for example, a Serial Advanced Technology Attachment (SATA) standard, a Parallel Advanced Technology Attachment (PATA) standard, a Universal Serial Bus (USB) standard, a Secure Digital (SD) Interface standard, a multimedia memory Card (Multi Media Card, MMC) Interface standard, a Serial Peripheral Interface (SPI) standard, or the like.

The non-volatile memory 10 includes a memory cell array 100, a plurality of Word lines (Word lines) WL0-WLM, a plurality of Bit lines (Bit lines) BL0-BLN, a controller 102, a page buffer 104, a charge pump 106, a Word line decoder 108, a Bit line decoder 110, and a charge sharing module 112. The memory cell array 100 may be a two-dimensional or horizontal memory cell array, or may be a three-dimensional (3D) or vertical memory cell array.

The nonvolatile memory 10 is, for example, a NOR flash memory, a NAND flash memory, a Resistive Random Access Memory (RRAM), a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), or a spin transfer matrix random access memory (STT-RAM). The following description will be given taking an example in which the nonvolatile memory 10 is a NOR flash memory.

Fig. 2 shows an arrangement in which the memory cell array 100 is a NOR flash memory. The plurality of memory cells shown in fig. 2 is, for example, one block of the memory cell array 100. The memory cell array 100 includes (M +1) rows by (N +1) columns of memory cells. The memory cell array 100 includes a plurality of blocks, each of which is formed in a common well, for example. The memory cell may be a transistor having a floating gate or a transistor having a charge trapping layer formed of an insulating film, the transistor further including a source, a drain, and a control gate. The memory cells are addressed by the plurality of word lines WL0-WLM and the plurality of bit lines BL 0-BLN. Each row of memory cells is connected to the same word line, and specifically, the control gates of each row of memory cells are connected to the same word line. Each column of memory cells is connected to the same bit line, and specifically, the drains of each column of memory cells are connected to the same bit line. The sources of the memory cells are grounded or connected to a source line.

The controller 102 is used to decode commands, addresses or data that may be communicated by the host 20 or exchanged with the host 20, and execute instructions of the host 20 and/or access the memory cell array 100. The instructions are used to perform operations on the memory cell array 100, including at least read operations, write operations, erase verify operations, and other operations.

The page buffer 104 is used to store data read from the memory cell array 100 or data to be written to a page. The page buffer 104 is, for example, a Static Random-Access Memory (SRAM). The page buffer 104 includes a plurality of memory cells corresponding to the memory cells of one row.

The charge pump 106 is used to provide various voltages required for read operation, write operation, erase operation, and erase verify operation. For example, the charge pump 106 is used to provide a read operation voltage or a verify operation voltage in an erase operation.

The word line decoder 108 is electrically coupled to the charge pump 106 and word line WL 0-WLM. The word line decoder 108 is used for selecting at least one word line based on address information and controlling the charge pump 106 to be electrically connected or disconnected with the word lines WL 0-WLM.

The bit line decoder 110 is coupled to the bit lines BL0-BLN and is used to select at least one bit line based on address information.

The charge sharing module 112 is used for controlling electrical connection or electrical disconnection between word lines. For example, the charge sharing module 112 may control the electrical connection or disconnection of a plurality of word line pairs of word lines WL0-WLM, each word line pair including two word lines.

After the operation on one of the two word lines is finished, the word line decoder 108 disconnects the electrical connection between the charge pump 106 and the word line, the charge sharing module 112 controls the two word lines to be electrically connected to realize charge sharing between the two word lines (charge is transferred from the word line of which the operation is finished to the other word line), after the two word lines are electrically connected for a predetermined time, the charge sharing module 112 controls the two word lines to be electrically disconnected, and the word line decoder 108 controls the charge pump 106 to be electrically connected with the other word line of the two word lines. The operation may be a verify operation in a read operation or an erase operation. In some embodiments, the two word lines are adjacent two word lines.

Referring to FIG. 2, FIG. 2 shows a detailed circuit diagram of the memory cell array 100, the word lines WL0-WLM, the bit lines BL0-BLN, the charge pump 106, the word line decoder 108 and the charge sharing module 112 of FIG. 1.

The exemplary word line decoder 108 includes a plurality of switches S0-SM, the switches S0-SM corresponding to the word lines WL0-WLM, respectively, the voltage of the charge pump 106 being applied to the word line corresponding to the closed switch when one or some of the switches is closed (conductive) and the voltage of the charge pump 106 not being applied to the word line corresponding to the open switch when one or some of the switches is open (non-conductive).

The controller 102 receives an operation instruction for the memory cell array 100, an operation region of the operation instruction including a plurality of word lines. For example, the controller 102 receives a read instruction from the host 20. The read instruction corresponds to multiple rows of memory cells, i.e., the data to be read is stored in multiple rows of memory cells. Since the read operation is performed row by row, it is necessary to sequentially charge (apply a read voltage) and discharge (finish the operation) the corresponding word line. As another example, the controller 102 receives an erase command from the host 20. The erase command corresponds to a plurality of rows of memory cells, i.e., data stored in a plurality of rows of memory cells needs to be erased. The erase operation of the NOR flash memory generally includes an erase voltage applying operation, an erase verify operation, and an over-erase verify operation. The erase verify operation is to verify whether the threshold voltage of the erased memory cell is less than a predetermined upper limit value. The over-erase verify operation is to verify whether a threshold voltage of the erased memory cell is greater than a predetermined lower limit value. The erase verify operation is similar to the over-erase verify operation except that the voltage applied to the word line is different in magnitude. In the erase verify operation and the over-erase verify operation, it is also necessary that the word line is sequentially charged (an erase verify voltage or an over-erase verify voltage is applied) and discharged.

In order to reduce a large amount of power consumption consumed by the non-volatile memory 10 to continuously charge and discharge the word lines when performing various operations, the non-volatile memory 10 of the present invention is provided with the charge sharing module 112 to implement charge sharing between the word lines, thereby reducing the time and power consumption of the charge pump 106 to charge the word lines.

The charge sharing module 112 includes a plurality of switches SW0-SWM-1, each of the plurality of switches SW0-SWM-1 is used for controlling two word lines to be electrically connected or disconnected, and the switch SW0-SWM-1 is used for providing a charge sharing path.

In the present embodiment, the two word lines are adjacent two word lines, that is, the switch SW0 is connected between the word lines WL0 and WL1, the switch SW1 is connected between the word lines WL1 and WL2, and so on, the switch SWM-2 is connected between the word lines WLM-2 and WLM-1, and the switch SWM-1 is connected between the word lines WLM-1 and WLM.

In one embodiment, in response to the end of the operation (to be discharged) for the ith word line (I is an integer between 0 and M), the word line decoder 108 disconnects the charge pump 106 from the ith word line (I is an open switch SI), the charge sharing module 112 controls the ith word line to be electrically connected to the I +1 th word line (close switch SWI), thereby realizing the sharing of the charge stored on the control gate of the transistor connected to the ith word line to the control gate of the transistor connected to the I +1 th word line, after the electrical connection of the ith word line to the I +1 th word line lasts for a predetermined time, the charge sharing module 112 controls the I word line to be electrically disconnected from the I +1 th word line (open switch SWI), and the word line decoder 108 controls the charge pump 106 to be electrically connected to the I +1 th word line (close switch S (I +1)) to perform the operation for the I +1 th word line Operation of the strip word line.

Such as a read operation. The read operation of the NOR flash memory is performed for the memory cells 100 row by row. In a read operation of the NOR flash memory, a read voltage is applied to the word line of the selected row, and an off voltage (e.g., 0V) is applied to the word line of the unselected row, which makes the memory cells of the unselected row in a non-conductive state. For example, the word line decoder 108 connects the charge pump 106 to the I-th word line to perform the read operation of the memory cells in the I-th row, after the read operation of the memory cells in the I-th row is completed, the word line decoder 108 disconnects the charge pump 106 from the I-th word line, the charge sharing module 112 controls the I-th word line to be electrically connected to the I + 1-th word line (close switch SWI), the charge stored on the control gate of the transistor connected to the I-th word line is shared with the control gate of the transistor connected to the I + 1-th word line, after the electrical connection between the I-th word line and the I + 1-th word line lasts for a predetermined time, the charge sharing module 112 controls the I-th word line to be electrically disconnected from the I + 1-th word line (open switch SWI), the word line decoder 108 controls the charge pump 106 to be electrically connected to the I + 1-th word line to charge the I + 1-th word line to the read voltage, a read operation of the memory cells of row I +1 is performed. When the operation is a verify operation (an erase verify operation and an over-erase verify operation) in the erase operation, a verify voltage (an erase verify voltage and an over-erase verify voltage) is applied to the word line, and the timing of the switch is similar to that of the read operation.

The switch S0-SM between the charge pump 106 and the word lines WL0-WLM and the switch SW0-SWM-1 between the word lines WL0-WLM can realize the closing and opening of the switches in a decoding mode, and the switch SW0-SWM-1 is closed only when the WL0-WLM shares charge, so that the time and the power consumption of the charge pump 106 for charging the word lines WL0-WLM can be reduced through charge sharing.

It is noted that in the embodiment of FIG. 2, each of the switches SW0-SWM-1 is connected between two adjacent word lines. In another embodiment, each of the switches SW0-SWM-1 may be connected between two non-adjacent word lines.

Referring to fig. 3, fig. 3 is a functional block diagram of an electronic device according to an embodiment of the invention. The electronic device 30 comprises the above-mentioned non-volatile memory 10.

The nonvolatile memory and the electronic device comprise the charge sharing module to realize charge sharing among the word lines, so that the time and the power consumption of the charge pump for charging the word lines are reduced.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims

1. A non-volatile memory, wherein the non-volatile memory comprises:

an array of memory cells;

a plurality of word lines;

a charge pump;

a word line decoder electrically coupled to the charge pump and configured to control the charge pump to be electrically connected to or disconnected from the plurality of word lines; and

the charge sharing module is used for controlling the two word lines to be electrically connected or electrically disconnected.

2. The non-volatile memory according to claim 1, wherein the charge sharing module comprises a plurality of switches, each of the switches being connected between corresponding two word lines.

3. The non-volatile memory according to claim 1, wherein the two word lines are adjacent two word lines, and the charge sharing module comprises a plurality of switches, each of the switches being connected between the corresponding adjacent two word lines.

4. The non-volatile memory of claim 1, wherein the non-volatile memory is NOR flash memory.

5. An electronic device characterized by comprising the non-volatile memory according to any one of claims 1 to 4.