CN115035933A

CN115035933A - Phase change memory, operation method thereof and memory system

Info

Publication number: CN115035933A
Application number: CN202210778685.7A
Authority: CN
Inventors: 周光乐; 刘万良; 蔡旺; 邱雅琪; 杨海波; 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-09-09

Abstract

The embodiment of the invention provides an operation method of a phase change memory, the phase change memory and a memory system. The operation method comprises the following steps: performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current; wherein the first reset current is less than or greater than the second reset current.

Description

Phase change memory, operation method thereof and memory system

Technical Field

The present invention relates to the field of memory technologies, and in particular, to an operation method of a phase change memory, and a memory system.

Background

Phase change memories are memory elements that are used to store information using the conductivity or resistance difference characteristics between crystalline and amorphous states of a particular phase change material. In setting the operation of the phase change memory to switch between the crystalline and amorphous states of the phase change material, different pulses may be used to control the heating of the phase change material. At present, the used operation mode generates a relatively large surge current, and relatively serious influence is generated on the service life of the phase change memory.

Disclosure of Invention

The present invention provides a method for operating a phase change memory, a phase change memory and a memory system. By adopting the two-phase reset mode, and making the reset current provided to the phase change memory cell in the T2 phase smaller than the reset current provided to the phase change memory cell in the T3 phase, the surge current for performing the reset operation on a certain phase change memory cell of the phase change memory is reduced, thereby improving the service life of the phase change memory.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides an operation method of a phase change memory, including:

the phase change memory includes a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell; the operation method comprises the following steps:

performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current;

wherein the first reset current is less than or greater than the second reset current.

Optionally, when a peripheral circuit included in the phase change memory and used for controlling the selected memory block is disposed on a side of a lower phase change memory cell close to the selected memory block, the first reset current is smaller than the second reset current; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first reset current is greater than the second reset current.

Optionally, the first reset current and the second reset current are controlled by a current mirror coupled to a bit line of the selected memory block.

Optionally, the duration of the first reset current and the duration of the second reset current are not greater than the duration of a set current provided when the phase change memory cell is set.

Optionally, the operation method further includes:

applying a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block;

and when the first selector of the lower phase change memory unit of the selected memory block is conducted under the action of the first voltage and the second voltage, carrying out reset operation on the lower phase change memory unit of the selected memory block based on the first reset current.

Optionally, the operation method further includes:

applying a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block;

and when the second selector of the upper phase change memory unit of the selected memory block is conducted under the action of the third voltage and the fourth voltage, resetting the upper phase change memory unit of the selected memory block based on the second reset current.

Optionally, when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block, the first voltage is smaller than the third voltage; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

Optionally, when the first voltage is less than the third voltage, the operating method further includes: adjusting a ramp pulse width of the third voltage such that the ramp pulse width of the third voltage is adjusted from a first value to a second value, wherein the second value is greater than the first value;

or, when the first voltage is greater than the third voltage, the operating method further includes:

adjusting the ramp pulse width of the first voltage such that the ramp pulse width of the first voltage is adjusted from the first value by the second value.

Optionally, the first voltage and the third voltage are positive voltages; the second voltage and the fourth voltage are negative voltages.

Optionally, the operation method further includes: applying a fifth voltage to word lines coupled to phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block, and applying a sixth voltage to bit lines coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block; and under the action of the fifth voltage and the sixth voltage, enabling selectors of all unselected phase change memory cells applied to the memory array block to be in a non-conduction state.

In a second aspect, an embodiment of the present invention provides a phase change memory, including: a plurality of storage arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell;

and peripheral circuitry coupled to and for controlling the plurality of memory arrays; wherein the content of the first and second substances,

the peripheral circuitry configured to: performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current;

Optionally, the peripheral circuit includes a current mirror coupled to the bit line of the selected memory block and configured to control the first reset current and the second reset current.

Optionally, the peripheral circuit further comprises a word line driver configured to: applying a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block; applying a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block.

Optionally, when a peripheral circuit included in the phase change memory and used for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block, the first voltage is smaller than the third voltage; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

Optionally, the peripheral circuit further includes a voltage regulator configured to: when the first voltage is less than the third voltage, adjusting a ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

or when the first voltage is greater than the third voltage, adjusting the ramp pulse width of the first voltage so that the ramp pulse width of the first voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value.

Optionally, the peripheral circuit is further configured to: applying a fifth voltage to word lines coupled to phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block, and applying a sixth voltage to bit lines coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block; and under the action of the fifth voltage and the sixth voltage, enabling selectors of all unselected phase change memory cells applied to the memory array block to be in a non-conduction state.

In a third aspect, an embodiment of the present invention further provides a memory system, including: one or more of any of the phase change memories described above and a memory controller coupled to the phase change memory and configured to control the phase change memory.

The embodiment of the invention provides an operation method of a phase change memory, the phase change memory and a memory system. Wherein the phase change memory comprises a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell; the operation method comprises the following steps: performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current; wherein the first reset current is less than or greater than the second reset current. That is, different reset currents are used for two phase change memory cells in one memory block, for example, in a case where a first reset current is used for a lower phase change memory cell in a selected memory block and a second reset current larger than the first reset current is used for an upper phase change memory cell, so that an instantaneous current (a surge current plus a reset current) applied when a selector of the lower phase change memory cell is turned on is reduced, damage to the lower phase change memory cell is reduced, and the life of the phase change memory is prolonged.

Drawings

FIG. 1 is a schematic diagram of pulses in the operation of a phase change memory cell according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of threshold voltage distributions for set and reset states of a phase change memory cell according to an embodiment of the present invention;

FIG. 3 is a block diagram of an exemplary system including a memory of phase change memory cells provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of an exemplary memory including peripheral circuitry provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of an implementation of a phase change memory array 401 according to an embodiment of the present invention;

FIG. 6 is a partial three-dimensional schematic diagram of a phase change memory cell according to an embodiment of the present invention;

FIG. 7 is a partial three-dimensional schematic diagram of a phase change memory cell according to an embodiment of the present invention;

FIG. 8 is a block diagram of an exemplary memory including a memory array and peripheral circuitry provided by an embodiment of the present invention;

FIG. 9 is a circuit diagram illustrating a reset operation performed on a phase change memory cell according to an embodiment of the present invention;

FIG. 10 is a flowchart illustrating a method for operating a phase change memory according to an embodiment of the present invention;

FIG. 11 is a circuit diagram illustrating a phase change memory cell reset operation according to an embodiment of the present invention;

FIG. 12 is a timing diagram of voltage signals based on the schematic circuit diagram shown in FIG. 11 according to an embodiment of the present invention;

FIG. 13 is a graph of the current-voltage characteristics of an OTS when the selector provided by the embodiment of the present invention is an OTS;

FIG. 14 is a schematic diagram illustrating a reset current provided during a reset operation performed on a selected phase change memory cell in accordance with an embodiment of the present invention;

fig. 15 is a timing diagram of an implementation of a reset operation according to an embodiment of the present invention.

Fig. 16 is a schematic circuit diagram of a circuit structure for controlling a first reset current and a second reset current by using a current mirror according to an embodiment of the present invention.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be readily utilized without departing from the scope of the present invention. In addition, the present invention may be used in a variety of other applications. The functional and structural features as described in the present invention may be combined, adjusted and modified with each other and in a manner not specifically shown in the drawings so that the combination, adjustment and modification are within the scope of the present disclosure.

Generally, terms may be understood at least in part from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may describe a feature, structure, or combination of features in the plural, depending at least on the context. Similarly, terms such as "a," "an," or "the" may likewise be understood to convey singular or plural usage, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of other factors not necessarily expressly described, again depending at least in part on the context.

Phase Change Memory (PCM) is a non-volatile Memory device that stores data using a Phase Change material. PCMs may utilize the difference between the resistivity of the amorphous and crystalline states in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quenching of the phase change material. The phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion thereof blocking the current path) between the two phases to store data. The set state is a low resistance state of the PCM cell that may be obtained by creating a crystalline region in a chalcogenide material. Crystallization occurs when a chalcogenide material is heated at a crystallization temperature for a sufficient time. Conversely, the reset state is a high resistance state of the PCM cell, which may be obtained by creating an amorphous region in the chalcogenide material. An amorphous state may be created when a chalcogenide material is heated above its melting temperature and then rapidly quenched to form an amorphous state. Wherein, the set state may be referred to as an on state; and the reset state may be referred to as an off state.

As described above, when a phase change material in a PCM is switched between crystalline and amorphous states, different pulses (e.g., light pulses, electrical pulses) may be used to control the phase change material heating. In an alternative embodiment, as shown in fig. 1, when a long and medium-intensity programming Pulse (also referred to as Set Pulse) is applied to raise the temperature of the phase-change material layer of the phase-change memory cell below the melting temperature Tm and above the crystallization temperature Tx for a period of time and to promote crystal nucleus growth, the phase-change material layer of the phase-change memory cell can be switched from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state), which is generally referred to as a Set (Set) process or a write operation process; after applying a short and strong Reset Pulse (also referred to as Reset Pulse) to raise the temperature of the phase-change material layer of the phase-change memory cell above the melting temperature Tm, and then performing rapid Cooling (Cooling Down), the phase-change material layer of the phase-change memory cell can be transformed from a crystalline state to an amorphous state, and a process of transforming the phase-change material layer of the phase-change memory cell from a low resistance state (1 state) to a high configuration (0 state) is generally referred to as a Reset (Reset) process or an erase operation process. The Reset process and the Set process are reversible processes, and the phase change memory cell may use a crystalline state to represent a unit binary data 1 and an amorphous state to represent a binary data 0. In some embodiments, the phase change memory may include a plurality of memory arrays, and the threshold voltage distribution of the phase change memory cells included in each memory array may be as shown in fig. 2. It should be noted that there may be some differences in the threshold voltage distributions corresponding to the phase change memory cells in different memory arrays, i.e., the threshold voltage distributions counted for different numbers of phase change memory cells may have slightly different shapes but substantially similar shapes. In addition, after a very weak read pulse that does not affect the phase change material layer is applied, the resistance value of the phase change memory cell is measured to realize reading of data stored in the phase change memory cell.

Currently, in the related art, during Reset of a phase change memory cell, a relatively large Inrush Current Spike (Inrush Current Spike) is introduced by an applied Reset pulse, where the Inrush Current Spike is a main factor affecting the lifetime of the phase change memory cell. Note that the reset pulse may be a voltage or a current. The method for operating the phase change memory cell is improved based on a current pulse test system, so that the pulse used herein is a current pulse, and therefore, the pulse used in the set process or the reset process is a current pulse in the following case that is not particularly described.

In order to solve the above problem, an embodiment of the present invention provides an operation method for a phase change memory, in which different reset Current pulses are applied to phase change memory cells at different positions in the same memory block to reduce the irrush Current Spike during the reset operation, thereby prolonging the life of the phase change memory cells.

The technical scheme of the invention is explained in detail in the following with the accompanying drawings.

FIG. 3 is a block diagram of an exemplary system including a memory of phase change memory cells provided by an embodiment of the present invention. The system 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 3, system 300 may include a host 308 and a memory system 302, where memory system 302 has one or more memories 304 and a memory controller 306; the host 308 may be a Processor of an electronic device, such as a Central Processing Unit (CPU) or a System on Chip (SoC), which may be an Application Processor (AP), for example. Host 308 may be configured to send data to memory 304 or receive data from memory 304.

Specifically, Memory 304 may be any of the Memory devices disclosed in the present invention, as disclosed in detail below, Memory 304, such as Phase Change Random Access Memory (PCRAM); the memory 304 may also be referred to as a three-dimensional phase change memory.

According to some embodiments, memory controller 306 is coupled to memory 304 and host 308. And is configured to control the memory 304. Memory controller 306 may manage data stored in memory 304 and communicate with host 308. In some embodiments, memory controller 306 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) Flash drive, or other media for use in electronic devices in low duty cycle environments, such as personal computers, Digital cameras, mobile phones, and the like. In some embodiments, the memory controller 306 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia Card (eMMC), where the SSD or eMMC is used as a data storage and enterprise storage array for mobile devices in a high duty cycle environment, such as smart phones, tablet computers, laptop computers, and the like. The memory controller 306 may be configured to control operations of the memory 304, such as read, erase, and program operations. The memory controller 306 may also be configured to manage various functions with respect to data stored or to be stored in the memory 304, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 306 is also configured to process Error Correction Codes (ECCs) with respect to data read from or written to the memory 304. The memory controller 306 may also perform any other suitable functions, such as formatting the memory 304. The memory controller 306 may communicate with external devices (e.g., the host 308) according to a particular communication protocol. For example, the memory controller 306 may communicate with external devices via at least one of various Interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (Integrated Drive Electronics) protocol, a Firewire protocol, and so forth.

The memory controller 306 and the one or more memories 304 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 302 may be implemented and packaged into different types of end electronic products. In one example, the memory controller 306 and the single memory 304 may be integrated into a memory card. The memory card may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card may also include a memory card connector that couples the memory card to a host (e.g., host 308 in fig. 3). In another example, the memory controller 306 and the plurality of memories 304 may be integrated into an SSD. The SSD may also include an SSD connector to couple the SSD with a host (e.g., host 308 in fig. 3). In some embodiments, the storage capacity and/or operating speed of the SSD is greater than the storage capacity and/or operating speed of the memory card. In addition, the memory controller 306 may also be configured to control erase, read, and write operations of the memory 304.

Fig. 4 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present invention. Memory 304 may be a three-dimensional phase change memory that may include a phase change memory array 401 and peripheral circuitry 402 coupled to phase change memory array 401. Phase change memory array 401 may include word lines 4011, bit lines 4012, and phase change memory cells 4013 formed between word lines 4011 and bit lines 4012. In some embodiments, each phase change memory cell 4013 may include a PCM element (containing a phase change material, not shown) in series with a selector (not shown). In some embodiments, the phase change memory cell 4013 may comprise a DRAM cell of paired transistors and capacitors. To operate phase change memory array 401, a word line voltage (Vw) may be applied to selected word line 4011, and a bit line voltage (Vb) may be applied to selected bit line 4012.

Regarding the structure of the phase change memory array 401, in some embodiments, as shown in fig. 5, it illustrates a schematic structural diagram of an implementation manner of the phase change memory array 401 according to an embodiment of the present invention. As can be seen in FIG. 5, the phase change memory array 401 is a three-dimensional memory array comprised of a plurality of small memory array blocks having individual bit lines, word lines, and phase change memory cells. Three-dimensional phase change memories generally include a top bit line, a word line, a bottom bit line, and a memory cell located at the intersection of the bit line and the word line. In practical applications, the word lines, the top bit lines and the bottom bit lines are typically formed by a pattern of lines of constant width (L/S, Line/Space) of 20nm/20nm formed after a patterning process. Fig. 6 shows a partial three-dimensional schematic diagram of the phase change memory cell 4013 according to an embodiment of the present invention. The phase change memory cell 4013 includes: stacked PCM element 602, selector 604 and a plurality of

electrodes

601, 603 and 605. The PCM element 602 may utilize the difference between the resistivity of the amorphous (i.e., amorphous) and crystalline (i.e., crystalline) phases in the phase change material based on the electro-thermally heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material of the PCM element 602 (or at least part of the current path it blocks) between the two phases to store data. A single bit of data may be stored in each memory cell 4013, and a write operation or a read operation of the single bit may be performed by changing a voltage applied to the corresponding selector 604.

In some embodiments, the material of the PCM element 602 comprises a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the selector 604 material may comprise any suitable Ovonic Threshold Switch (OTS) material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, and the like.

Electrodes

601, 603, and 605 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of

electrodes

601, 603, and 605 comprises carbon, such as amorphous carbon.

It should be noted that the upper and lower two phase change memory cells in phase change memory array 401 may also share a word line, for example, as shown in FIG. 7.

FIG. 8 is a block diagram of an exemplary memory including a memory array and peripheral circuitry provided by an embodiment of the present invention. As shown in FIG. 8, memory 304 includes a phase change memory array 401, which has been described above, and peripheral circuitry 402. The peripheral circuit 402 includes: control logic 4021, address register 4022, voltage generator 4023, row decoder/word line driver 4024, page buffer/sense amplifier circuit 4025, column decoder/bit line driver/data latch 4026, data register/data I/O4027, among others;

page buffer/sense amplifier circuit 4025 may be configured to read data from phase change memory array 401 and program (write) data to phase change memory array 401 according to a control signal from control logic 4021. In one example, page buffer/sense amplifiers 4025 may store a page of program data (write data) to be programmed into a page of phase change memory array 401 (e.g., in fig. 4). In another example, page buffer/sense amplifier 4025 may perform a program verify operation to ensure that data has been properly programmed into the phase change memory cells 4013 coupled to the selected word line 4011. In yet another example, page buffer/sense amplifier 4025 may also sense a low power signal from selected bit line 4012 representing a data bit stored in phase change memory cell 4013 and amplify a small voltage swing to an identifiable logic level in a read operation. In some embodiments, page buffer/sense amplifier 4025 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) to a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). Column decoder/bit line driver/data latch 4026 may be configured to be controlled by control logic 4021 and to select one or more phase change memory cells 4013 and bit lines 4012. Column decoder/bit line driver/data latch 4026 may be further configured to drive a selected bit line 4012. The column decoder/bit line driver/data latch 4026 may be further configured to drive a bit line 4012 using a bit line voltage generated from the voltage generator 4023. The column decoder/bit line driver/data latch 4026 may be a temporary binary data storage for storing bits. In some embodiments, the column decoder/bit line driver/data latches 4026 may include read data latches to temporarily store read data.

Data register/data I/O416 may be coupled to page buffer/sense amplifiers 4025 and/or column decoder/bit line driver/data latches 4026 and configured to direct (route) data input from data bus 4028 to desired phase change memory cells 4013 of phase change memory array 401 and to direct (route) data output from the desired memory cells to data bus 4028.

Row decoder/word line driver 4024 may be configured to be controlled by control logic 4021 and to select one or more phase change memory cells 4013 and word line 4011 of phase change memory array 401. The row decoder/word line driver 4024 may be further configured to drive the selected word line 4011. The row decoder/word line driver 4024 may be further configured to drive the word line 4011 using the word line voltage generated from the voltage generator 4023.

Voltage generator 4023 may be configured to be controlled by control logic 4021 according to a control signal from control logic 4021, and to generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to phase change memory array 401.

The control logic 4021 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The control logic 4021 is configured to receive clock signals, command signals, address signals, and data signals from a host (e.g., 308 in fig. 3), wherein the command signals are received via a command bus 4029; the data signals are received via a data bus 4028. In some embodiments, the control Logic 4021 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller Unit (MCU)), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a state machine, gating Logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described.

FIG. 9 is a block diagram illustrating a reset operation performed on a phase change memory cell according to an embodiment of the present invention. As shown in fig. 9, once the control logic 4021 determines that the command signal is a reset command, the control logic 4021 triggers a reset operation by applying a word line voltage (Vhh) to a word line of the selected phase change memory cell through a word line driver, applying a bit line voltage (-VII) to a bit line of the selected phase change memory cell through a bit line driver, turning on a selector of the selected phase change memory cell by the word line voltage and the bit line voltage, and then supplying a current for resetting (transition to an amorphous state) to the selected phase change memory cell to perform the reset operation on the selected phase change memory cell. It should be noted that the voltages applied to the bit lines described later are all bit line voltages, and different names are selected only for distinguishing under different scenes, which does not limit the present invention. Similarly, the voltages applied to the word lines described below are all word line voltages, and different names are selected only for distinguishing under different scenarios, which is not intended to limit the present invention.

Based on the three-dimensional phase change memory, in order to solve the technical problem described above, an embodiment of the invention provides an operation method of a phase change memory, as shown in fig. 10, which illustrates a schematic structural diagram of the operation method of the phase change memory provided in the embodiment of the invention. Specifically, the phase change memory includes a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell; based on this, as shown in fig. 10, the operation method may include:

s1001: performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current; wherein the first reset current is less than or greater than the second reset current.

It should be noted that the structure of the phase change memory according to the embodiment of the present invention may be the structure shown in fig. 6 or fig. 7, that is: the lower phase change memory cell and the upper phase change memory cell share one bit line or word line.

The operation method provided by the embodiment of the invention can be understood as follows: performing a reset operation on the lower phase change memory cell based on a first reset current while performing a reset operation on the selected memory block; performing a reset operation on the upper phase change memory cell based on a second reset current; wherein the first reset current is less than the second reset current, or the second reset current is less than the first reset current.

When a peripheral circuit for controlling the selected memory block included in the phase change memory is arranged on one side of a lower phase change memory unit close to the selected memory block, the first reset current is smaller than the second reset current; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first reset current is greater than the second reset current.

It should be noted that, through research, it is found that, the closer the phase change memory cell is to the peripheral circuit, when the phase change memory cell is reset, because the loss of the voltage applied from the voltage source is smaller, and because the resistance value of the phase change memory cell in the set state is smaller, when the OTS is turned on, the generated surge current is larger, the instantaneous current flowing through the phase change memory cell is larger, that is, the influence of the surge current on the phase change memory cell closer to the peripheral circuit is larger, and at this time, in order to reduce the instantaneous current passing through the phase change memory cell when the phase change memory cell is reset, the generated current is not easy to control due to the characteristics of the OTS, and at this time, the reset current externally supplied to the phase change memory cell may be reduced, that is, the peripheral circuit included in the phase change memory and used for controlling the selected memory block is disposed at the lower portion of the selected memory block for phase change memory In one side of the memory cell, the reset current provided to the lower phase change memory cell is less than the reset current provided to the upper phase change memory cell, i.e., the first reset current is less than the second reset current. Similarly, if the peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on the side of the upper phase change memory cell close to the selected memory block, the first reset current is greater than the second reset current.

That is, when the upper and lower phase change memory cells included in the selected memory block are subjected to a reset operation, the upper and lower phase change memory cells included in the selected memory block are reset using different reset currents, e.g., in an alternative manner, providing a second reset current to an upper phase change memory cell included in the selected memory block, providing a first reset current to a lower phase change memory cell included in the selected memory block, wherein the first reset current is less than the second reset current, or the first reset current is greater than the second reset current, in this way, the transient current (surge current plus reset current) applied when the selector of the lower phase change memory cell is turned on is reduced, damage to the lower phase change memory cell is reduced, and the life of the phase change memory is improved.

Taking the example that the peripheral circuit is disposed at the side of the lower phase change memory cell close to the selected memory block, how to reduce the instantaneous current flowing through the phase change memory cell by changing the reset current of the phase change memory cell at different positions to improve the lifetime of the phase change memory cell will be described.

In the related art, as shown in fig. 11, there is shown a schematic diagram of a circuit structure for applying voltages to bit lines and word lines of a phase change memory cell; as shown in fig. 12, which shows a graph of the voltages applied to the word lines and bit lines of a phase change memory cell based on the circuit diagram of fig. 11. Wherein, in fig. 11; WL _ Driver represents a voltage source of a word line voltage applied to the word line; BL _ Driver represents a voltage source for the bit line voltage applied to the bit line; the Ireset current source represents a user-provided reset current source. V2 represents a voltage value; v1 represents a voltage value, where V2 is greater than V1. Based on this, in fig. 12, the curve corresponding to IBL represents the transient current curve for reset flowing through the selected phase change memory cell in the selected memory block; VWL represents the voltage profile applied to the word line coupled to the selected phase change memory cell; the curve corresponding to VBL represents the curve of the voltage applied to the bit line coupled to the selected phase change memory cell, which may be provided by the bit line driver BL _ driver through the corresponding select transistor; the curve corresponding to BL _ driver represents the curve of the voltage applied to the bit line driver; the curve corresponding to Ireset is the reset current curve provided by the user.

It should be noted that, in fig. 12, the stage T2 corresponds to a process of performing a reset operation on the lower phase change memory cell of the selected memory block; phase T3 is a process of performing a reset operation on the upper phase change memory cells of the selected memory block. During the reset operation, whether in the T2 phase or the T3 phase of the reset operation, the transient current IBL for reset flowing through the selected phase change memory cell includes two parts, one part is user-supplied Ireset and the other part is inrush current induced by sudden change of the applied voltage, wherein the peak value of the inrush current is relatively large and has a serious influence on the life of the phase change memory cell.

Specifically, based on the foregoing description of the structure of the phase change memory cell, the phase change memory cell includes a PCM element 602 and a selector 604, wherein the selector 604 is an OTS, which is an ovonic threshold switch having a current-voltage characteristic as shown in fig. 13. Based on this, when a reset operation is performed on the phase change memory cell, once a voltage difference between a word line voltage applied to a word line coupled to the selected phase change memory cell and a bit line voltage applied to a bit line coupled to the selected phase change memory cell is greater than a threshold voltage Vt of the OTS, a voltage across the OTS may instantaneously drop from Vt to a holding voltage Vhold thereof, which induces a relatively large inrush current to flow through the selected phase change memory cell due to the abrupt voltage change. Due to the characteristics of the OTS device, the magnitude of the inrush current induced by the OTS device is uncontrollable, and due to the sum of Ireset provided by a user by the current flowing through the selected phase change memory cell and the inrush current induced based on the voltage change on the OTS device, then, in order to reduce the maximum peak value of the instantaneous current flowing through the selected phase change memory cell, a reset current provided by the user may be used, that is: less user-supplied reset current to reduce the instantaneous current flowing entirely through the phase change memory cell. And because the peripheral circuit is relatively close to the lower phase change memory unit of the selected memory block, the influence on the lower phase change memory unit is relatively large during the reset operation, so that when the reset operation is carried out on the selected memory block, the reset current adopted when the reset is carried out on the lower phase change memory unit can be only reduced, and the reset time of the whole selected memory block is ensured not to be overlong. That is, during the entire reset operation, the same Ireset is used for the T2 phase and the T3 phase, and the first reset current is used for the T2 phase and the second reset current is used for the T3 phase, wherein the first reset current is smaller than the second reset current. That is, by lowering the user-supplied Ireset during the T2 phase, the maximum peak value of the instantaneous current flowing through the selected phase change memory cell during the T2 phase of the reset operation is reduced, thereby improving the lifetime of the phase change memory cell.

That is, the embodiment of the present invention provides a reset operation of a phase change memory cell, as shown in fig. 14, Ireset is a reset current provided by a user, where Ireset1 is a first reset current; ireset2 is the second reset current. By means of the arrangement, based on the superposition characteristic of the current, the instantaneous current flowing through the selected phase change memory cell in the T2 phase can be rapidly reduced by reducing Ireset provided by a user in the T2 phase, so that the peak value of the instantaneous current flowing through the selected phase change memory cell in the T2 phase of the reset operation can be reduced, damage to the selected phase change memory cell is reduced, and the service life of the phase change memory cell is prolonged; and may also accelerate the stabilization of the current flowing through the selected phase change memory cell during phase T2, thereby reducing the reset time for the phase change memory.

Based on the operation method provided in the embodiment of the present invention, an alternative implementation manner is shown in fig. 15, which illustrates an implementation timing chart of the reset operation provided in the embodiment of the present invention. Wherein, the curve corresponding to the IBL represents the current curve for resetting flowing through the selected phase change memory unit; VWL represents the voltage profile applied to the word line coupled to the selected phase change memory cell; the curve corresponding to VBL represents the curve of the voltage applied to the bit line coupled to the selected phase change memory cell, which may be provided by the bit line driver BL _ driver through the corresponding select transistor; the curve corresponding to BL _ driver represents the curve of the voltage applied to the bit line driver. The curve corresponding to I1 is Ireset1 shown in fig. 14, i.e., the first reset current; the curve corresponding to Ireset is the reset current curve provided by the user, i.e. the second reset current. That is, in the timing chart provided in fig. 15, in the period T2, the first reset current supplied by the user is smaller than before; during the T3 phase, the second reset current supplied by the user is unchanged, so that the first reset current is less than the second reset current to reduce the current through the selected phase change memory cell for resetting during the T2 phase.

In some embodiments, the duration of the first reset current and the duration of the second reset current may be set according to practical situations, and there is no particular relationship between the duration of the first reset current and the duration of the second reset current, but the duration of the first reset current and the duration of the second reset current are on an order of magnitude, that is, the duration of the first reset current and the duration of the second reset current are similar.

In some embodiments, the duration of the first reset current and the second reset current is not greater than the duration of a set current provided when setting the selected phase change memory cell.

It should be noted that, based on the time relationship diagram of the set process and the reset process described in fig. 1, the duration of the reset process should be shorter than the duration of the set process, that is, the durations of the first reset current and the second reset current are both shorter than the duration of the set current provided when setting the selected phase change memory cell.

In some embodiments, the first and second reset currents are controlled by a current mirror coupled on bit lines of the selected memory block.

Here, the first reset current and the second reset current magnitudes may be controlled by a current mirror coupled to a bit line of the selected memory block.

As an implementation manner, as shown in fig. 16, a schematic diagram of a circuit structure that uses a current mirror to control the first reset current and the second reset current is shown. In fig. 16, the other structure is the same as that in fig. 11, except that the Ireset current source in fig. 11 is implemented by using a current mirror in fig. 16, so that the magnitude of the reset current provided by the user in the stage T2 or the stage T3 is controlled by the current mirror. It should be noted that this is merely an exemplary illustration, and the parameters and structure of a specific current mirror can be designed according to specific requirements, and the specific structure is not limited herein.

According to the foregoing description, when performing a reset operation on a phase change memory cell, it is necessary to turn on a selector of the phase change memory cell, and therefore, in some embodiments, the operating method further includes:

In other embodiments, the method of operation further comprises:

It should be noted that, according to the structure of the phase change memory cell shown in fig. 6 and 7, the upper phase change memory cell and the lower phase change memory cell may share one word line or bit line, and thus, the first word line and the second word line presented here may be the same word line, or the first bit line or the second bit line may be the same bit line.

In some embodiments, the first voltage is less than the third voltage when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed at a side of a lower phase change memory cell adjacent to the selected memory block; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

It should be noted that phase change memory cells that are remote from the peripheral circuitry may require a higher voltage to ensure that the voltage applied to the phase change memory cell is able to turn on the selector. Therefore, in the phase change memory array structure shown in fig. 6, the peripheral circuit is close to the side, and the voltage applied to the word line coupled to the phase change memory cell on the side can be smaller, for example, when the peripheral circuit is close to the lower phase change memory cell of the selected memory block, the first voltage applied to the first word line coupled to the lower phase change memory cell can be smaller than the third voltage applied to the second word line coupled to the upper phase change memory cell. On the contrary, when the peripheral circuit is close to one side of the upper phase change memory unit, the first voltage is larger than the third voltage.

Based on this, since the selected phase change memory cell is in the set state during the reset operation, at which the resistance value of the selected phase change memory cell is in the low resistance state, the first voltage on the word line rises to the T3 stage from the T2 stage, and the second voltage on the word line rises, at which the current flowing through the selected phase change memory cell is relatively large for a short time based on the change from the first voltage to the third voltage, and thus, in order to reduce the peak value of this current, in some embodiments, when the first voltage is less than the third voltage, the operation method further includes: adjusting a ramp pulse width of the third voltage such that the ramp pulse width of the third voltage is adjusted from a first value to a second value, wherein the second value is greater than the first value;

adjusting the ramp pulse width of the first voltage such that the ramp pulse width of the first voltage is adjusted from the first value to the second value.

For example, assuming that the first voltage is smaller than the third voltage, the above adjustment is specifically shown in fig. 13 and fig. 15, in fig. 13, it is assumed that the ramp pulse width of the third voltage is the first value; assuming that the ramp pulse width of the third voltage is the second value in fig. 15, compared to the period T3 shown in fig. 13, since the time required for the voltage to rise from the first voltage to the third voltage is relatively long, that is, the time for the voltage to change is relatively long, the instantaneous current flowing through the selected phase change memory cell is reduced, and the damage to the phase change memory cell is reduced, thereby increasing the lifetime of the phase change memory cell.

In some embodiments, the first voltage and the third voltage are positive voltages; the second voltage and the fourth voltage are negative voltages.

In some embodiments, the method of operation further comprises:

applying a fifth voltage to word lines coupled to phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block, and applying a sixth voltage to bit lines coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block as the selected memory block; and under the action of the fifth voltage and the sixth voltage, enabling selectors of all unselected phase change memory cells applied to the memory array block to be in a non-conduction state.

It should be noted that, here, it is described that the reset operation is performed only on the selected phase change memory cell, a fifth voltage and a sixth voltage are applied to the word lines of the unselected phase change memory cells in the same memory array block, and under the action of the fifth voltage and the sixth voltage, the threshold voltage of the selector of the phase change memory cell which is not selected is applied to the voltage difference between the bit lines and the word lines corresponding to all the unselected phase change memory cells in the memory array block, but is not turned on, so that the reset operation is not performed on the unselected phase change memory cells.

In the phase change memory operating method provided by the embodiment of the invention, the first reset current adopted in the T2 stage is smaller than the second reset current adopted in the T3 stage in the two-stage reset operation, so that the instantaneous maximum value of the current flowing through the phase change memory unit in the T2 stage is reduced, and the service life of the phase change memory is prolonged.

Based on the same inventive concept, the embodiment of the invention also provides a phase change memory, which comprises a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell;

and peripheral circuitry coupled to and for controlling the plurality of memory arrays; wherein, the first and the second end of the pipe are connected with each other,

In some embodiments, the peripheral circuit includes a current mirror coupled to bit lines of the selected memory block and configured to control the first reset current and the second reset current.

In some embodiments, the peripheral circuitry further comprises a word line driver configured to: applying a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block; applying a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block.

In some embodiments, the peripheral circuit further comprises a voltage regulator configured to: when the first voltage is less than the third voltage, adjusting a ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

It should be noted that the voltage regulator is any circuit structure that can be used to adjust the ramp pulse width of the third voltage or the first voltage.

In some embodiments, the peripheral circuitry is further configured to: applying a fifth voltage to word lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block, and applying a fifth voltage to bit lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block, of the selected memory block; and under the action of the fifth voltage and the sixth voltage, enabling selectors of all unselected phase change memory cells applied to the memory array block to be in a non-conduction state.

It should be noted that the phase change memory and the operation method are the same inventive concept, and the terms and operations presented herein have been described in detail in the foregoing, and are not repeated herein.

Based on the same inventive concept, an embodiment of the present invention further provides a memory system, including: one or more of the phase change memories of any of the preceding claims and a memory controller coupled to the phase change memory and configured to control the phase change memory.

In some embodiments, the peripheral circuitry is configured to: performing a reset operation on a selected phase change memory cell in the phase change memory in response to a received reset instruction, wherein the reset operation includes: performing a reset operation on a lower phase change memory cell of a selected memory block among the plurality of memory blocks based on a first reset current while resetting the selected memory block; performing a reset operation on an upper phase change memory cell of the selected memory block based on a second reset current;

In some embodiments, the peripheral circuit includes a current mirror coupled to a bit line of the selected memory block for controlling the first reset current and the second reset current.

In some embodiments, the first voltage is less than the third voltage when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

In some embodiments, the peripheral circuit further comprises a voltage regulator configured to: when the first voltage is lower than the third voltage, adjusting the slope pulse width of the third voltage, so that the slope pulse width of the third voltage is adjusted from a first value to a second value;

Here, the reset instruction is transmitted to the peripheral circuit by the memory controller through a communication interface connected to the peripheral circuit, so that the peripheral circuit performs a reset operation on the selected phase change memory cell in the phase change memory in response to the received reset instruction.

The memory system, the operation method and the phase change memory belong to the same inventive concept, and the terms and operations presented herein have been described in detail and are not repeated herein.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. The operating method of a phase change memory is characterized in that the phase change memory comprises a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell; the operation method comprises the following steps:

2. The operating method according to claim 1, wherein the first reset current is smaller than the second reset current when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first reset current is greater than the second reset current.

3. The method of claim 1, wherein the first and second reset currents are controlled by a current mirror coupled to a bit line of the selected memory block.

4. The method of claim 1, wherein a duration of the first reset current and the second reset current is no greater than a duration of a set current provided when setting the phase change memory cell.

5. The method of operation of claim 1, further comprising:

6. The method of operation of claim 5, further comprising:

and when the second selector of the upper phase change memory unit of the selected memory block is conducted under the action of the third voltage and the fourth voltage, carrying out reset operation on the upper phase change memory unit of the selected memory block based on the second reset current.

7. The operating method according to claim 6, wherein the first voltage is smaller than the third voltage when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

8. The method of operation of claim 7, wherein when the first voltage is less than the third voltage, the method of operation further comprises: adjusting a ramp pulse width of the third voltage such that the ramp pulse width of the third voltage is adjusted from a first value to a second value, wherein the second value is greater than the first value;

9. The operating method according to claim 6, wherein the first voltage and the third voltage are positive voltages; the second voltage and the fourth voltage are negative voltages.

10. The method of operation of claim 1, further comprising:

applying a fifth voltage to word lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block, and applying a sixth voltage to bit lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block; and under the action of the fifth voltage and the sixth voltage, enabling selectors of all unselected phase change memory cells applied to the memory array block to be in a non-conduction state.

11. A phase change memory, comprising: a plurality of storage arrays; each memory array includes a plurality of memory blocks, each memory block including a lower phase change memory cell and an upper memory cell;

12. The phase change memory of claim 11, wherein the peripheral circuit comprises a current mirror coupled to the bit line of the selected memory block configured to control the first reset current and the second reset current.

13. The phase change memory of claim 12, wherein the peripheral circuitry further comprises a word line driver configured to: applying a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block; applying a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block.

14. The phase change memory according to claim 13, wherein the first voltage is smaller than the third voltage when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of a lower phase change memory cell adjacent to the selected memory block; when a peripheral circuit included in the phase change memory for controlling the selected memory block is disposed on a side of an upper phase change memory cell adjacent to the selected memory block, the first voltage is greater than the third voltage.

15. The phase change memory of claim 14, wherein the peripheral circuit further comprises a voltage regulator configured to: when the first voltage is less than the third voltage, adjusting a ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

16. The phase change memory of claim 11, wherein the peripheral circuitry is further configured to: applying a fifth voltage to word lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block, and applying a sixth voltage to bit lines of the phase change memory, which are coupled to the phase change memory cells included in all unselected memory blocks of the phase change memory, which belong to the same memory array block; under the action of the fifth voltage and the sixth voltage, selectors of all unselected phase change memory cells of the memory array block are enabled to be in a non-conducting state.

17. A memory system, comprising: one or more of the phase change memory of any of claims 11-16 and a memory controller coupled to the phase change memory and configured to control the phase change memory.