WO2020093266A1

WO2020093266A1 - Wafer, intelligent processor and electrical equipment

Info

Publication number: WO2020093266A1
Application number: PCT/CN2018/114356
Authority: WO
Inventors: 杨帅; 郭函
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-11-07
Filing date: 2018-11-07
Publication date: 2020-05-14

Abstract

A wafer (10), an intelligent processor and electrical equipment. The wafer (10) is provided thereon with a first power supply zone (101). The first power supply zone (101) comprises a plurality of first bonding pads (1011) and a plurality of second bonding pads (1012). The first bonding pads (1011) in the first power supply zone (101) are connected in parallel, the second bonding pads (1012) in the first power supply zone (101) are connected in parallel, the first bonding pads (1011) in the first power supply zone (101) serve as a power input end of the first power supply zone (101), and the second bonding pads (1012) in the first power supply zone (101) serve as a grounding end of the first power supply zone (101), so that the first bonding pads (1011) in the first power supply zone (101) can be connected to a power supply by means of one or more first solder balls on a substrate (20), and the second bonding pads (1012) in the first power supply zone can be grounded by means of one or more second solder balls. The number of the first solder balls and the number of the second solder balls are less than the number of all the bonding pads in the first power supply zone (101). Compared with the mode that each bonding pad in the first power supply zone (101) is correspondingly provided with one solder ball, the number of the solder balls on the substrate (20) is reduced, the structure of the substrate (20) is simplified, and the production cost is reduced.

Description

Wafers, intelligent processors and electrical equipment

Technical field

This application relates to the field of electrical equipment, for example, to a wafer, intelligent processor and electrical equipment.

Background technique

A circuit board and an intelligent processor installed on the circuit board are provided in the electrical equipment, and the intelligent processor is electrically connected to the circuit on the circuit board.

In the prior art, an intelligent processor includes a wafer and a substrate. The wafer has a first power supply area and a second power supply area spaced apart. Each of the first power supply area and the second power supply area has a plurality of pads, and each A pad is electrically connected to a solder ball on the substrate; the substrate is connected to the circuit board, and the solder ball on the substrate is electrically connected to the circuit on the circuit board to realize the connection between the intelligent processor and the circuit board.

However, there are more pads on the wafer, which results in more solder balls connected to the pads on the substrate, resulting in a higher production cost of the intelligent processor.

Summary of the invention

An embodiment of the present disclosure provides a wafer having a first power supply area on the wafer, the first power supply area including a plurality of first pads and a plurality of second pads; the first power supply area The first pad of the first power supply area is connected in parallel, and the second pad of the first power supply area is connected in parallel, and the first pad in the first power supply area is used as a power input end of the first power supply area to supply power for the first The internal components of the area supply power; the second pad in the first power supply area serves as the ground terminal of the first power supply area.

As described above, preferably, the wafer has a second power supply area spaced apart from the first power supply area, the second power supply area includes a plurality of second pads and third pads, The second pads in the second power supply area are connected in parallel, and the third pads in the second power supply area are connected in parallel; and the second pads in the second power supply area are used as the power input end of the second power supply area To supply power to the internal components of the second power supply area; the third pad in the second power supply area serves as the ground terminal of the second power supply area.

In the wafer as described above, preferably, the second pad in the first power supply area is connected to the second pad in the second power supply area.

For the wafer as described above, preferably, the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area, and the third power supply The area includes a plurality of third pads and a plurality of fourth pads;

The third pads in the third power supply area are connected in parallel, and the fourth pads in the third power supply area are connected in parallel; and the third pad in the third power supply area serves as the power input end of the third power supply area To supply power to the internal components of the third power supply area; the fourth pad in the third power supply area serves as the ground terminal of the third power supply area.

In the wafer as described above, preferably, the third pad in the third power supply area is connected to the third pad in the second power supply area.

For the wafer as described above, preferably, the internal components of the first power supply area, the second power supply area, and the third power supply area include multiple computing cores.

An embodiment of the present disclosure also provides an intelligent processor, including: a substrate and a wafer mounted on the substrate;

The wafer has a first power supply area, the first power supply area includes a plurality of first pads and a plurality of second pads; the first pads in the first power supply area are connected in parallel, the first The second pads in the power supply area are connected in parallel, and the first pads in the first power supply area are used as the power input end of the first power supply area to supply power to the internal components of the first power supply area; the first power supply The second pad in the area serves as the ground terminal of the first power supply area.

In the smart processor as described above, preferably, the wafer has a second power supply area spaced apart from the first power supply area, and the second power supply area includes a plurality of second pads and third pads , The second pads in the second power supply area are connected in parallel, and the third pads in the second power supply area are connected in parallel; and the second pads in the second power supply area are used as the power input of the second power supply area Terminal to power the internal components of the second power supply area; the third pad in the second power supply area serves as the ground terminal of the second power supply area.

In the smart processor as described above, preferably, the second pad in the first power supply area is connected to the second pad in the second power supply area.

In the smart processor as described above, preferably, the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area. The power supply area includes multiple third pads and multiple fourth pads;

In the smart processor as described above, preferably, the third pad in the third power supply area is connected to the third pad in the second power supply area.

In the above intelligent processor, preferably, the internal components of the first power supply area, the second power supply area, and the third power supply area include multiple computing cores.

In the smart processor as described above, preferably, a first circuit is provided on the substrate, and the second pad in the first power supply area and the second pad in the second power supply area pass through the first One circuit connection.

In the smart processor as described above, preferably, a second circuit is further provided on the substrate, and the third pad in the second power supply area and the third pad in the third power supply area pass through the Second circuit connection.

The smart processor as described above, preferably, the smart processor further includes a packaging cover, the wafer is provided on a mounting surface of the substrate, the packaging cover is provided on the wafer, and the The mounting surface is connected.

In the above intelligent processor, preferably, the packaging cover is a plastic cover, a ceramic cover or a metal cover.

As described above, the intelligent processor is preferably a chip.

An embodiment of the present disclosure also provides an electrical device, including: the intelligent processor as described above.

In the wafer, the intelligent processor and the electrical equipment provided by the embodiments of the present disclosure, by connecting the first pads in the first power supply area in parallel and the second pads in the first power supply area in parallel, the first One pad can be connected to the power supply through one or several first solder balls on the substrate, and the second pad of the first power supply area can be grounded through one or several second solder balls, so that the first solder balls and the second solder balls The number is less than the number of all pads in the first power supply area; compared with a solder ball corresponding to each pad in the first power supply area, the number of solder balls on the substrate is reduced, thereby simplifying the substrate The structure reduces the production cost.

BRIEF DESCRIPTION

One or more embodiments are exemplified by the corresponding drawings. These exemplary descriptions and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

1 is a schematic structural diagram of an intelligent processor provided by this embodiment;

FIG. 2 is a schematic structural diagram of a wafer provided by this embodiment.

Description of reference signs:

10. Wafer;

20. Substrate;

30. Encapsulation cover;

101. The first power supply area;

102. The second power supply area;

103. The third power supply area;

1011, the first pad in the first power supply area;

1012. The second pad in the first power supply area;

1021, the second pad in the second power supply area;

1022, the third pad in the second power supply area;

1031, the third pad in the third power supply area;

1032. The fourth pad in the third power supply area.

detailed description

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the following describes the implementation of the embodiments of the present disclosure in detail with reference to the drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, various details are provided to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, to simplify the drawings, well-known structures and devices can be simplified.

Example 1

Please refer to Figure 2. This embodiment provides a wafer 10 having a first power supply area 101 on the wafer 10, the first power supply area 101 includes a plurality of first pads and a plurality of second pads; the first solder in the first power supply area The disks 1011 are connected in parallel, the second pads 1012 in the first power supply area are connected in parallel, and the first pads 1011 in the first power supply area serve as the power input end of the first power supply area 101, and the second pads in the first power supply area 1012 serves as the ground terminal of the first power supply area.

In this embodiment, the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area may be metal sheets disposed on the wafer 10.

In this embodiment, the first pad 1011 in the first power supply area is used as a power input terminal, and the first pad 1011 in the first power supply area can be connected to the power supply to the first pad 1011 in the first power supply area Provide a higher potential. The second pad 1012 in the first power supply area as the ground terminal may be that the potential of the second pad 1012 in the first power supply area is zero, and of course the second pad 1012 in the first power supply area may not be zero , As long as the second pad 1012 in the first power supply area has a certain reference potential, so that there is a certain voltage between the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area can.

As shown in FIG. 2, in this embodiment, the first power supply area 101 includes a plurality of first pads and a plurality of second pads, and the first pads 1011 in the plurality of first power supply areas are arranged in parallel to each other. In the first vertical column, the second pads 1021 in the plurality of first power supply regions are arranged in parallel to each other, and the first vertical column and the second vertical column are alternately arranged. In an implementation, the first pads 1011 in each first power supply area may be connected in parallel for each first vertical column of the first pad. Correspondingly, the second pads 1012 in the first power supply area may be connected in parallel The second pads of each second vertical column are connected in parallel. In other implementation manners, the parallel connection of the first pads 1011 in the first power supply area may be parallel to all the first vertical pads. Correspondingly, the parallel connection of the second pads 1012 in the first power supply area may be all The second pads of the second vertical column are connected in parallel.

In this embodiment, the first pad 1011 in the first power supply area may be connected in parallel through the first connection metal layer with a certain pattern on the wafer 10, and similarly, the second pad 1012 in the first power supply area may be The second connecting metal layer with a certain pattern on the wafer 10 is connected in parallel.

The wafer 10 in this embodiment is provided on the mounting surface of the substrate, and the first solder ball and the second solder ball are provided on the bonding surface of the substrate opposite to the mounting surface, and the first pad in the first power supply area 1011 is connected to the power source through the first solder ball, and the second pad 1012 in the first power supply area is grounded through the second solder ball.

In the smart processor provided in this embodiment, by connecting the first pad 1011 in the first power supply area in parallel and the second pad 1012 in the first power supply area in parallel, the first pad 1011 in the first power supply area can pass through One or several first solder balls on the substrate are connected to the power supply, and the second pad 1012 of the first power supply area may be grounded through one or several second solder balls, so that the number of first solder balls and second solder balls is less than The number of all pads in the first power supply area 101; compared with each solder pad in the first power supply area 101, the number of solder balls on the substrate is reduced, thereby simplifying the structure of the substrate 20 , Reducing production costs.

In this embodiment, the wafer 10 has a second power supply area 102 spaced apart from the first power supply area 101. The second power supply area 102 includes a plurality of second pads and a third pad. The two pads 1021 are connected in parallel, and the third pads 1022 in the second power supply area are connected in parallel; and the second pads 1021 in the second power supply area serve as the power input end of the second power supply area 102 to be the internal components of the second power supply area Power supply; the third pad 1022 in the second power supply area serves as the ground terminal of the second power supply area 102.

Further, the second pads 1021 in the plurality of second power supply areas are arranged in parallel third columns, and the third pads 1022 in the second power supply areas are arranged in parallel fourth positions. The vertical column, the third vertical column and the fourth vertical column are alternately arranged.

In a possible implementation manner, the second pads 1021 in each second power supply area may be connected in parallel for each second vertical pad, and correspondingly, the third pads 1022 in the second power supply area may be connected in parallel The third pads of each fourth vertical column may be connected in parallel. In other implementation manners, the parallel connection of the second pads 1021 in each second power supply area may be parallel of all second vertical second pads. Correspondingly, the parallel connection of the third pads 1022 in the second power supply area may be All third pads 1022 in the second vertical column are connected in parallel.

In this embodiment, the second pad 1021 in the second power supply area may be connected in parallel through a third connection metal layer with a certain pattern on the wafer 10, and similarly, the third pad 1022 in the second power supply area may be The fourth connection metal layer with a certain pattern on the wafer 10 is connected in parallel.

Further, the second pad 1012 in the first power supply area is connected to the second pad 1021 in the second power supply area. Only the first pad 1011 in the first power supply area and the second pad 1022 in the second power supply area can supply power to the first power supply area 101 and the second power supply area 102, so as to further reduce the installation on the substrate 20 Number of solder balls.

In this embodiment, the wafer 10 further includes a third power supply area 103, which is spaced apart from the first power supply area 101 and the second power supply area 102. The third power supply area 103 includes a plurality of third pads and A plurality of fourth pads; the third pad 1031 in the third power supply area is connected in parallel, and the fourth pad 1032 in the third power supply area is connected in parallel; and the third pad 1031 in the third power supply area serves as the third power supply area The power input terminal of 103 is used to supply power to the internal components of the third power supply area; the fourth pad 1032 in the third power supply area serves as the ground terminal of the third power supply area 103.

Further, the third pads 1031 in the plurality of third power supply areas are arranged in a plurality of fifth vertical columns parallel to each other, and the fourth pads 1032 in the plurality of third power supply areas are arranged in a plurality of parallel sixth numbers. Vertical columns, fifth vertical columns and sixth vertical columns are alternately arranged.

In this embodiment, the third pad 1031 in the third power supply area may be connected in parallel through the fifth connecting metal layer with a certain pattern on the wafer 10, and similarly, the fourth pad 1032 in the third power supply area may be The sixth connection metal layer with a certain pattern on the wafer 10 is connected in parallel.

Further, the third pad 1031 in the third power supply area is connected to the third pad 1022 in the second power supply area. It is only necessary to supply power to the first power supply area 101, the second power supply area 102, and the third power supply area 103 through the first pad 1011 in the first power supply area and the fourth pad 1032 in the third power supply area, to The number of solder balls provided on the substrate 20 is further reduced.

In this embodiment, the internal components in the first power supply area, the internal components in the second power supply area, and the internal components in the third power supply include multiple computing cores. In this embodiment, the calculation core is provided on the wafer 10 and has a certain logical structure. The calculation core is used for data processing, calculation, and other operations.

The wafer 10 in this embodiment may also have four power supply areas, five power supply areas, etc .; correspondingly, each power supply area has an internal component and a pad connected to the internal component. The disk as the power input end of the power supply area is connected to a pad of the previous power supply area, and the other pad of the power supply area is connected to a pad of the next power supply area as the ground terminal of the power supply area, that is, each The internal components in the power supply area are connected in series, so that only the first pad 1011 in the first power supply area is used as the power input terminal, and the last pad in the last power supply area is used as the ground terminal. The internal parts are powered.

Example 2

FIG. 1 is a schematic structural diagram of an intelligent processor provided in this embodiment. Please refer to Figure 1 and Figure 2.

This embodiment provides an intelligent processor, including: a substrate 20 and a wafer 10 mounted on a substrate 02; wherein the structure of the wafer 10 is substantially the same as that of the above-mentioned wafer 10, which will not be repeated here.

In this embodiment, a first circuit is provided on the substrate 20, and the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area are connected by the first circuit. The first circuit on the substrate 20 realizes the connection between the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area, which can avoid crystals caused by placing more metal pieces on the wafer 10 Circle 10 is difficult to process.

Further, a second circuit is further provided on the substrate 20, and the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area are connected by a second circuit. The connection between the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be achieved by the second circuit on the substrate 20, which can further avoid placing more metal on the wafer 10 The wafer 10 is difficult to process due to the wafer.

Further, the first circuit connects the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area, and connects all the second pads 1012 in the first power supply area and all the first The second pads 1021 in the second power supply area are connected in parallel; similarly, the second circuit connects the third pads 1022 in the second power supply area and the third pads 1031 in the third power supply area The third pads 1022 in the power supply area and the third pads 1031 in all third power supply areas are connected in parallel.

In this embodiment, the substrate 20 may include at least two metal plates and an insulating plate between two adjacent metal plates, and the corresponding first circuit and second circuit may be formed on the same metal plate; of course, in order to avoid the same metal plate The circuit pattern on the above is relatively complicated, and the first circuit and the second circuit can be located on different metal layers.

Exemplarily, the first circuit and the second circuit may be both provided on the metal plate of the substrate 20 near the mounting surface, or the first circuit and the second circuit are both provided on the metal plate of the substrate 20 near the bonding surface. When there are more than two metal plates on the substrate 20, the first circuit is provided on the metal plate close to the mounting surface, and the second circuit is provided on the metal between the metal plate close to the mounting surface and the metal plate close to the bonding surface Board; or the first circuit is set on the metal plate near the bonding surface, and the second circuit is set on the metal plate between the metal plate near the mounting surface and the metal plate near the bonding surface; or the second circuit is set On the metal plate close to the mounting surface, and the first circuit is set on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface; or the second circuit is set on the metal plate close to the bonding surface And the first circuit is provided on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface. When there are more than three metal plates on the substrate 20, both the first circuit and the second circuit may be disposed between the metal plate near the mounting surface and the metal plate near the bonding surface, and the first circuit and the second circuit are located Different metal plates.

The first circuit and the second circuit in this embodiment are metal plates with certain patterns formed by patterning the metal plates. When the first circuit is located on the metal plate close to the mounting surface, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be directly connected to the first circuit when the first circuit is located On other metal plates, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be connected to the first circuit through the via; similarly, when the second circuit is located close to the installation On the metal plate on the surface, the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be directly connected to the second circuit. When the second circuit is located on another metal plate, The third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area may be connected to the second circuit through a via.

In this embodiment, the intelligent processor further includes a packaging cover 30, the wafer 10 is disposed on the mounting surface of the substrate 20, the packaging cover 30 is disposed on the wafer 10, and is connected to the mounting surface. The encapsulation cover 30 can seal the wafer 10, and at the same time, the encapsulation cover 30 can also protect the wafer 10 to prevent damage to the wafer 10 caused by contact of external objects with the wafer 10.

Further, the package cover 30 is a plastic cover, a ceramic cover or a metal cover.

The intelligent processor in this embodiment is a chip.

In other embodiments, an electrical device is also provided, including: the intelligent processor as described above.

When used in this application, although the terms "first", "second", etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element" are consistently renamed and all occurrences of The "second component" can be renamed consistently. The first element and the second element are both elements, but they may not be the same element.

In addition, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no excessively detailed details are required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed according to these embodiments are provided separately to add context and help to understand the described embodiments. The above description is not intended to be without omission or to limit the described embodiments to the precise form of this disclosure. Based on the above teachings, several modifications, choices and changes are possible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

A wafer, characterized in that the wafer has a first power supply area, the first power supply area includes a plurality of first pads and a plurality of second pads; One pad is connected in parallel, the second pad in the first power supply area is connected in parallel, and the first pad in the first power supply area is used as the power input end of the first power supply area to The internal components supply power; the second pad in the first power supply area serves as the grounding terminal of the first power supply area.
The wafer according to claim 1, wherein the wafer has a second power supply area spaced apart from the first power supply area, and the second power supply area includes a plurality of second pads and first Three pads, the second pad in the second power supply area is connected in parallel, and the third pad in the second power supply area is connected in parallel; and the second pad in the second power supply area is used as the second power supply area The power input terminal of the power supply for powering the internal components of the second power supply area; the third pad in the second power supply area serves as the ground terminal of the second power supply area.
The wafer according to claim 2, wherein the second pad in the first power supply area is connected to the second pad in the second power supply area.
The wafer according to claim 3, wherein the wafer further comprises a third power supply area, and the third power supply area is arranged at a distance from the first power supply area and the second power supply area, so The third power supply area includes a plurality of third pads and a plurality of fourth pads;

The third pads in the third power supply area are connected in parallel, and the fourth pads in the third power supply area are connected in parallel; and the third pad in the third power supply area serves as the power input end of the third power supply area To supply power to the internal components of the third power supply area; the fourth pad in the third power supply area serves as the ground terminal of the third power supply area.
The wafer according to claim 4, wherein the third pad in the third power supply area is connected to the third pad in the second power supply area.
The wafer according to claim 4, wherein the internal components of the first power supply area, the second power supply area, and the third power supply area include a plurality of computing cores.
An intelligent processor, comprising: a substrate and a wafer mounted on the substrate;

The wafer has a first power supply area, the first power supply area includes a plurality of first pads and a plurality of second pads; the first pads in the first power supply area are connected in parallel, the first The second pads in the power supply area are connected in parallel, and the first pads in the first power supply area are used as the power input end of the first power supply area to supply power to the internal components of the first power supply area; The second pad in the area serves as the ground terminal of the first power supply area.
The intelligent processor according to claim 7, wherein the wafer has a second power supply area spaced apart from the first power supply area, the second power supply area includes a plurality of second pads and A third pad, the second pad in the second power supply area is connected in parallel, and the third pad in the second power supply area is connected in parallel; and the second pad in the second power supply area is used as the second power supply A power input terminal of the power supply area to supply power to internal components of the second power supply area; and a third pad in the second power supply area serves as a ground terminal of the second power supply area.
The intelligent processor according to claim 8, wherein the second pad in the first power supply area is connected to the second pad in the second power supply area.
The intelligent processor according to claim 9, wherein the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area, The third power supply area includes a plurality of third pads and a plurality of fourth pads;

The third pads in the third power supply area are connected in parallel, and the fourth pads in the third power supply area are connected in parallel; and the third pad in the third power supply area serves as the power input end of the third power supply area To supply power to the internal components of the third power supply area; the fourth pad in the third power supply area serves as the ground terminal of the third power supply area.
The intelligent processor according to claim 10, wherein the third pad in the third power supply area is connected to the third pad in the second power supply area.
The intelligent processor of claim 10, wherein the internal components of the first power supply area, the second power supply area, and the third power supply area include multiple computing cores.
The intelligent processor according to any one of claims 9 to 11, wherein a first circuit is provided on the substrate, the second pad in the first power supply area and the second power supply area The second pad is connected through the first circuit.
The intelligent processor according to claim 11, wherein a second circuit is further provided on the substrate, the third pad in the second power supply area and the third solder in the third power supply area The disk is connected through the second circuit.
The intelligent processor according to claim 7, wherein the intelligent processor further comprises a packaging cover, the wafer is provided on a mounting surface of the substrate, and the packaging cover is provided on the wafer And connected to the mounting surface.
The intelligent processor according to claim 15, wherein the packaging cover is a plastic cover, a ceramic cover or a metal cover.
The intelligent processor according to claim 7, wherein the intelligent processor is a chip.
An electric appliance, characterized by comprising: the intelligent processor according to any one of claims 7-15.